Semiconductor structure and three-dimensional NAND memory device

Abstract

A semiconductor structure is disclosed, comprising: a memory level assembly located over a semiconductor substrate and including at least one alternating stack and a memory stack structure; a plurality of laterally elongated contact via structures vertically extending through the memory level assembly, laterally extending along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally spaced apart blocks, including a set of three adjacent blocks including, in order, a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; a through-memory-level via region located adjacent to a longitudinal end of the second block and between a staircase region of the first block and a staircase region of the third block, wherein the through-memory-level via region includes a vertically extending through-memory-level via structure embedded in a portion of a dielectric fill material; and a word line switch device. A three-dimensional NAND memory device is also disclosed.

Description

[0001] This application is a continuation-in-part of Chinese National Stage Patent Application No. 201680055260.6, filed of PCT International Patent Application No. PCT / US2016 / 054018 having an international filing date of September 27, 2016, which claims priority to U.S. Provisional Patent Application No. 62 / 271,210 filed December 22, 2015, and U.S. Non-Provisional Patent Application Nos. 15 / 269,041, 15 / 269,112, 15 / 269,294, 15 / 269,946, and 15 / 269,017, filed September 19, 2016.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to U.S. Provisional Application Serial No. 62 / 271,210, filed December 22, 2015; U.S. Non-Provisional Application Serial No. 15 / 269,041, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269,112, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269,294, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269,946, filed September 19, 2016; and U.S. Non-Provisional Application Serial No. 15 / 269,017, filed September 19, 2016, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0004] The present disclosure relates generally to the field of semiconductor devices, and more specifically to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of manufacturing the same. BACKGROUND

[0005] Recently, ultra-high density memory devices using three-dimensional (3D) stacked memory stack structures, sometimes referred to as bit cost scalable (BiCS) architecture, have been proposed. For example, a 3D NAND stacked memory device can be formed from an array of alternating stacks of insulating material and spacer material layers that are formed into or replaced with conductive layers. Memory openings are formed through the alternating stacks and filled with memory stack structures, each including a vertically stacked memory element and a vertical semiconductor channel. A memory level assembly including the alternating stacks and the memory stack structures is formed on a substrate. The conductive layers can serve as word lines for the 3D NAND stacked memory device, and bit lines covering the array of memory stack structures can be connected to drain ends of the vertical semiconductor channels. As three-dimensional memory devices are scaled down to smaller device sizes, device area of peripheral devices occupies a large portion of the overall chip area. Therefore, it is desirable to provide various peripheral devices (e.g., word line driver circuits) without significantly increasing the overall chip size. In addition, an efficient power distribution network in the array of memory stack structures can improve the performance of the three-dimensional memory device. It is also desirable to have a method to enhance power distribution without unduly increasing the footprint of the semiconductor chip. SUMMARY

[0006] According to one aspect of the disclosure, a three-dimensional NAND memory device is provided, including a word line driver device located on or above a substrate, an alternating stack of word lines and insulating layers located above the word line driver device, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a through-memory-level via structure electrically coupling a word line in a first memory block to the word line driver device. The through-memory-level via structure extends through a through-memory-level via region between a staircase region of the first memory block and a staircase region of another memory block.

[0007] According to an aspect of the present disclosure, a semiconductor structure is provided that includes a memory level assembly located over a semiconductor substrate and including at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack, wherein the at least one alternating stack includes alternating layers of respective insulative layers and respective conductive layers; a plurality of laterally-elongate contact via structures extending vertically through the memory level assembly, extending laterally along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally-spaced blocks, wherein the plurality of blocks includes a set of three adjacent blocks including, in order, a first block, a second block, and a third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction; and a through-memory-level via region located adjacent to a longitudinal end of the second block and between a staircase region of the first block and a staircase region of the third block. Each staircase region of the first and third blocks includes a staircase in which each lower layer conductive layer extends farther along the first horizontal direction than any upper layer conductive layer within the memory level assembly. The through-memory-level via region includes a through-memory-level via structure extending vertically at least from a first horizontal plane including a topmost surface of the memory level assembly to a second horizontal plane including a bottommost surface of the memory level assembly.

[0008] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A memory level assembly is formed on a semiconductor substrate. The memory level assembly includes at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack. The at least one alternating stack includes alternating layers of respective insulative layers and respective conductive layers, and the at least one alternating stack includes a staircase region including a staircase in which each lower layer conductive layer extends farther along a first horizontal direction than any upper layer conductive layer within the memory level assembly. A plurality of laterally-elongate contact via structures is formed through the memory level assembly. The plurality of laterally-elongate contact via structures extends laterally along the first horizontal direction and laterally divides the at least one alternating stack into a plurality of laterally-spaced blocks. The plurality of blocks includes a set of at least three adjacent blocks including, in order, a first block, a second block, and a third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction; and respectively includes a first staircase region, a second staircase region, and a third staircase region. The second staircase region is removed. The second staircase region is removed. A through-memory-level via structure is formed in an area of the removed second staircase region while the first and third staircase regions remain intact. Each through-memory-level via structure extends vertically at least from a first horizontal plane including a topmost surface of the memory level assembly to a second horizontal plane including a bottommost surface of the memory level assembly.

[0009] According to yet another aspect of the present disclosure, a three-dimensional NAND memory device is provided, comprising: a word line driver device located on or over a substrate; alternating stacks of word lines and insulating layers located over the word line driver device; a plurality of memory stack structures extending through the alternating stacks, each memory stack structure comprising a memory film and a vertical semiconductor channel; and a through-memory-level via structure electrically coupling a word line in a first memory block to the word line driver device. The through-memory-level via structure extends through a portion of a dielectric fill material located between a staircase region of the first memory block and a staircase region of another memory block.

[0010] According to yet another aspect of the present disclosure, a semiconductor structure is provided, comprising: a word line switch device comprising a field effect transistor and located on a semiconductor substrate; and a memory level assembly overlying the semiconductor substrate and comprising at least one alternating stack and memory stack structures extending vertically through the at least one alternating stack. Each of the at least one alternating stack comprises alternating layers of a respective insulating layer and a respective conductive layer comprising a word line for a memory stack structure. A plurality of laterally elongated contact via structures extend vertically through the memory level assembly, extend laterally along a first horizontal direction, and laterally divide the memory level assembly into a plurality of laterally spaced apart blocks. The plurality of blocks comprises a set of three adjacent blocks comprising, in order, a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction. A through-memory-level via region is directly located over a region of the word line switch device on a longitudinal end of the second block and between a staircase region of the first block and a staircase region of the third block, each staircase region of the first and third blocks comprising a staircase in which each lower layer conductive layer extends further along the first horizontal direction than any upper layer conductive layer within the memory level assembly, and the through-memory-level via region comprises a through-memory-level via structure, each of which provides an electrically conductive path between a respective word line switch device and a respective word line.

[0011] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A wordline switch device including a field effect transistor is formed on a semiconductor substrate. A memory level assembly is formed over the semiconductor substrate, the memory level assembly including at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack. Each of the at least one alternating stack includes alternating layers of a respective insulating layer and a respective conductive layer, and the at least one alternating stack includes a staircase region including a staircase in which each lower conductive layer extends farther along a first horizontal direction than any upper conductive layer within the memory level assembly. A plurality of laterally elongated contact via structures is formed through the memory level assembly. The plurality of laterally elongated contact via structures extends laterally along the first horizontal direction and laterally divides the at least one alternating stack into a plurality of laterally spaced apart blocks. The plurality of blocks includes a set of three adjacent blocks including, in order, a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; and including, respectively, a first staircase region, a second staircase region, and a third staircase region. A node of the wordline switch device is electrically connected to portions of conductive layers in the first and third staircase regions using a through-memory-level via structure formed in an area of the second staircase region.

[0012] According to yet another aspect of the present disclosure, a semiconductor structure is provided including: a memory level assembly over a semiconductor substrate and including at least one first alternating stack of conductive layers and first portions of insulating layers, and further including memory stack structures extending vertically through the at least one first alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel, wherein the conductive layers include word lines for the memory stack structures; an insulative deep trench structure extending vertically through the memory level assembly and defining an area of a through-memory-level via region laterally spaced apart from the at least one first alternating stack; at least one second alternating stack in the through-memory-level via region, wherein the at least one second alternating stack includes alternating layers of a dielectric spacer layer and second portions of the insulating layers, and each of the dielectric spacer layers is at a same level as a respective conductive layer; and a through-memory-level via structure within the through-memory-level via region and extending vertically from a first horizontal plane including a topmost surface of the memory level assembly and a bottommost surface of the memory level assembly and including a conductive material.

[0013] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. At least one alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. Deep trench grooves defining regions of through-memory-level via regions are formed through the at least one alternating stack. A portion of the at least one alternating stack is present within the through-memory-level via regions. Portions of the dielectric spacer layers outside the through-memory-level via regions are replaced with electrically conductive layers while portions of the at least one alternating stack in the deep trench grooves remain intact. The electrically conductive layers constitute word lines for the memory stack structures. Through-memory-level via structures are formed within the through-memory-level via regions. The through-memory-level via structures extend vertically from a topmost surface including a remaining portion of the at least one alternating stack and a first level of a bottommost surface of the at least one alternating stack.

[0014] According to yet another aspect of the present disclosure, a semiconductor structure is provided, comprising: a memory level assembly located over a semiconductor substrate and including at least one alternating stack of electrically conductive layers and first portions of insulating layers, and further including memory stack structures extending vertically through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. The electrically conductive layers constitute word lines for the memory stack structures. A plurality of laterally elongated contact via structures extend vertically through the memory level assembly, extend laterally along a first horizontal direction, and laterally divide the at least one alternating stack into a plurality of laterally spaced apart blocks within the memory level assembly. At least one through-memory-level via structure is located in a through-memory-level via region in a block; wherein the through-memory-level via region is located between a pair of laterally elongated contact via structures and between two groups of memory stack structures located in the block; wherein each of the at least one through-memory-level via structure extends vertically through the memory level assembly.

[0015] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure is provided. A memory level assembly is formed on a semiconductor substrate. The memory level assembly includes at least one alternating stack of conductive layers and first portions of insulating layers, and further includes memory stack structures extending vertically through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. A plurality of laterally elongated contact via structures are formed through the memory level assembly. The plurality of laterally elongated contact via structures extend laterally along a first horizontal direction and laterally divide the at least one alternating stack into a plurality of laterally spaced apart blocks within the memory level assembly. At least one through-memory-level via structure is formed in a through-memory-level via region in a block. The through-memory-level via region is located between a pair of laterally elongated contact via structures and between two groups of memory stack structures located in the block and including the through-memory-level via structure. Each of the at least one through-memory-level via structure extends vertically through the memory level assembly. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1A is a vertical cross-sectional view of a first exemplary structure after forming a semiconductor device, at least one lower level dielectric layer, and a lower level metal interconnect structure on a semiconductor substrate according to the first embodiment of the present disclosure.

[0017] Figure 1B is a horizontal cross-sectional view of the first exemplary structure of Figure 1A along a horizontal plane B-B' of Figure 1A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 1A .

[0018] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming a first layer alternating stack of planar semiconductor material layers and first insulating layers and first spacer material layers according to the first embodiment of the present disclosure.

[0019] Figure 3 is a vertical cross-sectional view of a first exemplary structure after patterning a first layer stepped region on the first layer alternating stack and forming a first layer back-stepped dielectric material portion according to the first embodiment of the present disclosure.

[0020] Figure 4A is a vertical cross-sectional view of a first exemplary structure after forming a first layer support pillar structure and an interlayer dielectric layer according to the first embodiment of the present disclosure.

[0021] Figure 4B is a horizontal cross-sectional view of the first exemplary structure of Figure 4AFIG. 1A is a vertical cross-sectional view of a first exemplary structure in accordance with a first embodiment of the present disclosure. Figure 4A FIG. 1B is a horizontal cross-sectional view of the first exemplary structure in FIG. 1A along the horizontal plane B-B’.

[0022] Figure 5A FIG. 1C is a vertical cross-sectional view of the first exemplary structure in FIG. 1A after formation of a first layer of memory openings in accordance with the first embodiment of the present disclosure.

[0023] Figure 5B FIG. 1D is a horizontal cross-sectional view of the first exemplary structure in FIG. 1C along the horizontal plane B-B’. Figure 5A FIG. 1E is a vertical cross-sectional view of the first exemplary structure in FIG. 1C along the vertical plane A-A’. Figure 5A FIG. 1F is a horizontal cross-sectional view of the first exemplary structure in FIG. 1C along the horizontal plane B-B’.

[0024] Figure 6 FIG. 1G is a vertical cross-sectional view of the first exemplary structure in FIG. 1C after formation of a sacrificial memory opening fill portion in accordance with the first embodiment of the present disclosure.

[0025] Figure 7 FIG. 1H is a vertical cross-sectional view of the first exemplary structure in FIG. 1G after formation of a second layer of alternating stacks of a second insulating layer and a second spacer material layer, a second layer of backside dielectric material portions, and a second insulating cap layer in accordance with the first embodiment of the present disclosure.

[0026] Figure 8A FIG. 1I is a vertical cross-sectional view of the first exemplary structure in FIG. 1H after formation of a second layer of dielectric support pillars and a drain select level shallow trench isolation structure in accordance with the first embodiment of the present disclosure.

[0027] Figure 8B FIG. 1J is a horizontal cross-sectional view of the first exemplary structure in FIG. 1I along the horizontal plane B-B’. Figure 8A FIG. 1K is a vertical cross-sectional view of the first exemplary structure in FIG. 1I along the vertical plane A-A’. Figure 8A FIG. 1L is a horizontal cross-sectional view of the first exemplary structure in FIG. 1I along the horizontal plane B-B’.

[0028] Figure 9A FIG. 1M is a vertical cross-sectional view of the first exemplary structure in FIG. 1I after formation of a memory opening in accordance with the first embodiment of the present disclosure.

[0029] Figure 9B FIG. 1N is a horizontal cross-sectional view of the first exemplary structure in FIG. 1M along the horizontal plane B-B’. Figure 9A FIG. 1O is a vertical cross-sectional view of the first exemplary structure in FIG. 1M along the vertical plane A-A’. Figure 9A FIG. 1P is a horizontal cross-sectional view of the first exemplary structure in FIG. 1M along the horizontal plane B-B’.

[0030] Figure 10A FIG. 1Q is a vertical cross-sectional view of the first exemplary structure in FIG. 1M after formation of a memory stack structure and a contact level dielectric layer in accordance with the first embodiment of the present disclosure.

[0031] Figure 10B is a horizontal cross-sectional view of the first exemplary structure in FIG. 1A along the horizontal plane B-B’. Figure 10A FIG. 1A is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B’ in FIG. 1. The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 1B. Figure 10A

[0032] Figure 11A FIG. 1C is a vertical cross-sectional view of the first exemplary structure after forming dielectric fill material in accordance with the first embodiment of the present disclosure.

[0033] Figure 11B FIG. 1D is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B’ in FIG. 1C. The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 1E. Figure 11A Figure 11A

[0034] Figure 12A FIG. 1F is a vertical cross-sectional view of the first exemplary structure after forming backside contact trenches in accordance with the first embodiment of the present disclosure.

[0035] Figure 12B FIG. 1G is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B’ in FIG. 1F. The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 1H. Figure 12A Figure 12A

[0036] Figure 13A FIG. 1I is a vertical cross-sectional view of the first exemplary structure after forming backside recesses by removing spacer material layers in accordance with the first embodiment of the present disclosure.

[0037] Figure 13B FIG. 1J is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B’ in FIG. 1I. The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 1K. Figure 13A Figure 13A

[0038] Figure 14A FIG. 1M is a vertical cross-sectional view of the first exemplary structure along the jagged vertical plane C-C’ in FIG. 1L in accordance with the first embodiment of the present disclosure.

[0039] Figure 14B FIG. 1N is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B’ in FIG. 1M. The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 1O. Figure 14A Figure 14A

[0040] Figure 14C FIG. 1P is a vertical cross-sectional view of the first exemplary structure along the jagged vertical plane C-C’ in FIG. 1N in accordance with the first embodiment of the present disclosure. Figure 14B

[0041] Figure 15A ​​​​​​​​​​is a vertical cross-sectional view of the first exemplary structure after forming the conductive layer, the insulating spacer, and the backside contact via structure according to the first embodiment of the present disclosure.

[0042] Figure 15B is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B' in Figure 15A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 15A . The pattern of the upper level line structures is superimposed in a dashed line shape.

[0043] Figure 15C is a vertical cross-sectional view of the first exemplary structure along the jagged vertical plane C-C' in Figure 15B .

[0044] Figure 16A is a vertical cross-sectional view of the first exemplary structure after forming the through-memory-level via structure, the wordline contact via structure, and the upper level via structure according to the first embodiment of the present disclosure.

[0045] Figure 16B is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B' in Figure 16A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 16A . The pattern of the upper level line structures is superimposed in a dashed line shape.

[0046] Figure 16C is a vertical cross-sectional view of the first exemplary structure along the jagged vertical plane C-C' in Figure 16B .

[0047] Figure 17A is a vertical cross-sectional view of the first exemplary structure after forming the upper level line structure according to the first embodiment of the present disclosure.

[0048] Figure 17B is a horizontal cross-sectional view of the first exemplary structure along the horizontal plane B-B' in Figure 17A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 17A . The pattern of the upper level line structures is superimposed in a dashed line shape.

[0049] Figure 17C is a vertical cross-sectional view of the first exemplary structure along the jagged vertical plane C-C' in Figure 17B .

[0050] Figure 17D is a top view of the first exemplary structure according to the first embodiment of the present disclosure.

[0051] Figure 17E and 17Fis a top-down view of an alternative exemplary structure according to the first embodiment of the present disclosure.

[0052] Figure 18 is a vertical cross-sectional view of a second exemplary structure according to the second embodiment of the present disclosure after forming a semiconductor device, lower level metal interconnect structures, and at least one lower level dielectric layer.

[0053] Figure 19A is a vertical cross-sectional view of a second exemplary structure according to the second embodiment of the present disclosure after forming a through-memory-level via structure and an upper level metal interconnect structure.

[0054] Figure 19B is a cross-sectional plan view of a metal interconnect structure according to the second embodiment of the present disclosure.

[0055] Figure 20 is a vertical cross-sectional view of a variation of a second exemplary structure according to the second embodiment of the present disclosure after forming a semiconductor device, lower level metal interconnect structures, and at least one lower level dielectric layer.

[0056] Figure 21 is a vertical cross-sectional view of a variation of a second exemplary structure according to the second embodiment of the present disclosure after forming a first level structure including a sacrificial memory opening fill portion and a first level support pillar structure.

[0057] Figure 22 is a vertical cross-sectional view of a variation of a second exemplary structure according to the second embodiment of the present disclosure after forming a second level structure, a memory stack structure, a second level support pillar structure, a contact level dielectric layer, and a backside contact trench.

[0058] Figure 23 is a vertical cross-sectional view of a variation of a second exemplary structure according to the second embodiment of the present disclosure after forming a through-memory-level via structure.

[0059] Figure 24A is a vertical cross-sectional view of a third exemplary structure according to the third embodiment of the present disclosure after forming a first level alternating stack, a first level support pillar structure, a sacrificial memory opening fill portion, and a sacrificial backside contact trench fill portion.

[0060] Figure 24B is a horizontal cross-sectional view of the third exemplary structure along a horizontal plane B-B' in Figure 24A corresponding to the vertical cross-sectional view of Figure 24A .

[0061] Figure 25Ais a vertical cross-sectional view of the third exemplary structure after formation of the second-tier alternating stack, the second-tier support pillar structure, the drain-select-level shallow trench structure, the memory opening, and the deep trench groove according to the third embodiment of the present disclosure.

[0062] Figure 25B is a horizontal cross-sectional view of the third exemplary structure along the horizontal plane B-B' in Figure 25A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 25A .

[0063] Figure 26A is a vertical cross-sectional view of the third exemplary structure after formation of the memory stack structure and the insulative deep trench groove structure according to the third embodiment of the present disclosure.

[0064] Figure 26B is a horizontal cross-sectional view of the third exemplary structure along the horizontal plane B-B' in Figure 26A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 26A .

[0065] Figure 27A is a vertical cross-sectional view of the third exemplary structure after formation of the backside contact trench according to the third embodiment of the present disclosure.

[0066] Figure 27B is a horizontal cross-sectional view of the third exemplary structure along the horizontal plane B-B' in Figure 27A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 27A .

[0067] Figure 28A is a vertical cross-sectional view of the third exemplary structure after formation of the laterally-elongated contact via structure according to the third embodiment of the present disclosure.

[0068] Figure 28B is a horizontal cross-sectional view of the third exemplary structure along the horizontal plane B-B' in Figure 28A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 28A .

[0069] Figure 29A is a vertical cross-sectional view of the third exemplary structure after formation of the through-memory-level via structure according to the third embodiment of the present disclosure.

[0070] Figure 29B is a horizontal cross-sectional view of the third exemplary structure along the horizontal plane B-B' in Figure 29A . The jagged vertical plane A-A' corresponds to the plane of the vertical cross-sectional view of Figure 29A .

[0071] Figure 29C According to the third embodiment of this disclosure, along Figure 29B A vertical cross-sectional view of the third exemplary structure in the sawtooth vertical plane C-C'.

[0072] Figure 30 This is a vertical cross-sectional view of a third exemplary structure after the formation of an upper-level metal interconnect structure, according to a third embodiment of the present disclosure.

[0073] Figure 31A This is a vertical cross-sectional view of a variation of a third exemplary structure after the formation of an insulating deep trench structure according to a third embodiment of the present disclosure.

[0074] Figure 31B It is along Figure 31A A horizontal cross-sectional view of a variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 31A The plane of the vertical cross-section.

[0075] Figure 32A This is a vertical cross-sectional view of a variation of a third exemplary structure following the formation of a memory stack structure, a laterally elongated contact via structure, and a through-memory layer via structure, according to a third embodiment of the present disclosure.

[0076] Figure 32B It is along Figure 32A A horizontal cross-sectional view of a variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 32A The plane of the vertical cross-section.

[0077] Figure 33A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a first layer alternating stack, a second layer alternating stack, and a memory stack structure according to a fourth embodiment of the present disclosure.

[0078] Figure 33B It is along Figure 33A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 33A The plane of the vertical cross-section.

[0079] Figure 34A This is a horizontal cross-sectional view of a fourth exemplary structure after forming a through-memory level opening and a rear contact trench, according to a fourth embodiment of the present disclosure.

[0080] Figure 34B It is along Figure 34A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 34A the vertical cross-sectional view of FIG. 4B.

[0081] Figure 35A is a vertical cross-sectional view of the fourth exemplary structure after deposition and patterning of an insulating spacer layer according to the fourth embodiment of the present disclosure.

[0082] Figure 35B is a horizontal cross-sectional view of the fourth exemplary structure along the horizontal plane B-B’ in Figure 35A corresponding to the vertical plane A-A’ in Figure 35A the vertical cross-sectional view of FIG. 4B.

[0083] Figure 36A is a vertical cross-sectional view of the fourth exemplary structure after formation of a backside recess according to the fourth embodiment of the present disclosure.

[0084] Figure 36B is a horizontal cross-sectional view of the fourth exemplary structure along the horizontal plane B-B’ in Figure 36A corresponding to the vertical plane A-A’ in Figure 36A the vertical cross-sectional view of FIG. 4B.

[0085] Figure 37A is a vertical cross-sectional view of the fourth exemplary structure after formation of a conductive layer according to the fourth embodiment of the present disclosure.

[0086] Figure 37B is a horizontal cross-sectional view of the fourth exemplary structure along the horizontal plane B-B’ in Figure 37A corresponding to the vertical plane A-A’ in Figure 37A the vertical cross-sectional view of FIG. 4B.

[0087] Figure 38A is a vertical cross-sectional view of the fourth exemplary structure after formation of an insulating deep trench structure and laterally elongated contact via structure according to the fourth embodiment of the present disclosure.

[0088] Figure 38B is a horizontal cross-sectional view of the fourth exemplary structure along the horizontal plane B-B’ in Figure 38A corresponding to the vertical plane A-A’ in Figure 38A the vertical cross-sectional view of FIG. 4B.

[0089] Figure 39A is a vertical cross-sectional view of the fourth exemplary structure after formation of a through-memory-level via structure according to the fourth embodiment of the present disclosure.

[0090] Figure 39B is a horizontal cross-sectional view of the fourth exemplary structure along the horizontal plane B-B’ in Figure 39A corresponding to the vertical plane A-A’ in Figure 39A the vertical cross-sectional view of FIG. 4A.

[0091] Figure 40 is a vertical cross-sectional view of a fourth exemplary structure after formation of an upper level metal interconnect structure in accordance with the fourth embodiment of the present disclosure.

[0092] Figure 41 is a vertical cross-sectional view of a first variation of the fourth exemplary structure after formation of a patterned insulating liner layer in accordance with the fourth embodiment of the present disclosure.

[0093] Figure 42 is a vertical cross-sectional view of a first variation of the fourth exemplary structure after formation of an insulating deep trench structure, laterally elongated contact via structure, and through-memory-level via structure in accordance with the fourth embodiment of the present disclosure.

[0094] Figure 43 is a vertical cross-sectional view of a first variation of the fourth exemplary structure after formation of an upper level metal interconnect structure in accordance with the fourth embodiment of the present disclosure.

[0095] Figure 44A is a vertical cross-sectional view of a second variation of the fourth exemplary structure after formation of a first-tier alternating stack, a second-tier alternating stack, a memory stack structure, and a drain-select-level shallow trench isolation structure in accordance with the fourth embodiment of the present disclosure.

[0096] Figure 44B is a horizontal cross-sectional view of the second variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 44A . The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 4A. Figure 44A

[0097] Figure 45A is a vertical cross-sectional view of a second variation of the fourth exemplary structure after formation of a through-memory-level opening and a backside contact trench in accordance with the fourth embodiment of the present disclosure.

[0098] Figure 45B is a horizontal cross-sectional view of the second variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 45A . The jagged vertical plane A-A’ corresponds to the plane of the vertical cross-sectional view of FIG. 4A. Figure 45A

[0099] Figure 46A is a vertical cross-sectional view of a second variation of the fourth exemplary structure after replacement of a sacrificial material layer with a conductive layer in accordance with the fourth embodiment of the present disclosure.

[0100] Figure 46B is a horizontal cross-sectional view of the second variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 46A ​​A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 46A The plane of the vertical cross-section.

[0101] Figure 47A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure following the deposition of a conformal insulating layer and anisotropic etching, according to a fourth embodiment of the present disclosure, wherein the anisotropic etching removes a horizontal portion of the conformal insulating layer and deepens an opening through the memory hierarchy.

[0102] Figure 47B It is along Figure 47A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 47A The plane of the vertical cross-section.

[0103] Figure 48A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure after forming a laterally elongated contact via structure and a through-memory layer via structure, according to a fourth embodiment of the present disclosure.

[0104] Figure 48B It is along Figure 48A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 48A The plane of the vertical cross-section.

[0105] Figure 49 This is a vertical cross-sectional view of a second variant of a fourth exemplary structure after the formation of an upper-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0106] Figure 50A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure following the formation of a first layer alternating stack, a second layer alternating stack, a memory stack structure, and a drain selection layer shallow trench isolation structure, according to the fourth embodiment of this disclosure.

[0107] Figure 50B It is along Figure 50A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 50A The plane of the vertical cross-section.

[0108] Figure 51A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after forming an opening through the memory hierarchy, according to a fourth embodiment of the present disclosure.

[0109] Figure 51B It is along Figure 51AA horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 51A The plane of the vertical cross-section.

[0110] Figure 52A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after replacing the sacrificial material layer with a conductive layer, according to a fourth embodiment of the present disclosure.

[0111] Figure 52B It is along Figure 52A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 52A The plane of the vertical cross-section.

[0112] Figure 53A This is a vertical cross-sectional view of a third variation of a fourth exemplary structure after the formation of an insulating liner, according to a fourth embodiment of the present disclosure.

[0113] Figure 53B It is along Figure 53A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 53A The plane of the vertical cross-section.

[0114] Figure 54A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after forming a through-hole structure in accordance with the fourth embodiment of this disclosure.

[0115] Figure 54B It is along Figure 54A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 54A The plane of the vertical cross-section.

[0116] Figure 55A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure following the formation of a laterally elongated contact via structure and an upper-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0117] Figure 55B It is along Figure 55A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 55A The plane of the vertical cross-section.

[0118] Figure 56Ais a vertical cross-sectional view of a fourth modification of the fourth exemplary structure after formation of the memory stack structure and the laterally-elongated contact via structure according to the fourth embodiment of the present disclosure.

[0119] Figure 56B is a horizontal cross-sectional view of the fourth modification of the fourth exemplary structure along the horizontal plane B-B' in Figure 56A corresponding to the plane of the vertical cross-sectional view of Figure 56A .

[0120] Figure 57A is a vertical cross-sectional view of a fourth modification of the fourth exemplary structure after formation of the through-memory-level opening according to the fourth embodiment of the present disclosure.

[0121] Figure 57B is a horizontal cross-sectional view of the fourth modification of the fourth exemplary structure along the horizontal plane B-B' in Figure 57A corresponding to the plane of the vertical cross-sectional view of Figure 57A .

[0122] Figure 58A is a vertical cross-sectional view of a fourth modification of the fourth exemplary structure after formation of the insulating liner according to the fourth embodiment of the present disclosure.

[0123] Figure 58B is a horizontal cross-sectional view of the fourth modification of the fourth exemplary structure along the horizontal plane B-B' in Figure 58A corresponding to the plane of the vertical cross-sectional view of Figure 58A .

[0124] Figure 59A is a vertical cross-sectional view of a fourth modification of the fourth exemplary structure after formation of the through-memory-level via structure and the upper-level metal interconnect structure according to the fourth embodiment of the present disclosure.

[0125] Figure 59B is a horizontal cross-sectional view of the fourth modification of the fourth exemplary structure along the horizontal plane B-B' in Figure 59A corresponding to the plane of the vertical cross-sectional view of Figure 59A .

[0126] Figure 60 is a horizontal cross-sectional view of a fifth modification of the fourth exemplary structure according to the fourth embodiment of the present disclosure.

[0127] Figure 61A is a vertical cross-sectional view of a second modification of the third exemplary structure after formation of the memory stack structure according to the third embodiment of the present disclosure.

[0128] Figure 61B yes Figure 61A A horizontal cross-sectional view of the second variant of the third exemplary structure. The serrated vertical plane A-A' corresponds to... Figure 61A The plane of the vertical cross-section.

[0129] Figure 62A This is a vertical cross-sectional view of a second variant of a third exemplary structure after simultaneously forming a rear contact groove and a deep trench, according to a third embodiment of the present disclosure.

[0130] Figure 62B yes Figure 62A A horizontal cross-sectional view of the second variant of the third exemplary structure. The serrated vertical plane A-A' corresponds to... Figure 62A The plane of the vertical cross-section.

[0131] Figure 63A This is a vertical cross-sectional view of a second variant of a third exemplary structure after the formation of an upper-level line structure, according to a third embodiment of the present disclosure.

[0132] Figure 63B It is along Figure 63A A horizontal cross-sectional view of the second variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 63A The plane of the vertical cross-section.

[0133] Figure 63C According to the third embodiment of this disclosure, along Figure 63B A vertical cross-sectional view of a second variant of the third exemplary structure of the sawtooth vertical plane C-C' in the figure.

[0134] Figure 64 This is a vertical cross-sectional view of a third variant of a third exemplary structure after the formation of an upper-level line structure, according to a third embodiment of the present disclosure.

[0135] Figure 65A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure after the formation of the sacrificial memory opening fill portion and the sacrificial deep trench fill portion, according to the fourth embodiment of this disclosure.

[0136] Figure 65B It is along Figure 65A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 65A The plane of the vertical cross-section.

[0137] Figure 66A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure after the formation of a memory stack structure and a pseudo memory stack structure according to the fourth embodiment of this disclosure.

[0138] Figure 66B is a horizontal cross-sectional view of the sixth variation of the fourth exemplary structure along the horizontal plane B-B' in Figure 66A corresponds to the plane of the vertical cross-sectional view of Figure 66A

[0139] Figure 67A is a vertical cross-sectional view of the sixth variation of the fourth exemplary structure after forming the backside recess according to the fourth embodiment of the disclosure.

[0140] Figure 67B is a horizontal cross-sectional view of the sixth variation of the fourth exemplary structure along the horizontal plane B-B' in Figure 67A corresponds to the plane of the vertical cross-sectional view of Figure 67A

[0141] Figure 68A is a vertical cross-sectional view of the sixth variation of the fourth exemplary structure after forming the conductive layer and the laterally elongated contact via structure according to the fourth embodiment of the disclosure.

[0142] Figure 68B is a horizontal cross-sectional view of the sixth variation of the fourth exemplary structure along the horizontal plane B-B' in Figure 68A corresponds to the plane of the vertical cross-sectional view of Figure 68A

[0143] Figure 69A is a vertical cross-sectional view of the sixth variation of the fourth exemplary structure after forming the through-memory-level via structure and the upper-level metal interconnect structure according to the fourth embodiment of the disclosure.

[0144] Figure 69B is a horizontal cross-sectional view of the sixth variation of the fourth exemplary structure along the horizontal plane B-B' in Figure 69A corresponds to the plane of the vertical cross-sectional view of Figure 69A

[0145] Figure 70A is a vertical cross-sectional view of the seventh variation of the fourth exemplary structure after forming the memory stack structure and the contact-level dielectric layer according to the fourth embodiment of the disclosure.

[0146] Figure 70B is a horizontal cross-sectional view of the seventh variation of the fourth exemplary structure along the horizontal plane B-B' in Figure 70A corresponds to the plane of the vertical cross-sectional view of Figure 70A

[0147] ​​​​​ Figure 71A is a vertical cross-sectional view of a seventh variation of the fourth exemplary structure after formation of the laterally extending contact via structures and the through-memory-stack via structures according to the fourth embodiment of the present disclosure.

[0148] Figure 71B is a horizontal cross-sectional view of the seventh variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 71A corresponding to the plane of the vertical cross-sectional view of Figure 71A

[0149] Figure 72A is a vertical cross-sectional view of a seventh variation of the fourth exemplary structure after replacement of the sacrificial material layers with electrically conductive layers according to the fourth embodiment of the present disclosure.

[0150] Figure 72B is a horizontal cross-sectional view of the seventh variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 72A corresponding to the plane of the vertical cross-sectional view of Figure 72A

[0151] Figure 73A is a vertical cross-sectional view of a seventh variation of the fourth exemplary structure after formation of the laterally extending contact via structures and the through-memory-stack via structures according to the fourth embodiment of the present disclosure.

[0152] Figure 73B is a horizontal cross-sectional view of the seventh variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 73A corresponding to the plane of the vertical cross-sectional view of Figure 73A

[0153] Figure 73C is a vertical cross-sectional view of a seventh variation of the fourth exemplary structure along the Figure 73B corresponding to the plane of the vertical cross-sectional view of

[0154] Figure 74 is a vertical cross-sectional view of a seventh variation of the fourth exemplary structure after formation of the upper metal interconnect structures according to the fourth embodiment of the present disclosure.

[0155] Figure 75A is a vertical cross-sectional view of an eighth variation of the fourth exemplary structure after formation of the through-memory-stack via structures according to the fourth embodiment of the present disclosure.

[0156] Figure 75B is a horizontal cross-sectional view of the eighth variation of the fourth exemplary structure along the horizontal plane B-B’ in Figure 75A corresponding to the plane of the vertical cross-sectional view of​​​FIG. 75A the plane of the vertical cross-sectional view of FIG. 8A.

[0157] FIG. 76 is a vertical cross-sectional view of an eighth variation of the fourth exemplary structure after formation of an upper metal interconnect structure according to the fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0158] As described above, the present disclosure relates to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of manufacturing the same, various aspects of which are described below. Embodiments of the present disclosure can be employed to form various semiconductor devices, such as three-dimensional monolithic memory array devices including multiple NAND memory strings. The drawings are not to scale. Unless explicitly described or otherwise clear from context, multiple instances of an element can be duplicated in situations where a single instance of the element is described.

[0159] Numerical descriptors such as “first,” “second,” and “third” are used merely to identify similar elements, and different numerical descriptors can be employed in the specification and claims of the present disclosure. As used herein, a first element located “on” a second element can be located on the outer surface of the second element or on the inner side of the second element. As used herein, a first element is “directly on” a second element if there exists no physical interface between the surface of the first element and the surface of the second element. As used herein, an “in-process” structure or “transient” structure refers to a structure that is subsequently modified.

[0160] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer can extend across an entirety of an underlying or overlying structure, or can have a region that is less than the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes located between a top surface and a bottom surface of a continuous structure, or at either of the top surface and the bottom surface. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon and / or thereunder.

[0161] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general region between a first horizontal plane comprising a topmost surface of an array of memory elements (i.e., a plane parallel to a top surface of a substrate) and a second horizontal plane comprising a bottommost surface of the array of memory elements. As used herein, a “through-memory-level” element refers to an element that extends vertically through a memory level.

[0162] As used herein, a “semiconductor material” refers to a material having a 1.0 x 10 -6 S / cm to 1.0 x 10 5a material having a conductivity in the range of 1.0 S / cm to 1.0 x 10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0 x 10 5 S / cm. As used herein, "insulative material" or "dielectric material" refers to a material having a conductivity less than 1.0 x 10 -6 S / cm. All conductivity measurements are made under standard conditions.

[0163] Monolithic three-dimensional memory arrays are arrays in which multiple levels of memory are formed above a single substrate, such as a semiconductor wafer, without the use of an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional structure memory," non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and stacking the memory levels vertically. The substrates can be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed on separate substrates, such memories are not truly monolithic three-dimensional memory arrays. The substrates can include integrated circuits fabricated thereon, such as driver circuits for the memory device.

[0164] Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using various embodiments described herein. The monolithic three-dimensional NAND strings are in a monolithic three-dimensional array of NAND strings disposed above a substrate. At least one memory cell in a first device level of the three-dimensional array of NAND strings is over another memory cell in a second device level of the three-dimensional array of NAND strings.

[0165] Reference is made to FIG. 1A and 1BFIG. 1 illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a semiconductor substrate 9 and semiconductor devices 710 formed thereon. Shallow trench isolation structures 720 can be formed in an upper portion of the semiconductor substrate 9 to provide electrical isolation between the semiconductor devices. For example, the semiconductor devices 710 can include field effect transistors including respective source regions 742, drain regions 744, channel regions 746, and gate structures 750. The field effect transistors can be arranged in a CMOS configuration. Each gate structure 750 can include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor devices can include any semiconductor circuitry to support operation of a subsequently formed memory structure, commonly referred to as driver circuitry, which is also referred to as peripheral circuitry. As used herein, peripheral circuitry refers to any one or all of word line decoder circuitry, word line switch circuitry, bit line decoder circuitry, bit line sense and / or switch circuitry, power supply / distribution circuitry, data buffers and latches, etc., or any other semiconductor circuitry that can be implemented outside of a memory array structure for a memory device. For example, the semiconductor devices can include word line switch devices for electrically biasing word lines of a subsequently formed three-dimensional memory structure.

[0166] At least one dielectric layer is formed over the semiconductor device, which is referred to herein as at least one lower level dielectric layer 760. The at least one lower level dielectric layer 760 can include, for example, an optional dielectric liner 762, such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to underlying structures, a planarization dielectric layer 764 that is used to provide a planar surface that is coplanar with the topmost surface of the dielectric liner 762 or the topmost surface of the gate structure 750, an optional planarization liner 766, and at least one lower level interconnect dielectric layer 768 that collectively function as a matrix of lower level metal interconnect structures 780 that provide electrical routing between various nodes of the semiconductor device and subsequently formed landing pads for through-memory-level via structures. The lower level metal interconnect structures 780 can include various device contact via structures 782 (e.g., source and drain or gate electrode contacts that contact respective source and drain nodes of the device), lower level metal lines 784, lower level via structures 786, and lower level topmost metal structures 788 that are configured to function as landing pads for subsequently formed through-memory-level via structures. The region of the semiconductor device and the combination of the at least one lower level dielectric layer 760 and the lower level metal interconnect structures 780 are referred to herein as a lower peripheral device region 700, which underlies the subsequently formed memory level assembly and includes peripheral devices for the memory level assembly. The lower level metal interconnect structures 780 are embedded in the at least one lower level dielectric layer 760. In an embodiment, the topmost surface of the lower level topmost metal structures 788 can be at or below the level of the topmost surface of the at least one lower level dielectric layer 760.

[0167] The lower level metal interconnect structures 780 can be electrically shorted to a node (e.g., source 742, drain 744, or gate electrode 750) of the semiconductor device 710 (e.g., a CMOS device) and are at the level of the at least one lower level dielectric layer 760. Through-memory-level via structures (not shown in FIG. 1A and 1B ) can be subsequently formed directly on the lower level metal interconnect structures 780. In an embodiment, the pattern of the lower level metal interconnect structures 780 can be selected such that the lower level topmost metal structures 788 (which are a subset of the lower level metal interconnect structures 780 that are at the topmost portion of the lower level metal interconnect structures 780) can provide landing pad structures within the through-memory-level via region 400. The through-memory-level via region 400 is the region in which the through-memory-level via structures that vertically extend through the memory level assembly are subsequently formed.

[0168] As FIG. 1BAs shown, the through-memory-level via region 400 can be located adjacent to a memory array region 100 in which an array of memory devices is subsequently formed. The word line contact via region 200 can be located adjacent to the through-memory-level via region 400 and the memory array region 100. In an embodiment, the through-memory-level via region 400 and the word line contact via region 200 can be located at a peripheral edge of the memory array region 100 that is perpendicular to a first horizontal direction hi (e.g., a word line direction) and parallel to a second horizontal direction hd2(e.g., a bit line direction). In an embodiment, the regions of the first exemplary structure can be divided into a plurality of blocks (Bl, B2, B3,...) that are laterally separated along the second horizontal direction hd2and can be mapped one-to-one with positive integers, i.e., can be indexed with positive integers. The same word line in a given device level can be used as a control gate electrode for each memory cell in the same device level in each respective memory block.

[0169] Multiple instances of the through-memory-level via region 400 and the word line contact region 200 can alternate along the second horizontal direction hd2. In the illustrative example, each instance of the through-memory-level via region 400 can be located within the region of a respective even-numbered block (such as B2, B4, etc.), and each instance of the word line contact via region 200 can be located within the region of a respective odd-numbered block (such as Bl, B3, etc.). Adjacent pairs of odd-numbered and even-numbered blocks (e.g., Bl and B2) can be periodically repeated along the second horizontal direction.

[0170] Although a particular pattern for the lower-level topmost metal structure 788 is shown here, it should be understood that the pattern of the lower-level topmost metal structure 788 can be varied to optimize wiring in the lower-level peripheral device region 700, so long as the lower-level topmost metal structure 788 provides a suitable landing pad region for the subsequently formed through-memory-level via structure.

[0171] Referring to FIG. 2 An optional planar conductive material layer 6 and a planar semiconductor material layer 10 can be formed on the lower-level peripheral device region 700. The optional planar conductive material layer 6 includes a conductive material, such as a metal or a heavily doped semiconductor material. For example, the optional planar conductive material layer 6 can include a layer of tungsten having a thickness in a range of 3 nm to 100 nm, although smaller and larger thicknesses can also be employed. A metal nitride layer (not shown) can be provided on top of the planar conductive material layer 6 as a diffusion barrier layer. The layer 6 can be used as a special source line in a finished device. Alternatively, the layer 6 can include an etch stop layer and can include any suitable conductive, semiconductive, or insulative layer.

[0172] A planar semiconductor material layer 10 can be formed on the at least one lower-level dielectric layer 760. The planar semiconductor material layer 10 includes a semiconductor material, which can include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, and / or other semiconductor materials known in the art. In an embodiment, the planar semiconductor material layer 10 can include a polycrystalline semiconductor material, such as polysilicon, or an amorphous semiconductor material, such as amorphous silicon, that is converted into a polycrystalline semiconductor material in a subsequent processing step, such as an annealing step. The planar semiconductor material layer 10 can be formed directly over a subset of semiconductor devices on a semiconductor substrate 9, such as a silicon wafer. As used herein, a first element is “directly on top of” a second element if the first element is located above the level of the topmost surface of the second element and the area of the first element and the area of the second element have an area that overlaps in a plan view (i.e., along a vertical plane or direction that is perpendicular to the top surface of the substrate 9). In an embodiment, the planar semiconductor material layer 10, or portions thereof, can be doped with electrical dopants, which can be p-type dopants or n-type dopants. The conductivity type of the dopants in the planar semiconductor material layer 10 is referred to herein as a first conductivity type. A dielectric spacer layer 52 can be formed on a top surface of the planar semiconductor material layer 10.

[0173] An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer can include a first material, and each second material layer can include a second material that is different from the first material. In the case where at least one other alternating stack of material layers is subsequently formed over the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first-tier alternating stack. The tiers of the first-tier alternating stack are referred to herein as first-tier tiers, and the tiers of an alternating stack that is subsequently formed directly above the first-tier tiers are referred to herein as second-tier tiers, and so on.

[0174] The first-tier alternating stack can include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In an embodiment, the first spacer material layer can be a sacrificial layer that is subsequently replaced with a conductive layer. In another embodiment, the first spacer material layer can be a conductive layer that is not subsequently replaced with other layers. While the present disclosure is described with embodiments in which a sacrificial layer is replaced with a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby avoiding the need to perform a replacement process) are expressly

[0175] In an embodiment, the first material layers and the second material layers can be first insulating layers 132 and first sacrificial material layers 142, respectively. In an embodiment, each first insulating layer 132 can comprise a first insulating material, and each first sacrificial material layer 142 can comprise a first sacrificial material. An alternating plurality of first insulating layers 132 and first sacrificial material layers 142 is formed over the planar semiconductor material layer 10. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.

[0176] As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first element that is not an end element of the alternating plurality is contiguous on both sides with two instances of the second element, and each instance of the second element that is not an end element of the alternating plurality is contiguous on both sides with two instances of the first element. The first elements can have the same thickness therein, or can have different thicknesses. The second elements can have the same thickness therein, or can have different thicknesses. The alternating plurality of first material layers and second material layers can begin with an instance of a first material layer or with an instance of a second material layer, and can end with an instance of a first material layer or with an instance of a second material. In an embodiment, instances of the first elements and instances of the second elements can form a unit that repeats periodically within the alternating plurality.

[0177] The first layer alternating stack (132, 142) can include first insulating layers 132 composed of a first material and first sacrificial material layers 142 composed of a second material different from the first material. The first material of the first insulating layers 132 can be at least one insulating material. Insulating materials that can be used for the first insulating layers 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In an embodiment, the first material of the first insulating layers 132 can be silicon oxide.

[0178] The second material of the first sacrificial material layers 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layers 132. As used herein, the removal of a first material is “selective” to a second material if a removal process removes the first material at a rate that is at least twice the rate at which the second material is removed. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process for the first material relative to the second material.

[0179] The first sacrificial material layers 142 can comprise an insulative material, a semiconductive material, or a conductive material. The second material of the first sacrificial material layers 142 can later be replaced with a conductive electrode, which can be used, for example, as a control gate electrode of a vertical NAND device. In an embodiment, the first sacrificial material layers 142 can be a material layer comprising silicon nitride.

[0180] In an embodiment, the first insulative layers 132 can comprise silicon oxide, and the sacrificial material layers can comprise silicon nitride sacrificial material layers. The first material of the first insulative layers 132 can be deposited, for example, by chemical vapor deposition (CVD). If silicon oxide is used for the first insulative layers 132, for example, tetraethyl orthosilicate (TEOS) can be used as a precursor material for the CVD process. The second material of the first sacrificial material layers 142 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0181] The thickness of the first insulative layers 132 and the first sacrificial material layers 142 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each of the first insulative layers 132 and each of the first sacrificial material layers 142. The number of repetitions of pairs of the first insulative layers 132 and the first sacrificial material layers 142 can be in a range from 2 to 1024, and is typically from 8 to 256, although greater numbers of repetitions can also be employed. In an embodiment, each of the first sacrificial material layers 142 in the first tier-alternate stack (132, 142) can have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

[0182] A first insulative cap layer 170 is then formed over the stack (132, 142). The first insulative cap layer 170 comprises a dielectric material, which can be any of the dielectric materials that can be used for the first insulative layers 132. In an embodiment, the first insulative cap layer 170 comprises the same dielectric material as the first insulative layers 132. The thickness of the insulative cap layer 170 can be in a range from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed.

[0183] Referring to FIG. 3The first insulative cap layer 170 and the first-tier alternating stack (132, 142) can be patterned to form first staircase surfaces in each through-memory-level via region 400 and each word line contact via region 200. Each through-memory-level via region 400 and word line contact via region 200 can include a respective first staircase region SAl in which a first staircase surface is formed and a second staircase region SA2 in which additional staircase surfaces will subsequently be formed in a second-tier structure (subsequently formed over the first-tier structure) and / or additional tier structures. For example, the first staircase surfaces can be formed by forming a mask layer with openings therein, etching a cavity within tiers of the first insulative cap layer 170, and repeatedly expanding the etch region and vertically recessing the cavity by etching each pair of first insulative layer 132 and first sacrificial material layer 142 that is directly beneath a bottom surface of the etched cavity within the etch region. A dielectric material can be deposited to fill the first staircase cavity to form a first-tier back-staircase dielectric material portion 165. As used herein, a "back-staircase" element refers to an element having a staircase surface and a horizontal cross-sectional area that monotonically increases with a vertical distance from a top surface of a substrate on which the element is present. The first-tier alternating stack (132, 142) and the first-tier back-staircase dielectric material portion 165 collectively constitute a first-tier structure, which is the structure in processing that is subsequently modified.

[0184] Referring to FIG. 4A and 4B A first-tier support pillar structure 171 can be formed in portions of the first-tier alternating stack (132, 142) in which memory stack structures are not formed with sufficiently high density in subsequent processing steps. For example, the first-tier support pillar structure 171 can be formed in the through-memory-level via regions 400 and the word line contact via regions 200. For example, the first-tier support pillar structure 171 can be formed by forming a via cavity through the first-tier alternating stack (132, 142) and by filling the via cavity with a dielectric material such as silicon oxide and / or a dielectric metal oxide such as aluminum oxide. Locations of the staircases S in the first-tier alternating stack (132, 142) are shown as dashed lines in FIG. 4B

[0185] Optionally, an inter-tier dielectric layer 180 can be deposited over the first-tier structure (132, 142, 165, 170). The inter-tier dielectric layer 180 includes a dielectric material such as silicon oxide. The thickness of the inter-tier dielectric layer 180 can be in a range from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed.

[0186] Referring to FIG. 5A and 5B ​A first-tier memory opening 149 extending at least to the top surface of the planar semiconductor material layer 10 is formed through the first-tier alternating stack (132, 142). The first-tier memory opening 149 can be formed in the memory array region 100 at a location where a memory stack structure including a vertical stack of memory elements is to be subsequently formed. For example, a photoresist material stack (not shown) including at least one photoresist layer can be formed over the first insulating cap layer 170 (and optional layer 180), and can be lithographically patterned to form openings within the photoresist material stack. The pattern in the photoresist material stack can be transferred through the first insulating cap layer 170 (and optional layer 180) and through the entire first-tier alternating stack (132, 142) by at least one anisotropic etch that employs the patterned photoresist material stack as an etch mask. Portions of the first insulating cap layer 170 (and optional layer 180) and the first-tier alternating stack (132, 142) underlying the openings in the patterned photoresist material stack are etched to form the first-tier memory opening 149. In other words, transfer of the pattern in the patterned photoresist material stack through the first insulating cap layer 170 and the first-tier alternating stack (132, 142) forms the first-tier memory opening 149.

[0187] In one embodiment, the chemistry of the anisotropic etch process used to etch through the first-tier alternating stack (132, 142) can be alternated to optimize etching of the first and second materials in the first-tier alternating stack (132, 142). For example, the anisotropic etch can be a series of reactive ion etches or a single etch (e.g., CF4 / O2 / Ar etch). The sidewalls of the first-tier memory opening 149 can be substantially vertical, or can be tapered. Subsequently, the patterned photoresist material stack can be removed, e.g., by ashing.

[0188] Optionally, portions of the first-tier memory opening 149 at the level of the interlayer dielectric layer 180 can be laterally expanded by an isotropic etch. For example, if the interlayer dielectric layer 180 includes a dielectric material (such as borosilicate glass) having a greater etch rate than the first insulating layer 132 (which can include undoped silicate glass), an isotropic etch (such as a wet etch employing HF) can be used to enlarge the lateral dimensions of the first-tier memory opening at the level of the interlayer dielectric layer 180. Portions of the first-tier memory opening 149 at the level of the interlayer dielectric layer 180 can optionally be widened to provide a larger landing pad for a second-tier memory opening to be subsequently formed through a second-tier alternating stack (subsequently formed prior to formation of the second-tier memory opening).

[0189] A sacrificial memory opening fill portion 131 can be formed in the first tier memory opening 149. For example, a sacrificial fill material layer is deposited in the first tier memory opening 149. The sacrificial fill material layer includes a sacrificial material that can be subsequently removed selective to the materials of the first insulator layer 132 and the first sacrificial material layer 142. In an embodiment, the sacrificial fill material layer can include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a group III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop layer (such as a silicon oxide layer having a thickness in a range from 1 nm to 3 nm) can be employed prior to depositing the sacrificial fill material layer. The sacrificial fill material layer can be formed by a non-conformal deposition or a conformal deposition method. In another embodiment, the sacrificial fill material layer can include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that can be subsequently removed by ashing.

[0190] Portions of the deposited sacrificial material can be removed from the top surface of the first insulative cap layer 170 (and optional layer 180, if present). For example, the sacrificial fill material layer can be recessed to the top surface of the first insulative cap layer 170 (and optional layer 180, if present) using a planarization process. The planarization process can include a recess etch, a chemical mechanical planarization (CMP), or a combination thereof. The top surface of the first insulator layer 170 (and optional layer 180, if present) can serve as an etch stop layer or a planarization stop layer. Each remaining portion of the sacrificial material in the first tier memory opening 149 constitutes a sacrificial memory opening fill portion 131. The top surface of the sacrificial memory opening fill portion 131 can be coplanar with the top surface of the interlayer dielectric layer 180. The sacrificial memory opening fill portion 131 can or can not include a cavity therein.

[0191] Referring to FIG. 7 A second tier structure can be formed on the first tier structure (132, 142, 170, 131). The second tier structure can include an additional alternating stack of insulator layers and spacer material layers, which can be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers can be subsequently formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes a plurality of third material layers and fourth material layers that are alternating. Each third material layer can include a third material and each fourth material layer can include a fourth material that is different from the third material. In an embodiment, the third material can be the same as the first material of the first insulator layer 132 and the fourth material can be the same as the second material of the first sacrificial material layer 142.

[0192] In one embodiment, the third material layer can be a second insulating layer 232, and the fourth material layer can be a second spacer material layer that provides vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer can be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 can be at least one insulating material. The fourth material of the second sacrificial material layer 242 can be a sacrificial material that can be selectively removed relative to the third material of the second insulating layer 232. The second sacrificial material layer 242 can include an insulating material, a semiconducting material, or a conductive material. The fourth material of the second sacrificial material layer 242 can be later replaced with a conductive electrode that can be used, for example, as a control gate electrode of a vertical NAND device.

[0193] In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second stack (232, 242) can include a plurality of second insulating layers 232 and second sacrificial material layers 242 that alternate. The third material of the second insulating layer 232 can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0194] The third material of the second insulating layer 232 can be at least one insulating material. The insulating material that can be used for the second insulating layer 232 can be any of the materials that can be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be selectively removed relative to the third material of the second sacrificial material layer 242. The sacrificial material that can be used for the second sacrificial material layer 242 can be any of the materials that can be used for the first sacrificial material layer 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material.

[0195] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the pair of second insulating layer 232 and second sacrificial material layer 242 can be in a range from 2 to 1024, and is typically from 8 to 256, although greater numbers of repetitions can also be employed. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0196] A second set of processing steps can be employed to form the second staircase surfaces in the second staircase region SA2, which are the same as the processing steps used to form the first staircase surfaces in the first staircase region SA1, and the pattern of at least one mask layer is appropriately adjusted. The second staircase surfaces can be formed in the through-memory-level via regions 400 and the word line contact via regions 200. The second layer backside staircase dielectric material portions 265 can be formed over the second staircase surfaces in the through-memory-level via regions 400 and the word line contact via regions 200.

[0197] A second insulating cap layer 270 can be subsequently formed over the second alternating stack (232, 242). The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In an embodiment, the second insulating cap layer 270 can include silicon oxide. In an embodiment, the first and second sacrificial material layers (142, 242) can include silicon nitride.

[0198] In general, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed on the planar semiconductor material layer 10, and at least one backside staircase dielectric material portion (165, 265) can be formed over a staircase region on the at least one alternating stack (132, 142, 232, 242).

[0199] Referring to FIG. 8A and 8B A second layer support pillar structure 271 can be formed in a portion of the second layer alternating stack (132, 142) that covers the first layer support pillar structure 171. For example, the second layer support pillar structure 271 can be formed directly on a top surface of the first layer support pillar structure 171 in the through-memory-level via regions 400 and the word line contact via regions 200. For example, the second layer support pillar structure 271 can be formed by forming a via cavity through the second layer alternating stack (232, 242) and by filling the via cavity with a dielectric material such as silicon oxide and / or a dielectric metal oxide such as aluminum oxide.

[0200] Optionally, a drain select level shallow trench isolation structure 72 can be formed through a subset of layers in an upper portion of the second layer alternating stack (232, 242). The second sacrificial material layer 242 that is cut by the selected drain select level shallow trench isolation structure 72 corresponds to a level in which a drain select level conductive layer is subsequently formed. The drain select level shallow trench isolation structure 72 divides the blocks (B1, B2, B3,...) into a plurality of sub-blocks along the first horizontal direction hdl. The drain select level shallow trench isolation structure 72 includes a dielectric material such as silicon oxide. The locations of the staircases S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) are indicated by the dashed lines in FIG. 2. FIG. 8BThe staircase regions in the first, second, and third memory blocks are shown rising in the same diagonal direction (e.g., from left to right).

[0201] Referring to FIG. 9A and 9B A second-tier memory opening extending through the second-tier structure (232, 242, 270) is formed in the region overlying the sacrificial memory opening fill portion 131. A photoresist layer can be applied over the second-tier structure (232, 242, 270) and can be photopatterned to form a pattern identical to the pattern of the sacrificial memory opening fill portion 131 (i.e., the pattern of the first-tier memory openings). The photomask used to pattern the first-tier memory openings 149 can be used to pattern the second-tier memory openings. An anisotropic etch can be performed to transfer the pattern of the photopatterned photoresist layer through the second-tier structure (232, 242, 270). In an embodiment, the chemistry of the anisotropic etch process used to etch through the materials of the second-tier alternating stack (232, 242) can be alternated to optimize etching of the alternating material layers in the second-tier alternating stack (232, 242). For example, the anisotropic etch can be a series of reactive ion etches. The patterned photoresist material stack can be removed, for example, by ashing after the anisotropic etch process.

[0202] The top surface of the underlying sacrificial memory opening fill portion 131 can be physically exposed at the bottom of each second-tier memory opening. After the top surface of the sacrificial memory opening fill portion 131 is physically exposed, an etch process can be performed that selectively removes the sacrificial material (e.g., C4F8 / O2 / Ar etch) of the sacrificial memory opening fill portion 131 to the materials of the second-tier alternating stack (232, 242) and the first-tier alternating stack (132, 142).

[0203] Upon removal of the sacrificial memory opening fill portion 131, each vertically abutting pair of second-tier memory openings and first-tier memory openings 149 forms a continuous cavity extending through the first-tier alternating stack (132, 142) and the second-tier alternating stack (232, 242). The continuous cavity is referred to herein as a memory opening 49. The top surface of the planar semiconductor material layer 10 can be physically exposed at the bottom of each memory opening 49.

[0204] Referring to FIG. 10A and 10BA base trench portion 11 can optionally be formed at the bottom of each memory opening 49 by a selective semiconductor deposition process. Selective semiconductor deposition grows semiconductor material only from semiconductor surfaces (i.e., physically exposed surfaces of the planar semiconductor material layer 10) and inhibits semiconductor material growth from insulator surfaces. During the selective semiconductor deposition process, a reactant (such as silane, dichlorosilane, trichlorosilane, disilane, etc.) can be flowed into the deposition chamber concurrently or alternately with an etchant (such as hydrogen chloride). Selective growth can be achieved by setting the etch rate between the deposition rate of semiconductor material on semiconductor surfaces and the deposition rate of semiconductor material on insulator surfaces. In an embodiment, the top surface of the base trench portion 11 can extend through the level of the source select level in which a source select level conductive layer can be subsequently formed.

[0205] A memory stack structure 55 can be formed in the memory opening 49. In the illustrative example, each memory stack structure 55 can include a memory film 50, a vertical semiconductor channel 60, and optionally a dielectric core 62. In an embodiment, each memory film 50 can include an optional blocking dielectric layer 51, a memory material layer 54, and a tunneling dielectric layer 56, as shown in the inset. In an embodiment, each vertical semiconductor channel 60 can include a first semiconductor channel 601 and a second semiconductor channel 602. While the memory openings 49 and support openings for the first tier support pillar structure 171 are shown as being made in separate steps in FIG. 5A and 4A In another embodiment, however, the memory openings 49 and support openings for the first tier support pillar structure 171 are formed in the same step. In this embodiment, the first tier support pillar structure 171 including a dummy memory stack structure without an electrical connection to a bit line can be formed in the support openings at the same time that the memory stack structures 55 are formed in the memory openings 49.

[0206] The blocking dielectric layer 51 includes a blocking dielectric layer material, such as silicon oxide, a dielectric metal oxide (such as aluminum oxide), or a combination thereof. Alternatively, the blocking dielectric layer 51 can be omitted during this process step and instead can be formed by a backside recess, as will be described in more detail below. In an embodiment, the memory material layer 54 can be a charge-trapping material including a dielectric charge-trapping material, which can be, for example, silicon nitride.

[0207] The memory material layer 54 can be formed as a single memory material layer of uniform composition, or can include a stack of multiple memory material layers. If employed, the multiple memory material layers can include multiple spaced-apart floating gate material layers that include a conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or a semiconductive material (e.g., a polycrystalline or amorphous semiconductive material that includes at least one elemental semiconductive element or at least one compound semiconductive material). Alternatively or additionally, the memory material layer 54 can include an insulative charge-trapping material such as one or more silicon nitride portions. Alternatively, the memory material layer 54 can include conductive nanoparticles such as metal nanoparticles that can be, for example, ruthenium nanoparticles. The memory material layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electric charge therein. The thickness of the memory material layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0208] The tunneling dielectric layer 56 includes a dielectric material through which electric charge tunneling can be performed under suitable electric bias conditions. Depending on the operational pattern of the monolithic three-dimensional NAND string memory device to be formed, the electric charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, a dielectric metal oxide such as aluminum oxide and hafnium oxide, a dielectric metal oxynitride, a dielectric metal silicate, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0209] A first semiconductor channel layer can be deposited on the memory films 50 by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The first semiconductor channel layer can have a thickness in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The first semiconductor channel layer and the memory films 50 can be anisotropically etched to remove horizontal portions thereof. The horizontal bottom of each memory film 50 can be removed from the bottom of each memory opening. Each remaining portion of the first semiconductor channel layer constitutes a first semiconductor channel 601. The first semiconductor channel can comprise a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel 601 can comprise amorphous or polysilicon.

[0210] A second semiconductor channel layer can be deposited on the first semiconductor channel 601 (i.e., the remaining vertical portions of the first semiconductor channel layer) and on the top surface of the epitaxial channel portion 11 (or of the substrate semiconductor layer 10 in the absence of the epitaxial channel portion 11). The second semiconductor channel layer comprises a semiconductor material, which can be any semiconductor material usable for the first semiconductor channel layer. The first and second semiconductor channel layers can have a doping of a first conductivity type (i.e., the same conductivity type as the substrate semiconductor layer 10) or can be substantially intrinsic, i.e., have a dopant concentration not exceeding 1.0 x 1010 / cm3. 17 / cm 3 In one embodiment, the second semiconductor channel layer can comprise amorphous or polysilicon. The second semiconductor channel layer can have a thickness in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.

[0211] A dielectric material can be deposited in the cavities surrounded by the second semiconductor channel layer and subsequently recessed below the top surface of the second insulating cap layer 270. Each remaining portion of the dielectric material in the memory openings constitutes a dielectric core 62. A doped semiconductor material having a second conductivity type (which is opposite to the first conductivity type) can be deposited on the dielectric cores 62 and within the cavities in the memory openings to form drain regions 63. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second insulating layer cap layer 270, for example, by chemical-mechanical planarization (CMP) or recess etching to form the drain regions 63. Each remaining portion of the second semiconductor channel layer constitutes a second semiconductor channel 602. The combination of the first semiconductor channel 601 and the second semiconductor channel 602 within the memory openings constitutes a vertical semiconductor channel 60.

[0212] Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60 adjacent to a respective horizontal channel within the planar semiconductor material layer 10. Each memory film 50 can include a blocking dielectric layer 51 contacting sidewalls of the memory opening, a plurality of charge storage regions (embodied as portions of a memory material layer 54 at each level of a sacrificial material layer (142, 242)) on inner sidewalls of the blocking dielectric layer 51, and a tunneling dielectric layer 56 within the plurality of charge storage regions.

[0213] The first tier structure (132, 142, 170, 165, 171), the second tier structure (232, 242, 270, 265, 271), the interlayer dielectric layer 180, and the memory stack structure 55 collectively constitute a memory level assembly. The memory level assembly is formed over the planar semiconductor material layer 10 such that the planar semiconductor material layer 10 includes a horizontal semiconductor channel electrically connected to the vertical semiconductor channel 60 within the memory stack structure 55.

[0214] A first contact level dielectric layer 280 can be formed over the memory level assembly. The first contact level dielectric layer 280 is formed at a contact level through which various contact via structures are subsequently formed to the drain region 63 and various conductive layers that replace the sacrificial material layer (142, 242) in subsequent processing steps.

[0215] Referring to FIG. 11A and 11B A through-memory-level opening 769 can be formed through the memory level assembly in each through-memory-level via region 400. For example, a through-memory-level opening 769 extending through the memory level assembly can be formed in a region of the second staircase region. The through-memory-level opening 769 can be formed, for example, by applying a photoresist layer 767 over the first contact level dielectric layer 280, lithographically patterning the photoresist layer 767 to form openings over each through-memory-level via region 400, and anisotropically etching portions of the first contact level dielectric layer 280 and the memory level assembly underlying the openings in the photoresist layer. In an embodiment, an area of each opening can include a substantial portion (i.e., more than 50%) of a total area of the respective through-memory-level via region 400.

[0216] The through-memory-level opening 769 is formed only in the through-memory-level via region 400 and is not formed in the word line contact via region 200 or in the memory array region 100. The region in the word line contact via region 200 or the memory array region 100 is covered by a mask layer, such as a patterned photoresist layer 767.

[0217] The through-memory-level openings 769 can extend through the entire memory-level assembly, the planar semiconductor material layer 10, the optional planar conductive material layer 6, and into at least one lower-level dielectric material layer 760. In an embodiment, a bottom surface of each through-memory-level opening 769 can be located above a topmost surface of a lower-level metal interconnect structure 780. Alternatively, a topmost surface of the lower-level metal interconnect structure 780 can be physically exposed in the through-memory-level opening 769. In an embodiment, the through-memory-level openings 769 can include substantially vertical sidewalls that extend through the memory-level assembly and the planar semiconductor material layer 10. As used herein, a sidewall is "substantially vertical" if the sidewall is vertical or deviates from a vertical plane by an angle that is less than 5 degrees.

[0218] Referring to FIG. 12A and 12B A dielectric fill material portion 430 is formed within each through-memory-level opening 769, for example by depositing a dielectric fill material and removing excess dielectric fill material from a horizontal plane that includes a top surface of the first contact-level dielectric layer 280. The dielectric fill material portion 430 includes a dielectric material such as an undoped silicate glass (e.g., silicon oxide), a doped silicate glass, or a spin-on glass (SOG). The dielectric fill material can be deposited by a conformal deposition process, a non-conformal deposition process in combination with a reflow material, or a spin-on process. Excess portions of the dielectric fill material can be removed by a recess etch, a chemical mechanical planarization (CMP), or a combination thereof.

[0219] Referring to FIG. 13A and 13B A backside contact trench 79 is subsequently formed through the first contact-level dielectric layer 280 and the memory-level assembly. For example, a photoresist layer can be lithographically patterned on the first contact-level dielectric layer 280 to form elongated openings that extend along the first horizontal direction hd1. A subset of the openings in the patterned photoresist layer falls on a boundary between blocks (B0, B1, B2, B3,...). An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the first contact-level dielectric layer 280 and the memory-level assembly to a top surface of the planar semiconductor material layer 10. The photoresist layer can be subsequently removed, for example by ashing.

[0220] The backside contact trenches 79 extend along the first horizontal direction hd1 and are thus elongated along the first horizontal direction hd1. The backside contact trenches 79 include a first subset of the backside contact trenches 79 that extend through the memory array region 100, abut the word line contact via region 200, and abut the through-memory-level via region 400. The first subset of backside contact trenches 79 are formed through the memory-level assembly, extend laterally along the first horizontal direction hd1, and laterally divide the memory-level assembly (which generally includes at least one alternating stack (132, 142, 232, 242)) into laterally spaced-apart blocks (B0, B1, B2, B3,...).

[0221] Each block (B0, B1, B2, B3,...) includes a respective portion of the memory array region between an adjacent pair of backside contact trenches 79 in the first subset of backside contact trenches 79. Each block (B0, B1, B2, B3,...) can include a respective portion of the memory array region 100, a staircase region on one longitudinal end of the respective portion of the memory array region 100 and including the word line contact via region 200, and another staircase region on the other longitudinal end of the respective portion of the memory array region 100 and including the through-memory-level via region 400. In an embodiment, the placement of the word line contact via region 200 along successive blocks (B0, B1, B2, B3,...) can alternate between two opposite sides. In an illustrative example, each odd block (B1, B3, etc.) has a respective word line contact via region 200 on one side (such as the left side) and each even block (B2, B4, etc.) has a respective word line contact via region 200 on the opposite side (such as the right side). Similarly, the placement of the through-memory-level via region 400 along successive blocks (B0, B1, B2, B3,...) can alternate between two opposite sides such that the through-memory-level via region 400 does not overlap the word line contact via region 200. In an illustrative example, each even block (B0, B2, B4, etc.) has a respective through-memory-level via region 400 on one side (such as the left side) and each odd block (B1, B3, etc.) has a respective word line contact via region 200 on the opposite side (such as the right side).

[0222] In an illustrative example, the plurality of blocks can include a set of three adjacent blocks (e.g., B1, B2, B3) that include, in order, a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The first block B1, the second block B2, and the third block B3 can include, respectively, a first staircase region (such as the region of the word line contact via region 200 on the left side of the block B1 shown in FIG. 1), a second staircase region (such as the region of the through-memory-level via region 400 on the right side of the block B1 shown in FIG. 1), and a third staircase region (such as the region of the word line contact via region 200 on the left side of the block B3 shown in FIG. 1). FIG. 10B FIG. 10B ​The third staircase region is a region of the word line contact via region 200 on the left side of block B3. As described above, adjacent pairs of odd and even blocks (such as Bl and B2) can be periodically repeated along the second horizontal direction.

[0223] Optionally, a second subset of backside contact trenches 79 can be provided within each block (B0, Bl, B2, B3,...). If employed, the second subset of backside contact trenches 79 can extend along the first horizontal direction hd1 and can be positioned to suitably divide each block into a plurality of sub-blocks. The backside contact trenches 79 can include sub-block boundaries within each memory block. The backside contact trenches 79 can be discontinuous to allow a connection region 778 of the same word line to extend between two adjacent sub-blocks in the same block. If a drain contact level shallow trench isolation structure 72 is employed, the drain contact level shallow trench isolation structure 72 can extend along the first horizontal direction hd1 to separate a subset of layers in the upper portion of the second alternating stack (232, 242) within each sub-block or within each block. Various design optimizations can be employed to divide the blocks into sub-blocks or dependent cells.

[0224] Referring to FIG. 14A-14C An etchant can be introduced into the backside contact trenches 79 that selectively etches the material of the first and second sacrificial material layers (142, 242) relative to the material of the first and second insulating layers (132, 232), the first and second insulating cap layers (142, 242), and the material of the outermost layer of the memory film 50, for example employing an isotropic etch process. A first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. A second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed. In one embodiment, the first and second sacrificial material layers (142, 242) can comprise silicon nitride, and the material of the first and second insulating layers (132, 232) can be silicon oxide. In another embodiment, the first and second sacrificial material layers (142, 242) can comprise a semiconductor material, such as germanium or a silicon-germanium alloy, and the material of the first and second insulating layers (132, 232) can be selected from silicon oxide and silicon nitride.

[0225] The isotropic etch process can be a wet etch process employing a wet etch solution or can be a vapor (dry) etch process in which an etchant is introduced in the vapor phase into the backside contact trench 79. For example, if the first and second sacrificial material layers (142, 242) comprise silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed in a wet etch bath comprising phosphoric acid, which etches silicon nitride selectively to silicon oxide, silicon, and various other materials used in the art. In the case where the sacrificial material layers (142, 242) comprise a semiconductor material, a wet etch process (which can employ a wet etchant such as KOH solution) or a dry etch process (which can comprise vapor phase HCl) can be employed.

[0226] Each of the first and second backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than a vertical dimension of the cavity. In other words, each of the first and second backside recesses (143, 243) can have a lateral dimension that is greater than a height of the respective backside recess (143, 243). A plurality of first backside recesses 143 can be formed in a volume from which material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which material of the second sacrificial material layer 242 is removed. Each of the first and second backside recesses (143, 243) can extend substantially parallel to a top surface of the substrate 9. The backside recesses (143, 243) can be vertically bounded by a top surface of an underlying insulating layer (132 or 232) and a bottom surface of an overlying insulating layer (132 or 232). In an embodiment, each of the first and second backside recesses (143, 243) can have a uniform height throughout.

[0227] In an embodiment, after the first and second sacrificial material layers (142, 242) are removed, a sidewall surface of each pedestal channel portion 11 can be physically exposed at each bottommost first backside recess 143. In addition, a top surface of the planar semiconductor material layer 10 can be physically exposed at a bottom of each backside contact trench 79. By oxidizing the physically exposed peripheral portions of the pedestal channel portions 11, an annular dielectric spacer 116 can be formed around each pedestal channel portion 11. In addition, a semiconductor oxide portion 616 can be formed from each physically exposed surface portion of the planar semiconductor material layer 10 at the same time that the annular dielectric spacer 116 is formed.

[0228] Referring to FIG. 15A to 15CA backside blocking dielectric layer (not shown) can optionally be deposited in the backside recesses (143, 243) and the backside contact trenches 79 and on the first contact level dielectric layer 280. The backside blocking dielectric layer can be deposited on the physically exposed portions of the outer surfaces of the memory stack structures 55. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. If employed, the backside blocking dielectric layer can be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer can be in a range from 1 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0229] At least one electrically conductive material can be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the backside contact trenches 79, and over the first contact level dielectric layer 280. The at least one electrically conductive material can comprise at least one metallic material, i.e., an electrically conductive material comprising at least one metallic element.

[0230] A plurality of first electrically conductive layers 146 can be formed in the plurality of first backside recesses 143, a plurality of second electrically conductive layers 246 can be formed in the plurality of second backside recesses 243, and a continuous metallic material layer (not shown) can be formed on the sidewalls of each backside contact trench 79 and over the first contact level dielectric layer 280. Thus, the first and second sacrificial material layers (142, 242) can be replaced with first and second electrically conductive material layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with a first electrically conductive layer 146 and an optional portion of the backside blocking dielectric layer, and each second sacrificial material layer 242 can be replaced with a second electrically conductive layer 246 and an optional portion of the backside blocking dielectric layer. A backside cavity exists in the portion of each backside contact trench 79 that is not filled with the continuous metallic material layer 46L.

[0231] The metallic material can be deposited by a conformal deposition method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The metallic material can be an elemental metal, an intermetallic alloy of at least two elemental metals, an electrically conductive nitride of at least one elemental metal, an electrically conductive metal oxide, an electrically conductive doped semiconductor material, an electrically conductive metal-semiconductor alloy such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metallic materials that can be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In an embodiment, the metallic material can comprise a metal such as tungsten and / or a metal nitride. In an embodiment, the metallic material used to fill the backside recesses (143, 243) can be a combination of a titanium nitride layer and a tungsten fill material. In an embodiment, the metallic material can be deposited by chemical vapor deposition or atomic layer deposition.

[0232] Residual conductive material can be removed from within the backside contact trenches 79. In particular, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each backside contact trench 79 and from above the first contact level dielectric layer 280, e.g., by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess 143 constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess 243 constitutes a second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure.

[0233] A subset of the second conductive layers 246 located at the level of the drain select level shallow trench isolation structures 72 constitutes drain select gate electrodes. A subset of the first conductive layers 146 located at each level of the annular dielectric spacers 116 constitutes source select gate electrodes. A subset of the conductive layers (146, 246) located between the drain select gate electrodes and the source select gate electrodes can function as a combination of control gates and word lines located at the same level. A control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including a memory stack structure 55.

[0234] Each memory stack structure 55 includes a vertical stack of memory elements located at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) can include word lines for the memory elements. The semiconductor devices in the lower periphery device region 700 can include word line switch devices configured to control a bias voltage to a respective word line. The memory level assembly is located above the semiconductor substrate 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and memory stack structures 55 extending vertically through the at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). The at least one alternating stack (132, 146, 232, 246) includes a staircase region including a staircase in which each lower conductive layer (146, 246) extends further along a first horizontal direction hd1 than any upper conductive layer (146, 146) in the memory level assembly.

[0235] Dopant of a second conductivity type, opposite to the first conductivity type of the planar semiconductor material layer 10, can be implanted into the surface portion of the substrate semiconductor layer 10 to form a source region 61 below the bottom surface of each backside contact trench 79. An insulating spacer 74 comprising a dielectric material can be formed at the periphery of each backside contact trench 79, for example by depositing a conformal insulating material such as silicon oxide and subsequent anisotropic etching. The first contact level dielectric layer 280 can be thinned due to parallel etching during the anisotropic etching of the vertical portions of the level portions of the deposited conformal insulating material that are removed.

[0236] A conformal insulating material layer can be deposited in the backside contact trench 79 and can be anisotropically etched to form the insulating spacer 74. The insulating spacer 74 comprises an insulating material such as silicon oxide, silicon nitride and / or a dielectric metal oxide. A cavity extending laterally along the first horizontal direction hd1 is present within each insulating spacer 74.

[0237] A backside contact via structure can be formed in the remaining volume of each backside contact trench 79, for example by depositing at least one electrically conductive material and removing excess portions of the deposited at least one electrically conductive material from above the level of the top surface of the first contact level dielectric layer 280 by a planarization process such as chemical mechanical planarization or recess etching. The backside contact via structure is electrically insulating in all lateral directions and is laterally elongated along the first horizontal direction hd1. Hence, the backside contact via structure is referred to herein as a laterally elongated contact via structure 76. As used herein, a structure is “laterally elongated” if the maximum lateral dimension of the structure along the first horizontal direction is at least 5 times larger than the maximum lateral dimension of the structure along a second horizontal direction perpendicular to the first horizontal direction.

[0238] Optionally, each laterally elongated contact via structure 76 can include a plurality of backside contact via portions, such as a lower backside contact via portion and an upper backside contact via portion. In an illustrative example, the lower backside contact via portion can include a doped semiconductor material, such as doped polysilicon, and can be formed by depositing a layer of the doped semiconductor material to fill the backside contact trench 79 and removing the deposited doped semiconductor material from an upper portion of the backside contact trench 79. The upper backside contact via portion can include at least one metallic material, such as a combination of a TiN liner and a W fill material, and can be formed by depositing the at least one metallic material over the lower backside contact via portion and removing excess portions of the at least one metallic material from a level of a top surface including the first contact level dielectric layer 280. The first contact level dielectric layer 280 can be thinned and removed during a later portion of a planarization process that can employ chemical mechanical planarization (CMP), recess etching, or a combination thereof. Each laterally elongated contact via structure 76 can be formed through the memory level assembly and over a respective source region 61. A top surface of each laterally elongated contact via structure 76 can be above a level of a top surface including the memory stack structure 55.

[0239] The plurality of laterally elongated contact via structures 76 extend laterally along a first horizontal direction hd1 and laterally divide the at least one alternating stack (132, 146, 232, 246) into a plurality of laterally spaced-apart blocks (B0, B1, B2, B3,...), where the plurality of blocks includes a set of three adjacent blocks that in turn include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1, and respectively include a first stepped region (such as a word line contact via region 200 shown in FIG. 13B FIG. 13B a second stepped region (such as a through-memory-level via region 400 shown in FIG. 13B ), and a third stepped region (which can be below the through-memory-level via region 400 in the third block B3 outside of the regions of

[0240] Referring to FIG. 16A-16C A second contact level dielectric layer 282 can optionally be formed on the first contact level dielectric layer 280. The second contact level dielectric layer 282 includes a dielectric material, such as silicon oxide or silicon nitride. A thickness of the second contact level dielectric layer 282 can be in a range from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed.

[0241] ​Various contact via structures can be formed through the contact level dielectric layers (280, 282) on various nodes of the memory devices in the memory hierarchy assembly and on the underlying level metal interconnect structures 780, the dielectric fill material portions 430, and the underlying dielectric material. In particular, the through-memory hierarchy via structures 488 can be formed through the dielectric fill material portions 430 and optionally through the contact level dielectric layers (280, 282) to electrically contact (i.e., electrically couple to) the underlying level metal interconnect structures 780. The word line contact via structures 86 can be formed through the contact level dielectric layers (280, 282) and the second layer backside stepped dielectric material portions 265 in the region 200.

[0242] A subset of the word line contact via structures 86 that contact the second conductive layer 246 extend through the second layer backside stepped dielectric material portions 265 in the region 200 and do not extend through the first layer backside stepped dielectric material portions 165. Another subset of the word line contact via structures 86 that contact the first conductive layer 146 extend through the second layer backside stepped dielectric material portions 265 and through the first layer backside stepped dielectric material portions 165 in the region 200.

[0243] The drain contact via structures 88 that contact the drain region 63 can extend through the contact level dielectric layers (280, 282) and the second insulating cap layer 270 in the device region 100. The source connection via structures 91 can extend through the contact level dielectric layers (280, 282) to provide electrical connections to the laterally-elongated contact via structures 76 in the regions 100, 200, and / or 400.

[0244] Each of the via structures (488, 86, 88, 91) can be formed using a respective set of patterning and fill processes. Alternatively, two or more types of via structures (488, 86, 88, 91) can be formed using a common set of patterning and fill processes, provided that the anisotropic etch processes therein can be controlled to the vertical extent of the cavities at each target height level for each type of cavity being formed simultaneously.

[0245] In an embodiment, the word line contact via structures 86 can be formed through at least one backside stepped dielectric material portion (165, 265) on the first stepped region (such as the word line contact via region 200 shown in FIG. 16B and the third stepped region (such as the other example of the word line contact via region 200 shown in FIG. 16B below the region shown in FIG. 16BThe through-memory layer via region 400 shown (e.g., in even-numbered blocks) forms any contact via structure.

[0246] Each through-memory level via 488 can be formed through a dielectric filler portion 430 (e.g., in an even-numbered block). The through-memory level via 488 can be formed separately from other via structures (86, 88, 91) by patterning the dielectric filler portion 430 and depositing a conductive material (e.g., TiN, W, Al, Ti, Cu, etc.) into openings in the portion 430. Alternatively, the through-memory level via 488 can be formed during the same patterning and deposition steps as one or more other via structures (86, 88, 91) and / or the back-contact via structure 76.

[0247] While odd and even blocks have been described above, it should be noted that regions 400 and 200 do not necessarily alternate sequentially on one side of region 100. For example, a set of two adjacent regions 200 may be separated by a single region 400 or by a set of two adjacent regions 400 on a given side (e.g., left or right) of region 100. On one side (e.g., left) of device region 100, a subset of through-memory-level via structures 488 may be formed in regions 400 of even-numbered step regions after removing these even-numbered step regions, such as the second step region, while odd-numbered step regions, such as the first and third step regions, remain intact. As used herein, a region or structure is “intact” if there is no substantial structural change to it. Each through-memory-level via structure 488 extends vertically from at least a first horizontal plane including the topmost surface of the memory-level component to a second horizontal plane including the bottommost surface of the memory-level component.

[0248] On the contrary, such as FIG. 17E As shown, on the opposite side (e.g., the right side) of region 100, after removing these odd-numbered step regions, such as the first step region, a subset of through-hole structures that penetrate the memory hierarchy can be formed in region 400 of the region of odd-numbered step regions, while even-numbered step regions, such as the second step region, remain intact.

[0249] Therefore, as FIG. 2 to 7 As shown, multiple alternating sacrificial layers (142, 242) and insulating layers (132, 232) are deposited to form at least one alternating stack. Then, multiple rear-side trenches 79 are formed, extending laterally along the first horizontal direction hd1 through the at least one alternating stack, as shown. FIG. 13A-13BThe sacrificial layers (142, 242) are selectively removed from at least one alternating stack of the plurality of backside trenches 79 to form a plurality of backside recesses (143, 243) between the insulating layers (132, 232), as shown. FIG. 14A-14C

[0250] A plurality of conductive layers (146, 246) is formed in the backside recesses through the plurality of backside trenches, an insulating spacer 74 is formed in the plurality of backside trenches 79, and a plurality of laterally elongated contact via structures 76 is formed in the plurality of backside trenches 79 over the insulating spacer 74, as shown. FIG. 15A-15C

[0251] The plurality of conductive layers is formed in the backside recesses through the plurality of backside trenches after the step of removing the second staircase region and forming the dielectric fill material portion 430, as shown. FIG. 11A-12B The step of removing the second staircase region includes removing the insulating layers and the sacrificial layers in the second staircase region to form the through-memory-level opening 769. The conductive layers 46 are not formed in the dielectric fill material portion 430 located in the through-memory-level opening 769.

[0252] Referring to FIG. 17A-17F A line-level dielectric layer 110 can be formed on the contact-level dielectric layers (280, 282). Various metal interconnect structures (108, 103, 101) can be formed in the line-level dielectric layer 110. The metal interconnect structures (108, 103, 101) can include an upper-level metal interconnect structure 108 electrically coupled to (e.g., formed on or in physical contact with) a respective pair of word line contact via structures 86 and through-memory-level via structures 488, a bit line 103 extending along a second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and a source connection line structure 101 contacting a source connection via structure 91 to provide a conductive path for biasing the source region 61 through the laterally elongated contact via structures 76. Drain side select gate electrode contact via structures 87 are located in the region 200 adjacent to the device region 100. There can be two or more staircases in each sub-block between adjacent backside contact trenches 79 in the region 200, exposing two or more word lines vertically separated from adjacent device levels. In this case, two or more word line contact via structures 86 (e.g., two structures 86 as shown in FIG. 17E and 17F are positioned in parallel to each other in the same sub-block to contact the respective vertically separated word lines.

[0253] An exemplary layout for the upper-level metal interconnect structure 108 is shown in FIG. 17B and 17D . FIG. 17D is a top-down view,​​FIG. 17B is a horizontal cross-sectional view in which the shape of the upper level metal interconnect structures 108 and the bit lines 103 are shown in dashed lines. The upper level metal interconnect structures 108 can extend across adjacent blocks, i.e., across the respective laterally elongated contact via structures 76. For example, some of the upper level metal interconnect structures 108 can extend through the second block as well as one of the first and third blocks. FIG. 17E and 17F shows another exemplary layout of the upper level metal interconnect structures. In this embodiment, some of the upper level metal interconnect structures 108 are electrically coupled to the lower level metal interconnect structures 780 through the through-memory-level via structures 488 located in the region 400 and to the word lines 46 through the word line contact via structures 86 in the region 200. Other upper level metal interconnect structures 208 are electrically coupled to the word lines 46 through the word line contact via structures 86 in the region 200 but not to the lower level metal interconnect structures 780 through the through-memory-level via structures 488 located in the region 400. These upper level metal interconnect structures 208 can be electrically coupled to driver circuit devices at locations other than the region 400. The bit lines 103 are formed on the memory level assembly and are electrically coupled to the nodes (e.g., drain regions 63) of the memory stack structures 55 through the drain contact via structures 88. As used herein, a first element is electrically coupled to a second element if there is any one of an electrical short (i.e., ohmic contact), electronic tunneling communication, or a resistive (i.e., Schottky) contact between the first element and the second element. In this case, the upper level metal interconnect structures 108 can be electrically shorted to the respective word lines through the word line contact via structures 86, implemented as the electrically conductive layers 46.

[0254] The first exemplary structure includes a memory hierarchy assembly located above a semiconductor substrate 9 and including at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through the at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). A plurality of laterally elongated contact via structures 76 vertically extend through the memory hierarchy assembly, laterally extend along a first horizontal direction hd1, and laterally divide the at least one alternating stack (132, 146, 232, 246) into a plurality of laterally spaced-apart blocks (B0, B1, B2, B3...). The plurality of blocks (B0, B1, B2, B3...) includes a set of at least three adjacent blocks that in turn include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The through-memory-level via region 400 is located on a longitudinal end of the second block B2 and between a staircase region of the first block B1 and a staircase region of the third block B3.

[0255] Each staircase region of the first and third blocks (B1, B3) includes a staircase in which each lower conductive layer (146 or 246) extends further along the first horizontal direction hd1 than any upper conductive layer (146 or 246) in the memory hierarchy assembly. The through-memory-level via region 400 includes a through-memory-level via structure 488 that vertically extends at least from a first horizontal plane that includes a topmost surface of the memory hierarchy assembly to a second horizontal plane that includes a bottommost surface of the memory hierarchy assembly.

[0256] At least one lower level dielectric layer 760 overlies the semiconductor substrate 9. A planar semiconductor material layer 10 overlies the at least one lower level dielectric layer 760 and includes a horizontal semiconductor channel 58 electrically connected to a vertical semiconductor channel 60 within the memory stack structure 55. A semiconductor device 710 (e.g., a CMOS transistor of a word line driver circuit) can be located on the semiconductor substrate 9. A lower level metal interconnect structure 780 can be electrically shorted to a node (e.g., a source, a drain, and a drain / gate electrode) of the semiconductor device 710 and embedded in the at least one lower level dielectric layer 760 that overlies the planar semiconductor material layer 10. The through-memory-level via structure 488 contacts the lower level metal interconnect structure 780.

[0257] The upper-level metal interconnect structures 108 overlie the memory-level assemblies and are embedded in at least one upper-level dielectric layer 110. At least a portion of the upper-level metal interconnect structures 108 are electrically coupled to respective lower-level metal interconnect structures 780 through respective through-memory-level via structures 488 located in the region 400, respectively, and are electrically coupled to respective word lines 46 through respective word line contact via structures 86 in the region 200. Bit lines 103 also overlie the memory-level assemblies and are electrically coupled to nodes of the memory stack structures 55 (through the drain regions 63) and are embedded in at least one upper-level dielectric layer 110. Each memory stack structure 55 includes a vertical stack of memory elements located at each level conductive layer (146, 246). The conductive layers (146, 246) include word lines for the memory elements. In an embodiment, the semiconductor device can include word line switch devices configured to control a bias voltage to respective word lines.

[0258] In an embodiment, each through-memory-level via structure 488 can contact a respective lower-level lower-level metal interconnect structure 780. In an embodiment, a subset of the semiconductor devices 710 on the semiconductor substrate 9 can be located below a region of the planar semiconductor material layer 10, i.e., have an area overlap with the upper planar semiconductor material layer 10.

[0259] In an embodiment, a dielectric fill material portion 430 can be located within the through-memory-level via region 400. The dielectric fill material portion 430 can laterally surround the through-memory-level via structure 488 and can vertically extend from a first level that includes a topmost surface of the memory-level assembly to a second level that is below a bottommost surface of the memory-level assembly.

[0260] The planar semiconductor material layer 10 is located below the memory-level assembly and can include a horizontal semiconductor channel 58 that is electrically connected to the vertical semiconductor channel 60 within the memory stack structure 55. The second level is below a bottom surface of the planar semiconductor material layer. In an embodiment, the dielectric fill material portion 430 can include a substantially vertical sidewall that extends through the memory-level assembly and the planar semiconductor material layer 10.

[0261] In an embodiment, the plurality of laterally elongated contact via structures 76 can extend vertically through the memory hierarchy assembly, extend laterally along the first horizontal direction hd1, and laterally divide the memory hierarchy assembly into a plurality of laterally spaced-apart blocks (B0, B1, B2, B3,...). The plurality of blocks may, for example, include a set of three adjacent blocks that in turn include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The dielectric fill material portion 430 can be located on a longitudinal end of the second block B2 and between the stepped regions of the first block B1 and the third block B3. Each stepped region of the first and third blocks (B1, B3) includes a step in which each underlying conductive layer (146 or 246) extends further along the first horizontal direction hd1 than any overlying conductive layer (146 or 246) within the memory hierarchy assembly.

[0262] Each memory stack structure 55 can include a memory film 50 and a vertical semiconductor channel 60 that adjoins a respective horizontal channel 58 within the planar semiconductor material layer 10 underneath the memory hierarchy assembly. The word line contact via structures 86 can extend through the backside stepped dielectric material portions (265, 165) of the stepped regions of the first and third blocks (B1, B3) in the coverage region 200 and can contact respective portions of the conductive layers (146, 246) in the first and third blocks (B1, B3). The upper level metal interconnect structure 108 can electrically short respective pairs of the word line contact via structures 86 and the through-memory hierarchy via structures 488, can cover the memory hierarchy assembly, and can span the second block B2 in the region 400 and one of the first and third blocks (B1, B3) in the region 200.

[0263] Referring to FIG. 18 , a second exemplary structure according to a second embodiment of the present disclosure is shown. Specifically, in this second embodiment, the word line switch devices 710 for the semiconductor devices of the second exemplary structure are located in the region 400 instead of under the region 100 as in the first embodiment. Otherwise, the steps and structures described above with respect to the first embodiment can be used in the second embodiment. The second exemplary structure can be derived from the first exemplary structure of FIG. 1A and 1B by changing the pattern of the semiconductor devices and the lower level metal interconnect structure 780.

[0264] In the illustrative example, word line switching device 710 may be a field-effect transistor in a CMOS configuration, formed in a through-memory via region 400. Alternatively, a subset of word line switching devices may be formed outside the region through-memory via region 400, such as below a region of memory array region 100 or below a region of word line contact via region 200. The active region 730 of the word line switching device (…) FIG. 1A The source region 742 and drain region 744 shown can be laterally surrounded by the shallow trench isolation structure 720.

[0265] The lower-level metal interconnect structure 780 may be embedded in at least one lower-level dielectric layer 760 and may be electrically shorted to the node of a word line switching device located above or on the semiconductor substrate 9. The lower-level metal interconnect structure 780 may be configured such that the lower-level topmost metal structure 788 provides suitable bonding pads for subsequent through-memory-level via structures formed in each region of the through-memory-level via region 400.

[0266] Reference FIG. 19A-19B ,implement FIG. 2 to FIG. 17A The -17D processing steps form a planar semiconductor material layer 10, memory-level components, various contact via structures (88, 86, 91, 488), a line-level dielectric layer 110, and metal interconnect structures (108, 101), as well as bit lines 103 embedded in the line-level dielectric layer 110.

[0267] In one embodiment, the field-effect transistor of the word line switching device can be as follows: FIG. 19B The CMOS-configured pairings shown share a common power node, which can be the source or drain region 730 connected to the power metal interconnect structure 7802. The gate structure 750 can span the channel region of the field-effect transistor. A switch output node metal interconnect structure can be connected to the output node of each field-effect transistor, which can be the drain or source region of the corresponding field-effect transistor. The power metal interconnect structure 7802 and the switch output node metal interconnect structure are subsets of the lower-level metal interconnect structure 780. The word line switching devices can be arranged as a periodic array that repeats periodically along the second horizontal direction hd2 at the width of two adjacent blocks (e.g., the width of a combination of the first block B1 and the second block B2).

[0268] Specifically, such as FIG. 19AAs shown, a planar semiconductor material layer 10 can be formed over the at least one lower level dielectric layer 760. A memory level assembly can be formed over the planar semiconductor material layer 10, and the planar semiconductor material layer 10 can include horizontal semiconductor channels 58 electrically connected to vertical semiconductor channels 60 within memory stack structures 55. A memory level assembly can be formed over the semiconductor substrate 9 and the planar semiconductor layer 10. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and memory stack structures 55 extending vertically through the at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). Each memory stack structure 55 includes a vertical stack of memory elements at each level of the conductive layers (146, 246). The conductive layers (146, 246) include word lines for the memory elements.

[0269] The at least one alternating stack (132, 146, 232, 246) includes a staircase region including a staircase in which each lower conductive layer (146, 246) extends further along a first horizontal direction than any upper conductive layer (146, 146) in the memory level assembly. At least one back-staircase dielectric material portion (165, 265) can be formed on the staircase region on the at least one alternating stack (132, 146, 232, 246).

[0270] A plurality of laterally elongated contact via structures 76 is formed through the memory level assembly. The plurality of laterally elongated contact via structures 76 extends laterally along a first horizontal direction hd1 and laterally divides the at least one alternating stack (132, 146, 232, 246) into a plurality of laterally spaced-apart blocks (Bl, B2, B3, B4...). The plurality of blocks (Bl, B2, B3, B4...) includes a set of three adjacent blocks including, in order, a first block Bl, a second block B2, a third block B3, and a fourth block B4 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and respectively including a first staircase region (such as a word line contact via region 200 containing the remaining staircase of the third and fourth blocks B3 and B4) and a second staircase region (from which the staircase is removed, such as a through-memory-level via region 400 of the first and second blocks Bl and B2) and a third staircase region (such as a word line contact via region 200 containing the remaining third staircase of additional blocks such as BO (not shown for clarity)).

[0271] A through-memory-level opening 769 extending through the memory-level assembly can be formed in the area of the removed stepped region, such as the second stepped region. The through-memory-level opening 769 can extend into the at least one lower-level dielectric material layer 760. The through-memory-level opening 769 can include substantially vertical sidewalls extending through the memory-level assembly and the planar semiconductor material layer 10. A dielectric fill material portion 430 can be formed in the through-memory-level opening 769. These steps are then followed by forming backside trenches 79, replacing the sacrificial material layers (142, 242) with conductive layers (146, 246) and forming insulating spacers 74 and contact via structures (e.g., source electrodes or local interconnects) 76 in the backside trenches 79, as described above.

[0272] The word line contact via structures 86 can be formed on or over portions of the conductive layers (146, 246) in the remaining stepped regions, such as the first and third stepped regions, without concurrently forming any contact via structures over the removed stepped region, such as the second stepped region. The word line contact via structures 86 can be formed over the remaining stepped regions, such as the first and third stepped regions, through the at least one backside stepped dielectric material portion (165, 265) and directly on respective portions of the conductive layers (146, 246) in the first and third blocks (Bl, B3) without concurrently forming any contact via structures over the removed stepped region, such as the second stepped region B2.

[0273] As described in previous embodiments, each through-memory-level via structure 488 can be formed through the dielectric fill material portion 430. Each through-memory-level via structure 488 extends vertically at least from a first level including a topmost surface of the memory-level assembly to a second level including a bottommost surface of the memory-level assembly.

[0274] The nodes of the word line switching devices can be electrically connected to portions of the conductive layers (146, 246) in the remaining stepped regions, such as the first and third stepped regions, that employ the through-memory-level via structures 488 formed in the area of the removed stepped region, such as the second stepped region. For example, the upper-level metal interconnect structures 108 can be formed on the through-memory-level via structures 488 and over the memory-level assembly and on the word line contact via structures 86. For example, the upper-level metal interconnect structures 108 can be formed on respective pairs of the word line contact via structures 86 and the through-memory-level via structures 488 formed over the memory-level assembly. At least one upper-level metal interconnect structure 108 can extend across the second block B2 and the third block B3. In an embodiment, each upper-level metal interconnect structure 108 can span a respective laterally elongated contact via structure 76 located between the first block Bl and the third block B3.

[0275] Referring to FIG. 20 , a variation of the second exemplary structure is shown that can be derived from the second exemplary structure of FIG. 18 by forming an optional dielectric spacer 52 and a subset of the first-tier alternating stack (132, 142) at the same level as the word line switch devices, the at least one lower-tier dielectric layer 760, and the lower-tier metal interconnect structure 780. For example, the word line switch devices and the lower-tier metal interconnect structure 780 can be formed in the through-memory-stack via region 400 and outside the area of the memory array region 100.

[0276] In an embodiment, the dielectric spacer 52 and the subset of the first-tier alternating stack (132, 142) can be formed on the substrate 9. Subsequently, portions of the subset of the first-tier alternating stack (132, 142) can be removed from outside the memory array region 100, and a staircase region with steps of the subset of the first-tier alternating stack (132, 142) can be formed in the peripheral portion of the memory array region 100 adjoining the through-memory-stack via region 400 or the word line contact via region 200. The lower-tier backside dielectric material portion 765 can be formed over each staircase region and removed in the region 700. Then, the semiconductor devices 710, the at least one lower-tier dielectric layer 760, and the lower-tier metal interconnect structure 780 are formed on the substrate 9 in the region 700. The lower-tier backside dielectric material portion 765 can have a top surface that is substantially at the same level as the top surface of the deposited subset of the first-tier alternating stack and the top surface of the at least one lower-tier dielectric layer 760.

[0277] Referring to FIG. 21 , a complementary subset of the first-tier alternating stack (132, 142) can be formed over the deposited subset of the first-tier alternating stack (132, 142). The processing steps of FIG. 3 , FIG. 4A and 4B , FIG. 5A and 5B as well as FIG. 6 can be performed to form a first-tier structure. Referring to FIG. 22 , the processing steps of FIG. 7 can be performed to FIG. 10A and 10B to form a second-tier structure. In this embodiment, the horizontal channels are within the substrate 9 underneath the memory-level assembly, as layer 10 can be omitted in this embodiment. Alternatively, layer 10 is formed directly on the substrate 9 outside the region 10.

[0278] Referring to FIG. 23 , the processing steps of FIG. 11A and 11B can be performed to FIG. 17A-17Dprocessing steps to electrically connect the node of the word line switching device to portions of the conductive layers (146, 246) in the remaining stepped regions, such as the first and third stepped regions, of the through-memory-level via structure 488 in regions employing the removed stepped region, such as the second stepped region.

[0279] Referring FIG. 24A and 24B The third exemplary structure according to the third embodiment of the disclosure includes deep trench grooves that separate a first portion of the alternating stack of insulating layers and sacrificial insulating material layers from a second portion of the alternating stack of insulating stacks in which the sacrificial insulating material layers are replaced with conductive word line layers. The third exemplary structure can be derived from the first exemplary structure, the second exemplary structure, or variations thereof, by performing processing steps up to the formation of the first layer of alternating stacks. As in the first and second embodiments, the underlying level metal interconnect structure 780 can be electrically shorted to the nodes of the semiconductor device, and can be embedded in at least one underlying level dielectric layer 760 formed on the semiconductor substrate 9. The layout of the pattern of the first layer of support pillar structures 171 can optionally be changed to optionally remove the first layer of support pillar structures 171 from a central portion of each through-memory-stack via region 400. The processing steps of FIG. 5A 、 5B and 6 can be performed, with variations, to form the pattern of the first layer of memory openings 149. The optional planar conductive material layer 6 and the planar semiconductor material layer 10 can be patterned to form openings 151 that extend through these layers to the underlying insulating layer 760. The openings 151 are located under the regions 400, and can be filled with another insulating material layer (e.g., silicon oxide or doped silicate glass) 760.

[0280] In particular, concurrently with the formation of the first layer of memory openings 149, the first layer of deep trench grooves can be formed in each through-memory-stack via region 400. For example, a photoresist layer can be applied after the formation of the first insulating cap layer 170 or the interlayer dielectric layer 180, and can be lithographically patterned to form a patterned photoresist layer that includes the pattern of memory openings and the pattern of the first layer of deep trench grooves to be formed through the first layer of alternating stacks (132, 142). Anisotropic etching is performed through the first layer of alternating stacks (132, 142) to form the first layer of memory openings 149 and the first layer of deep trench grooves.

[0281] Sacrificial memory opening fill portion 131 may be formed in the first layer memory opening 149, and sacrificial deep trench fill portion 141 may be formed in the first layer deep trench. For example, a sacrificial filler material layer is deposited in the first layer memory opening 149 and the first layer deep trench, and excess portions of the sacrificial filler material layer may be removed from above the top surface of the interlayer stacked dielectric layer 180. The sacrificial filler material may include the same material as in the first and second embodiments.

[0282] Each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial memory opening fill portion 131. Each remaining portion of the sacrificial material in the first layer deep trench constitutes a sacrificial deep trench fill portion 141. The top surfaces of the sacrificial memory opening fill portion 131 and the sacrificial deep trench fill portion 141 may be coplanar with the top surface of the first insulating capping layer 170. The sacrificial memory opening fill portion 131 may or may not include cavities therein.

[0283] Reference FIG. 25A and 25B It can be executed FIG. 7 , 8A The processing steps 8B, 9A, and 9B modify the pattern used to form the second layer opening. Specifically, the pattern of the first layer deep trench can be added to the pattern of the second layer memory opening. After transferring the pattern in the photoresist layer through anisotropic etching of the second layer alternating stack (232, 242), the second layer deep trench is formed above the first layer deep trench. The pattern of the second layer deep trench can be the same as the pattern of the first layer deep trench. The sacrificial memory opening filling portion 131 and the sacrificial deep trench filling portion 141 are then removed by selective etching or ashing (if portions 131 and 141 contain carbon-based material). Each stack of the first layer deep trench and the second layer deep trench constitutes a deep trench 449. Memory openings 49 extending through at least one alternating stack (132, 142, 232, 242) can be formed simultaneously with the formation of the deep trench 449.

[0284] In an embodiment, each deep trench 449 can have a U-shaped horizontal cross-sectional shape, such that the two open ends of the U-shape include vertical sidewalls that are composed of surfaces of at least one backside stepped dielectric material portion (165, 265). In this case, the two sides of each deep trench 449 can extend along a first horizontal direction hd1 that is parallel to a longitudinal direction of the backside contact trench 79, can abut each other through a connecting portion of the deep trench 449. The two sides extend parallel to a second longitudinal direction hd2 at a proximal side of the deep trench 449, and can extend along the first horizontal direction beyond an area of a bottommost layer of the first alternating stack (132, 142) at a distal side of the deep trench 449. As used herein, the “proximal” side of the deep trench 449 refers to a side that is close to the memory array region 100, and the “distal” side of the deep trench 449 refers to a side that is distal from the memory array region 100.

[0285] In another embodiment, each deep trench 449 can have a closed shape (e.g., polygonal, circular, elliptical, irregular, etc.) such that a region of the memory hierarchical assembly is located inside each deep trench 449, and a complementary region of the memory hierarchical assembly is located outside each deep trench 449. In this case, the deep trench 449 separates the inside of the deep trench 449 from the outside of the deep trench 449, where the closed shape corresponds to the region of the deep trench 449. As used herein, a closed shape is a shape that has a closed outer perimeter and an opening within the closed outer perimeter defined by a closed inner perimeter. The opening in the deep trench 449 is located over the opening 151 in the layer 10, and can have the same or similar shape and / or dimensions as the opening 151.

[0286] The deep trench 449 defines a respective region of the through-memory-level via region 400, and extends through at least one alternating stack (132, 142, 232, 242). A portion of the at least one alternating stack (132, 142, 232, 242) is present within the through-memory-level via region 400. Specifically, a portion of the at least one alternating stack (132, 142, 232, 242) that includes a layer of insulative sacrificial material (142, 242) can laterally surround within a set of inner sidewalls of the deep trench 449 in the case where the deep trench 449 has a closed shape, or within a combination of the set of inner sidewalls of the deep trench 449 and a vertical surface of a plane that contains a pair of vertical edges of the deep trench 449 located at a distal end of the deep trench 449 in the case where the deep trench 449 is U-shaped.

[0287] Referring to FIG. 26A and 26B may be performed FIG. 10A and 10Ba subset of the processing steps of FIG. 1 to form the optional base channel portion 11 and the memory stack structure 55. The drain region 63 can be formed on top of each vertical semiconductor channel 60.

[0288] In an embodiment, all surfaces of the deep trench 449 can be dielectric surfaces. The base channel portion 11 is formed using a selective semiconductor deposition process such that the base channel portion 11 grows only from the physically exposed semiconductor surfaces of the planar semiconductor material layer 10 at the bottom of each memory opening 49 without semiconductor material deposition in the deep trench 449.

[0289] The pseudo memory stack structure 155 is formed within each deep trench 449 at the same time as the memory stack structure 55. For example, the memory film 50 can be formed within each memory opening 49 at the same time as the insulative liner 50 is formed in each deep trench 449 by depositing and anisotropically etching a stack of layers including at least one dielectric material layer (51, 54, 56). Subsequently, a conformal semiconductor material layer can be deposited on the memory film 50 and the insulative liner 50, and portions of the conformal semiconductor material layer can be removed from above the at least one alternating stack (132, 142, 232, 242) by employing a planarization process. Each remaining portion of the conformal semiconductor material layer constitutes a vertical semiconductor channel 60, which can be an active channel of a vertical field effect transistor if present within the memory stack structure 55 or a semiconductor fill material portion 60 if present within the pseudo memory stack structure 155 within the deep trench 449.

[0290] Each pseudo memory stack structure 155 can have the same set of elements as the memory stack structure 55. A set of insulative films formed in the deep trench 449 and having the same material stack as the memory film 50 is referred to herein as the insulative liner 50. A pseudo drain region 463 can be formed on top of each pseudo memory stack structure 155. The pseudo memory stack structure 155 can be electrically isolated from all underlying elements and laterally surrounding elements. For example, each pseudo memory stack structure 155 can contact a top surface of at least one underlying level dielectric layer 760, such as at least one underlying level interconnect dielectric layer 768 that fills the opening 151, as well as sidewalls of the at least one alternating stack (132, 142, 232, 242), the interlayer dielectric layer 180, the first insulative cap layer 170, and the second insulative cap layer 270.

[0291] Each combination of the pseudo memory stack structure 155 and the pseudo drain region 463 constitutes an insulative deep trench structure (155, 463) that fills the corresponding deep trench 449. Each region of the through-memory-level via region 400 includes a region defined by a closed inner perimeter of the corresponding insulative deep trench structure (155, 463).

[0292] Reference FIG. 27A and 27B It can be executed FIG. 13A and 13B A complementary subset of the processing steps to form the first contact level dielectric layer 280 and the rear contact trench 79.

[0293] Reference FIG. 28A and 28B It can be executed FIG. 14B , 14C The processing steps 15B and 15C involve replacing the sacrificial material layers (142, 242) with conductive layers (246, 246). In one embodiment, the sacrificial material layers (142, 242) may include dielectric spacer layers, i.e., dielectric material layers perpendicularly spaced from the insulating layers (132, 232). The insulating deep trench structures (155, 463), either alone or in combination with the backward stepped dielectric material portions (165, 265), prevent etchant from propagating laterally into the region laterally surrounded by the insulating deep trench structures (155, 463), such that no rear recesses (143, 243) are formed within the region 400 surrounded by the deep trench structures (155, 463). A portion of the dielectric spacer layer (i.e., sacrificial material layers (142, 242)) located outside the deep trench structure (i.e., outside the through-hole region 400 of the memory layer) is replaced by a conductive layer (146, 246), while at least one alternating stacked portion (132, 142, 232, 242) in each deep trench 449 remains intact. The conductive layer (146, 246) constitutes the word lines for the memory stack structure 55, which are formed outside the deep trench structure (i.e., outside region 400) but not inside the deep trench structure (i.e., inside region 400).

[0294] Subsequently, a conformal insulating material layer is deposited and anisotropically etched within each rear contact trench 79 to form an insulating spacer 74. Laterally extending contact via structures 76 are present within each rear contact trench 79. A plurality of laterally elongated contact via structures 76 extending along a first horizontal direction hd1 laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks (B1, B2, B3...). The plurality of blocks (B1, B2, B3...) may include a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0295] When the deep trench 449 is U-shaped, the remaining portion of the backward stepped dielectric material portion (265 or 165) can be in the portion of the conductive layer (146, 246) in the first stepped region (e.g.) FIG. 28Bthe illustrated word line contact via region 200) in the first block B1 in the first tier 100 and the remaining portion of the dielectric spacer layer (i.e., the sacrificial material layer (142, 242)) in the second tier 200. FIG. 28B continuously extends over the through-memory-level via region 400) in the second block B2 in the second tier 200.

[0296] Referring to FIG. 29A-29C A through-memory-level via structure 488 can be formed in each through-memory-level via region 400. For example, a via cavity can be formed that extends through the remaining portion of the second tier alternating stack of the second contact interlayer dielectric layer 280, the second insulative layer 232, and the second sacrificial layer 242, the remaining portion of the first tier alternating stack of the first insulative layer 132 and the first sacrificial layer 142, and the upper portion of the at least one lower tier dielectric layer 760. In general, the through-memory-level via structure 488 can extend vertically from a first level that includes a topmost surface of the remaining portion of the at least one alternating stack (132, 142, 232, 242) and a bottommost surface of the at least one alternating stack (132, 142, 232, 242). The same processing steps as FIG. 16A-16C The same processing steps as

[0297] Referring to FIG. 30 A line tier dielectric layer 110 can be formed over the contact tier dielectric layer (280, 282). Using the same processing steps as FIG. 17A-17D Various metal interconnect structures (108, 101) and bit lines 103 can be formed in the line tier dielectric layer 110. As in the first and second embodiments, the bit lines 103 can overlie the memory tier components, can be electrically coupled to nodes (e.g., drain regions 63) of the memory stack structures 55, and can be embedded in at least one upper tier dielectric layer such as the line tier dielectric layer 110. The through-memory-level via structures 488 can contact respective pairs of upper tier metal interconnect structures 108 and lower tier metal interconnect structures 780. The upper tier metal interconnect structures 108 interconnect respective pairs of via structures (86, 488) and (87, 488).

[0298] Referring to FIG. 31A and 31BA variation of the third exemplary structure can be derived from the third exemplary structure by forming the deep trench 149 and the insulative deep trench structure 466 in a separate step from forming the respective memory openings 49 and memory stack structures 55. By forming the deep trench prior to forming the second tier memory openings, a variation of the third exemplary structure can be derived from FIG. 8A and 8B The method of fabricating the third exemplary structure can be derived from the method steps shown in FIG. 8A and 8B A photoresist layer can be applied over the first exemplary structure of FIG. 25A and 25B and can be lithographically patterned to form openings corresponding to the pattern of deep trenches shown in

[0299] The deep trenches can then be filled with a dielectric material such as silicon oxide to form deep trench isolation structures, which are deep trench fill structures 466 that fill the deep trenches. In an embodiment, the deep trench fill structures 466 can consist essentially of a dielectric material. In an embodiment, the area throughout the memory level via region 400 can include a closed inner perimeter of the insulative deep trench structures 466.

[0300] Referring to FIG. 32A and 32B The steps of FIG. 9A to 15C can be performed in sequence to replace the sacrificial material layers (142, 242) with conductive layers (246, 246) and to form the insulative spacers 74 and the laterally extending contact via structures 76. Subsequently, the processing steps of FIG. 29A-29C can be employed to form a through-memory-level via structure 488 in each memory level via region 400. Various additional via structures (86, 87, 88) can be formed using the same processing steps as the processing steps of FIG. 16A-16C Subsequently, a line-level dielectric layer 110 can be formed over the contact-level dielectric layers (280, 282) and various interconnect structures (108, 101) and bit lines 103 can be formed in the line-level dielectric layer 110 using the processing steps of FIG. 17A-17D

[0301] FIG. 30 The third exemplary structure shown in FIG. 32A and 32B ​Variations of the foregoing include a semiconductor structure that includes a memory level assembly that is located above a semiconductor substrate 9 and includes at least one first alternating stack of electrically conductive tiers (146, 246) and first portions of insulative tiers (132, 232), and further includes memory stack structures 55 that vertically extend through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The electrically conductive tiers (146, 246) constitute word lines for the memory stack structures 55. The semiconductor structure further includes an insulative deep trench structure {466 or (155, 463)} that vertically extends through the memory level assembly and defines a region of a through-memory-level via region 400 that is laterally spaced apart from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure also includes at least one second alternating stack that is located in the through-memory-level via region 400. The at least one second alternating stack includes alternating tiers of dielectric spacer tiers (142, 242) and second portions of insulative tiers (132, 232), and each dielectric spacer tier (142, 242) is located at the same level as a respective electrically conductive tier (146, 246). The semiconductor structure further includes a through-memory-level via structure 488 that is located within the through-memory-level via region 400 and vertically extends from a first horizontal plane that includes a topmost surface of the memory level assembly and a bottommost surface of the memory level assembly and includes an electrically conductive material.

[0302] In an embodiment, the region of the through-memory-level via region 400 includes a closed inner periphery of the insulative deep trench structure {466 or (155, 463)}. In this case, an entire set of outer sidewalls of the at least one second alternating stack (132, 142, 232, 242) can contact the inner sidewalls of the insulative deep trench structure {466 or (155, 463)}.

[0303] In an embodiment, a plurality of laterally elongated contact via structures 76 can extend along a first horizontal direction hd1 and can laterally divide the memory level assembly into a plurality of laterally spaced apart blocks (B1, B2, B3...). In an embodiment, the plurality of blocks (B1, B2, B3...) can include a set of three adjacent blocks that in turn include a first block B1, a second block B2, and a third block B3 that are arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The insulative deep trench structure {466 or (155, 463)} can be located on a longitudinal end of the second block B2 and between a staircase region of the first block B1 and a staircase region of the third block B3. Each staircase region of the first and third blocks (B1, B3) can include a staircase in which each lower electrically conductive tier (146, 246) extends farther along the first horizontal direction hd1 than any upper electrically conductive tier (146, 146) within the memory level assembly.

[0304] In an embodiment, the stepped bottom surface of the back stepped dielectric material portion (265 or 165) can contact the stepped top surface of the first and third stepped regions in the respective first and third blocks (Bl, B3). In an embodiment, an additional back stepped dielectric material portion (265 or 165) can be present within the interior sidewall of the insulative deep trench structure {466 or (155, 463)}. In this case, the stepped bottom surface of the additional back stepped dielectric material portion can comprise the same material as the back stepped dielectric material portion (165, 265) and can be laterally spaced apart from the back stepped dielectric material portion by the insulative deep trench structure {466 or (155, 463)} and can contact the stepped top surface of at least one second alternating stack (132, 142, 232, 242).

[0305] In an embodiment, the insulative deep trench structure {466 or (155, 463)} can be U-shaped. In this case, the additional stepped bottom surface of the back stepped dielectric material portion (165 or 265) can contact the stepped top surface of at least one second alternating stack (132, 142, 232, 242).

[0306] In an embodiment, each of the plurality of laterally elongated contact via structures 76 can be laterally surrounded by an insulative spacer 74. The insulative deep trench structure (155, 463) can comprise an insulative liner 50 comprising the same material as the memory film 50 in the memory stack structure 55.

[0307] In an embodiment, the plurality of laterally elongated contact via structures 76 can comprise a source line contacting a respective underlying source region 61, which contacts a respective horizontal semiconductor channel 58.

[0308] In an embodiment, the insulative trench structure (155, 463) can comprise a layer stack comprising the same set of layers as included in each memory stack structure 55, namely the memory film 50 and the vertical semiconductor channel 60.

[0309] In an embodiment, the insulative trench structure 466 can consist essentially of a dielectric fill material portion.

[0310] The semiconductor structure can further comprise a semiconductor device located on the semiconductor substrate 9, a lower level metal interconnect structure 780 electrically shorted to a node of the semiconductor device and embedded in at least one lower level dielectric layer 760 covering the semiconductor substrate 9, and a planar semiconductor material layer 10 covering the at least one lower level dielectric layer 760 and comprising a horizontal semiconductor channel 58 connected to a vertical semiconductor channel 60 within the memory stack structure 55.

[0311] In one embodiment, the semiconductor structure can further include an upper level metal interconnect structure 108 overlying the memory level assembly, which is electrically coupled to nodes of the memory stack structures 55 and embedded in at least one upper level dielectric layer 110. The through-memory-level via structures 488 can vertically extend through the memory level assembly and can contact respective pairs of the upper level metal interconnect structures 108 and the lower level metal interconnect structures 780.

[0312] Referring to FIG. 33A and 33B , a fourth exemplary structure according to a fourth embodiment of the present disclosure is shown, which can be formed concurrently with any of the first, second, and third exemplary structures or variations thereof, or can be formed as a standalone structure. The fourth exemplary structure shown in FIG. 10A and 10B can be formed using the same processing steps as used to form the first exemplary structure of FIG. 33A and 33B , without forming the backside contact trenches 79. The through-memory-level via regions 500 can be formed within the memory array region 100. Each of the through-memory-level via regions 500 can be formed entirely within a block (Bl, B2, etc.). The through-memory-level via regions 500 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or can be formed in addition to the through-memory-level via regions 400 of the first, second, and third embodiments through the same memory level assemblies.

[0313] Each of the at least one alternating stack of insulating layers (132, 232) and sacrificial material layers (142, 242) is an in-process alternating stack that is modified in subsequent processing steps. Although embodiments are described herein in which the through-memory-level via regions 500 are formed within the memory array region 100, embodiments are also contemplated herein in which additional or alternative through-memory-level via regions 500 are formed in the staircase region. Various dummy memory stack structures 55D can be formed around the through-memory-level via regions 500, which are not electrically connected as device components, but are used for structural support during the formation of the backside recesses in subsequent processing steps.

[0314] Referring to FIG. 34A and 34BThe backside contact trench 79 and the deep trench trench 579 can be formed simultaneously through the memory level assembly. For example, a photoresist layer can be applied over the first contact level dielectric layer 280 and can be lithographically patterned to form openings including the pattern of the backside contact trench 79 and the pattern of the deep trench trench, which can be the same as the pattern of the deep trench trench of the third embodiment or variations thereof as in previous embodiments. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the memory level assembly, thereby forming the backside contact trench 79 and the deep trench trench 579. The photoresist layer can be subsequently removed, for example, by ashing. Each deep trench trench 579 can include a region within its outer periphery that is through the memory level via region 400.

[0315] Referring to FIG. 35A and 35B An insulating liner layer 572L can be deposited in the deep trench trench 579 and the backside contact trench 79. The insulating liner layer 572L includes a dielectric material such as silicon oxide, silicon nitride, and / or a dielectric metal oxide such as aluminum oxide. The insulating liner layer 572L can be deposited as a conformal layer of material by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the insulating liner layer 572L can be in a range from 3 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0316] A photoresist layer 577 can be applied over the insulating liner layer 572L and can be lithographically patterned to cover the insulating liner layer 572L in the memory level via region 500, while the insulating liner layer 572L is not covered by the photoresist layer outside of the memory level via region 500. An etch process, which can be an isotropic etch or an anisotropic etch, can be employed to remove physically exposed portions of the insulating liner layer 572L from outside of the memory level via region 500. The patterned insulating liner layer 572L is formed on the sidewalls of the deep trench trench 579 and over portions of the first contact level dielectric layer 280 within the memory level via region 500. The sidewalls of the backside contact trench 76 are physically exposed to the environment. As used herein, “environment” refers to any gaseous environment to which the semiconductor substrate can be physically exposed during the fabrication sequence, and includes air, vacuum, inert environments, and reduced pressure environments. The photoresist layer 577 is subsequently removed, for example, by ashing.

[0317] Referring to FIG. 36A and 37A An insulating liner layer 572L can be deposited in the deep trench trench 579 and the backside contact trench 79. The insulating liner layer 572L includes a dielectric material such as silicon oxide, silicon nitride, and / or a dielectric metal oxide such as aluminum oxide. The insulating liner layer 572L can be deposited as a conformal layer of material by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the insulating liner layer 572L can be in a range from 3 nm to 60 nm, although lesser and greater thicknesses can also be employed. FIG. 11A 11B ​processing steps of

[0318] Referring to FIG. 37A and 37B processing steps of FIG. 12A and 12B may be performed to form a conductive layer (146, 246) in the backside recess (143, 243). The conductive layer (146, 246) can be formed by introducing a reactant through the backside contact trench 79, thereby forming at least one alternating stack of the insulating layer (132, 232) and the conductive layer (146, 246). A trench cavity 579’ is present within each patterned insulating liner layer 572L. The remaining portions of the at least one alternating stack (132, 142, 232, 242) in processing remain within each region enclosed by the deep trench groove 579.

[0319] Referring to FIG. 38A and 38B processing steps of FIG. 13A and 13B may be performed to form the insulating spacers 74 and the laterally elongated contact via structures 76. Specifically, an insulating material layer can be conformally deposited and anisotropically etched to form the insulating spacers 74 in each backside contact trench 79 and the inner insulating liners 574 in each trench cavity 579’. The inner insulating liners 574 can be formed within each patterned insulating liner layer 572L at the same time as the insulating spacers 74 are formed. The insulating spacers 74 and the insulating liners (i.e., the inner insulating liners 574) can be formed in the backside contact trenches 79 and the deep trench grooves 579, respectively, at the same time. The inner insulating liners 574 and the insulating spacers 74 can comprise the same dielectric material and can have the same thickness.

[0320] Conductive material is deposited to fill the remaining volume of the rear contact trench 79 and trench cavity 579'. Excess conductive material can be removed from a horizontal plane, including the top surface of the first contact level dielectric layer 280, through a planarization process such as chemical mechanical planarization. Each remaining portion of the conductive material within the insulating spacer 74 constitutes a laterally elongated contact via structure 76. Each remaining portion of the conductive material within the inner insulating pad 574 constitutes a conductive fill portion 576. Multiple laterally elongated contact via structures 76 and conductive fill portions 576 can be formed simultaneously on the insulating spacer 74 and the insulating pad, respectively. Horizontal portions of the patterned insulating pad layer 572L can be removed from above the top surface of the first contact level dielectric layer 280. Each remaining portion of the patterned insulating pad layer 572L constitutes an outer insulating pad 572.

[0321] Multiple laterally elongated contact via structures 76 are formed through the memory hierarchy assembly. The multiple laterally elongated contact via structures 76 extend laterally along a first horizontal direction hd1 and divide at least one alternately stacked laterally into multiple laterally spaced blocks (B1, B2, B3...) within the memory hierarchy assembly.

[0322] Reference FIG. 39A and 39B At least one through-memory level opening is formed within the region of each through-memory level via area 500 of the memory level assembly. This can be achieved during the initial etching process. FIG. 2 and 7 During the anisotropic etching of at least one alternating stack of materials (132, 142, 232, 242) and at least one lower-level dielectric layer 760 formed in the processing steps, a photolithographically patterned mask including openings in a region through the memory level via region 500 is employed. The top surface of the lower-level metal interconnect structure 780 can be physically exposed at the bottom of each through-memory level opening. Conductive material is deposited in the through-memory level cavity, and excess portions of the conductive material can be removed from a horizontal plane including the top surface of the first contact level dielectric layer 280. Each remaining portion of the conductive material in the through-memory level opening constitutes a through-memory level via structure 588, which can contact the corresponding lower-level metal interconnect structure 780.

[0323] In one embodiment, at least one through-memory-level via structure 588 can be formed in a through-memory-level via region 500 in the block. The through-memory-level via region 500 can be disposed between a pair of laterally-elongated contact via structures 76 and between two groups of memory stack structures 55 in the block. The through-memory-level via region 500 can include the through-memory-level via structure 588. Each of the at least one through-memory-level via structure 588 extends vertically through the memory-level assembly.

[0324] Referring to FIG. 40 The drain contact via structures 88 and the word line contact via structures can be formed as in the first through third embodiments. A line-level dielectric layer 110 can be formed over the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first through third embodiments. The metal interconnect structures can include the upper-level metal interconnect structures 108, which can be formed over respective pairs of the word line contact via structures 86 and the through-memory-level via structures 588, the bit lines 103 extending along the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown). Alternatively, the upper-level metal interconnect structures 108 can include source shunt lines or power straps in contact with the through-memory-level via structures 588. The source shunt lines can be shunt lines that run parallel to and between the bit lines 103. The power straps can be any electrically conductive lines that connect the driver circuit to an external power source.

[0325] FIG. 40The fourth example structure shown in FIG. 4 includes a semiconductor structure that includes a memory level assembly located above a semiconductor substrate 9 and including at least one first alternating stack of electrically conductive tiers (146, 246) and first portions of insulative tiers (132, 232), and further including memory stack structures 55 that vertically extend through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The electrically conductive tiers (146, 246) constitute word lines for the memory stack structures 55. The semiconductor structure further includes insulative deep trench structures (572, 574, 576) that vertically extend through the memory level assembly and define regions of a through-memory-level via region 500 laterally offset from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure further includes at least one second alternating stack located in the through-memory-level via region 500. The at least one second alternating stack includes alternating tiers of dielectric spacer tiers (142, 242) and second portions of insulative tiers (132, 232), and each dielectric spacer tier (142, 242) is located at the same level as a respective electrically conductive tier (146, 246). The semiconductor structure further includes a through-memory-level via structure 588 located within the through-memory-level via region 500 and vertically extending from a first horizontal plane that includes a topmost surface of the memory level assembly and a bottommost surface of the memory level assembly and includes an electrically conductive material.

[0326] In an embodiment, the plurality of laterally elongated contact via structures 76 extending along the first horizontal direction hd1 can laterally divide the memory level assembly into a plurality of laterally spaced apart blocks, and each of the plurality of laterally elongated contact via structures 76 can be laterally surrounded by an insulative spacer 74. The insulative deep trench structures (572, 574, 576) can include electrically conductive fill portions 576 that include the same electrically conductive material as the plurality of laterally elongated contact via structures 76.

[0327] Referring to FIG. 41 , a first variation of the fourth example structure is shown that can be derived from the fourth example structure shown in FIG. 4 by increasing a thickness of the insulative liner layer 572L. FIG. 37A and 37B The fourth example structure shown in FIG. 4 includes a semiconductor structure that includes a memory level assembly located above a semiconductor substrate 9 and including at least one first alternating stack of electrically conductive tiers (146, 246) and first portions of insulative tiers (132, 232), and further including memory stack structures 55 that vertically extend through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The electrically conductive tiers (146, 246) constitute word lines for the memory stack structures 55. The semiconductor structure further includes insulative deep trench structures (572, 574, 576) that vertically extend through the memory level assembly and define regions of a through-memory-level via region 500 laterally offset from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure further includes at least one second alternating stack located in the through-memory-level via region 500. The at least one second alternating stack includes alternating tiers of dielectric spacer tiers (142, 242) and second portions of insulative tiers (132, 232), and each dielectric spacer tier (142, 242) is located at the same level as a respective electrically conductive tier (146, 246). The semiconductor structure further includes a through-memory-level via structure 588 located within the through-memory-level via region 500 and vertically extending from a first horizontal plane that includes a topmost surface of the memory level assembly and a bottommost surface of the memory level assembly and includes an electrically conductive material.

[0328] Referring to FIG. 42The thickness of the layer of insulating material is such that the layer of insulating material completely fills the backside contact trenches 79 while completely filling the deep trench 579. An anisotropic etch is performed to remove horizontal portions of the layer of insulating material. Each remaining vertical portion of the layer of insulating material in the backside contact trenches 79 constitutes an insulating spacer. Each remaining portion of the layer of insulating material filling the volume within the insulating liner layer 572 constitutes an insulating material fill portion 575. Subsequently, a conductive material is deposited and planarized to form laterally extending contact via structures 76. The remaining portion of each insulating liner layer 572L constitutes an outer insulating liner 572.

[0329] In an embodiment, the insulating spacers 74 can be formed in the backside contact trenches 79 at the same time as the insulating material fill portions 575 are formed in the deep trench 579. A plurality of laterally elongated contact via structures 76 can be formed on the insulating spacers 74. The remaining portion of the at least one alternating stack (132, 142, 232, 242) under processing remains within the area enclosed by each deep trench 579.

[0330] Subsequently, processing steps of FIG. 39A and 39B may be performed to form at least one through-memory-level via structure 588 within each through-memory-level via region domain 500.

[0331] Referring to FIG. 43 , the drain contact via structures 88 and the word line contact via structures can be formed as in the first to third embodiments. A line level dielectric layer 110 can be formed on the first contact level dielectric layer 280. Various metal interconnect structures can be formed in the line level dielectric layer 110 as in the first to third embodiments. The metal interconnect structures can include upper level metal interconnect structures 108 which are either formed on respective pairs of word line contact via structures 86 and through-memory-level via structures 588 or which include shunt lines or power straps connected to the structures 588, bit lines 103 extending in the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown).

[0332] FIG. 43A first variation of the fourth exemplary structure shown in FIG. 1 1 1 includes a semiconductor structure that includes a memory level assembly located above a semiconductor substrate 9 and including at least one first alternating stack of electrically conductive tiers (146, 246) and first portions of insulative tiers (132, 232), and further including memory stack structures 55 that extend vertically through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The electrically conductive tiers (146, 246) constitute word lines for the memory stack structures 55. The semiconductor structure further includes insulative deep trench structures (572, 575) that extend vertically through the memory level assembly and define regions of a through-memory-level via region 500 laterally offset from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure further includes at least one second alternating stack located in the through-memory-level via region 500. The at least one second alternating stack includes alternating tiers of dielectric spacer tiers (142, 242) and second portions of insulative tiers (132, 232), and each dielectric spacer tier (142, 242) is located at the same level as a respective electrically conductive tier (146, 246). The semiconductor structure further includes a through-memory-level via structure 588 located within the through-memory-level via region 500 and extending vertically from a first horizontal plane that includes a topmost surface of the memory level assembly and a bottommost surface of the memory level assembly and includes an electrically conductive material.

[0333] In an embodiment, a plurality of laterally elongated contact via structures 76 extending along a first horizontal direction hdl can laterally divide the memory level assembly into a plurality of laterally spaced apart blocks, and each of the plurality of laterally elongated contact via structures 76 can be laterally surrounded by an insulative spacer 74. The insulative deep trench structures (572, 575) can consist essentially of a dielectric material.

[0334] Referring to FIG. 44A and 44B , a second variation of the fourth exemplary structure can be the same as the fourth exemplary structure shown in FIG. 33A and 33B . The second variation of the fourth exemplary structure can be formed simultaneously with forming any of the first, second, and third exemplary structures or variations thereof, or can be formed as a standalone structure. As with the previously described embodiments, an alternating stack of insulative tiers (132, 232) and dielectric spacer tiers (which can be sacrificial material tiers (142, 242)) can be formed in at least one of the processes on the semiconductor substrate 9.

[0335] Through-memory-level via regions 600 can be formed within memory array region 100 at their respective central regions not including memory stack structures 55. Each through-memory-level via region 600 can be formed entirely within a block (Bl, B2, etc.). Pseudo memory stack structures 55D can be provided at the periphery of through-memory-level via regions 600. The pseudo memory stack structures 55 are not active components of the semiconductor structure, but are provided to provide structural support during formation of the backside recesses (143, 243). Through-memory-level via regions 600 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or can be formed in addition to the through-memory-level via regions 400 of the first, second, and third embodiments through the same memory-level assembly.

[0336] Referring to FIG. 45A and 45B , a photoresist layer 677 can be applied over first contact level dielectric layer 280 and can be lithographically patterned to form openings therein. The pattern of openings includes the pattern of backside contact trenches 79 described above as well as the pattern of through-memory-level via structures subsequently formed in through-memory-level regions 600.

[0337] The pattern in photoresist layer 677 can be transferred through first contact level dielectric layer 280 and through the alternating stack in processing of insulating layers (132, 232) and dielectric spacer material layers (142, 242) to form backside contact trenches 79 in memory array region 100 and to form through-memory-level openings 679 in through-memory-level via regions 600. The top surface of planar semiconductor layer 10 can be physically exposed at the bottom of each backside contact trench 79. Backside contact trenches 79 can be formed concurrently with forming through-memory-level openings 679.

[0338] The top surface of at least one lower level dielectric layer 760 can be physically exposed at the bottom of each through-memory-level opening 679. The top surface of lower level metal interconnect structure 780 can or can not be physically exposed at the bottom of through-memory-level opening 679. In one embodiment, the width of through-memory-level opening 679 can be greater than the width of backside contact trench 79. In this case, more reactant can be provided to through-memory-level opening 679 during anisotropic etching, and the bottom surface of through-memory-level opening 679 can be located below the bottom surface of backside contact trench 79.

[0339] Referring to FIG. 46A and 46B , photoresist layer 677 can be removed, for example, by ashing. The photoresist layer 677 can be removed by ashing. FIG. 11A 11B ​processing steps of FIG. 12A and 12B to form the electrically conductive layers (146, 246). A reactant can be introduced through the backside contact trenches 79 and the through-memory-level openings 679 to deposit the electrically conductive layers (146, 246). An etch-back process can be employed to remove excess portions of the deposited electrically conductive material from inside the backside contact trenches 79 and the through-memory-level openings 679 as well as from above the first contact-level dielectric layer 280. An alternating stack (132, 146, 232, 246) of the insulative layers (232, 232) and the electrically conductive layers (146, 246) is thereby formed.

[0340] Referring to FIG. 47A and 47B , a conformal insulative material layer is deposited in the backside contact trenches 79 and the through-memory-level openings 689 by a conformal deposition process such as chemical vapor deposition or atomic layer deposition. The conformal insulative material layer includes a dielectric material such as silicon oxide, silicon nitride, a dielectric metal oxide, or a combination thereof.

[0341] An anisotropic etch is performed to remove horizontal portions of the conformal insulative material layer. In the absence of the top surface of the underlying metal interconnect structure 780 being physically exposed at the bottom of the through-memory-level openings 679 prior to the anisotropic etch, the anisotropic etch can remove additional material of the at least one underlying dielectric layer 760 to physically expose the top surface of the underlying metal interconnect structure 780. In this case, the through-memory-level openings 679 can extend downwardly while the conformal insulative material layer is anisotropically etched. During the anisotropic etch, the underlying metal interconnect structure 780 can be physically exposed at the bottom of one or more of the through-memory-level openings 679.

[0342] Each remaining portion of the conformal insulative material layer in the backside contact trenches 79 constitutes an insulative spacer 74. Each remaining portion of the conformal insulative material layer in the through-memory-level openings 679 constitutes an insulative liner 674. The insulative spacers 74 and the insulative liners 674 are formed in the backside contact trenches 79 and the through-memory-level openings 679, respectively, simultaneously after the electrically conductive layers (146, 246) are formed. A backside cavity 79' is present within each insulative spacer 74. A through-memory-level cavity 679' is present within each insulative liner 674.

[0343] Referring to FIG. 48A and 48BAt least one electrically conductive material can be deposited in the backside cavity 79' and the through-memory-level cavity 679'. Excess portions of the at least one electrically conductive material can be removed from above the level of the top surface of the first contact-level dielectric layer 280 by a planarization process such as chemical-mechanical planarization. Each remaining portion of the at least one electrically conductive material in the backside contact trench 79' constitutes a laterally-elongated contact via structure 76. Each remaining portion of the at least one electrically conductive material in the through-memory-level opening 679' constitutes a through-memory-level via structure 676. Each through-memory-level via structure 676 is a portion of electrically conductive fill material. The laterally-elongated contact via structures 76 and the through-memory-level via structures 676 can be formed simultaneously in the backside contact trenches 79' and in the through-memory-level openings 679', respectively.

[0344] Referring to FIG. 49 The drain contact via structures 88 and the wordline contact via structures can be formed as in the first through third embodiments. A line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first through third embodiments. The metal interconnect structures can include upper-level metal interconnect structures 108 that are formed on respective pairs of the wordline contact via structures 86 and the through-memory-level via structures 588, or that include shunt lines or power straps connected to the structures 588, bitlines 103 extending in the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown).

[0345] Referring to FIG. 50A and 50B A third variation of the fourth exemplary structure can be the same as the second variation of the fourth exemplary structure shown in FIG. 44A and 44B with optional modifications to the pattern for the drain-select-level shallow trench isolation structures 72. The first-tier alternating stack (132, 242), the second-tier alternating stack (232, 242), the memory stack structures, and the drain-select-level shallow trench isolation structures 72 can be formed as described above.

[0346] Referring to FIG. 51A and 51B A photoresist layer 677 can be applied and patterned with only the pattern of the through-memory-level openings 679 and without the pattern of the backside contact trenches 79' shown in FIG. 45A and 45B The first-tier alternating stack (132, 242), the second-tier alternating stack (232, 242), the memory stack structures, and the drain-select-level shallow trench isolation structures 72 can be formed as described in FIG. 45A and 45BAn anisotropic etch is performed to transfer the pattern in the photoresist layer 677 through the alternating stack (132, 142, 232, 242) and into the upper portion of the at least one dielectric layer 760 as with the processing steps of FIG. 6. A through-memory-level opening 679 is formed in the through-memory-level region 600 without forming a backside contact trench in the semiconductor structure.

[0347] Referring to FIG. 52A and 52B The photoresist layer 677 can be removed, e.g., by ashing. Processing steps of FIG. 11A and 11B may be performed to remove the sacrificial material layer (142, 242) selective to the insulating layers (132, 232). In this case, the through-memory-level openings 679 can be employed to introduce an etchant that etches the sacrificial material layer (142, 242) selective to the insulating layers (132, 232). Subsequently, processing steps of FIG. 12A and 12B may be performed to form the conductive layer (146, 246). A reactant can be introduced through the through-memory-level openings 679 to deposit the conductive layer (146, 246). An etch-back process can be employed to remove excess portions of the deposited conductive material from inside the through-memory-level openings 679 and from above the first contact-level dielectric layer 280. An alternating stack (132, 146, 232, 246) of insulating layers (232, 232) and conductive layers (146, 246) is thereby formed.

[0348] Referring to FIG. 53A and 54B A conformal insulating material layer is deposited in the through-memory-level openings 689 by a conformal deposition process such as chemical vapor deposition or atomic layer deposition. The conformal insulating material layer comprises a dielectric material such as silicon oxide, silicon nitride, a dielectric metal oxide, or a combination thereof.

[0349] An anisotropic etch is performed to remove horizontal portions of the conformal insulating material layer. In the absence of the top surface of the underlying metal interconnect structure 780 being physically exposed at the bottom of the through-memory-level openings 679 prior to the anisotropic etch, the anisotropic etch can remove additional material of the at least one underlying dielectric layer 760 to physically expose the top surface of the underlying metal interconnect structure 780. In this case, the through-memory-level openings 679 can extend downwardly while the conformal insulating material layer is anisotropically etched. During the anisotropic etch, the underlying metal interconnect structure 780 can be physically exposed at the bottom of one or more of the through-memory-level openings 679. Each remaining portion of the conformal insulating material layer in the through-memory-level openings 679 constitutes an insulating liner 674. A through-memory-level cavity 679' is present within each insulating liner 674.

[0350] Referring to FIG. 54A and 54B at least one electrically conductive material can be deposited in the through-memory-level cavities 679'. Excess portions of the at least one electrically conductive material can be removed from above the level of the top surface of the first contact-level dielectric layer 280 by a planarization process such as chemical-mechanical planarization. Each remaining portion of the at least one electrically conductive material in the through-memory-level openings 679 constitutes a through-memory-level via structure 676. Each through-memory-level via structure 676 is a portion of electrically conductive fill material.

[0351] Referring to FIG. 55A and 55B a plurality of insulating spacers 74 and a plurality of laterally extending contact via structures 76 can be formed within the respective insulating spacers 74. The backside contact trenches can be formed through an alternating stack (132, 146, 232, 246) of insulating layers (132, 232) and electrically conductive layers (146, 246) employing the pattern shown in FIG. 11B The insulating spacers 74 can be formed by deposition of a dielectric material and anisotropic etching. The source regions 61 can be formed below each of the backside contact trenches. The laterally extending contact via structures 76 can be formed by deposition of at least one electrically conductive material and removal of excess portions of the at least one electrically conductive material employing a planarization process.

[0352] Subsequently, the drain contact via structures 88 and the wordline contact via structures can be formed as in the first through third embodiments. A line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first through third embodiments. The metal interconnect structures can include upper-level metal interconnect structures 108 which are either formed on respective pairs of the wordline contact via structures 86 and the through-memory-level via structures 588 or which include shunt lines or power straps connected to the structures 588, bitlines 103 extending in a second horizontal direction and perpendicular to the first horizontal direction, and source connection line structures (not shown).

[0353] Referring to FIG. 56A and 56B a fourth variant of the fourth exemplary structure can be derived from any one of the first exemplary structure shown in FIG. 13A and 13B or the second, third, and fourth exemplary structures described above or variants thereof corresponding to the processing steps of FIG. 13A and 13B .

[0354] Through-memory-level via regions 600 can be formed within memory array region 100 at respective central regions thereof that do not include memory stack structures 55. Each through-memory-level via region 600 can be formed entirely within a block (Bl, B2, etc.). Pseudo memory stack structures 55D can be disposed at a periphery of through-memory-level via regions 600. The pseudo memory stack structures 55 are not active components of the semiconductor structure, but are for providing structural support during formation of backside recesses (143, 243). Through-memory-level via regions 600 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or can be formed in addition to the through-memory-level via regions 400 of the first, second, and third embodiments through the same memory-level assembly.

[0355] Referring to FIG. 57A and 57B , a photoresist layer 677 can be applied and patterned with a pattern of through-memory-level openings 679 shown in FIG. 51A and 51B . An anisotropic etch can be performed to transfer the pattern in photoresist layer 677 through the alternating stack (132, 142, 232, 242) and into an upper portion of at least one dielectric layer 760. Through-memory-level openings 679 are formed in through-memory-level regions 600 while there are multiple laterally extending contact via structures 76 and insulative spacers 74 in the semiconductor structure. A top surface of an underlying lower-level metal interconnect structure 780 can be physically exposed at a bottom of through-memory-level openings 679.

[0356] Referring to FIG. 58A and 58B , processing steps of FIG. 53A and 53B can be performed to form insulative liners 674 laterally surrounding respective through-memory-level cavities 679'.

[0357] Referring to FIG. 59A and 59B , drain contact via structures 88 and wordline contact via structures can be formed as in the first through third embodiments. A line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in line-level dielectric layer 110 as in the first through third embodiments. The metal interconnect structures can include upper-level metal interconnect structures 108 that are either formed on respective pairs of wordline contact via structures 86 and through-memory-level via structures 588 or that include shunt lines or power rails connected to structures 588, bitlines 103 extending in a second horizontal direction and perpendicular to the first horizontal direction, and source connection line structures (not shown).

[0358] Referring to FIG. 60 A fifth variation of the fourth exemplary structure according to the fourth embodiment of the present disclosure is shown, which can be derived from any one of the second, third and fourth variations of the fourth exemplary structure by patterning the through-memory-level opening 679 in a manner that does not separate the drain contact level shallow trench isolation structure 72. In this case, the through-memory-level via structure 676 can be formed as a two-dimensional array.

[0359] Referring to FIG. 61A and 61B The second variation of the third exemplary structure can be derived from the structure of FIG. 10A and 10B or from the structure of FIG. 22 The memory stack structure 55 and the first contact level dielectric layer 280 can be formed using any of the methods described above.

[0360] Referring to FIG. 62A and 62B The processing steps of FIG. 34A and 34B can be performed to simultaneously form the backside contact trench 79 and the deep trench trench 579 through the memory-level assembly. In this embodiment, the location of the deep trench trench 579 is selected to be outside of the memory array region 100 and within each through-memory-level via region 400, which can have the same location as the through-memory-level via region 400 in the first, second and third embodiments.

[0361] For example, a photoresist layer can be applied on the first contact level dielectric layer 280 and can be lithographically patterned to form openings including the pattern of the backside contact trench 79 as in the previous embodiments and the pattern of the deep trench trench 579. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the memory-level assembly, thereby forming the backside contact trench 79 and the deep trench trench 579. The photoresist layer can be subsequently removed, for example, by ashing. Each deep trench trench 579 can include a region of the through-memory-level via region 400 within its outer periphery.

[0362] Referring to FIG. 63A-63C The processing steps of FIG. 35A and 35Bprocessing steps of FIGS. 36A and 36B, 37A and 37B, 38A and 38B, 39A and 39B, and 40 to form a plurality of laterally-elongate contact via structures 76 through the memory-level assembly, and fill each deep trench 579 with an insulative deep trench structure (572, 574, 576) extending vertically through the memory-level assembly. The through-memory-level via structure 488 can be formed through each dielectric material assembly laterally surrounded by a respective insulative deep trench structure (572, 573, 576). Each dielectric material assembly can include at least one alternating stack of insulative layers (132, 232) and spacer dielectric layers (142, 242), a second-tier back-kicked dielectric material portion 265, and optionally a first-tier back-kicked dielectric material portion 165.

[0363] Various contact via structures (88, 86), line-level dielectric layers 110, and various metal interconnect structures and bit lines 103 extending through the line-level dielectric layers 110 can be formed. The metal interconnect structures can include upper-level metal interconnect structures 108. In an embodiment, a subset of the upper-level metal interconnect structures 108 can be electrically coupled to (e.g., formed on or in physical contact with) respective pairs of word line contact via structures 86 and through-memory-level via structures 488. The bit lines 103 extend along a second horizontal direction hd2 and are perpendicular to the first horizontal direction hd1. The word line interconnect structures 106 can include portions of the upper-level metal interconnect structures 108 that are electrically shorted to the through-memory-level via structures 488, and / or can include metal lines connected to peripheral circuitry for driving word lines of the memory stack structures 55 in the memory array region 100. Alternatively or additionally, at least a subset of the through-memory-level via structures 488 can be used for different purposes, such as providing a power supply voltage, an electrical ground, etc.

[0364] Referring to FIG. 64 A third variant of the third exemplary structure can be derived from the second variant of the third exemplary structure by performing processing steps of FIG. 41 and 42 to form insulative deep trench structures (572, 575) each including a pair of insulative spacers 572 and an insulative material fill portion 575.

[0365] Referring to FIG. 65A and 65B A sixth variant of the fourth exemplary structure can be derived from the third exemplary structure of FIG. 44B and FIG. 24A by forming a first-tier deep trench within the through-memory-level via region 600 shown in 24B and FIG. 24A 24B ​The processing steps of

[0366] Referring to FIG. 66A and 66B , processing steps of FIG. 25A , 25B , 26A and 26B form a second-tier alternating stack (232, 242) and a memory stack structure 55 and a pseudo-memory stack structure 155. The pseudo-memory stack structure 155 is an insulative deep trench structure that provides electrical isolation between an interior of the pseudo-memory stack structure 155 and an exterior.

[0367] Referring to FIG. 67A and 67B , processing steps of FIG. 27A and 27B may be performed as well as a subset of processing steps of FIG. 28A and FIG. 28B to form backside recesses (143, 243).

[0368] Referring to FIG. 68A and 68B , a complementary subset of processing steps of FIG. 28A and 28B may be performed to form a conductive layer (146, 246) outside of the through-memory-level via regions 600. The insulative spacers 74 and the laterally-extending contact via structures 76 can be formed in the backside contact trenches 79.

[0369] Referring to FIG. 69A and 69B , at least one through-memory-level opening is formed through a memory-level assembly within a region of each through-memory-level via region 600. A mask including a photoresist pattern of openings in the region of the through-memory-level via region 600 can be employed during an anisotropic etch of materials of the at least one alternating stack (132, 142, 232, 242) and materials of the at least one lower-level dielectric layer 760 formed in processing steps of FIG. 2 and 7 . A top surface of the lower-level metal interconnect structure 780 can be physically exposed at a bottom of each through-memory-level opening. A conductive material is deposited in the through-memory-level cavity, and excess portions of the conductive material can be removed from above a level of a top surface of the first contact-level dielectric layer 280. Each remaining portion of the conductive material in the through-memory-level opening constitutes a through-memory-level via structure 588, which can contact a respective underlying lower-level metal interconnect structure 780.

[0370] In an embodiment, at least one through-memory-level via structure 588 can be formed in a through-memory-level via region 600 in the block. The through-memory-level via region 600 can be disposed between a pair of laterally-elongated contact via structures 76 and between two groups of memory stack structures 55 in the block. The through-memory-level via region 600 can include the through-memory-level via structure 588. Each of the at least one through-memory-level via structure 588 extends vertically through the memory-level assembly.

[0371] The drain contact via structures 88 and the word line contact via structures can be formed as in the first through third embodiments. A line-level dielectric layer 110 can be formed over the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first through third embodiments. The metal interconnect structures can include upper-level metal interconnect structures 108 that are either formed over respective pairs of the word line contact via structures 86 and the through-memory-level via structures 588 or that include shunt lines or power straps connected to the structures 588, bit lines 103 extending along a second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown).

[0372] Referring to FIG. 70A and 70B , a seventh variation of the fourth exemplary structure can be derived from the first exemplary structure shown in FIG. 10A and 10B . The memory stack structures 55 and the first contact-level dielectric layer 280 can be formed using the methods described above. The pattern of the support pillar structures (171, 271) can be modified to avoid regions where the through-memory-level via structures are to be subsequently formed.

[0373] Referring to FIG. 71A and 71B , a photoresist layer is applied and patterned photolithographically to form openings including the pattern of the backside contact trenches 79 described above and the pattern of the through-memory-level via structures to be formed in each through-memory-level via region 400. The pattern in the photoresist layer is transferred through the memory-level assembly to simultaneously form the backside contact trenches 79 and the through-memory-level via cavities 479. In an embodiment, an anisotropic etch can be selective to the semiconductor material of the planar semiconductor layer 10 to effect etching of the physically exposed portions of the at least one lower-level dielectric layer 760. In an embodiment, top surfaces of the lower-level metal interconnect structures 780 can be physically exposed at the bottom of the through-memory-level via cavities 479.

[0374] Referring to FIG. 72A and 72B , the FIG. 52A and52B The processing steps of the fourth exemplary structure of FIG. 4A can be performed to replace the sacrificial material layer (142, 242) with a conductive layer (146, 246). Each of the through-memory-level via cavities 479 and the backside contact trenches 79 can be used to provide an etchant to remove material of the sacrificial material layer (142, 242) to form backside recesses (143, 243), and to provide a reactant to deposit a conductive material of the conductive layer (146, 246).

[0375] Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by FIG. 73A-73C Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by

[0376] Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by FIG. 74 Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by

[0377] Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by FIG. 75A and 75B Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by FIG. 70A and 70B A seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A by

[0378] Referring now to FIG. 4B, a seventh variant of the fourth exemplary structure of FIG. 4A can be derived from the fourth exemplary structure of FIG. 4A byFIG. 76 As described above, backside contact trenches 79, insulating spacers 74, source regions 61, laterally extending contact via structures 76, additional contact via structures 88, line level dielectric layers 110, and various metal interconnect structures 108 and bit lines 103 extending therethrough can be formed.

[0379] Various through-memory-level via structures (588, 676) can be employed in the fourth exemplary structure or variations thereof to provide vertical conductive paths within selected regions of the memory array region 100. The through-memory-level via structures (588, 676) can be used as part of a power distribution network, or can be used to provide various control signals to the three-dimensional memory device in a manner that shortens signal paths and thus minimizes signal loss and capacitive coupling.

[0380] The fourth exemplary structure or any variations thereof can include a semiconductor structure including a memory-level assembly located over the semiconductor substrate 9 and including at least a first portion of alternating stacks of conductive layers (146, 246) and insulating layers (132, 232), and further including vertically extending through the at least one alternating stack of memory stack structures 55. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The conductive layers (146, 246) constitute word lines for the memory stack structures 55. A plurality of laterally elongated contact via structures 76 vertically extend through the memory-level assembly, laterally extend along a first horizontal direction hdl, and laterally divide the at least one alternating stack into a plurality of laterally spaced apart blocks (Bl, B2, B3,...) within the memory-level assembly. At least one through-memory-level via structure (588, 676) is located in a through-memory-level via region 400 in a block. The through-memory-level via region 400 is located between a pair of laterally elongated contact via structures 76 and between two groups of memory stack structures 55 in the block. Each of the at least one through-memory-level via structure (588, 676) vertically extends through the memory-level assembly.

[0381] A semiconductor device can be located on the semiconductor substrate 9. Lower level metal interconnect structures 680 can be electrically shorted to nodes of the semiconductor device, and can be embedded in at least one lower level dielectric layer 760 that covers the semiconductor substrate 9. The lower level metal interconnect structures 680 can contact the at least one through-memory-level via structure (588, 676). A planar semiconductor material layer 10 can cover the at least one lower level dielectric layer 760, and can include horizontal semiconductor channels 58 connected to the vertical semiconductor channels 60 within the memory stack structures 55.

[0382] In an embodiment, each of the at least one through-memory-level via structure 676 can be laterally electrically isolated from the conductive layers (146, 246) by a respective insulative liner 674. In an embodiment, a bottom of each sidewall of the at least one through-memory-level via structure (588, 676) is in physical contact with the at least one lower-level dielectric layer 760. In some embodiments, each insulative liner 674 can have a smaller vertical extent than the respective through-memory-level via structure 676 enclosed by the insulative liner 674 as shown. FIG. 49

[0383] In an embodiment, each of the plurality of laterally-elongate contact via structures 76 is laterally electrically isolated from the at least one alternating stack (132, 246, 232, 246) by an insulative spacer 74. In an embodiment, each of the at least one through-memory-level via structure 676 is laterally electrically isolated from the at least one alternating stack (132, 246, 232, 246) by an insulative liner 674 having the same material composition and the same thickness as the insulative spacer 74.

[0384] The planar semiconductor material layer 10 can overlie the semiconductor substrate 9 and can include horizontal semiconductor channels 58 connected to the vertical semiconductor channels 60 within the memory stack structures 55. The at least one through-memory-level via structure (588, 686) can extend through an opening in the planar semiconductor material layer 10. In an embodiment, the plurality of laterally-elongate contact via structures 76 can terminate on a top surface of the planar semiconductor material layer 10. The plurality of laterally-elongate contact via structures 76 can include source lines that contact respective lower source regions 61 of respective horizontal channels 58 located within the planar semiconductor material layer 10.

[0385] In some embodiments, the at least one second alternating stack (132, 142, 232, 242) can be located in the through-memory-level via region 400. The at least one second alternating stack (132, 142, 232, 242) includes alternating layers of dielectric spacer layers (142, 242) and second portions of insulative layers (132, 232), and each dielectric spacer layer (142, 242) is located at the same level as a respective conductive layer (146, 246). The through-memory-level via region 400 can include an insulative deep trench structure {(572, 574, 576), (572, 575) laterally surrounding the at least one second alternating stack (132, 142, 232, 242).

[0386] ​The inner sidewalls of the insulative deep trench groove structures (572, 574, 576), (572, 575) and the sidewalls of the at least one through-memory-level via structure 588 are in physical contact with the at least one second alternating stack (132, 142, 232, 242).

[0387] In an embodiment, the insulative trench structures (572, 574, 576) can include an outer insulative liner 572 and an inner insulative liner 574. Each of the plurality of laterally-elongated contact via structures 76 can be laterally surrounded by an insulative spacer 74 that includes a dielectric material that is the same composition and the same thickness as the inner insulative liner 574.

[0388] In an embodiment, the insulative deep trench groove structures (572, 574, 576) can include a conductive fill portion 576 that is the same material composition as the plurality of laterally-elongated contact via structures 76.

[0389] In an embodiment, the insulative deep trench groove structures (572, 575) can be composed of an outer insulative liner 572 and an inner insulative fill portion 565, and each of the plurality of laterally-elongated contact via structures 76 can be laterally surrounded by an insulative spacer 74 that includes the same dielectric material as the inner insulative fill portion 574.

[0390] Each of the example structures and variations thereof can include a three-dimensional memory structure. The memory stack structure 55 can include memory elements of a vertical NAND device. The electrically conductive layers (146, 246) can include or can be electrically connected to respective word lines of the vertical NAND device. The semiconductor substrate 9 can include a silicon substrate. The vertical NAND device can include an array of monolithic three-dimensional NAND strings on the silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit including word line driver circuitry and bit line driver circuitry for the memory device. The array of monolithic three-dimensional NAND strings can include a plurality of semiconductor channels, where at least one end portion of each of the plurality of semiconductor channels (58, 11, 60), such as a vertical semiconductor channel 60, extends substantially perpendicular to a top surface of the semiconductor substrate 9; a plurality of charge storage elements (such as embodied as portions of the memory material layer 54 located at each word line level), each charge storage element located adjacent to a respective one of the plurality of semiconductor channels (58, 11, 60); and a plurality of control gate electrodes (such as embodied as a subset of the electrically conductive layers (146, 246) having a strip shape extending substantially parallel to the top surface of the semiconductor substrate 9, e.g., along a first horizontal direction hd1), the plurality of control gate electrodes including at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

[0391] The via contact structures located in the above-described regions 400, 500, and / or 600 provide electrical contact to driver circuitry located below the memory array to reduce the overall device size / footprint on the substrate and utilize device area that is not fully utilized in prior art devices, which reduces device cost.

[0392] While the foregoing has described specific embodiments, it is understood that the present disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the described embodiments, and such modifications are intended to be within the scope of the present disclosure. Where an embodiment is shown in the present disclosure employing a particular structure and / or configuration, at least analogous structures and / or configurations employing functional equivalents should also be considered to be within the scope of the present disclosure. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A semiconductor structure, comprising: a memory level assembly located over a semiconductor substrate and including at least one alternating stack and a memory stack structure, the memory stack structure vertically extending through the at least one alternating stack, wherein the at least one alternating stack includes alternating layers of respective insulative layers and respective conductive layers; a plurality of laterally elongated contact via structures vertically extending through the memory level assembly, laterally extending along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally spaced-apart blocks, wherein the plurality of blocks includes a set of three adjacent blocks, the set of three adjacent blocks including, in order, a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; a through-memory-level via region located adjacent to a longitudinal end of the second block and between a staircase region of the first block and a staircase region of the third block, wherein the through-memory-level via region includes a vertically extending through-memory-level via structure embedded in a dielectric fill material portion; and a word line switch device located on or over the substrate in the through-memory-level via region under the vertically extending through-memory-level via structure and the dielectric fill material portion.

2. The semiconductor structure of claim 1, further comprising: at least one lower level dielectric layer overlying the semiconductor substrate; and a lower level metal interconnect structure electrically shorted to a node of the word line switch device and embedded in the at least one lower level dielectric layer, wherein the through-memory-level via structure contacts the lower level metal interconnect structure.

3. The semiconductor structure of claim 2, wherein: each of the memory stack structures includes a vertical stack of memory elements located at each level of the conductive layers; the conductive layers include word lines for the memory elements; and the word line switch device is configured to control a bias voltage to a respective word line.

4. The semiconductor structure of claim 3, further comprising: a word line contact via structure extending through a back stepped dielectric material portion and contacting the word lines, the back stepped dielectric material portion overlying a staircase region of the first block and a staircase region of the third block; and an upper level metal interconnect structure electrically shorting a respective pair of a word line contact via structure and a through-memory-level via structure, wherein the upper level metal interconnect structure overlies the memory level assembly and straddles the second block and one of the first block and the third block.

5. The semiconductor structure of claim 4, wherein each of the through-memory-level via structures contacts a respective overlying upper level metal interconnect structure.

6. The semiconductor structure of claim 1, wherein: the dielectric fill material portion includes a substantially vertical sidewall extending through the memory level assembly; ​ ​ Each of the staircase region of the first block and the staircase region of the third block includes a staircase in which each underlying conductive layer extends further along the first horizontal direction than any overlying conductive layer within the memory hierarchy assembly; and Each of the memory stack structures includes a memory film and a vertical semiconductor channel that is contiguous to a respective horizontal channel within the substrate below the memory hierarchy assembly.

7. The semiconductor structure of claim 6, further comprising a plurality of bit lines electrically coupled to drain regions of the memory stack structures.

8. The semiconductor structure of claim 1, wherein: the memory stack structures comprise memory elements of vertical NAND devices; the conductive layers comprise respective word lines of the vertical NAND devices or are electrically connected to respective word lines of the vertical NAND devices; the semiconductor substrate comprises a silicon substrate; the vertical NAND devices comprise an array of monolithic three-dimensional NAND strings of the silicon substrate; at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; the silicon substrate contains an integrated circuit comprising word line driver circuitry and bit line driver circuitry for the memory devices; and the array of monolithic three-dimensional NAND strings comprises: a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate; a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and a plurality of control gate electrodes having a strip shape that extends substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprising at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

9. A three-dimensional NAND memory device comprising: a word line driver device located on or above a substrate; an alternating stack of word lines and insulating layers located above the word line driver device; a plurality of memory stack structures extending through the alternating stack, each memory stack structure comprising a memory film and a vertical semiconductor channel; and a through-memory-level via structure electrically coupling a word line in a first memory block to the word line driver device; wherein the through-memory-level via structure extends through a portion of a dielectric fill material between a staircase region of the first memory block and a staircase region of another memory block, and the word line driver device is located below the through-memory-level via structure and the portion of the dielectric fill material.

10. The three-dimensional NAND memory device of claim 9, further comprising: ​ a word line contact via structure extending through the dielectric material portion and contacting a word line in the first memory block, the dielectric material portion covering a staircase region of the first memory block; and an upper level metal interconnect structure electrically shorting a respective pair of the word line contact via structure and the through-memory-level via structure, wherein the upper level metal interconnect structure covers the alternating stack and spans across the first memory block and the dielectric fill material portion.

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