Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory comprises: a storage stack structure; a plurality of storage channel structures penetrating the storage stack structure; a selection stack structure located on the storage stack structure; a top selection gate cut structure penetrating the selection stack structure; and a plurality of selection channel structures penetrating the selection stack structure and connected with the plurality of storage channel structures respectively, wherein the plurality of selection channel structures are arranged in rows along the extension direction of the top selection gate cut structure, and the top selection gate cut structure extends between adjacent selection channel structure rows; each side of the top selection gate cut structure has at least one offset selection channel structure row, wherein the axis of the selection channel structure in the offset selection channel structure row is farther from the top selection gate cut structure than the axis of the storage channel structure connected therewith.

Description

[0001] Divisional application statement

[0002] This application is a divisional application of Chinese invention patent application filed on June 21, 2021, entitled "Three-dimensional memory and method for preparing the same", with application number 202110687429.2. Technical Field

[0003] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and methods for its fabrication. Background Technology

[0004] 3D NAND flash memory can increase its storage capacity by increasing the number of vertically stacked layers or the unit storage density of the channel structure. Specifically, the unit storage density of 3D NAND flash memory can be increased by optimizing the arrangement of the channel structure.

[0005] In some channel structure layouts, the channels are arranged in an interleaved pattern, dividing the memory block into nine rows. Top Select Gate (TSG) cutouts are located between these rows to divide the memory block into several parts, facilitating programming and erasing operations on the divided blocks. To avoid overlap between the TSG and the channel rows, the distance between the channel rows can be increased. Alternatively, the TSG can extend through a middle channel row, treating it as a virtual channel row, thus rendering the channels in that middle row without storage functionality. However, all these layouts limit the increase in unit storage density.

[0006] Therefore, how to improve the unit storage density of three-dimensional storage cells is one of the research topics in this field. Summary of the Invention

[0007] In a first aspect, this application provides a three-dimensional memory. The three-dimensional memory includes: a memory stack structure; a plurality of memory channel structures penetrating the memory stack structure; a selection stack structure located on the memory stack structure; a top selection gate cutout structure penetrating the selection stack structure; and a plurality of selection channel structures penetrating the selection stack structure and respectively connected to the plurality of memory channel structures, wherein the plurality of selection channel structures are arranged in rows along the extending direction of the top selection gate cutout structure, and the top selection gate cutout structure extends between adjacent rows of selection channel structures; each side of the top selection gate cutout structure has at least one offset selection channel structure row, wherein the distance between the axis of a selection channel structure in the offset selection channel structure row and the top selection gate cutout structure is greater than the distance between the axis of the memory channel structure to which it is connected and the top selection gate cutout structure.

[0008] In some implementations, the maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

[0009] In some embodiments, the selected channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

[0010] In some embodiments, the three-dimensional memory further includes a selection channel plug located at the end of the selection channel structure away from the storage channel structure and in contact with the conductive layer, wherein the size of the selection channel plug is larger than the size of the selection channel structure in a stacking direction perpendicular to the selection stack structure and the storage stack structure.

[0011] In some implementations, there are multiple rows of selection channel structures between adjacent top selection gate cutout structures, wherein the number of offset selection channel structure rows between adjacent top selection gate cutout structures is less than or equal to the number of multiple selection channel structure rows.

[0012] In some implementations, the number of offset selection channel structure rows located between adjacent top selection gate cutout structures where the distance between the axis of the selection channel structure and one of the adjacent top selection gate cutout structures is greater than the distance between the axis of the storage channel structure connected to the selection channel structure and the top selection gate cutout structure is equal to the number of offset selection channel structure rows where the distance between the axis of the selection channel structure and the other of the adjacent top selection gate cutout structures is greater than the distance between the axis of the storage channel structure connected to the selection channel structure and the top selection gate cutout structure.

[0013] In some implementations, the cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

[0014] Secondly, this application provides a three-dimensional memory. The three-dimensional memory includes: a memory stack structure; a plurality of memory channel structures penetrating the memory stack structure; a selection stack structure located on the memory stack structure; a top selection gate cutout structure penetrating the selection stack structure; and a plurality of selection channel structures penetrating the selection stack structure and respectively connected to the plurality of memory channel structures, wherein the plurality of selection channel structures are arranged in rows along the extending direction of the top selection gate cutout structure, and the top selection gate cutout structure extends between adjacent rows of selection channel structures; each side of the top selection gate cutout structure has at least one offset selection channel structure row, wherein the selection channel structures in the offset selection channel structure rows are offset axially away from the top selection gate cutout structure relative to the memory channel structures connected to them.

[0015] In some implementations, the maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

[0016] In some embodiments, the selected channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

[0017] In some embodiments, the three-dimensional memory further includes a selection channel plug located at the end of the selection channel structure away from the storage channel structure and in contact with the conductive layer, wherein the size of the selection channel plug is larger than the size of the selection channel structure in a stacking direction perpendicular to the selection stack structure and the storage stack structure.

[0018] In some implementations, there are multiple rows of selection channel structures between adjacent top selection gate cutout structures, wherein the number of offset selection channel structure rows between adjacent top selection gate cutout structures is less than or equal to the number of multiple selection channel structure rows.

[0019] In some implementations, the number of offset selection channel structure rows located between adjacent top selection gate cutout structures, where the selection channel structure is offset relative to the storage channel structure connected thereto in a directional off-axis away from one of the adjacent top selection gate cutout structures, is equal to the number of offset selection channel structure rows located relative to the storage channel structure connected thereto in a directional off-axis away from the other of the adjacent top selection gate cutout structures.

[0020] In some implementations, the cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

[0021] Thirdly, this application provides a three-dimensional memory. The three-dimensional memory includes: a memory stack structure; a memory channel structure extending through the memory stack structure; a selection stack structure located on the memory stack structure; a selection channel structure extending through the selection stack structure and connected to the memory channel structure; and a top selection gate cutout structure extending through the selection stack structure, wherein the top selection gate cutout structure extends between adjacent rows of selection channel structures, and along the arrangement direction of the top selection gate cutout structure, the distance between the selection channel structures on either side of the adjacent top selection gate cutout structure is greater than the distance between the memory channel structures respectively connected to the selection channel structure.

[0022] In some implementations, the maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

[0023] In some embodiments, the selected channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

[0024] In some embodiments, the three-dimensional memory further includes a selection channel plug located at the end of the selection channel structure away from the storage channel structure and in contact with the conductive layer, wherein the size of the selection channel plug is larger than the size of the selection channel structure in a stacking direction perpendicular to the selection stack structure and the storage stack structure.

[0025] In some implementations, multiple selection channel structures are arranged in rows along the extension direction of the top selection gate cutout structure, with the multiple selection channel structure rows arranged between adjacent top selection gate cutout structures.

[0026] In some implementations, the cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

[0027] Fourthly, this application provides a three-dimensional memory. The three-dimensional memory includes: a memory stack structure; a plurality of memory channel structures penetrating the memory stack structure; a selection stack structure located on the memory stack structure; a top selection gate cutout structure penetrating the selection stack structure, the cross-sectional shape of which includes a wavy shape in a direction perpendicular to the stacking direction of the selection stack structure and the memory stack structure; and a plurality of selection channel structures penetrating the selection stack structure and respectively connected to the plurality of memory channel structures, wherein the plurality of selection channel structures are arranged in rows along the extending direction of the top selection gate cutout structure, the top selection gate cutout structure extending between adjacent rows of selection channel structures; wherein the selection channel structure includes a dielectric core, the end face of the dielectric core near the memory channel structure resting above the memory channel structure.

[0028] In some implementations, the maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

[0029] In some implementations, the dielectric core does not overlap with the storage channel structure in the stacking direction.

[0030] In some implementations, the outer contour of the dielectric core is cylindrical, or a frustum with critical dimensions gradually decreasing along the direction toward the storage channel structure.

[0031] In some implementations, the memory stack structure includes multiple sub-memory stack structures in the stacking direction, and the memory channel structure includes multiple sub-memory channel structures.

[0032] In some implementations, the channel structure is selected to be coaxially arranged relative to the storage channel structure to which it is connected.

[0033] In some implementations, for each select channel structure in at least one select channel structure row on each side of the top select gate cutout structure, the distance between its axis and the top select gate cutout structure is greater than the distance between the axis of the storage channel structure to which it is connected and the top select gate cutout structure.

[0034] In some embodiments, the selected channel structure further includes a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

[0035] In some embodiments, the three-dimensional memory further includes a selection channel plug located at the end of the selection channel structure away from the storage channel structure and in contact with the conductive layer, wherein the size of the selection channel plug is larger than the size of the selection channel structure in the stacking direction.

[0036] Fifthly, this application provides a method for fabricating a three-dimensional memory. The method includes: forming a memory stack structure and a memory channel structure penetrating the memory stack structure; forming a selection stack structure layered on the memory stack structure and a selection channel structure penetrating the selection stack structure and connected to the memory channel structure; and forming a top selection gate cutout structure penetrating the selection stack structure.

[0037] In some implementations, the maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

[0038] In some embodiments, both the storage stack structure and the selection stack structure include multiple dielectric layers and multiple sacrificial layers stacked alternately. The fabrication method further includes: forming a gate gap that penetrates the selection stack structure and the storage stack structure; using the gate gap to remove multiple sacrificial layers in the storage stack structure and the selection stack structure to form multiple sacrificial gaps; and filling the multiple sacrificial gaps with conductive material to form multiple gate layers.

[0039] The three-dimensional memory and its fabrication method provided in this application increase the process window for the top selection gate cutout structure formed between the selection channel structures by fabricating the selection channel structure and the storage channel structure separately, and by making the critical dimension of the selection channel structure smaller than that of the storage channel structure. Furthermore, this fabrication method avoids increasing the distance between rows of storage channel structures or adding virtual storage channel structure rows, thereby improving the unit storage density. Attached Figure Description

[0040] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0041] Figure 1This is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0042] Figures 2A to 2G This is a schematic cross-sectional view of the fabrication method of the three-dimensional memory according to the embodiments of this application;

[0043] Figure 3 yes Figure 2F A top-view diagram of the three-dimensional memory structure.

[0044] Figure 4 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of this application; and

[0045] Figure 5 yes Figure 4 A top-view diagram of the three-dimensional memory structure. Detailed Implementation

[0046] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0047] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0048] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0050] This application provides a method 1000 for fabricating a three-dimensional memory. Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 1As shown, the method 1000 for fabricating a three-dimensional memory includes the following steps.

[0051] S110, forming a memory stack structure and a memory channel structure through the memory stack structure on the substrate.

[0052] S120, forming a selectable stacked structure on the memory stacked structure and forming a selectable channel structure that penetrates the selectable stacked structure and is connected to the memory channel structure, wherein the size of the selectable channel structure is smaller than the size of the memory channel structure in a plane parallel to the substrate.

[0053] S130, forming a top selection gate cutout structure that penetrates the selection stack structure.

[0054] Figures 2A to 2G This is a schematic cross-sectional view of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described herein]. Figure 1 The execution order is shown below. (Followed by...) Figures 2A to 2G The above steps S110 to S130 are further described.

[0055] S110, forming a memory stack structure and a memory channel structure through the memory stack structure on the substrate.

[0056] In step S110, as Figure 2A As shown, substrate 110 can be used to support device structures thereon. Substrate 110 can be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The material of substrate 110 can also be a compound semiconductor. For example, substrate 110 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. It is worth noting that substrate 110 described in this application can also be fabricated using at least one of other semiconductor materials known in the art.

[0057] The memory stack structure 120 may be formed on a first side of the substrate 110 and may include a plurality of dielectric layers 121 and a plurality of sacrificial layers 122 stacked in a direction perpendicular to the substrate 110. The formation method of the memory stack structure 120 may include thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In the memory stack structure 120, the thicknesses of the plurality of dielectric layers 121 and the plurality of sacrificial layers 122 may be the same or different, and may be set according to specific process requirements. Furthermore, in the manufacturing process of the storage stack structure 120, different numbers of stacked layers correspond to different stacking heights. For example, the number of stacked layers in the storage stack structure 120 can be 8, 32, 64, 128, etc. The more layers the storage stack structure 120 has, the higher the integration and the more storage cells it forms. The number of stacked layers and the stacking height of the storage stack structure 120 can be designed according to actual storage needs. This application does not impose specific restrictions on this.

[0058] In this step, a storage channel via can be formed in the storage stack structure 120 using, for example, a dry or wet etching process. The storage channel via can extend perpendicularly toward the substrate 110, thereby exposing the substrate 110. Further, a functional layer 131 and a channel layer 132 can be sequentially formed on the sidewalls of the storage channel via using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, a dielectric material can be filled into the storage channel via with the functional layer 131 and channel layer 132 formed, thereby forming the storage channel structure 130. The functional layer 131 may include a barrier layer, a charge trapping layer, and a tunneling layer sequentially formed along the inner wall of the storage channel via. In other words, a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer can be sequentially formed on the inner wall of the storage channel via. Exemplarily, the materials of the barrier layer, charge trapping layer, tunneling layer, and channel layer may sequentially include silicon oxide, silicon nitride, silicon oxide, and polysilicon. It is worth noting that the same process can be used to form multiple memory channel structures 130 in the memory stack structure 120. The number and arrangement of the memory channel structures 130 are not specifically limited in this application.

[0059] In some embodiments, a dielectric material, such as silicon oxide, can be filled into the memory channel vias where the functional layer 131 and the channel layer 132 are formed, using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, a portion of the filled dielectric material away from the substrate 110 can be etched back using, for example, a dry or wet etching process to expose the channel layer 132 and fill it with a conductive material to form a memory channel plug 133 in contact with the channel layer 132. The memory channel plug 133 can be made of the same material as the channel layer 132, such as polysilicon. The memory channel plug 133 can form an electrically coupled region with a corresponding selected channel structure formed in a subsequent process.

[0060] The fabrication method comprising one sub-memory stack structure and one sub-memory channel structure has been described above. In some embodiments, the memory stack structure 120 may include multiple sub-memory stack structures, and the memory channel structure 130 may include multiple sub-memory channel structures. Accordingly, during the process of forming multiple sub-memory channel structures, memory channel vias may include multiple sub-memory channel vias, and the multiple sub-memory stack structures may correspond one-to-one with the multiple sub-memory channel vias. Specifically, a first sub-memory stack structure may be formed on a first side of the substrate 110, and a first sub-memory channel via may be formed penetrating the first sub-memory stack structure and extending into the substrate 110. Further, subsequent sub-memory stack structures and sub-memory channel vias are formed on the first side until a predetermined number of sub-memory stack structures and sub-memory channel vias are formed. The remaining sub-memory channel vias, except for the last one formed, are correspondingly filled with a via-filling sacrificial layer. Furthermore, based on the last formed sub-memory channel via, all the via-filling sacrificial layer is removed, such that adjacent sub-memory channel vias in a predetermined number of sub-memory channel vias are at least partially aligned with each other, thereby obtaining the memory channel vias. Further, multiple sub-memory channel structures can be formed according to the same process described above.

[0061] S120, forming a selectable stacked structure on the memory stacked structure and forming a selectable channel structure that penetrates the selectable stacked structure and is connected to the memory channel structure, wherein the size of the selectable channel structure is smaller than the size of the memory channel structure in a plane parallel to the substrate.

[0062] In step S120, as Figure 2BAs shown, the selected stack structure 140 can be formed on a first side of the substrate 110 using the same process as in step S110, such as the surface of the storage stack structure 120 away from the substrate 110, to cover the storage channel structure 130. The selected stack structure 140 may include a plurality of alternately stacked dielectric layers 141 and a plurality of sacrificial layers 142. The thicknesses of the plurality of dielectric layers 141 and the plurality of sacrificial layers 142 may be the same or different, and can be set according to specific process requirements. Similarly, in the manufacturing process of the selected stack structure 140, different numbers of stacked layers correspond to different stacking heights, and the number of sacrificial layers 141 in the selected stack structure 140 may correspond to the number of top selected transistors.

[0063] In some embodiments, the dielectric layer 121 and sacrificial layer 122 in the storage stack 120 and the dielectric layer 141 and sacrificial layer 142 in the selection stack 140 may have different etching selectivity ratios. The sacrificial layers 122 and 142 may be removed and replaced by conductive material in subsequent processes to form the gate layer, i.e., the word line. Optionally, the material of the dielectric layers 121 and 141 may include silicon oxide, and the material of the sacrificial layers 122 and 142 may include silicon nitride.

[0064] It should be understood that although this application adopts the implementation method in which sacrificial layers 122 and 142 are subsequently filled with conductive material to form a gate layer, the implementation method of forming a gate layer in this application is not limited to this. It can also be implemented by, for example, directly alternatingly stacking dielectric layers and gate layers made of conductive material.

[0065] In this step, the selection channel structure 150 can be formed, for example, using the specific process described below. First, a selection channel via can be formed in the selection stack structure 140 using, for example, a dry or wet etching process. This selection channel via can extend vertically through the storage channel structure 130 to expose the storage channel structure 130. Specifically, the selection channel via can expose the storage channel plug 133.

[0066] Furthermore, an insulating layer 151 can be formed on the inner wall of the select channel via using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, during the process of preparing the insulating layer 151, the insulating layer 151 can be formed on the surface of the select stack structure 140 away from the substrate 110. After the above processing, the portion of the insulating layer 151 located at the bottom of the select channel via can cover the exposed storage channel plug 133. Optionally, the material of the insulating layer 151 may include silicon oxide.

[0067] Furthermore, a portion of the insulating layer 151 located at the bottom of the select channel hole can be removed using, for example, a dry or wet etching process, to re-expose the storage channel plug 133, so that the insulating layer 151 only covers the sidewall of the select channel hole.

[0068] Furthermore, a conductive layer 152 can be formed on the surface where the insulating layer 151 is formed and on the surface at the bottom of the select channel via using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, during the process of preparing the conductive layer 152, the conductive layer 152 can be formed on the surface of the insulating layer 151 on the side of the select stack structure 140 away from the substrate 110. After the above processing, the conductive layer 152 can cover the inner wall of the select channel via and contact the storage channel plug 133, thereby forming an electrically coupled region with the storage channel plug 133. Optionally, the material of the conductive layer 152 may include doped polysilicon.

[0069] In some embodiments, a dielectric material can be filled into the selected channel vias where the insulating layer 151 and the conductive layer 152 are formed, using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, to form an insulating filling layer 153. Optionally, during the process of preparing the insulating filling layer 153, the insulating filling layer 153 can be formed on the surface of the conductive layer 152 on the side of the selected stack structure 140 away from the substrate 110. Optionally, the insulating filling layer 153 can be made of silicon oxide.

[0070] After the above-described process, the insulating layer 151 and conductive layer 152 corresponding to the sacrificial layer 142 in the selected channel structure 150 can form a top-select transistor. Using a MOS transistor structure for the top-select transistor can improve the stability of its threshold voltage and enhance its reliability.

[0071] In this step, multiple selection channel structures 150 can be formed in the selection stack structure 140 using the same process, and the positions of the selection channel structures 150 correspond one-to-one with the positions of the memory channel structures 130. In other words, the selection channel structures 150 are connected to their corresponding memory channel structures 130. Furthermore, on a plane parallel to the substrate 110, the size of the selection channel structure 150 is smaller than the size of its corresponding memory channel structure 130.

[0072] It should be understood that the outer shapes of the selection channel structure 150 and the storage channel structure 130 may include cylinders, prisms, or frustums, etc., and are not specifically limited herein. In some embodiments, the selection channel structure 150 and the sub-storage channel structure may be frustum structures. The critical dimension (CD) of the selection channel structure 150 and the sub-storage channel structure gradually decreases along the direction toward the substrate, and the maximum critical dimension of the selection channel structure 150 may be smaller than the maximum critical dimension of the sub-storage channel structure. For example, the maximum diameter of the selection channel structure 150 may be smaller than the maximum diameter of the sub-storage channel structure. After the above-described process, the space occupied by the selection channel structure 150 in the selection stack structure 140 can be reduced, thereby facilitating the provision of a larger process window for, for example, the top selection gate notch structure formed in the selection stack structure.

[0073] In some implementations, such as Figure 2C As shown, the fabrication method 1000 may include the step of forming a stop layer 143 at the end of the selected channel structure 150 away from the substrate 110. Specifically, a portion of the dielectric filling layer 153 in the selected channel structure 150 away from the substrate 110 and a portion of the selected stack structure 140 away from the substrate 110 may be removed using, for example, a dry or wet etching process to form a first recess exposing the conductive layer 152. The first recess may also be used to form a selected channel plug in a subsequent process, so that the first recess extends in the dielectric layer 141 in the selected stack structure 140 without extending into the sacrificial layer 142. Further, the stop layer 143 may be formed in the first recess using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. During the process of forming the stop layer 143, the stop layer 143 may be formed on the surface of the conductive layer 152 on the side of the selected stack structure 140 away from the substrate 110. The stop layer 143 may be made of, for example, silicon nitride.

[0074] In some implementations, such as Figure 2D As shown, portions of the stop layer 143, conductive layer 152, and insulating layer 151 located on the surface of the selective stack structure 140 away from the substrate 110 can be sequentially removed using, for example, etching or mechanical chemical polishing (CMP) processes to expose the selective stack structure 140. Further, a capping layer 144 can be formed on the side of the selective stack structure 140 away from the substrate 110 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to cover the stop layer 143 located in the selective channel structure 150 and the surface of the selective stack structure 140 away from the substrate 110. Optionally, the capping layer 144 can be made of, for example, silicon oxide.

[0075] In some embodiments, the method 1000 for fabricating a three-dimensional memory provided in this application may further include a step of performing a "gate replacement" operation.

[0076] In this step, such as Figure 2E As shown, a gate gap (not shown) extending vertically through the selectable stack structure 140 and the memory stack structure 120 and reaching the substrate 110 can be formed using, for example, dry or wet etching processes. Further, the gate gap formed after the above process can be used as a channel for the etchant, and a sacrificial layer 142 in the selectable stack structure 140 and the sacrificial layer 122 in the memory stack structure 120 can be removed using, for example, a wet etching process to form multiple sacrificial gaps. Further, conductive material can be filled into the sacrificial gaps using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof to form gate layers 123 and 145. Gate layers 123 and 145 can be fabricated using materials such as tungsten, cobalt, copper, aluminum, or doped crystalline silicon.

[0077] S130, forming a top selection gate cutout structure that penetrates the selection stack structure.

[0078] In step S130, as Figure 2F As shown, a top select gate notch penetrating the select stack structure 140 can be formed between adjacent channel structures 140 using, for example, dry or wet etching processes. Optionally, a top select gate notch penetrating the cap layer 144 to the dielectric layer 141 can be formed. Further, a dielectric material such as silicon oxide or silicon nitride can be deposited within the top select gate notch using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, thereby forming a top select gate notch structure 160. The top select gate notch structure 160 can divide the memory block formed by the array of select channel structures 150 and corresponding memory channel structures 130 into multiple sub-memory blocks, and can allow the gate layer 145 located in the select stack structure 140 to independently control the corresponding top select transistor, thereby enabling the fabricated three-dimensional memory to precisely control the desired sub-memory blocks, thereby effectively reducing programming, reading and erasing time and data transfer time, and improving data storage efficiency.

[0079] Figure 3 yes Figure 2F A top-view structural diagram of a three-dimensional memory. In some embodiments, such as... Figure 3As shown, multiple select channel structures 150 and corresponding memory channel structures 130 are arranged in staggered rows in a direction parallel to the y-axis of the substrate 110. A top select gate notch structure 160 can extend between adjacent rows of select channel structures. In other words, the top select gate notch structure 160 can extend in the y-axis direction. Optionally, the shape of the top select gate notch structure 160 in the plane parallel to the substrate 110, i.e., the xy plane, can be wavy. Setting the shape of the top select gate notch structure 160 in the plane planar with respect to the substrate 110 to wavy avoids overlapping areas between the select channel structures 130 and the top select gate notch structure 160, thereby increasing memory density.

[0080] It should be understood that the shape of the top selected gate cutout structure 160 on the plane parallel to the substrate 110, i.e., the xy plane, can also be other shapes, which are specifically defined herein.

[0081] Figure 4 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of this application. Figure 5 yes Figure 4 A top-view diagram of the three-dimensional memory structure. (See diagram below.) Figure 4 and Figure 5 As shown, during the process of forming the select channel structure 150, the select channel structures 150 in at least one select channel structure row (biased select channel structure row) located on both sides of the top select gate notch structure 160 can be offset relative to the corresponding memory channel structure 130 in a z-axis direction perpendicular to the substrate. This is such that the distance between the axis of the select channel structure 150 in at least one select channel structure row (biased select channel structure row) and the top select gate notch structure 160 is greater than the distance between the memory channel structure 130 connected to the select channel structure 150 and the top select gate notch structure 160. For example, when the number of select channel structure rows between adjacent top select gate notch structures 160 is four, the axes of the select channel structures 160 in the two select channel structure rows (biased select channel structure rows) located on both sides of the top select gate notch structure 160 are offset relative to the axis of the memory channel structure 130. This allows for an increase in the process window of the top selection gate cutout structure 160 without reducing the size of the selection channel structure 150 and the top selection gate cutout structure 160. It should be understood that this application does not specifically limit the number of selection channel structure rows between adjacent top selection gate cutout structures. Therefore, the number of selection channel structure rows with off-axis settings (offset selection channel structure rows) is not limited to 2. The process window of the top selection gate cutout structure can be increased when the number of selection channel structure rows (corresponding to the offset selection channel structure rows of any one of the top selection gate cutout structures) is less than or equal to half the number of selection channel structure rows between adjacent top selection gate cutout structures.

[0082] In some implementations, such as Figure 2F As shown, a capping layer 144 located on the side of the selected stack structure 140 away from the substrate 110 can also be removed using, for example, a CMP process. The stop layer 143 located at the end of the selected channel structure 150 away from the substrate 110 can stop the removal process here, thereby avoiding damage to the selected channel structure 150 during the process of removing the capping layer 144, which would affect the electrical performance of the fabricated three-dimensional memory.

[0083] In some embodiments, the method 1000 for fabricating a three-dimensional memory may further include the step of forming a select channel plug. In this step, the select channel plug may be formed at the end of the select channel structure 150 away from the substrate and in contact with the conductive layer 152.

[0084] Specifically, such as Figure 2G As shown, in this step, the stop layer 143, conductive layer 152, and insulating layer 151 corresponding to the stop layer 143 can be removed using, for example, a dry or wet etching process, to form a second recessed hole exposing the end face of the conductive layer 152. Further, the second recessed hole can be enlarged again using, for example, a dry or wet etching process, such that the size of the second recessed hole in the plane parallel to the substrate 110 is larger than the size of the selection channel structure 150 in the plane parallel to the substrate 110. Further, conductive material is filled into the second recessed hole to form a selection channel plug 154. The material of the selection channel plug 154 can be the same material used for the conductive layer 152. Enlarging the second recessed hole increases the landing area of ​​the selection channel plug located within it.

[0085] The method for fabricating a three-dimensional memory provided in this application increases the process window for the top selection gate cutout structure formed between the selection channel structures by fabricating the selection channel structure and the storage channel structure separately, and by making the critical dimension of the selection channel structure smaller than that of the storage channel structure. Furthermore, this fabrication method avoids increasing the distance between rows of storage channel structures or adding virtual storage channel structure rows, thereby improving the unit storage density.

[0086] In some embodiments, the three-dimensional memory formed after the above-described process can be flipped to perform the step of removing the substrate 110. In this step, the substrate 110 can be removed using, for example, dry or wet etching processes and CMP processes, to form an electrically coupled region contacting the channel layer 132 from the back side of the substrate 110. Optionally, after removing the substrate 110, the portion of the functional layer 131 extending into the substrate 110 in the memory channel structure 130 can be further removed to expose the channel layer 132. Further, on the side of the memory stack structure 120 away from the select stack structure 140, a semiconductor layer is formed surrounding the portion of the channel layer 132 extending from the memory stack structure 120, which can form an electrically coupled region with the channel layer 132.

[0087] This application also provides a three-dimensional memory. The three-dimensional memory can be obtained using any of the fabrication methods described in the above embodiments. The three-dimensional memory may include: a storage stack structure, a storage channel structure, a selection stack structure, a selection channel structure, and a top selection gate notch structure.

[0088] The memory channel structure may extend through the memory stack. The selection stack may be located on the memory stack, and the selection channel structure may extend through the selection stack and connect to the memory channel structure. In a plane parallel to the substrate, the size of the selection channel structure is smaller than the size of the memory channel structure. A top selection gate notch extends through the selection stack.

[0089] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0090] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory characterized by, include: Storage stack-up structure; Multiple storage channel structures penetrate the storage stack structure; Select a stacked structure, located on the storage stacked structure; The top selection grid cut-out structure extends through the selected stacked structure; as well as Multiple selection channel structures are provided, which penetrate the selection stack structure and are respectively connected to the multiple storage channel structures, wherein the multiple selection channel structures are arranged in rows along the extension direction of the top selection gate cutout structure, and the top selection gate cutout structure extends between adjacent rows of selection channel structures. Each side of the top select gate cutout structure has at least one offset select channel structure row, wherein the distance between the axis of the select channel structure in the offset select channel structure row and the top select gate cutout structure is greater than the distance between the axis of the storage channel structure to which it is connected and the top select gate cutout structure.

2. The three-dimensional memory of claim 1, wherein, The maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

3. The three-dimensional memory of claim 1, wherein, The selective channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

4. The three-dimensional memory of claim 3, wherein, Also includes: The select channel plug is located at the end of the select channel structure away from the storage channel structure and is in contact with the conductive layer, wherein the size of the select channel plug is larger than the size of the select channel structure in a stacking direction perpendicular to the selection stack and the storage stack.

5. The three-dimensional memory of claim 1, wherein, There are multiple rows of selection channel structures between adjacent top selection gate cutout structures, wherein the number of offset selection channel structure rows located between adjacent top selection gate cutout structures is less than or equal to the number of the multiple selection channel structure rows.

6. The three-dimensional memory according to claim 5, characterized in that, In the offset selection channel structure rows located between adjacent top selection gate cutout structures, the number of offset selection channel structure rows in which the distance between the axis of the selection channel structure and one of the adjacent top selection gate cutout structures is greater than the distance between the axis of the storage channel structure connected to the selection channel structure and the top selection gate cutout structure is equal to the number of offset selection channel structure rows in which the distance between the axis of the selection channel structure and another of the adjacent top selection gate cutout structures is greater than the distance between the axis of the storage channel structure connected to the selection channel structure and the top selection gate cutout structure.

7. The three-dimensional memory as recited in claim 1, further comprising: The cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

8. A three-dimensional memory characterized by, include: Storage stack-up structure; Multiple storage channel structures penetrate the storage stack structure; Select a stacked structure, located on the storage stacked structure; The top selection grid cut-out structure extends through the selected stacked structure; as well as Multiple selection channel structures are provided, which penetrate the selection stack structure and are respectively connected to the multiple storage channel structures, wherein the multiple selection channel structures are arranged in rows along the extension direction of the top selection gate cutout structure, and the top selection gate cutout structure extends between adjacent rows of selection channel structures. Each side of the top select gate cutout structure has at least one offset select channel structure row, wherein the select channel structure in the offset select channel structure row is offset away from the top select gate cutout structure relative to the storage channel structure connected thereto.

9. The three-dimensional memory as recited in claim 8, further comprising, The maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

10. The three-dimensional memory of claim 8, wherein, The selective channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

11. The three-dimensional memory as recited in claim 10, further comprising: Also includes: The select channel plug is located at the end of the select channel structure away from the storage channel structure and is in contact with the conductive layer, wherein the size of the select channel plug is larger than the size of the select channel structure in a stacking direction perpendicular to the selection stack and the storage stack.

12. The three-dimensional memory according to claim 8, characterized in that, There are multiple rows of selection channel structures between adjacent top selection gate cutout structures, wherein the number of offset selection channel structure rows located between adjacent top selection gate cutout structures is less than or equal to the number of the multiple selection channel structure rows.

13. The three-dimensional memory according to claim 12, characterized in that, In the offset selection channel structure rows located between adjacent top selection gate cutout structures, the number of offset selection channel structure rows in which the selection channel structure is offset away from one of the adjacent top selection gate cutout structures relative to the storage channel structure it is connected to is equal to the number of offset selection channel structure rows in which the selection channel structure is offset away from the other of the adjacent top selection gate cutout structures relative to the storage channel structure it is connected to.

14. The three-dimensional memory according to claim 8, characterized in that, The cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

15. A three-dimensional memory, characterized in that, include: Storage stack-up structure; A storage channel structure extends through the storage stack structure; Select a stacked structure, located on the storage stacked structure; Select a channel structure that extends through the selected stacked structure and connects to the storage channel structure; as well as A top selection gate cutout structure extends through the selection stack structure, wherein the top selection gate cutout structure extends between adjacent rows of selection channel structures, and the distance between the axes of the selection channel structures adjacent to both sides of the top selection gate cutout structure along the arrangement direction of the top selection gate cutout structure is greater than the distance between the axes of the storage channel structures respectively connected to the selection channel structure.

16. The three-dimensional memory according to claim 15, characterized in that, The maximum critical dimension of the selected channel structure is smaller than the maximum critical dimension of the storage channel structure.

17. The three-dimensional memory according to claim 15, characterized in that, The selective channel structure includes: a dielectric core and a conductive layer and an insulating layer sequentially surrounding the dielectric core, wherein the conductive layer is in contact with the storage channel structure.

18. The three-dimensional memory according to claim 17, characterized in that, Also includes: The select channel plug is located at the end of the select channel structure away from the storage channel structure and is in contact with the conductive layer, wherein the size of the select channel plug is larger than the size of the select channel structure in a stacking direction perpendicular to the selection stack and the storage stack.

19. The three-dimensional memory according to claim 15, characterized in that, Multiple selection channel structures are arranged in rows along the extension direction of the top selection gate cutout structure, with the multiple selection channel structure rows arranged between adjacent top selection gate cutout structures.

20. The three-dimensional memory according to claim 15, characterized in that, The cross-sectional shape of the top selection gate cutout structure in the direction perpendicular to the stacking direction of the selection stack and the storage stack includes a wavy shape.

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