Error voltage elimination modulation method for hybrid device three-level split output inverter

Abstract

The present invention discloses a hybrid device three-level split output inverter error voltage elimination modulation method. The Si IGBT in the main circuit works at a low switching frequency, the SiC MOSFET works at a high switching frequency of 100kHz, and the SiC SBD D a2 and D a3 Used for current follow-up, the isolation inductor isolates and separates the SiC MOSFET. In the error voltage elimination modulation method, the upper and lower stacked carriers are compared with the three-phase modulation wave input to the pulse generation module, the pulse generation module outputs the initial drive signal, and the error voltage elimination module outputs the drive signal. The low-pass filter filters out the high-frequency current harmonics in the output current to obtain the output current fundamental wave. According to the polarity of the modulation wave and the fundamental current, it is divided into 4 intervals for modulation. The hybrid device three-level split output inverter error voltage elimination modulation method proposed in the present invention can eliminate the error voltage caused by the opening delay of the traditional modulation method, improve the utilization rate of the DC voltage, and reduce the output current harmonics.

Description

Technical Field

[0001] The invention belongs to the field of new energy power conversion, relates to a modulation technology of an inverter, and specifically refers to a hybrid device three-level split output inverter error voltage elimination modulation method. Background Art

[0002] With the advancement of new energy generation technology and the rapid development of power electronic devices, the proportion of clean energy represented by wind power generation and photovoltaic power generation is increasing. As the core component of wind and photovoltaic power generation, the performance of the inverter directly affects the output power quality. However, after a long period of development, the performance of the traditional silicon insulated gate bipolar transistor (Silicon Insulated Gate Bipolar Transistor, Si IGBT) is almost close to the theoretical limit and can no longer meet the development requirements of high efficiency, high power density and high reliability. In recent years, the silicon carbide metal-oxide-semiconductor field-effect transistor (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor, SiCMOSFET) can increase the switching frequency of the converter to 100kHz due to its excellent material characteristic properties, breaking through the performance polarity of the Si IGBT inverter.

[0003] In the traditional hybrid device three-level inverter, both SiC IGBT and SiC MOSFET are used to combine the advantages of both. However, there are two disadvantages in the traditional hybrid device three-level inverter. First, if the traditional modulation method is adopted, the drive pulse adopts the opening delay to avoid the dead zone effect, but it will generate an error voltage, reduce the utilization rate of the DC bus voltage, and cause the output current distortion to contain a large number of harmonics. Second, there is an influence between SiC MOSFETs, which is prone to the risk of direct short circuit, weakening its advantage of high switching frequency. Summary of the invention

[0004] The purpose of the present invention is to provide a hybrid device three-level split output inverter error voltage elimination modulation method in view of the above technical problems. On the one hand, the error voltage caused by the turn-on delay of the traditional modulation method is eliminated, the DC voltage utilization rate is improved, and the output current harmonics are reduced; on the other hand, the SiC MOSFET is separated by an isolation inductor to prevent mutual influence and avoid the risk of direct short circuit.

[0005] The present invention is implemented by the following technical scheme: an error voltage elimination modulation method of a hybrid device three-level split output inverter, the main circuit includes three phases A, B, and C, taking the A phase main circuit as an example, Si IGBT Q a1 , Q a4 , Qa5 , Q a6 Operating at low switching frequency; SiC MOSFET Q a2 and Q a3 Works at 100kHz high switching frequency; SiC SBD D a2 and D a3 Used for current follow-up. Isolation inductor L a1 , L a2 For SiC MOSFET Q a2 and Q a3 Isolate and separate.

[0006] In the error voltage elimination modulation method, the upper and lower stacked carriers C 1 , C 2 The modulation wave u of phase A, phase B, and phase C a * 、u b * 、u c * Input to the pulse generation module for comparison; the pulse generation module outputs the initial drive signal S a1 ~S a6 , S b1 ~S b6 , S c1 ~S c6 ; The error voltage elimination module outputs the driving signal S a1 * ~S a6 * , S b1 * ~S b6 * , S c1 * ~S c6 * , used to drive SiIGBT and SiC MOSFET Q respectively a1 ~Q a6 , Q b1 ~Q b6 , Q c1 ~Q c6 ; Low-pass filter L(s) will output current i a1 The high-frequency current harmonics in the filter are removed to obtain the output current fundamental wave i a1 * .

[0007] Preferably, in the A-phase main circuit, the upper and lower DC bus capacitors C dc1 With C dc2 Connect vertically, forming a DC bus with the midpoint of O as point; C dc1 The anode and Q a1Connected together to the positive pole of the DC bus, point P, C dc2 The cathode and Q a4 They are connected together to the negative pole of the DC bus, point N. a1 , Q a4 , Q a5 , Q a6 Connect vertically in sequence, Q a1 With Q a5 The connection point is x a1 Point, Q a5 With Q a6 The connection point of is further connected with point O, Q a6 With Q a4 The connection point is x a2 Point; Q a2 With D a3 Connect vertically in sequence, the connection point is x a3 Point; D a2 With Q a3 Connect vertically in sequence, the connection point is x a4 Point. L a1 One end is connected to x a3 Point, L a2 One end is connected to x a4 Point, L a1 With L a2 The other ends are connected to form x a5 Point. x a5 Point A and then the inductance L a 、A phase current sensor M a , load resistance R a Connect in sequence.

[0008] Preferably, the transfer function of L(s) is:

[0009]

[0010] Preferably, in the pulse generation module, the A phase modulation wave u a * Compared with 0, on the one hand, if u a * >0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is low level. On the other hand, if u a * ≤0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is high level; A phase modulation wave u a * With upper carrier C1 Compare and obtain the upper temporary driving signal S a3 + , and download wave C 2 Compare and obtain the temporary drive signal S a3 At the same time, the selection switch Sel is used to modulate the A phase modulated wave u a * Compared with 0, if u a * >0, then S a3 =S a3 + , S a3 After the logic inversion of the "NOT" module, S is generated. a2 ; if u a * ≤0, then S a3 =S a3 - , S a3 After the logic inversion of the "NOT" module, S is generated. a2 .

[0011] Preferably, in the error voltage elimination module, the initial drive signal S a1 , S a6 , S a4 , S a5 Generate S through the "On Delay" module a1 * , S a6 * , S a4 * , S a5 * ; Output current fundamental wave i a1 * Compared with 0; on the one hand, if i a * >0, then S a2 ' is high level, and S a2 Perform AND operation to generate S a2 * ; if i a * ≤0, then S a2 ' is low level, and S a2 Perform AND operation to generate S a2 * On the other hand, if i a * ≤0, then S a3 ' is high level, and S a2 Perform AND operation to generate S a3 * ; if i a *>0, then S a3 ' is low level, and S a3 Perform AND operation to generate S a3 * .

[0012] Preferably, when the error voltage elimination modulation method A phase driving pulse is generated, according to u a * and i a * The polarity is divided into 4 intervals to generate different drive pulses:

[0013] 1) When u a * >0、i a * <0, A phase modulation u a * With upper carrier C 1 Compare. When u a * >C 1 When S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =1,

[0014] S a2 =0, S a4 =0, S a5 =0, S a6 =1;

[0015] 2) When u a * >0、i a * >0, A phase modulation u a * With upper carrier C 1 Compare. When u a * >C 1 When S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =1,

[0016] S a3 =0, S a4 =0, S a5 =0, S a6 =1;

[0017] 3) When ua * <0,i a * >0, A phase modulation u a * Download Wave C 2 Compare. When u a * >C 2 When S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =0,

[0018] S a3 =0, S a4 =1, S a5 =1, S a6 =0;

[0019] 4) When u a * <0,i a * <0, A phase modulation u a * Download Wave C 2 Compare. When u a * >C 2 When S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =0,

[0020] S a2 =0, S a4 =1, S a5 =1, S a6 =0.

[0021] The beneficial effects of the present invention compared with the prior art are:

[0022] 1) The hybrid device three-level split output inverter error voltage elimination modulation method proposed in the present invention can eliminate the error voltage caused by the turn-on delay of the traditional modulation method, improve the DC voltage utilization rate, and reduce the output current harmonics;

[0023] 2) The error voltage elimination modulation method of the hybrid device three-level split output inverter proposed by the present invention is based on u a * and i a *The polarity is divided into 4 intervals for modulation, the principle is clear and the implementation is convenient;

[0024] 3) The hybrid device three-level split output inverter proposed in the present invention separates SiC MOSFETs through isolation inductors to prevent mutual influence and avoid the risk of direct short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is the main circuit of the three-level split output inverter of the hybrid device;

[0026] Figure 2 The system block diagram of the error voltage elimination modulation method is shown;

[0027] Figure 3 This is the schematic diagram of the pulse generation module;

[0028] Figure 4 This is the schematic diagram of the error voltage elimination module;

[0029] Figure 5a for u a * >0、i a * <0 error voltage elimination modulation method A phase drive pulse generation principle diagram;

[0030] Figure 5b for u a * >0、i a * >0 error voltage elimination modulation method A phase drive pulse generation principle diagram;

[0031] Figure 5c for u a * <0,i a * >0 error voltage elimination modulation method A phase drive pulse generation principle diagram;

[0032] Figure 5d for u a * <0,i a * <0 error voltage elimination modulation method A phase drive pulse generation principle diagram;

[0033] Figure 6 Output current waveform of a hybrid device three-level split output inverter using a conventional modulation method;

[0034] Figure 7 Output current waveform of a hybrid device three-level split-output inverter using error voltage elimination modulation method. DETAILED DESCRIPTION

[0035] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0036] Take the A-phase main circuit as an example to explain the components of the main circuit and their connection methods. Figure 1 As shown, C dc1 , C dc2 They are the upper and lower DC bus capacitors respectively; Q a1 , Q a4 , Q a5 , Q a6 Si IGBT, low switching frequency, auxiliary inverter output three levels; Q a2 and Q a3 SiC MOSFET, operating at a high switching frequency of 100kHz; D a2 and D a3 It is a SiC Schottky Barrier Diode (SBD) used for current follow-up. a1 , L a2 As an isolation inductor, it is used to connect the SiC MOSFETQ a2 and Q a3 Isolate and separate them to avoid mutual interference and the risk of direct short circuit. a A phase current sensor, used to detect the A phase output current i a . R a is the load resistance, L a is the load inductance.

[0037] Continue to see Figure 1 , C dc1 With C dc2 Connect vertically, forming a DC bus with the midpoint of O as point; C dc1 The anode and Q a1 Connected together to the positive pole of the DC bus, point P, C dc2 The cathode and Q a4 They are connected together to the negative pole of the DC bus, point N. a1 , Q a4 , Q a5 , Q a6 Connect vertically in sequence, Q a1 With Q a5 The connection point is x a1 Point, Q a5 With Q a6 The connection point of is further connected with point O, Q a6 With Q a4 The connection point is x a2 Point; Qa2 With D a3 Connect vertically in sequence, the connection point is x a3 Point; D a2 With Q a3 Connect vertically in sequence, the connection point is x a4 Point. L a1 One end is connected to x a3 Point, L a2 One end is connected to x a4 Point, L a1 With L a2 The other ends are connected to form x a5 Point. x a5 Point A and then the inductance L a 、A phase current sensor M a , load resistance R a Connect in sequence.

[0038] Figure 1 In the hybrid device three-level split output inverter main circuit shown, the devices of phase B and phase C and their connection method are the same as those of the phase A main circuit, and will not be repeated here.

[0039] See also Figure 2 , in the error voltage elimination modulation method system block diagram, C 1 and C 2 are the upper and lower stacked carriers respectively; u a * 、u b * 、u c * is the modulation wave of phase A, phase B, and phase C; S a1 ~S a6 , S b1 ~S b6 , S c1 ~S c6 The initial driving signal output by the pulse generation module; S a1 * ~S a6 * , S b1 * ~S b6 * , S c1 * ~S c6 * The drive signals output by the error voltage elimination module are used to drive Si IGBT and SiC MOSFET Q respectively. a1 ~Q a6 , Q b1 ~Q b6 , Q c1 ~Qc6 If the drive signal is high, the Si IGBT or SiC MOSFET is turned on, otherwise the Si IGBT or SiC MOSFET is turned off. L(s) is a low-pass filter that converts the output current i a1 The high-frequency current harmonics in the filter are removed to obtain the output current fundamental wave i a1 * , and then obtain the accurate current direction. The transfer function of L(s) is shown in formula (1).

[0040]

[0041] Pulse generation module see Figure 3 , still taking phase A as an example for explanation. The initial drive signal S a1 , S a6 , S a4 , S a5 The generation method of A phase modulation wave u a * Compare with 0. On the one hand, if u a * >0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is low level; on the other hand, if u a * ≤0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is high level.

[0042] Continue to see Figure 3 , initial driving signal S a2 , S a3 The generation of needs to rely on the selection switch Sel. The selection switch Sel contains 4 terminals, 1, 2, 3 are input terminals, and 4 is an output terminal; when the signal of terminal 2 is greater than 0, terminal 4 will be connected to terminal 1; when the signal of terminal 2 is less than or equal to 0, terminal 4 will be connected to terminal 3. Terminal 1 of the selection switch Sel is connected to the upper temporary drive signal S a3 + Connect, terminal 2 to phase A modulation wave u a * Connect, terminal 3 and the lower temporary drive signal S a3 - Connect the No. 4 terminal to the initial drive signal S a3 connect.

[0043] Continue to see Figure 3 , initial driving signal Sa2 , S a3 The generation process of is as follows. First, the A phase modulation wave u a * With upper carrier C 1 Compare and obtain the upper temporary driving signal S a3 + , and download wave C 2 Compare and obtain the temporary drive signal S a3 - At the same time, the selection switch Sel is used to change the A phase modulation wave u a * Compared with 0, if u a * >0, then S a3 =S a3 + , S a3 After the logic inversion of the "NOT" module, S is generated. a2 ; if u a * ≤0, then S a3 =S a3 - , S a3 After the logic inversion of the "NOT" module, S is generated. a2 .

[0044] See also Figure 4 In the error voltage elimination module schematic, the initial drive signal S a1 , S a6 , S a4 , S a5 Generate S through the "OnDelay" module a1 * , S a6 * , S a4 * , S a5 * . The output current fundamental wave i a1 * Compare with 0. On the one hand, if i a * >0, then S a2 ' is high level, and S a2 Perform AND operation to generate S a2 * ; if i a * ≤0, then S a2 ' is low level, and S a2 Perform AND operation to generate S a2 * On the other hand, if i a *≤0, then S a3 ' is high level, and S a2 Perform AND operation to generate S a3 * ; if i a * >0, then S a3 ' is low level, and S a3 Perform AND operation to generate S a3 * .

[0045] The above describes in detail the A phase drive signal S a1 * ~S a6 * The generation process of the B-phase and C-phase drive signals S b1 * ~S b6 * , S c1 * ~S c6 * The generation process is the same and will not be repeated here.

[0046] To explain the principle of phase A drive pulse generation in the error voltage elimination modulation method in more detail, according to u a * and i a * The polarity of is divided into 4 intervals: 1) u a * >0、i a * <0,2)u a * >0、i a * >0,3)u a * <0,i a * >0,4)u a * <0,i a * <0. The method for generating the driving pulse in each interval is described as follows:

[0047] 5) See Figure 5a , when u a * >0、i a * <0, A phase modulation u a * With upper carrier C 1 Compare. When u a * >C 1When S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =1, S a2 =0, S a4 =0, S a5 =0, S a6 =1.

[0048] 6) See Figure 5b , when u a * >0、i a * >0, A phase modulation u a * With upper carrier C 1 Compare. When u a * >C 1 When S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =1, S a3 =0, S a4 =0, S a5 =0, S a6 =1.

[0049] 7) See Figure 5c , when u a * <0,i a * >0, A phase modulation u a * Download Wave C 2 Compare. When u a * >C 2 When S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =0, S a3 =0, S a4 =1, S a5 =1, S a6 =0.

[0050] 8) See Figure 5d , when u a * <0,i a* <0, A phase modulation u a * Download Wave C 2 Compare. When u a * >C 2 When S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =0, S a2 =0, S a4 =1, S a5 =1, S a6 =0.

[0051] In order to verify the proposed hybrid device three-level split output inverter error voltage elimination modulation method, simulation verification is carried out in Matlab / Simulink. The DC bus voltage is 600V, and the upper and lower DC bus capacitors C dc1 , C dc2 are 2200μF, load resistance R a is 33.3Ω, load inductance L a 1mH. Si IGBT Q a1 , Q a4 , Q a5 , Q a6 The switching frequency of SiC MOSFET Q is set to 50Hz; a2 and Q a3 The switching frequency is set to 100kHz. In the simulation model, the conventional modulation method and the error voltage elimination modulation method proposed in the present invention are respectively used for the hybrid device three-level split output inverter. The turn-on delay time of the conventional modulation method is set to 1μs. Figure 6 , the output current waveform of the traditional modulation method is seriously distorted. Through Fourier analysis, the three-phase current THD is 4.6%. Figure 7 The output current waveform of the error voltage elimination modulation method has good sinusoidality. Through Fourier analysis, the three-phase current THD is 1.3%. Figure 6 and Figure 7 This shows that the error voltage elimination modulation method proposed in the present invention can effectively suppress the output current harmonics of the hybrid device three-level split output inverter and improve the output power quality.

[0052] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A hybrid device three-level split output inverter error voltage elimination modulation method, characterized in that: The main circuit consists of three phases A, B, and C. Taking the A phase main circuit as an example, Si IGBT Q a1 , Q a4 , Q a5 , Q a6 Working at low switching frequency; SiCMOSFET Q a2 and Q a3 Works at 100kHz high switching frequency; SiC SBD D a2 and D a3 Used for current follow-up; isolation inductor L a1 , L a2 For SiC MOSFET Q a2 and Q a3 Isolation and separation; in the A-phase main circuit, the upper and lower DC bus capacitors C dc1 With C dc2 Vertical connection, C dc1 The negative electrode and C dc2 The positive pole of the DC bus is connected to form a DC bus with the midpoint of O; C dc1 The positive electrode and Q a1 The collectors of the two terminals are connected to the positive pole of the DC bus, point P. dc2 The cathode and Q a4 The emitters of Q are connected to the negative pole of the DC bus, point N; a1 The emitter and Q a5 The collector connection, Q a5 The emitter and Q a6 The collector connection, Q a6 The emitter and Q a4 Collector connection, Q a1 With Q a5 The connection point is x a1 Point, Q a5 With Q a6 The connection point of is further connected with point O, Q a6 With Q a4 The connection point is x a2 Point; Q a2 The drain and x a1 Connect the dots, D a3 The anode and x a2 Connect the dots, Q a2 The source and D a3 The cathode connection of a3 Point; D a2 The cathode and x a1 Connect the dots, Q a3 The source and x a2 Connect the dots, D a2 The anode and Q a3 The drain connection of a4 Point; L a1 One end is connected to x a3 Point, L a2 One end is connected to x a4 Point, L a1 With L a2 The other ends are connected to form x a5 point; x a5 Point A and then the inductance L a 、A phase current sensor M a , load resistance R a Connect in sequence; in the error voltage elimination modulation method, the upper and lower stacked carriers C1, C2 and the modulation waves u of phase A, phase B, and phase C a * 、u b * 、u c * The input is compared to the pulse generation module, and the initial driving signal output by the pulse generation module is S a1 ~S a6 , S b1 ~S b6 , S c1 ~S c6 ; Part of the input signal of the error voltage elimination module comes from the output current fundamental wave i obtained by the low-pass filter L(s) a1 * 、i b1 * 、i c1 * The other part comes from the initial driving signal S output by the pulse generation module. a1 ~S a6 , S b1 ~S b6 , S c1 ~S c6 ; The output signal of the error voltage elimination module is S a1 * ~S a6 * , S b1 * ~S b6 * , S c1 * ~S c6 * ; S a1 * ~S a6 * , S b1 * ~S b6 * , S c1 * ~S c6 * Used to drive Si IGBT and SiC MOSFET Q respectively a1 ~Q a6 , Q b1 ~Q b6 , Q c1 ~Q c6 ; If the drive signal is high, the Si IGBT or SiC MOSFET is turned on, otherwise the Si IGBT or SiC MOSFET is turned off; The low-pass filter L(s) outputs the current i a1 、i b1 、i c1 The high-frequency current harmonics in the filter are removed to obtain the output current fundamental wave i a1 * 、i b1 * 、i c1 * , and then obtain the accurate current direction; in the error voltage elimination module, the initial drive signal S a1 , S a6 , S a4 , S a5 Generate S through the "On Delay" module a1 * , S a6 * , S a4 * , S a5 * ; Output current fundamental wave i a1 * Compared with 0; on the one hand, if i a * >0, then S a2 ' is high level, and S a2 Perform AND operation to generate S a2 * ; if i a * ≤0, then S a2 ' is low level, and S a2 Perform AND operation to generate S a2 * On the other hand, if i a * ≤0, then S a3 ' is high level, and S a2 Perform AND operation to generate S a3 * ; if i a * >0, then S a3 ' is low level, and S a3 Perform AND operation to generate S a3 * .

2. The hybrid device three-level split output inverter error voltage elimination modulation method according to claim 1, characterized in that: The transfer function of L(s) is:

3. The hybrid device three-level split output inverter error voltage elimination modulation method according to claim 1, characterized in that: In the pulse generation module, the A phase modulation wave u a * Compared with 0, on the one hand, if u a * >0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is low level. On the other hand, if u a * ≤0, then S a1 and S a6 At the same time, S a4 and S a5 At the same time, it is high level; A phase modulation wave u a * Compare with the upper carrier C1 to obtain the upper temporary drive signal S a3 + , compared with the download wave C2 to obtain the temporary drive signal S a3 At the same time, the selection switch Sel is used to modulate the A phase modulated wave u a * Compared with 0, if u a * >0, then S a3 =S a3 + , S a3 The "NOT" module generates S by logical inversion. a2 ; if u a * ≤0, then S a3 =S a3 - , S a3 The "NOT" module generates S by logical inversion. a2 .

4. The hybrid device three-level split output inverter error voltage elimination modulation method according to claim 1, characterized in that: Error voltage elimination modulation method When the A phase drive pulse is generated, according to u a * and i a * The polarity is divided into 4 intervals to generate different drive pulses: 1) When u a * >0、i a * <0, A phase modulation u a * Compared with the upper carrier C1; when u a * >C1, S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =1, S a2 =0、S a4 =0、S a5 =0、S a6 =1; 2) When u a * >0、i a * >0, A phase modulation u a * Compared with the upper carrier C1; when u a * >C1, S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =1, S a3 =0、S a4 =0、S a5 =0、S a6 =1; 3) When u a * <0,i a * >0, A phase modulation u a * Compared with the download wave C2; ​​when u a * >C2, S a2 * is high level, otherwise S a2 * The other 5 drive signals maintain a fixed level: S a1 =0, S a3 =0、S a4 =1、S a5 =1、S a6 =0; 4) When u a * <0,i a * <0, A phase modulation u a * Compared with the download wave C2; ​​when u a * >C2, S a3 * is high level, otherwise S a3 * The other 5 drive signals maintain a fixed level: S a1 =0, S a2 =0、S a4 =1、S a5 =1、S a6 =0。

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