Group iii nitride based radio frequency amplifier

Abstract

An RF amplifier is provided that includes an interconnect structure (270) and a Group III-nitride based RF amplifier die (210) mounted on top of the interconnect structure. The Group III-nitride based RF amplifier die includes a semiconductor layer structure (230). A plurality of unit cell transistors are disposed in an upper portion of the semiconductor layer structure, and a gate terminal (222), a drain terminal (224), and a source terminal (226) are disposed on a lower surface of the semiconductor layer structure adjacent to the interconnect structure.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application Serial No. 63 / 004,962, filed April 3, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to microelectronic devices, and more particularly to Group III nitride-based radio frequency (“RF”) amplifiers. BACKGROUND

[0004] RF amplifiers are widely used in cellular communication systems and other applications. RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide bandgap semiconductor materials such as silicon carbide (“SiC”) and Group III nitride materials. As used herein, the term “Group III nitride” refers to those semiconductor compounds formed between nitrogen and elements of Group III of the periodic table, which are typically aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of Group III elements.

[0005] Silicon-based RF amplifiers are typically implemented using laterally diffused metal oxide semiconductor (“LDMOS”) transistors. Silicon LDMOS RF amplifiers can exhibit high levels of linearity and can be relatively inexpensive to manufacture. Group III nitride-based RF amplifiers are typically implemented using high electron mobility transistors (“HEMTs”) and are primarily used in applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers can have inherent performance limitations.

[0006] RF amplifiers can include one or more amplification stages, each typically implemented as a transistor amplifier. To increase output power and current handling capability, RF amplifiers are typically implemented in a “unit cell” configuration in which a large number of individual “unit cell” transistors are arranged in electrical parallel. RF amplifiers can be implemented as a single integrated circuit chip or “die,” or can include multiple dies. When multiple RF amplifier dies are used, they can be connected in series and / or in parallel.

[0007] RF amplifiers often include matching circuits such as impedance matching circuits designed to improve impedance matching between the RF amplifier die and transmission lines connected thereto for RF signals at the fundamental operating frequency and harmonic termination circuits designed to at least partially terminate harmonics such as second and third order harmonics that can be generated during device operation. The RF amplifier die(s) and impedance matching and harmonic termination circuits can be encapsulated in a package. Electrical leads can extend from the package for electrically connecting the RF amplifier to external circuit elements such as input and output RF transmission lines and bias voltage sources.

[0008] As noted above, Group III nitride-based RF amplifiers are often used in high power and / or high frequency applications. Typically, a significant amount of heat is generated within the Group III nitride-based RF amplifier die(s) during operation. If the RF die(s) become too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) can degrade and / or the RF amplifier die(s) can be damaged. As such, Group III nitride-based RF amplifiers are typically mounted in a package that can be optimized for heat removal. FIG. 1A and FIG. 1B A conventional packaged Group III nitride-based RF amplifier is illustrated. In particular, FIG. 1A is a schematic side view of a conventional packaged Group III nitride-based RF amplifier 100, and FIG. 1B is a schematic cross-sectional view of an RF transistor amplifier die included in the packaged Group III nitride-based RF transistor amplifier 100, where the cross-section is taken along the line 1B-1B of FIG. 1A It should be appreciated that FIGS. 1A-1B (and various other figures) are highly simplified diagrams and actual RF amplifiers can include more unit cells and various circuitry and elements not shown in the simplified diagrams herein.

[0009] As FIG. 1AAs shown in the middle, the Group III nitride-based RF amplifier 100 includes an RF amplifier die 110 mounted within an open cavity package 170. The package 170 includes a gate lead 172, a drain lead 174, a metal flange 176, and ceramic sidewalls and lid 178. The RF transistor amplifier die 110 is mounted on an upper surface of the metal flange 176 in a cavity formed by the metal flange 176 and the ceramic sidewalls and lid 178. The RF amplifier die 110 has a top side 112 and a bottom side 114. The RF amplifier die 110 includes a bottom side (also referred to as a “back” side) metallization structure 120, a semiconductor layer structure 130, and a top side metallization structure 140 stacked in order. The back side metallization structure 120 includes a source terminal 126. The RF amplifier 100 can be a HEMT-based RF amplifier, in which case the semiconductor layer structure 130 can include at least a channel layer and a barrier layer, which are typically formed on a semiconductor or insulating growth substrate such as a SiC or sapphire substrate. The top side metallization structure 140 includes, among other things, a gate terminal 142 and a drain terminal 144.

[0010] An input matching circuit 190 and / or an output matching circuit 192 can also be mounted within the housing 170. The matching circuits 190, 192 can be impedance matching circuits that match the impedance of a fundamental component of an RF signal input to or output from the RF transistor amplifier 100 to the impedance at the input or output of the RF transistor amplifier die 110, respectively, and / or harmonic termination circuits configured to short to ground harmonics of the fundamental frequency RF signal that can be present at the input or output of the RF transistor amplifier die 110, such as second or third order harmonics. As shown in the bottom, the input matching circuit 190 includes a first inductor 191 and a first capacitor 193, and the output matching circuit 192 includes a second inductor 195 and a second capacitor 197. FIG. 1AAs shown schematically, the input and output matching circuits 190, 192 can be mounted on the metal flange 176. The gate lead 172 can be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 can be connected to the gate terminal 142 of the RF amplifier die 110 by one or more second bond wires 183. Similarly, the drain lead 174 can be connected to the output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 can be connected to the drain terminal 144 of the RF amplifier die 110 by one or more third bond wires 184. The source terminal 126 of the RF transistor amplifier die 110 can be mounted directly on the metal flange 176. The metal flange 176 can provide an electrical connection to the source terminal 126 and can also act as a heat dissipation structure. The first through fourth bond wires 182-185 can form part of the input and / or output matching circuits. The gate lead 172 and the drain lead 174 can extend through the ceramic side wall 178. The housing can include multiple components, such as a frame that forms the lower portion of the side wall and supports the gate and drain leads 172, 174, and a lid that is placed on top of the frame. The interior of the device can include a plenum.

[0011] FIG. 1B is a schematic cross-sectional view of the RF amplifier die 110 taken through a portion of the top side metallization structure 140. In FIG. 1B the dielectric layers that isolate the various conductive elements of the top side metallization structure 140 from one another are not shown to simplify the drawing.

[0012] As shown in FIG. 1B the RF amplifier die 110 includes a Group III Nitride-based HEMT RF amplifier having a plurality of unit cell transistors 116, each of which includes a gate finger 152, a drain finger 154, and a source finger 156. The gate fingers 152 are electrically connected to a common gate bus 146, and the drain fingers 154 are electrically connected to a common drain bus 148. The gate bus 146 is electrically connected to the gate terminal 142 (see FIG. 1A , implemented as a gate bond pad (see FIG. 1A , implemented as a drain bond pad (see

[0013] Referring again to FIG. 1AThe metal flange 176 can act as a heat spreader for dissipating heat generated in the RF transistor amplifier die 110. The heat is generated primarily in the upper portion of the RF transistor amplifier die 110, where relatively high current densities are generated in, for example, the channel region of the unit cell transistors 116. This heat can be transferred through both the source via 166 and the semiconductor layer structure 130 to the metal flange 176.

[0014] FIG. 1C is a schematic side view of a conventional packaged Group III nitride-based RF transistor amplifier 100' that is similar to the RF transistor amplifier discussed above with reference to FIG. 1A The RF transistor amplifier 100' differs from the RF transistor amplifier 100 in that it includes a different package 170'. The package 170' includes a metal base 176 (which acts as a metal heat spreader and can be implemented as a block of metal) and gate and drain leads 172', 174'. In some embodiments, a metal lead frame can be formed and then processed to provide the metal base 176 and / or the gate and drain leads 172', 174'. The RF transistor amplifier 100' also includes a plastic overmold 178' that at least partially surrounds the RF transistor amplifier die 110, the leads 172', 174', and the metal base 176. The plastic overmold 178' replaces the ceramic sidewalls and lid 178 included in the RF transistor amplifier 100.

[0015] Depending on the embodiment, the packaged transistor amplifier 100' can include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die 110, in which case the RF transistor amplifier die 110 incorporates multiple discrete devices. An example of such a Group III nitride-based RF amplifier is disclosed in U.S. Patent No. 9,947,616, the entire contents of which are incorporated herein by reference. When the RF transistor amplifier die 110 is a MMIC implementation, the input matching circuit 190 and / or the output matching circuit 192 can be omitted (as they can instead be implemented within the RF transistor amplifier die 110) and the bond wires 182 and / or 185 can extend directly from the gate and drain leads 172', 174' to the gate and drain terminals 142, 144. In some embodiments, the packaged RF transistor amplifier 100 can include multiple RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier and / or can include multiple transistor dies deployed in multiple paths (e.g., in parallel) to form an RF transistor amplifier with multiple RF transistor amplifier dies and multiple paths, such as in a Doherty amplifier configuration. SUMMARY

[0016] According to embodiments of the present invention, there is provided an RF amplifier comprising an interconnect structure and a Group III nitride-based RF amplifier die mounted on top of the interconnect structure. The Group III nitride-based RF amplifier die comprises a semiconductor layer structure and a gate terminal, a source terminal, and a drain terminal located on the semiconductor layer structure. A plurality of unit cell transistors are disposed in an upper portion of the semiconductor layer structure, and at least two of the gate terminal, the drain terminal, and the source terminal are disposed on a lower surface of the semiconductor layer structure adjacent to the interconnect structure.

[0017] In some embodiments, the drain terminal can be electrically connected to the unit cell transistors by one or more electrically conductive drain vias and / or the gate terminal can be electrically connected to the unit cell transistors by one or more electrically conductive gate vias.

[0018] In some embodiments, the semiconductor layer structure can comprise at least a growth substrate, a channel layer, and a barrier layer, wherein the channel layer is located between the growth substrate and the barrier layer. In some embodiments, the Group III nitride-based RF amplifier die further comprises a metallization structure comprising a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers located on the barrier layer opposite the channel layer. In these embodiments, the gate fingers can be electrically connected to the gate terminal via one or more electrically conductive gate vias, and the drain fingers can be electrically connected to the drain terminal via one or more electrically conductive drain vias.

[0019] In some embodiments, the one or more electrically conductive gate vias and the one or more electrically conductive drain vias can be plated vias extending through the semiconductor layer structure or at least through the growth substrate.

[0020] In some embodiments, the interconnect structure can comprise a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal. In example embodiments, the gate pad, the drain pad, and the source pad can be electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via contacts such as electrically conductive epoxy patterns or solder bumps.

[0021] In some embodiments, the gate terminal can overlap the gate pad along a first axis perpendicular to an upper surface of the interconnect structure, the drain terminal can overlap the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, and / or the source terminal can overlap the source pad along a third axis perpendicular to the upper surface of the interconnect structure.

[0022] In some embodiments, the one or more electrically conductive gate vias, the one or more electrically conductive drain vias, and the one or more electrically conductive source vias can all have substantially the same shape and substantially the same cross-sectional area.

[0023] In some embodiments, the interconnect structure can include at least a first portion of a matching circuit. In some embodiments, the one or more conductive gate vias can include a second portion of the matching circuit.

[0024] According to further embodiments of the present application, there is provided an RF amplifier including an interconnect structure having a gate pad connected to an input matching circuit, a drain pad connected to an output matching circuit, and a source pad coupled to a heat spreading structure. The RF amplifier further includes a Group III nitride-based RF amplifier die mounted on the interconnect structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure, a gate terminal on a first side of the semiconductor layer structure overlapping the gate pad along a first axis perpendicular to an upper surface of the interconnect structure, a drain terminal on the first side of the semiconductor layer structure overlapping the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, a source terminal on the first side of the semiconductor layer structure overlapping the source pad along a third axis perpendicular to the upper surface of the interconnect structure, a conductive gate via extending from a second side of the semiconductor layer structure to the first side of the semiconductor layer structure electrically connected to the gate terminal, and a conductive drain via extending from the second side of the semiconductor layer structure to the first side of the semiconductor layer structure electrically connected to the drain terminal.

[0025] In some embodiments, the Group III nitride-based RF amplifier die can further include a plurality of gate fingers, drain fingers, and source fingers on the second side of the semiconductor layer structure, and at least some of the gate fingers can be electrically connected to the gate terminal via the conductive gate via, and at least some of the drain fingers can be electrically connected to the drain terminal via the conductive drain via.

[0026] In some embodiments, the gate pad, the drain pad, and the source pad can be electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via a conductive epoxy pattern.

[0027] In some embodiments, the RF amplifier die can further include a conductive source via extending from the second side of the semiconductor layer structure to the first side of the semiconductor layer structure electrically connected to the source terminal.

[0028] In some embodiments, the conductive gate via, the conductive drain via, and the conductive source via can all have substantially the same shape and substantially the same cross-sectional area.

[0029] According to still further embodiments of the present invention, an RF amplifier including a Group III nitride-based RF amplifier die is provided. The Group III nitride-based RF amplifier die includes a semiconductor layer structure including a channel layer and a barrier layer on the channel layer, a gate terminal, a drain terminal, a source terminal, a plurality of gate fingers electrically connected to the gate terminal via at least one electrically conductive gate via, a plurality of drain fingers electrically connected to the drain terminal via at least one electrically conductive drain via, and a plurality of source fingers electrically connected to the source terminal via at least one electrically conductive source via. The gate fingers, the drain fingers, and the source fingers are all located on a first side of the semiconductor layer structure. Further, the gate terminal, the drain terminal, and the source terminal are all on a second side of the semiconductor layer structure opposite the first side.

[0030] In some embodiments, the semiconductor layer structure can further include a growth substrate, and the channel layer can be located between the growth substrate and the barrier layer.

[0031] In some embodiments, the at least one electrically conductive gate via and the at least one electrically conductive drain via can each include a through-substrate via.

[0032] In some embodiments, the at least one electrically conductive gate via and the at least one electrically conductive drain via can each include a through-substrate via.

[0033] In some embodiments, the RF amplifier can further include an interconnect structure including a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal.

[0034] In some embodiments, the gate pad, the drain pad, and the source pad can be electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via an electrically conductive epoxy pattern.

[0035] According to still further embodiments of the present invention, a Group III nitride-based RF amplifier die is provided. The Group III nitride-based RF amplifier die includes a semiconductor layer structure having a top side and a bottom side opposite the top side, a plurality of gate fingers on the top side of the semiconductor layer structure, and a gate terminal, a drain terminal, and a source terminal on the bottom side of the semiconductor layer structure.

[0036] In some embodiments, the Group III nitride-based RF amplifier die can further include a plurality of drain fingers on the top side of the semiconductor layer structure, a plurality of source fingers on the top side of the semiconductor layer structure, one or more electrically conductive gate vias, one or more electrically conductive drain vias, and one or more electrically conductive source vias. The gate terminal can be electrically connected to the plurality of gate fingers by the one or more electrically conductive gate vias, the drain terminal can be electrically connected to the plurality of drain fingers by the one or more electrically conductive drain vias, and the source terminal can be electrically connected to the plurality of source fingers by the one or more electrically conductive source vias.

[0037] In some embodiments, the semiconductor layer structure can include a growth substrate, a channel layer, and a barrier layer, wherein the channel layer is located between the growth substrate and the barrier layer, and the one or more electrically conductive gate vias, the one or more electrically conductive drain vias, and the one or more electrically conductive source vias can extend completely through the growth substrate. BRIEF DESCRIPTION OF DRAWINGS

[0038] FIG. 1A is a schematic side view of a conventional III-Nitride-based RF amplifier.

[0039] FIG. 1B is a schematic cross-sectional view taken along line 1B-1B of FIG. 1A illustrating the structure of the top metallization of the RF amplifier die included in the RF amplifier of FIG. 1A

[0040] FIG. 1C is a schematic side view of another conventional III-Nitride-based RF transistor amplifier.

[0041] FIG. 2A is a schematic side view of a III-Nitride-based RF amplifier according to an embodiment of the present application.

[0042] FIG. 2B is a schematic cross-sectional view taken along line 2B-2B of FIG. 2A illustrating the structure of the top metallization of the RF amplifier die included in the RF amplifier of FIG. 2A

[0043] FIG. 2C is a cross-sectional view taken along line 2C-2C of FIG. 2B

[0044] FIG. 2D is a cross-sectional view taken along line 2D-2D of FIG. 2B

[0045] FIG. 2E is a cross-sectional view taken along line 2E-2E of FIG. 2B

[0046] FIG. 2F is a cross-sectional view taken along line 2F-2F of FIG. 2B

[0047] FIG. 2G is a schematic backside view of the RF amplifier die included in the III-Nitride-based RF amplifier of FIG. 2A

[0048] FIG. 2H is​​​​​​​FIG. 2A Circuit diagram of a III-Nitride based RF amplifier.

[0049] FIG. 3 is an embodiment of an interconnect structure that can be used in FIGS. 2A-2H an RF amplifier.

[0050] FIG. 4 is a schematic diagram showing the structure of the top metallization of an RF amplifier die according to a further embodiment of the present application.

[0051] FIG. 5 is a schematic diagram showing the structure of the top metallization of an RF amplifier die according to a further embodiment of the present application.

[0052] FIG. 6A and FIG. 6B are schematic top side and back side views of an RF amplifier die according to a further embodiment of the present application, respectively.

[0053] FIG. 7A is a schematic cross-sectional view of a packaged RF transistor amplifier comprising FIG. 2B an RF transistor amplifier die of

[0054] FIG. 7B is a schematic cross-sectional view of a packaged RF transistor amplifier comprising FIG. 2B an RF transistor amplifier die of

[0055] FIGS. 8A-8E is a schematic cross-sectional view of a packaged RF transistor amplifier according to a still further embodiment of the present application. DETAILED DESCRIPTION

[0056] such as FIGS. 1A-1BConventional III-Nitride-based RF amplifiers such as RF amplifier 100 can use wirebonds to connect RF amplifier die 110 to gate and drain leads 172, 174. These wirebonds have an inherent inductance that can be used to implement some of the inductors in the RF amplifier's impedance matching and / or harmonic termination circuitry. The amount of inductance provided can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the wirebonds, such that the wirebonds provide a desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the wirebonds can exceed the desired amount of inductance for the impedance matching and / or harmonic termination circuitry. When this occurs, very short and / or large cross-sectional area wirebonds can be used in an effort to reduce their inductance to an appropriate level. However, very short wirebonds can be difficult to solder into place, which can increase manufacturing costs and / or can result in a higher device failure rate. Wirebonds with large cross-sectional areas can require larger gate and drain bond pads on the RF amplifier die, which requires an increase in the overall size of the RF amplifier die, which is also undesirable. Moreover, in some higher frequency applications, even very short wirebonds with large cross-sectional areas can have too much inductance, such that the matching network, for example, cannot properly terminate second or third order harmonics. While the RF amplifier can be implemented as a MMIC device to avoid the problem of excessive inductance in the wirebonds, MMIC RF amplifiers are more expensive to manufacture and can only be used in a narrow frequency range, thereby reducing flexibility.

[0057] In accordance with embodiments of the present application, a III-Nitride-based RF amplifier is provided that includes an RF amplifier die having its gate, drain, and source terminals located on the backside of the RF amplifier die. The gate, drain, and source terminals can all be connected to corresponding gate, drain, and source pads on an interconnect structure using bump technology, such as solder bumps, conductive epoxy, or other low inductance electrical connections, without the need for any wirebonds included in conventional RF amplifiers. FIGS. 1A-1C The RF amplifier die can include one or more gate vias and / or one or more drain vias for connecting gate and / or drain buses on the top side of the RF amplifier die to the respective gate and drain terminals located on the backside of the RF amplifier die. The length of the conductive vias can be a fraction (e.g., 10-30%) of the length of conventional wirebonds, and thus can significantly reduce the inductance of the connections between the gate and drain buses and the interconnect structure. As a result, the impedance matching and / or harmonic termination circuitry can be constructed to have a desired amount of inductance without the need for implementing the RF amplifier as a MMIC device. Thus, the size of the RF amplifier die can be reduced without affecting its performance, and the RF amplifier die can be used in applications in a variety of different frequency bands, as the frequency-specific portions of the device can be implemented on separate chips or circuitry.

[0058] Also, wire bonding equipment, which is typically used for high volume manufacturing, can have a tolerance of + / - 1 mil, which means that the length of any particular wire bond can vary by up to 4 mils. For high frequency applications, the variation in inductance associated with a 4 mil wire bond can be significant, so if the bond wire is too short or too long by 1-2 mils from the desired nominal length, then the performance of the matching circuit can be degraded. Forming the gate and drain terminals on the backside of the device and connecting these terminals to corresponding pads on the interconnect structure using bump technology can eliminate this process variation, resulting in improved performance.

[0059] In accordance with some embodiments of the present invention, an RF amplifier is provided that includes an interconnect structure and a Group III nitride-based RF amplifier die mounted on top of the interconnect structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are disposed in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal, and a source terminal are disposed on a lower surface of the semiconductor layer structure adjacent to the interconnect structure. The gate terminal is electrically connected to the unit cell transistors by one or more electrically conductive gate vias, the drain terminal is electrically connected to the unit cell transistors by one or more electrically conductive drain vias, and the source terminal is electrically connected to the unit cell transistors by one or more electrically conductive source vias. The gate vias, the drain vias, and the source vias can extend completely through the semiconductor layer structure.

[0060] The unit cell transistors can be HEMT devices, and each unit cell transistor can include a growth substrate, a channel layer, and a barrier layer. The channel layer is located between the growth substrate and the barrier layer. The RF amplifier die can also include a top metallization structure that includes a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers located on the barrier layer opposite the channel layer. The gate fingers can be electrically connected to the gate terminal via the one or more electrically conductive gate vias, and the drain fingers can be electrically connected to the drain terminal via the one or more electrically conductive drain vias. The electrically conductive gate via(s) and the electrically conductive drain via(s) can be plated vias that extend through the semiconductor layer structure or at least through the growth substrate.

[0061] The interconnect structure can include a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal. In example embodiments, the gate pad, the drain pad, and the source pad can be electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via a pattern of electrically conductive epoxy or solder bumps. In some embodiments, the interconnect structure can include at least a first portion of a matching circuit. The one or more electrically conductive gate vias can include a second portion of the matching circuit.

[0062] Embodiments of the present application will now be discussed in greater detail with reference to the drawings.

[0063] FIGS. 2A-2F A III-Nitride-based RF amplifier 200 according to certain embodiments of the present application is depicted. In particular, FIG. 2A is a schematic side view of the III-Nitride-based RF amplifier 200. FIG. 2B is a schematic cross-sectional view of the RF amplifier die 210 as a portion of the III-Nitride-based RF amplifier 200 taken along line 2B-2B of FIG. 2A FIG. 2A is a schematic cross-sectional view of the RF amplifier die 210 as a portion of the III-Nitride-based RF amplifier 200 taken along line 2C-2C to 2F-2F of FIGS. 2C-2F FIG. 2B is a schematic cross-sectional view of the RF amplifier die 210 as a portion of the III-Nitride-based RF amplifier 200 taken along line 2C-2C to 2F-2F of FIG. 2G is a schematic bottom view of the RF amplifier die 210. Finally, FIG. 2H is a circuit diagram of the III-Nitride-based RF amplifier 200.

[0064] As shown in FIG. 2A , the III-Nitride-based RF amplifier 200 includes an RF amplifier die 210 mounted on an upper surface of an interconnect structure 270. The RF amplifier die 210 has a top side 212 and a bottom side 214. The RF amplifier die 210 includes a bottom side metallization structure 220, a semiconductor layer structure 230, and a top side metallization structure 240 in a sequential stack. The bottom side metallization structure 220 includes a gate terminal 222, a drain terminal 224, and a source terminal 226. The RF amplifier 200 can be a HEMT-based RF amplifier, in which case the semiconductor layer structure 230 can include at least a channel layer and a barrier layer, as will be discussed in greater detail with reference to FIG. 2C and FIG. 2D . The top side metallization structure 240 will be discussed in greater detail with reference to FIG. 2B

[0065] ​​​The interconnect structure 270 can include, for example, a printed circuit board (e.g., a multi-layer printed circuit board), a metal core printed circuit board, a redistribution layer (“RDL”) laminate substrate, an interposer, a metal flange including conductive vias and / or pads, or a ceramic substrate. In other embodiments, the interconnect structure 270 can include a metal flange having an insulating pattern (e.g., a solder mask) on a top surface thereof and conductive traces on an insulating layer that provide electrical connections to the gate and drain terminals 222, 224, for example. More generally, the interconnect structure 270 can include any suitable mounting surface for the RF amplifier die 210 that can be in electrical connection with the backside 214 of the RF amplifier die 210. More than one interconnect structure 270 can be provided in a stacked manner. The RF transistor amplifier die 210 can be mounted on the interconnect structure 270 by the die manufacturer and packaged in any suitable package.

[0066] The gate, drain, and source pads 272, 274, 276 are disposed on a top surface of the interconnect structure 270. In some embodiments, the interconnect structure 270 can include pads 272, 274, 276 that can include, for example, copper pads exposed on the top surface of the interconnect structure 270. The gate terminal 222 can overlap the gate pad 272 along a first vertical axis that extends perpendicular to the top surface of the semiconductor layer structure, the drain terminal 224 can overlap the drain pad 274 along a second vertical axis that extends perpendicular to the top surface of the semiconductor layer structure, and the source terminal 226 can overlap the source pad 276 along a third vertical axis that extends perpendicular to the top surface of the semiconductor layer structure. “Overlap” means that the axis extends through the terminal and its corresponding pad, and “perpendicular” means a direction that is perpendicular to a major surface of the semiconductor layer structure 230. Each of the overlapping terminals and pads (e.g., the gate terminal 222 and the gate pad 272) can be physically and electrically connected to one another by any suitable means including, for example, conductive epoxy, solder bonding, or the like. It should be appreciated that any type of ball grid array technology can be used to connect the gate, drain, and source terminals 222, 224, 226 to the corresponding gate, drain, and source pads 272, 274, 276 while facilitating heat dissipation from the RF amplifier die 210. The interconnect structure 270 also includes a plurality of heat dissipation structures 290. In the depicted embodiment, the heat dissipation structures 290 include metal-filled vias that extend through the interconnect structure 270. Heat generated in the RF amplifier die 210 can be dissipated through the metal-filled vias 290. The interconnect structure can also include a plurality of conductive traces (not shown) and / or conductive vias (not shown) that can act as RF signal carrying paths, as will be discussed in detail herein.

[0067] The RF amplifier die 210 includes a Group III nitride-based HEMT RF amplifier that includes a plurality of unit cell transistors 216 electrically connected in parallel to each other. This can be seen best in FIG. 2B , FIG. 2B The top side metallization structure 240 of the RF amplifier die 210 is schematically depicted. As shown in FIG. 2B , the top side metallization structure 240 includes a gate bus 242 and a drain bus 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 256, all of which can be formed on an upper surface of the semiconductor layer structure 230. The gate bus 242 and gate fingers 252 can be implemented as a first monolithic metal pattern, and the drain bus 244 and drain fingers 254 can be implemented as a second monolithic metal pattern. The gate fingers 252 can be formed of a material that is capable of forming a Schottky contact with the Group III nitride-based semiconductor material, such as from Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain fingers 254 and source fingers 256 can include a metal, such as TiAlN, that can form an ohmic contact with the Group III nitride-based material. A dielectric layer (or series of dielectric layers) that helps to isolate the gate metallization 242, 252, the drain metallization 244, 254, and the source metallization 256 from each other is not shown in FIG. 2B to better illustrate the elements of the top side metallization structure 240. A conductive gate bond pad 243 and / or a conductive drain bond pad 253 can optionally be provided on the upper surface of the RF transistor amplifier die 210. The gate bond pad 243 can be electrically connected to the gate terminal 222, and the drain bond pad 253 can be electrically connected to the drain terminal 224.

[0068] One of the unit cell transistors 216 is also shown in FIG. 2B . As shown, the unit cell transistor 216 includes a gate finger 252, a drain finger 254, and a source finger 256, as well as a lower portion of the semiconductor layer structure 230. Since all of the gate fingers 252 are electrically connected to the common gate bus 242, all of the drain fingers 254 are electrically connected to the common drain bus 244, and all of the source fingers 256 are electrically connected together via the source pad 226, it can be seen that the unit cell transistors 216 are all electrically connected together in parallel.

[0069] The unit cell transistors 216 can be HEMT devices. Suitable structures for III- nitride based HEMT devices that can utilize embodiments of the present application are described, for example, in commonly assigned U.S. Patent Publication No. 2002 / 0066908 Al, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same," U.S. Patent Publication No. 2002 / 0167023 Al, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer," U.S. Patent Publication No. 2004 / 0061129, published April 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses," U.S. Patent No. 7,906,799, issued March 15, 2011, entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess," and U.S. Patent No. 6,316,793, issued November 13, 2001, entitled "Nitride Based Transistors On Semi- Insulating Silicon Carbide Substrates," the disclosures of which are hereby incorporated by reference herein in their entirety.

[0070] As FIG. 2BAs further shown in FIG. 2, a plurality of plated metal vias are provided that extend through the semiconductor layer structure 230 from the top metallization structure 240. The plated metal vias include plated metal gate vias 262, plated metal drain vias 264, and plated metal source vias 266. The plated metal gate vias 262 physically and electrically connect the gate bus 242 to the gate terminal 222, the plated metal drain vias 264 physically and electrically connect the drain bus 244 to the drain terminal 224, and the plated metal source vias 262 physically and electrically connect the source fingers 256 to the source terminal 226.

[0071] As further shown in FIG. 2, the conductive gate vias 262 and / or the conductive drain vias 264 can be offset (in the Y-direction of FIG. 2) from the conductive source vias 266. In particular, two or more conductive source vias 266 can be formed in each source finger 256, and the conductive source vias 266 formed in a particular source finger 256 can extend (at least generally) along a horizontal (X-direction) axis. Thus, the conductive source vias 266 included in each source finger 256 can define a respective horizontal axis in a view of FIG. 2, FIG. 2B As further shown in FIG. 2, the conductive gate vias 262 and / or the conductive drain vias 264 can be positioned between these horizontal axes (as opposed to being aligned along these horizontal axes, for example). In some cases, the conductive gate vias 262 and / or the conductive drain vias 264 can be positioned along a longitudinal axis defined by the respective drain finger 254. Offsetting the conductive gate vias 262 and the conductive drain vias 264 from the conductive source vias 266 can increase the distance between the conductive vias 262, 264, 266, which can reduce the likelihood of a wafer or die cracking due to mechanical weakness. This arrangement also reduces parasitic gate-to-source and / or parasitic source-to-drain coupling that can occur between the various vias 262, 264, 266. This parasitic coupling can result in gain loss and / or instability. FIG. 2B FIG. 2B As further shown in FIG. 2, the conductive gate vias 262 and / or the conductive drain vias 264 can be offset (in the Y-direction of FIG. 2) from the conductive source vias 266. In particular, two or more conductive source vias 266 can be formed in each source finger 256, and the conductive source vias 266 formed in a particular source finger 256 can extend (at least generally) along a horizontal (X-direction) axis. Thus, the conductive source vias 266 included in each source finger 256 can define a respective horizontal axis in a view of FIG. 2, FIG. 2B Line 2C-2C in FIG. 2 illustrates one such horizontal axis. As shown in FIG. 2, the conductive gate vias 262 and / or the conductive drain vias 264 can be positioned between these horizontal axes (as opposed to being aligned along these horizontal axes, for example). In some cases, the conductive gate vias 262 and / or the conductive drain vias 264 can be positioned along a longitudinal axis defined by the respective drain finger 254. Offsetting the conductive gate vias 262 and the conductive drain vias 264 from the conductive source vias 266 can increase the distance between the conductive vias 262, 264, 266, which can reduce the likelihood of a wafer or die cracking due to mechanical weakness. This arrangement also reduces parasitic gate-to-source and / or parasitic source-to-drain coupling that can occur between the various vias 262, 264, 266. This parasitic coupling can result in gain loss and / or instability. FIG. 2C

[0072] As further shown in FIG. 2, the conductive gate vias 262 and / or the conductive drain vias 264 can be offset (in the Y-direction of FIG. 2) from the conductive source vias 266. In particular, two or more conductive source vias 266 can be formed in each source finger 256, and the conductive source vias 266 formed in a particular source finger 256 can extend (at least generally) along a horizontal (X-direction) axis. Thus, the conductive source vias 266 included in each source finger 256 can define a respective horizontal axis in a view of FIG. 2, FIG. 2D FIGS. 2C-2G ​​​semiconductor layer structure 230 includes a plurality of semiconductor layers. In the depicted embodiment, a total of two semiconductor layers are shown, namely a channel layer 234 and a barrier layer 236 located on a top side of the channel layer 234. The semiconductor layer structure 230 can include additional semiconductor and / or non-semiconductor layers. For example, the semiconductor layer structure 230 can include a growth substrate 232 on which the other semiconductor layers are grown. The growth substrate 232 can include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate can include a different semiconductor material (e.g., silicon or a Group III nitride-based material, GaAs, ZnO, InP) or a non-semiconductor material (e.g., sapphire).

[0073] SiC is more closely lattice matched to Group III nitrides than sapphire (AI2O3), which is a very common substrate material for Group III nitride devices. The closer lattice match of SiC can result in higher quality Group III nitride films than are generally available on sapphire. SiC also has very high thermal conductivity, so the total output power of a Group III nitride device on silicon carbide is generally not as limited by substrate heat dissipation as is the case with forming the same device on sapphire. Moreover, the availability of semi-insulating SiC substrates can provide device isolation and reduced parasitic capacitance.

[0074] An optional buffer, nucleation, and / or transition layer (not shown) can be provided on the growth substrate 232 beneath the channel layer 234. For example, an AIN buffer layer can be included to provide an appropriate crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. In addition, a strain balancing transition layer(s) can also be provided, for example, as described in commonly assigned U.S. Patent Publication 2003 / 0102482 Al, published June 5, 2003, and entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," the disclosure of which is incorporated by reference as if fully set forth herein.

[0075] In some embodiments, the channel layer 234 is a Group III nitride material, such as Al x Ga 1-xN, where 0 < x < 1, with the condition that the energy of the conduction band edge of the channel layer 234 is less than the energy of the conduction band edge of the barrier layer 236 at the interface between the channel and barrier layers 234, 236. In certain embodiments of the present application, x = 0, indicating that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 can also be other Group III nitrides, such as InGaN, AlInGaN, etc. The channel layer 234 can be un-doped or intentionally doped, and can be grown to a thickness of, for example, greater than about 20 A. The channel layer 234 can also be a multi-layer structure, such as a superlattice or a combination of GaN, AlGaN, etc.

[0076] The bandgap of the channel layer 234 can be less than the bandgap of at least a portion of the barrier layer 236, and the channel layer 234 can also have a larger electron affinity than the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN, or AlInGaN, with a thickness between about 0.1 nm and about 10 nm or more. In particular embodiments, the barrier layer 236 is thick enough and has a high enough Al composition and doping to cause a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0077] The barrier layer 236 can be a Group III nitride and can have a larger bandgap and a smaller electron affinity than the channel layer 234. In certain embodiments, the barrier layer 236 is un-doped or doped with n-type dopants to a concentration less than about 10 19 cm -3 In some embodiments of the present application, the barrier layer 236 is Al x Ga 1-x N, where 0 < x < 1. In particular embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present application, the barrier layer 236 includes AlGaN with an aluminum concentration between about 5% and about 100%. In specific embodiments of the present application, the aluminum concentration is greater than about 10%.

[0078] A two-dimensional electron gas (2DEG) is induced in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236 due to the bandgap difference between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234. The 2DEG acts as a highly conductive layer that allows conduction between the source region of each unit transistor 216 and its associated drain region, where the source region is the portion of the semiconductor layer structure 230 directly beneath the source finger 256 and the drain region is the portion of the semiconductor layer structure 230 directly beneath the corresponding drain finger 254.

[0079] An interlevel dielectric layer 238 is formed over the gate fingers 252, drain fingers 254, and source fingers 256. The interlevel dielectric layer 238 can include a dielectric material such as SiN, Si02, etc.

[0080] FIGS. 2C-2F The plated metal gate vias 262, plated metal drain vias 264, and plated metal source vias 266 are illustrated in more detail. As shown in the cross-sectional view of FIG. 2B, the plated metal gate vias 262, plated metal drain vias 264, and plated metal source vias 266 can extend through the semiconductor layer structure 230 so as to physically and electrically connect the gate bus 242 to the gate terminal 222, physically and electrically connect the drain bus 244 to the drain terminal 224, and physically and electrically connect the source fingers 256 to the source terminal 226. FIG. 2G

[0081] In some embodiments, the plated metal gate vias 262, plated metal drain vias 264, and plated metal source vias 266 can all have the same shape and horizontal cross-section (i.e., the cross-section taken through the via in a plane parallel to the major surface of the semiconductor layer structure 230). For example, all of the vias 262, 264, 266 can be substantially cylindrical vias having the same diameter, or all can be frustoconical vias having the same diameter when measured at the same height above the bottom surface 214 of the RF amplifier die 210. Such an arrangement can allow all of the vias 262, 264, 266 to be easily formed in a single manufacturing step. In other embodiments, the plated metal gate vias 262 and / or the plated metal drain vias 264 can have a larger cross-sectional area than the plated metal source vias 266. For certain applications, such a technique can be used to further reduce the inherent inductance of the plated metal gate vias 262 and / or the plated metal drain vias 264, if desired.

[0082] The plated metal gate vias 262, plated metal drain vias 264, and plated metal source vias 266 can each be implemented by forming an opening through the semiconductor layer structure (e.g., by anisotropic etching) and then plating a metal layer over the sidewalls of the opening. In some applications, the metal can completely fill the opening so that the plated metal via is a metal-filled via. However, in many applications, the RF amplifier die 210 can be operated over a wide temperature range (due to outdoor applications and / or high levels of heat that can be generated within the RF amplifier die during device operation), which can result in high levels of stress in the device due to the metal and the semiconductor material having significantly different coefficients of thermal expansion. In such cases, the center of the plated metal vias 262, 264, 266 can remain open (i.e., gassed) so as to reduce the amount of stress that occurs due to thermal cycling.

[0083] ​The cross-sectional areas of vias 262, 264, and 266 can be selected, for example, based on thermal considerations and / or the desired series inductance. Whether a metallized via will dissipate more or less heat from the semiconductor material it penetrates will depend on a variety of considerations, including the heat dissipation quality of the semiconductor material and the metal used, the thickness of the metal plating, and the cross-sectional area of ​​the via(one or more) itself. Generally, metals such as copper dissipate heat more efficiently than semiconductor materials based on group III nitrides and silicon carbide, but any central vented opening in the via is less efficient at dissipating heat than the semiconductor material.

[0084] like FIG. 2G As shown, gate terminal 222, drain terminal 224, and source terminal 226 may each include a metallization pattern on the lower surface 232 of the semiconductor layer structure 230. Gaps may be provided between gate terminal 222 and drain terminal 224, and between drain terminal 224 and source terminal 226, to electrically insulate the gate, drain, and source terminals 222, 224, 226 from each other. In some embodiments, insulating patterns (not shown) may be deposited in the gaps. FIGS. 2A-2G As shown, the gate via 262, drain via 264, and source via 266 are physically and electrically connected to the corresponding gate terminal 222, drain terminal 224, and source terminal 226, respectively. It should also be noted that, although in FIG. 2H In the embodiments described, the metal-plated gate via 262, metal-plated drain via 264, and metal-plated source via 266 are shown to have elliptical horizontal cross-sections; however, metal-plated vias with elliptical horizontal cross-sections are merely examples. It will be appreciated that metal-plated vias with any arbitrary horizontal cross-section can be used, including, for example, circular, square, rectangular, etc. It will also be appreciated that the shape and / or size of the horizontal cross-section of any particular metal-plated via does not need to be constant. For example, some or all of the metal-plated vias may be tapered vias with an area that varies with depth. It will also be appreciated that the size and / or density of the metal-plated gate via 262, metal-plated drain via 264, and metal-plated source via 266 can also vary. For example, the size and / or density of the metal-plated drain via 264 can be selected based on the current handling capability of the device.

[0085] FIG. 2H This is a circuit diagram of an RF amplifier 200 based on group III nitrides. (Example:) FIG. 2HAs shown in FIG. 2, the Group III nitride-based RF amplifier 200 includes an RF input 201, an input impedance matching network 202, an input harmonic termination circuit 203, an RF amplifier 204, an output harmonic termination circuit 205, an output impedance matching network 206, and an RF output 207. The input impedance matching network 202 is coupled between the RF input 201 and a gate terminal of the RF amplifier 204. The input harmonic termination circuit 203 is coupled between the gate terminal of the RF amplifier 204 and ground, and is implemented as a series L-C circuit. The output harmonic termination circuit 205 is coupled between a drain terminal of the RF amplifier 204 and ground, and is also implemented as a series L-C circuit. In example embodiments, the harmonic termination circuits 203, 205 can both be configured to suppress second or third order harmonics. The output impedance matching network 206 is coupled between the drain terminal of the RF amplifier 204 and the RF output 207. In the depicted embodiment, the impedance matching networks 202, 206 both have a high-pass inductor-capacitor ("L-C") configuration, although it will be recognized that in other embodiments either or both of the impedance matching networks 202, 206 can have other topologies (e.g., a low-pass L-C topology).

[0086] While FIG. 2H One example embodiment of a matching network is illustrated, although it will be recognized that many modifications can be made thereto. For example, in other embodiments one or both of the impedance matching networks 202, 206 can be omitted, as can one or both of the harmonic termination circuits 203, 205. Also, additional harmonic termination circuits for second and third order harmonics (e.g., separate harmonic termination circuits) can be provided at the input and / or output of the RF amplifier 204. The various circuits can have configurations different from those shown. Moreover, the impedance matching and harmonic termination circuits at the input (or output) can be combined into a single multi-purpose circuit.

[0087] In FIG. 1A In the particular implementation shown in FIG. 2, the matching circuit includes a total of four inductors, which are coupled to the input (i.e., gate terminal) or output (i.e., drain terminal) of the RF amplifier 204. The intrinsic inductance of the gate via 262 in the RF amplifier 200 can comprise a portion of the input-side inductance. The remainder of the input-side inductance can be implemented using discrete circuits or distributed inductance implemented on or in the interconnect structure 270. Similarly, the intrinsic inductance of the drain via 264 in the RF amplifier 200 can comprise a portion of the output-side inductance. The remainder of the output-side inductance can be implemented using discrete circuits or distributed inductance implemented on or in the interconnect structure 270.

[0088] As discussed above, III-nitride-based RF amplifiers often include matching networks, such as input impedance matching circuits, output impedance matching circuits, input harmonic termination circuits, and output harmonic termination circuits. In some cases, III-nitride-based RF amplifiers can be implemented as MMIC devices, where the matching circuits can be formed on the same die as the RF amplifier circuits. However, implementing III-nitride-based RF amplifiers as MMICs adds to the size and manufacturing cost of the die, and also reduces flexibility, as the matching circuits are typically precisely tuned for the planned operating frequency band of the MMIC, so separate MMIC devices must be manufactured for each operating frequency band and output power level of interest. In other cases, the RF amplifier can be implemented on a separate die, and the matching circuits can be implemented on one or more separate substrates. In one such embodiment, the RF amplifier die is mounted on an interconnect structure, and the matching network is implemented using additional dies (e.g., capacitor dies, inductor dies) mounted and / or implemented on and / or within the interconnect structure. For example, the interconnect structure can be implemented as a printed circuit board, a metal core printed circuit board, an RDL layer stack, or as a substrate with conductive vias and / or traces.

[0089] When the RF amplifier die is mounted on an interconnect structure that includes the matching network, a conventional approach is to mount the RF amplifier die on the top surface of the interconnect structure, with the source terminal disposed on the bottom of the RF amplifier die and the gate and drain terminals formed on the top of the RF amplifier die, as discussed above with reference to FIG. 1. This configuration allows heat generated in the RF amplifier die during operation of the device to be removed from the device through the source via in the RF amplifier die and through heat dissipation structures in the interconnect structure, such as conductive vias. The gate and drain terminals on the top side of the RF amplifier die are electrically connected to the matching circuitry on the interconnect structure through bond wires. These bond wires also provide a portion of the inductance of the matching network. FIG. 3

[0090] ​As applications move to higher frequencies, the inductance required to properly impedance match and / or terminate certain harmonics such as second and / or third order harmonics at the fundamental frequency typically decreases. In some applications, even with very short, thick bond wires, the inductance of the bond wires can exceed the optimal series inductance required in one or more of the matching circuits. If the inductance is greater than the optimal series inductance of the impedance matching circuit, the return loss of the RF amplifier can increase and the operational bandwidth can decrease. If the inductance is greater than the optimal series inductance of the harmonic termination circuit, less of the harmonic in question can be achieved, which can degrade the efficiency, power and / or gain performance of the RF amplifier and result in an increase in the passive intermodulation distortion levels, which can degrade other aspects of the communication system in which the RF amplifier is used. While these problems can be avoided by switching to a MMIC implementation, as discussed above, MMIC RF amplifier designs have their own potential drawbacks.

[0091] The Group III Nitride-based RF amplifier 200 according to embodiments of the present application can avoid the problem of having too much series inductance discussed above because the gate and drain bond wires present in conventional RF amplifiers are replaced by gate and drain vias that extend through the RF amplifier die 210. Typically, the bond wires are at least 20 mils in length, and 30 mil or longer bond wire lengths are common. In contrast, the gate and drain vias can be much shorter, and are typically less than 8 mils in length, and in example embodiments can be less than 5 mils, less than 4 mils, or even less than 3 mils in length. As such, the series inductance injected by the gate and drain vias can be a fraction (e.g., perhaps around 15-20%) of the series inductance injected by comparable gate and drain bond wires, which can ensure that the series inductance is less than the optimal series inductance required by the various matching circuits of the Group III Nitride-based RF amplifier. Additional series inductance required to obtain the optimal series inductance for the matching network can be added using inductor chips and / or inductive traces (or other structures) mounted on or implemented in the interconnect structure.

[0092] Mounting the gate and drain terminals on the bottom side of the device can also reduce process variations during high volume manufacturing, as ball bonder machines used to solder bond wires to the gate and drain terminals on the RF amplifier die and the gate and drain pads on the interconnect structure typically have a tolerance of + / - 1 mil, which can result in a length of each bond wire that can vary by up to 4 mils. The amount of inductance associated with this variation in the length of the bond wires can be significant, particularly at higher frequencies, and can degrade the performance of the impedance matching circuit, and thus the RF amplifier. Further, connecting the gate and drain terminals to the corresponding gate and drain pads on the interconnect structure using a surface mount process of conductive epoxy or solder can allow for the use of smaller gate and drain terminals than can be used when requiring bond wire connections, and thus the RF amplifier die according to embodiments of the application can be smaller in applications where the gate and drain terminal size determines the size of the die. Further, using ball bonding techniques can reduce manufacturing costs as opposed to wire bonding.

[0093] Accordingly, RF amplifiers according to embodiments of the application can exhibit improved product assembly consistency, higher yields, increased product integration, reduced costs, and improved RF performance. The benefits can be enhanced with respect to higher frequency applications, as the inductance required in the matching circuit can be much lower in such applications, and thus too much inductance can be injected using conventional bond wires. Further, the tolerance in bond wire length can have a greater impact at higher frequencies, and in high frequency applications, particularly at lower power, the size of the bond pads can drive the size of the die. In some embodiments, any of the RF amplifiers disclosed herein can be configured to operate at frequencies greater than 1 GHz. In other embodiments, these RF amplifiers can be configured to operate at frequencies greater than 2.5 GHz. In still other embodiments, these RF amplifiers can be configured to operate at frequencies greater than 3.1 GHz. In still additional embodiments, these RF transistor amplifier dies can be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF amplifiers can be configured to operate in at least one of the 2.5-2.7 GHz, 3.4-4.2 GHz, or 5.1-5.8 GHz frequency bands, or sub-portions thereof.

[0094] As discussed in further detail herein, the RF amplifiers according to embodiments of the application can be mounted within a package that protects the RF amplifier die and provides input and output leads that connect the RF amplifier to external signals and power supplies. In example embodiments, the package can be a plastic overmold package that covers some, but not all, of the interconnect structure. In such embodiments, the input and output leads can be implemented, for example, as conductive traces on the interconnect structure. However, it will be recognized that any suitable package can be used, including ceramic packages, other plastic packages, etc.

[0095] FIGS. 2A-2H Is included FIG. 3 A schematic top view of an example embodiment of the interconnect structure 270 in the RF amplifier 200. (See attached image.) FIG. 3 As shown, interconnect structure 270 may include a printed circuit board, such as a multilayer printed circuit board or an RDL stack-up structure. Gate pad 272, drain pad 274, and source pad 276 are implemented on the upper surface of interconnect structure 270. Each of these pads may include a corresponding metal pattern (e.g., a copper pattern). Gate pad 272, drain pad 274, and source pad 276 may have the same or similar size and shape as the corresponding gate terminal 222, drain terminal 224, and source terminal 226 on RF amplifier die 210. A plurality of metal-filled vias 290 may be disposed below the source pad 276, extending through interconnect structure 270. The metal-filled vias 290 may act as heat sinks, carrying heat generated in RF amplifier die 210 and transferred through semiconductor layer structure 230 and source vias 260 to the bottom side of interconnect structure 270, where the heat is dissipated to the surrounding environment. Also as FIG. 3 As shown, in some embodiments, additional metal-filled vias 290 may be provided below the gate pad 272 and / or below the source pad 276.

[0096] like FIG. 4 As further shown, multiple additional integrated circuit chips 280 or other chips 282 may be mounted on interconnect structure 270. These chips 280, 282 may include, for example, chips comprising capacitors and / or inductors as part of input and / or output matching circuitry, chips for biasing RF amplifier die 210, chips for other RF circuitry systems such as transmit / receive switches, circulators, filters, etc. Interconnect structure 270 may also include zigzag or spiral trace patterns (not shown) implementing inductors included in input and / or output matching circuitry. Many other circuit elements may be mounted on or implemented in interconnect structure 270.

[0097] FIG. 5 and FIG. 4 This is a schematic diagram illustrating the top metallization structure of two RF amplifier dies according to a further embodiment of the present invention.

[0098] like FIGS. 1A-1B As shown, except that the RF amplifier die 310 does not include a drain via 264 and the drain terminal in the RF amplifier die 310 can be implemented on the top side of the semiconductor layer structure 230 and referenced above. FIG. 5Apart from the RF amplifier 100 discussed in the manner connected via (one or more) bonding wires to the drain pads on the interconnect structure, the RF amplifier die 310 according to an embodiment of the invention is very similar to the RF amplifier die 210. For example, the RF amplifier die 310 can be used when the bonding wires do not provide much inductance for any output matching network. The remainder of the RF amplifier die 310 may be identical to the RF amplifier 210, and therefore further description thereof will be omitted.

[0099] like FIGS. 1A-1B As shown, except that the RF amplifier die 410 does not include the gate via 262 and the gate terminal in the RF amplifier die 410 can be implemented on the top side of the semiconductor layer structure 230 and referenced above. FIG. 6A Apart from the RF amplifier 100 discussed in the manner discussed, which is connected to the gate pads on the interconnect structure via (one or more) bonding wires, the RF amplifier die 410 according to an embodiment of the invention is also very similar to the RF amplifier die 210. For example, the RF amplifier die 410 can be used when the bonding wires do not provide much inductance for any input matching network. The remainder of the RF amplifier die 410 may be the same as the RF amplifier 210, and therefore further description thereof will be omitted.

[0100] It will also be appreciated that the RF amplifier according to embodiments of the invention can have any suitable design and can include additional circuit elements. For example, the RF amplifier may include odd-mode and / or gate resistors, as discussed, for example, in U.S. Patent No. 10,128,365, the entire contents of which are incorporated herein by reference. FIG. 6B and FIG. 6A These are schematic top and back views of an RF amplifier die 510 according to a further embodiment of the present invention. Except that the RF amplifier die 510 also includes a series gate resistor 246 and an odd-mode resistor 248, the RF amplifier die 510 may be the same as the RF amplifier die 210 discussed above.

[0101] like FIG. 6A As shown, a series gate resistor 246 is included in the RF amplifier die 510. In the depicted embodiment, the series gate resistor 246 is disposed at the location where each gate finger 252 is connected to the gate bus 242. FIG. 6B and FIG. 7AAs shown, gate bus 242 and / or gate terminal 222 can also be segmented into multiple segments, and odd-mode resistor 248 can be deployed between these segments. In high-power devices, the gate can have a long gate width (i.e., extending further in the x-direction) to increase the gate perimeter of the device, resulting in a long feedback loop. Because these high-power devices can have large transconductance values, the feedback loop can be prone to instability. For example, the feedback loop may generate unwanted signals that may be within or outside the operating frequency band of the device. The generation of such signals can be problematic and may render the device unusable. The instability of the feedback loop tends to increase with the length of the feedback loop. Series gate resistor 246 and odd-mode transistor 248 can stabilize these feedback loops within the gate finger 252 and drain finger 254 of the device. It will be appreciated that series gate resistor 246 and / or odd-mode transistor 248 can be included in any RF transistor amplifier according to embodiments of the invention disclosed herein.

[0102] FIG. 2B This is a schematic cross-sectional view of a packaged RF transistor amplifier 600, which is included in an open-cavity package. FIG. 7A The RF transistor amplifier die 210. For example... FIG. 7B As shown, the open-cell package 610 includes a base 620 such as a metal flange and an upper housing 630 that may include, for example, sidewalls and a cover such as a ceramic cap. The RF transistor amplifier die 210 can be mounted on the interconnect structure 270 using contacts such as solder pads, conductive adhesive, conductive bumps, etc. The interconnect structure 270 can be mounted on the base 620 using, for example, a conductive die attachment material. The base 620 may include, for example, a metal base that can dissipate heat carried by heat dissipation structures in the interconnect structure 270 to the outside of the ceramic package 610.

[0103] Additional components 650, 660 can be mounted on the interconnect structure 270. These additional components can include, for example, one or more input matching components 650 and / or one or more output matching components 660 for impedance matching at the fundamental frequency and / or to terminate intermodulation products to ground. For example, these matching components 650, 660 can be passive RF components including resistors, capacitors, and / or inductors implemented at least partially in an integrated passive device or a printed circuit board. Conductive leads 640 extend through the housing 610 to allow the RF transistor amplifier 600 to be connected to external devices / circuitry / power sources. In the depicted embodiment, wire bonds 670 are used to connect the conductive leads 640 to the passive RF components 650, 660 on the interconnect structure 270. An RF signal input to the RF transistor amplifier 600 on the first lead 640-1 can be passed through the wire bond 670-1 to the input matching circuit 650 and from there to the gate terminal 222 of the RF transistor amplifier die 210 via a first conductive trace or path (not shown) on / in the interconnect structure 270, and an amplified output RF signal can be passed from the drain terminal 224 of the RF transistor amplifier die 210 via a second conductive trace or path (not shown) on / in the interconnect structure 270 to the output matching circuit 660 and from there to the bond wire 670-2, where the RF signal is output through the lead 640-2.

[0104] FIG. 2B is a schematic cross-sectional view of a packaged RF transistor amplifier 700 including the RF transistor amplifier die 210 in an overmolded plastic package. FIG. 7B FIG. 7A ​As shown in FIG. 7, the packaged RF transistor amplifier 700 includes a base 720, such as a metal heat sink that is part of a leadframe or metal block, surrounded at least in part by a plastic overmold 710. The RF transistor amplifier die 210 is mounted on the interconnect structure 270, and the interconnect structure 270 is mounted on the base 720. The base 720 can include, for example, a metal base that can dissipate heat carried by the heat spreading structure in the interconnect structure 270. Additional components 750, 760 are mounted on the interconnect structure 270. These additional components can include, for example, input matching components 750 and output matching components 760 that are used to impedance match at the fundamental frequency and / or to terminate intermodulation products to ground. Conductive leads 740 extend through the plastic overmold 710 to allow the RF transistor amplifier 700 to be connected to external devices / circuits / power supplies. In the depicted embodiment, wire bonds 770 are used to connect the conductive leads 740 to the passive RF components 750, 760 on the interconnect structure 270, but the wire bonds 770 can be omitted in other embodiments. Note that the term "overmold" is used broadly herein to encompass a protective plastic coating deposited on top of a wafer before the wafer is diced into individual dies, among other things.

[0105] It will be recognized that any of the RF transistor amplifiers according to embodiments of the application discussed herein can be mounted in a package, such as the open cavity and overmold packages shown in FIG. 7B and FIGS. 7A-7B respectively. Thus, FIG. 1A the RF transistor die 210 and interconnect structure 270 shown in FIG. 7 can be replaced with an RF transistor die and interconnect structure according to any of the embodiments of the application discussed herein to provide a number of further embodiments of a packaged RF transistor amplifier. Depending on the embodiment, the packaged RF transistor amplifier can include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, with the RF transistor amplifier die incorporating multiple discrete circuits in a single integrated die. Additionally and / or alternatively, the package can include multiple RF transistor amplifier dies connected in series in a path to form a multi-stage RF transistor amplifier and / or multiple RF transistor amplifier dies deployed in multiple paths (e.g., in parallel) to form an RF transistor amplifier with multiple transistor amplifier dies and multiple paths, such as in a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier can include an RF transistor amplifier die according to an embodiment of the application with conductive gates and / or conductive drain vias that provide electrical connections to a backside interconnect structure and a conventional RF transistor amplifier die, such as the RF transistor die 110 of FIG. 1, with gate and drain terminals connected to other structures via wire bonds. FIG. 8A

[0106] ​The number, spacing, density, and / or cross-sectional area of the conductive vias 262, 264, 266 can be varied as appropriate. As discussed above, the size, shape, and / or number of conductive vias can affect various performance parameters of the RF amplifier, such as heat dissipation performance and matching performance. The shape, size, location, and / or density of different types of conductive vias can therefore be selected to optimize various performance parameters. For example, FIG. 2A is a schematic cross-sectional view (taken along line 2B-2B of FIG. 8B ) of an RF amplifier die 800 that includes many more gate vias 262 than drain vias 264. This design can be desirable when the input matching circuit requires very low levels of inductance, as the increased number of gate vias 262 can reduce the total amount of inductance. Similarly, FIG. 8C is a similar schematic cross-sectional view of an RF amplifier die 810 in which the number of gate and drain vias is the same, but the size of the gate vias is increased to reduce inductance. FIG. 8D and FIG. 8E are schematic cross-sectional views of RF amplifier dies 820 and 830 that make the same changes to the drain vias 264, but not to the gate vias 262. It will also be appreciated that the location of the vias 262, 264 can be varied, as shown in FIG. 8E , ​ is a schematic cross-sectional view of yet another RF amplifier die 840.

[0107] While the example embodiments discussed above include a single RF amplifier die with a single stage amplifier, it will be appreciated that embodiments of the present invention are not limited thereto. In other embodiments, the amplifier can include multiple stages, can have a Doherty configuration, etc.

[0108] Embodiments of the inventive concept have been described above with the aid of figure drawings, of which embodiments of the invention are shown. The inventive concept, however, can be embodied in many different ways without departing from the scope of the invention. Specifically, the embodiments are provided for the purpose of illustration only and should not be construed as a limitation on the scope of the inventive concept. The same reference numerals in different drawings denote the same elements. The scope of the inventive concept should be determined solely by the claims.

[0109] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0110] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the terms "comprises", "comprising", "includes", "including" and / or "contains", "containing" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0111] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0112] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" can be used herein for the purposes of describing one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that such terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0113] In the drawings and specification, there have been disclosed typical embodiments of the application and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the application being set forth in the following claims.

Claims

1. A radio frequency amplifier, comprising: a group III-nitride based radio frequency amplifier die including a semiconductor layer structure and a gate terminal, a source terminal, and a drain terminal disposed on a lower surface of the semiconductor layer structure, wherein a plurality of unit cell transistors are disposed in an upper portion of the semiconductor layer structure, wherein the gate terminal is electrically connected to the unit cell transistors through one or more electrically conductive gate vias, and the drain terminal is electrically connected to the unit cell transistors through one or more electrically conductive drain vias, and wherein an inductance of at least one of the electrically conductive gate vias or at least one of the electrically conductive drain vias constitutes at least a portion of a matching circuit.

2. The radio frequency amplifier of claim 1, wherein, the semiconductor layer structure includes a growth substrate, a channel layer, and a barrier layer, wherein the channel layer is between the growth substrate and the barrier layer.

3. The radio frequency amplifier of claim 2, wherein, the plurality of unit cell transistors includes a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers on the barrier layer opposite the channel layer, and wherein the gate fingers are electrically connected to the gate terminal via the one or more electrically conductive gate vias, and the drain fingers are electrically connected to the drain terminal via the one or more electrically conductive drain vias.

4. The radio frequency amplifier of claim 3, wherein, the one or more electrically conductive gate vias and the one or more electrically conductive drain vias are plated through vias extending through the semiconductor layer structure.

5. The radio frequency amplifier of claim 2, wherein, the one or more electrically conductive gate vias and the one or more electrically conductive drain vias extend through the growth substrate.

6. The radio frequency amplifier of any one of claims 1-5, further comprising an interconnect structure including a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal.

7. The radio frequency amplifier of claim 6, wherein, the gate pad, the drain pad, and the source pad are respectively electrically connected to the gate terminal, the drain terminal, and the source terminal via an electrically conductive epoxy pattern.

8. The radio frequency amplifier of claim 6, wherein, the gate terminal overlaps the gate pad along a first axis perpendicular to an upper surface of the interconnect structure, the drain terminal overlaps the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, and the source terminal overlaps the source pad along a third axis perpendicular to the upper surface of the interconnect structure.

9. The radio frequency amplifier of any of claims 1-5, wherein, the one or more electrically conductive gate vias and the one or more electrically conductive drain vias all have substantially the same shape and substantially the same cross-sectional area.

10. The radio frequency amplifier of claim 6, wherein, the interconnect structure includes at least a first portion of the matching circuit.

11. A radio frequency amplifier, comprising: an interconnect structure including a gate pad connected to an input matching circuit, a drain pad connected to an output matching circuit, and a source pad coupled to a heat spreading structure; and a group III-nitride based radio frequency amplifier die mounted on the interconnect structure, the group III-nitride based radio frequency amplifier die including: a semiconductor layer structure having a first side and a second side opposite the first side; a gate terminal on the first side of the semiconductor layer structure, the gate terminal overlapping the gate pad along a first axis perpendicular to an upper surface of the interconnect structure; a source terminal on the second side of the semiconductor layer structure, the source terminal overlapping the source pad along a second axis perpendicular to the upper surface of the interconnect structure, and a drain terminal on the second side of the semiconductor layer structure, the drain terminal overlapping the drain pad along a third axis perpendicular to the upper surface of the interconnect structure. a drain terminal on a first side of the semiconductor layer structure, the drain terminal overlapping the drain pad along a second axis perpendicular to an upper surface of the interconnect structure; a source terminal on the first side of the semiconductor layer structure, the source terminal overlapping the source pad along a third axis perpendicular to the upper surface of the interconnect structure; a conductive gate via electrically connected to the gate terminal, the conductive gate via extending from a second side of the semiconductor layer structure to the first side of the semiconductor layer structure; a conductive drain via electrically connected to the drain terminal, the conductive drain via extending from the second side of the semiconductor layer structure to the first side of the semiconductor layer structure, wherein the group-III-nitride-based radio frequency amplifier die further comprises: a plurality of gate fingers, drain fingers, and source fingers on the second side of the semiconductor layer structure; and a matching circuit comprising a first portion coupled to at least some of the gate fingers through the conductive gate via, wherein at least some of the gate fingers are electrically connected to the gate terminal via the conductive gate via, and at least some of the drain fingers are electrically connected to the drain terminal via the conductive drain via.

12. The radio frequency amplifier of claim 11, wherein, the gate pad, the drain pad, and the source pad are respectively electrically connected to the gate terminal, the drain terminal, and the source terminal via a conductive epoxy pattern.

13. The radio frequency amplifier of any of claims 11-12, wherein the group-III-nitride-based radio frequency amplifier die further comprises a conductive source via electrically connected to the source terminal, the conductive source via extending from the second side of the semiconductor layer structure to the first side of the semiconductor layer structure.

14. The radio frequency amplifier of claim 13, wherein, the conductive gate via, the conductive drain via, and the conductive source via all have substantially the same shape and substantially the same cross-sectional area.

15. The radio frequency amplifier of any of claims 11-12, wherein, the interconnect structure comprises a second portion of the matching circuit.

16. A radio frequency amplifier, comprising: a group-III-nitride-based radio frequency amplifier die, comprising: a semiconductor layer structure comprising a channel layer and a barrier layer on the channel layer; a gate terminal; a drain terminal; a source terminal; a plurality of gate fingers electrically connected to the gate terminal via at least one conductive gate via; a plurality of drain fingers electrically connected to the drain terminal via at least one conductive drain via; and a plurality of source fingers electrically connected to the source terminal via at least one conductive source via; wherein the gate fingers, the drain fingers, and the source fingers are all on a first side of the semiconductor layer structure, wherein the gate terminal, the drain terminal, and the source terminal are all on a second side of the semiconductor layer structure opposite the first side, and wherein at least one of a number, a size, and a shape of at least one of the conductive gate via or the conductive drain via is configured to optimize impedance matching in the radio frequency amplifier.

17. The radio frequency amplifier of claim 16, wherein, the semiconductor layer structure further comprises a growth substrate, and the channel layer is between the growth substrate and the barrier layer.

18. The radio frequency amplifier of claim 17, wherein, The at least one conductive gate via and the at least one conductive drain via each include a plated via extending completely through the semiconductor layer structure.

19. The radio frequency amplifier of any of claims 16-18, wherein, The at least one conductive gate via and the at least one conductive drain via each include a plated via extending completely through the semiconductor layer structure.

20. The radio frequency amplifier of any of claims 16-18, further comprising an interconnect structure including a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal.

21. The radio frequency amplifier of claim 20, wherein, The gate pad, the drain pad, and the source pad are respectively electrically connected to the gate terminal, the drain terminal, and the source terminal via a conductive epoxy pattern.

22. The radio frequency amplifier of claim 20, wherein, The gate terminal overlaps the gate pad along a first axis perpendicular to an upper surface of the interconnect structure, the drain terminal overlaps the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, and the source terminal overlaps the source pad along a third axis perpendicular to the upper surface of the interconnect structure.

Images