Display panel, display device

Abstract

Provided are a display panel and a display device. The display panel comprises a base substrate, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence. The third conductive layer comprises a plurality of first signal lines (31), the plurality of first signal lines extend along a first direction (Y) and are spaced apart along a second direction (X); the fourth conductive layer comprises a plurality of second signal lines (42), the plurality of second signal lines extend along a first direction and are spaced apart along a second direction; the second signal line comprises a plurality of second signal line segments (421) spaced apart along the first direction; each second signal line segment is electrically connected to the first signal line corresponding thereto through a via (B); the fifth conductive layer comprises a plurality of electrode portions (51, 52), at least part of the electrode portions having an orthographic projection on the base substrate being located in a gap between two adjacent second signal line segments in the same second signal line having an orthographic projection on the base substrate. The display panel can avoid color deviation.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, the display panel can transmit the same signal through two layers of signal lines to reduce the attenuation of the signal on the signal lines. For example, the display panel can transmit the power signal through two layers of power lines. However, the overlapping two layers of signal lines will affect the flatness of the light-emitting unit electrode, thereby causing display problems such as color deviation on the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0004] Public Content

[0005] According to one aspect of the present disclosure, a display panel is provided, which includes: a base substrate, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the third conductive layer is located on one side of the base substrate, the third conductive layer includes a plurality of first signal lines, the plurality of first signal lines extend in a first direction on an orthographic projection of the base substrate and are distributed at intervals along a second direction, and the first direction and the second direction intersect; a fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a plurality of second signal lines, the plurality of second signal lines extend in a first direction on an orthographic projection of the base substrate and are distributed at intervals along the second direction; wherein the plurality of second signal lines are arranged in a one-to-one correspondence with the plurality of first signal lines, the second signal line includes a plurality of second signal line segments, and the same second signal line segments are connected to the base substrate. The orthographic projections of multiple second signal line segments in the signal line on the substrate are spaced apart along the first direction, and the orthographic projections of the second signal line segments on the substrate extend along the first direction; the orthographic projection of each second signal line segment on the substrate at least partially overlaps with the orthographic projection of the first signal line corresponding thereto on the substrate, and each second signal line segment is electrically connected to the first signal line corresponding thereto through a via; a fifth conductive layer is located on the side of the fourth conductive layer away from the substrate, the fifth conductive layer includes a plurality of electrode portions, and the electrode portions are used to form electrodes of the light-emitting unit; wherein the orthographic projections of at least some of the plurality of electrode portions on the substrate are located in the gap between the orthographic projections of two adjacent second signal line segments in the same second signal line on the substrate.

[0006] In an exemplary embodiment of the present disclosure, the first signal line and the second signal line are used to provide a power signal.

[0007] In an exemplary embodiment of the present disclosure, at least two adjacent portions of the first signal lines are electrically connected.

[0008] In an exemplary embodiment of the present disclosure, the fourth conductive layer also includes a plurality of third signal lines, the orthographic projections of the third signal lines on the substrate are located between the orthographic projections of two adjacent second signal lines on the substrate; the fifth conductive layer also includes a connecting portion, the connecting portion respectively connects two adjacent second signal lines through vias to connect two adjacent first signal lines.

[0009] In an exemplary embodiment of the present disclosure, the first direction is the column direction, and the second direction is the row direction; the multiple electrode portions include: an R electrode portion, a G electrode portion, and a B electrode portion, and the R electrode portion, the G electrode portion, and the B electrode portion are alternately distributed in sequence along the same electrode row; and in the same electrode row, two G electrode portions distributed along the column direction are arranged between the R electrode portion and the B electrode portion, and in adjacent electrode rows, electrode portions of the same color are located in different columns, and in two electrode rows separated by one electrode row, electrode portions of the same color are located in the same column.

[0010] In an exemplary embodiment of the present disclosure, the plurality of second signal lines include a first power line, a second power line, a third power line, and a fourth power line. The first power line includes a plurality of first power line segments spaced apart along the first direction; the second power line is disposed adjacent to the first power line, the second power line includes a plurality of second power line segments spaced apart along the first direction and a plurality of third power line segments, the second power line segments and the third power line segments are alternately distributed in sequence in the first direction; the third power line is disposed adjacent to the second power line, the third power line includes a plurality of fourth power line segments spaced apart along the first direction; the fourth power line is disposed adjacent to the third power line, the fourth power line includes a plurality of fifth power line segments spaced apart along the first direction and a plurality of sixth power line segments, the fifth power line segments and the sixth power line segments are spaced apart in the first direction. The first power line, the second power line, the third power line and the fourth power line are alternately distributed in sequence in the first direction; wherein, any one of the first power line, the second power line, the third power line and the fourth power line is used to form the second signal line, and any one of the first power line segment, the second power line segment, the third power line segment, the fourth power line segment, the fifth power line segment and the sixth power line segment is used to form the second signal line segment; there are multiple connecting parts, and the multiple connecting parts include: a first connecting part, a second connecting part and a third connecting part, the first power line segment is connected to the third power line segment through the first connecting part, the fourth power line segment is connected to the fifth power line segment through the second connecting part, and the fourth power line segment is connected to the sixth power line segment through the third connecting part.

[0011] In an exemplary embodiment of the present disclosure, the plurality of R electrode portions include a plurality of first R electrode portions and a plurality of second R electrode portions, the plurality of the first R electrode portions are located in the same electrode column, and the plurality of the second R electrode portions are located in the same electrode column. The plurality of B electrode portions include a plurality of first B electrode portions and a plurality of second B electrode portions, the plurality of the first B electrode portions are located in the same electrode column, and the plurality of the second B electrode portions are located in the same electrode column. The plurality of G electrode portions include a plurality of first G electrode portions and a plurality of second G electrode portions, the plurality of the first G electrode portions are located in the same electrode column, and the plurality of the second G electrode portions are located in the same electrode column. The electrode column where the first R electrode portion is located, the electrode column where the first B electrode portion is located, the electrode column where the first G electrode portion is located, the electrode column where the second R electrode portion is located, the electrode column where the second B electrode portion is located, and the electrode column where the second G electrode portion is located are distributed sequentially in the second direction. The orthographic projection of the first R electrode portion on the substrate substrate is located in the gap between the orthographic projections of two adjacent first power line segments on the substrate substrate, and the two adjacent first power line segments are located on the same first power line. The orthographic projection of the first B electrode portion on the substrate substrate is located in the gap between the orthographic projections of the adjacent second power line segment and the third power line segment on the substrate substrate, and the adjacent second power line segment and the third power line segment are located on the same second power line. The orthographic projection of the first G electrode portion on the substrate substrate is located in the gap between the orthographic projections of the adjacent second power line segment and the third power line segment on the substrate substrate, and the adjacent second power line segment and the third power line segment are located on the same second power line. The orthographic projection of the second R electrode portion on the substrate substrate is located in the gap between the orthographic projections of the adjacent two fourth power line segments on the substrate substrate, and the adjacent two fourth power line segments are located on the same third power line. The orthographic projection of the second B electrode portion on the substrate substrate is located in the gap between the orthographic projections of the adjacent fifth power line segment and the sixth power line segment on the substrate substrate, and the adjacent fifth power line segment and the sixth power line segment are located on the same fourth power line. The orthographic projection of the second G electrode portion on the substrate substrate is located in the gap between the orthographic projections of the adjacent fifth power line segment and the sixth power line segment on the substrate substrate, and the adjacent fifth power line segment and the sixth power line segment are located on the same fourth power line.

[0012] In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes: a first extension portion, a second extension portion, and a third extension portion. The first extension portion is connected to the first power line segment. In the second direction, the orthographic projection of the first extension portion on the substrate substrate is located between the orthographic projection of the first power line segment on the substrate substrate and the orthographic projection of the third power line segment on the substrate substrate, and the first extension portion is connected to the third power line segment through the first connection portion. The second extension portion is connected to the fourth power line segment. In the second direction, the orthographic projection of the second extension portion on the substrate substrate is located between the orthographic projection of the fourth power line segment on the substrate substrate and the orthographic projection of the fifth power line segment on the substrate substrate, and the second extension portion is connected to the fifth power line segment through the second connection portion. The third extension portion is connected to the fourth power line segment. In the second direction, the orthographic projection of the third extension portion on the substrate substrate is located between the orthographic projection of the fourth power line segment on the substrate substrate and the orthographic projection of the sixth power line segment on the substrate substrate, and the third extension portion is connected to the sixth power line segment through the third connection portion.

[0013] In an exemplary embodiment of the present disclosure, the orthographic projection of the third power line segment on the substrate substrate is located between the orthographic projections of two adjacent first G electrode portions on the substrate substrate, and the two adjacent first G electrode portions are located in the same electrode column and in different electrode rows; the orthographic projection of the fifth power line segment on the substrate substrate is located between the orthographic projections of two adjacent second G electrode portions on the substrate substrate, and the two adjacent second G electrode portions are located in the same electrode column and in different electrode rows; the orthographic projection of the sixth power line segment on the substrate substrate is located between the orthographic projections of two adjacent second G electrode portions on the substrate substrate, and the two adjacent second G electrode portions are located in the same electrode column and in different electrode rows.

[0014] In an exemplary embodiment of the present disclosure, the second signal line segment is connected to the corresponding first signal line through a plurality of vias.

[0015] In an exemplary embodiment of the present disclosure, the display panel further includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a first transistor, the first electrode of the first transistor is connected to the gate of the driving transistor, the second electrode of the first transistor is connected to the first electrode of the driving transistor, and the display panel further includes: an active layer, a first conductive layer, and a second conductive layer. The active layer is located between the substrate and the third conductive layer, and the active layer includes: a first active portion, a second active portion, a third active portion, and a fourth active portion, the first active portion is used to form a first channel region of the first transistor; the second active portion is used to form a second channel region of the first transistor; the third active portion is connected between the first active portion and the second active portion; the fourth active portion is connected to the second active portion, and is used to connect the first electrode of the first transistor. The first conductive layer is located between the active layer and the third conductive layer, and the first conductive layer includes: a first conductive portion and a first gate line, the first conductive portion is used to form the gate of the driving transistor; the first gate line covers the first active portion in the positive projection of the substrate, and a portion of the first gate line is used to form the first gate of the first transistor. The second conductive layer is located between the first conductive layer and the third conductive layer, the second conductive layer includes a second conductive portion, the second conductive portion is connected to the first signal line through a via, the orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the third active portion on the substrate, and the orthographic projection of the second conductive portion on the substrate is located on the side of the orthographic projection of the first gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate.

[0016] In an exemplary embodiment of the present disclosure, an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the fourth active portion on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, the first electrode of the second transistor is connected to the second electrode of the driving transistor, and the second electrode receives a data signal. The active layer further includes a plurality of fifth active portions, the fifth active portion is used to connect the second electrode of the second transistor, and the orthographic projection of the fifth active portion on the substrate and the orthographic projection of the fourth active portion on the substrate are spaced apart in the second direction; the second conductive layer further includes: a third conductive portion, the third conductive portion is connected to the second conductive portion, and the orthographic projection of the third conductive portion on the substrate is located between the orthographic projection of the fifth active portion on the substrate and the orthographic projection of the fourth active portion on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the display panel includes a first pixel driving circuit and a second pixel driving circuit arranged adjacent to each other in the second direction, and the first conductive layer further includes: a sixth protrusion, the sixth protrusion is connected to the first gate line, and the orthographic projection of the sixth protrusion on the substrate covers the second active part, and is used to form the second gate of the first transistor. The display panel also includes a light-emitting layer, which is located on the side of the fifth conductive layer away from the substrate, and the light-emitting layer includes a plurality of light-emitting parts, and the light-emitting parts are arranged one by one with the electrode part. The B electrode part includes a B electrode body, a first protrusion, and a second protrusion, and the orthographic projection of the B electrode body on the substrate and the orthographic projection of the corresponding light-emitting part on the substrate completely overlap; the first protrusion is connected to the B electrode body, and the orthographic projection of the first protrusion on the substrate at least partially overlaps with the orthographic projection of the sixth protrusion in the first pixel driving circuit on the substrate; the second protrusion is connected to the B electrode body, and the orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the sixth protrusion in the second pixel driving circuit on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting layer, which is located on a side of the fifth conductive layer away from the base substrate, and the light-emitting layer includes a plurality of light-emitting portions, which are arranged in a one-to-one correspondence with the electrode portion. The R electrode portion includes: an R electrode body, a third protruding portion, the orthographic projection of the R electrode body on the base substrate and the orthographic projection of the corresponding light-emitting portion on the base substrate completely overlap; the third protruding portion is connected to the R electrode body, and the orthographic projection of the third protruding portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate.

[0020] In an exemplary embodiment of the present disclosure, the display panel includes a third pixel driving circuit and a fourth pixel driving circuit arranged adjacent to each other in the first direction, and the display panel also includes a light-emitting layer, which is located on the side of the fifth conductive layer away from the substrate, and the light-emitting layer includes a plurality of light-emitting parts, and the light-emitting parts are arranged one by one with the electrode parts. Part of the G electrode part includes a G electrode body, a fourth protrusion, and a fifth protrusion, and the orthographic projection of the G electrode body on the substrate and the orthographic projection of the corresponding light-emitting part on the substrate completely overlap, and the orthographic projection of the G electrode body on the substrate does not intersect with the orthographic projection of the first conductive part on the substrate; the fourth protrusion is connected to the G electrode body, and the orthographic projection of the fourth protrusion on the substrate at least partially overlaps with the orthographic projection of the first conductive part in the third pixel driving circuit on the substrate; the fifth protrusion is connected to the G electrode body, and the orthographic projection of the fifth protrusion on the substrate at least partially overlaps with the orthographic projection of the sixth protrusion in the fourth pixel driving circuit on the substrate.

[0021] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 A structural diagram of a display panel in the related art;

[0025] Figure 2 for Figure 1 A partial cross-sectional view at the dotted line AA;

[0026] Figure 3 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0027] Figure 4 for Figure 3 The structural layout of the third conductive layer;

[0028] Figure 5 for Figure 3 The structural layout of the fourth conductive layer;

[0029] Figure 6 for Figure 3 The structural layout of the fifth conductive layer;

[0030] Figure 7 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0031] Figure 8 for Figure 7 The structural layout of the third conductive layer;

[0032] Fig. 9 for Figure 7 The structural layout of the fourth conductive layer;

[0033] Fig.10 for Figure 7 The structural layout of the fifth conductive layer;

[0034] Fig.11 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0035] Fig.12 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0036] Fig.13 for Fig.12 The structural layout of the active layer in the

[0037] Fig.14 for Fig.12 A structural layout of the first conductive layer;

[0038] Fig.15 for Fig.12 The structural layout of the second conductive layer;

[0039] Fig.16 for Fig.12 The structural layout of the third conductive layer;

[0040] Fig.17 for Fig.12 The structural layout of the fourth conductive layer;

[0041] Fig.18 for Fig.12 The structural layout of the fifth conductive layer;

[0042] Fig.19 for Fig.12 A structural layout of an active layer, a first conductive layer, and a second conductive layer;

[0043] Fig. 20 for Fig.12 A structural layout of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer;

[0044] Fig.21 for Fig.12 A structural layout of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;

[0045] Fig. 22 for Fig.12 Partial cross-sectional view along dotted line C in FIG. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0047] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0048] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0049] In the related art, the display panel can transmit the same signal through two layers of signal lines to reduce the attenuation of the signal due to the impedance of the signal line itself. Figure 1 , 2 As shown, Figure 1 It is the structural layout of the display panel in the related technology. Figure 2 for Figure 1 The display panel may include a base substrate 01, a first source-drain layer, a first planar layer 02, a second source-drain layer, a second planar layer 03, and an anode layer stacked in sequence. Figure 1As shown, the first source-drain layer may include a first power line 04, the second source-drain layer may include a second power line 05, and the anode layer may include an anode portion 06. The first power line 04 and the second power line 05 may be used to provide power signals to the sub-pixel units in the same column. Figure 2 As shown, the orthographic projection of the first power line 04 on the base substrate 01 partially overlaps with the orthographic projection of the second power line 05 on the base substrate 01. Since the thickness of the first power line 04 and the second power line 05 is relatively thick, the first power line 04 will affect the flatness of the first flat layer 02 located thereon, and the second power line 05 will affect the flatness of the second flat layer 03 located thereon. Under the dual effects of the first power line 04 and the second power line 05, the anode part 06 located above the second flat layer 03 will be significantly tilted. The tilt of the anode part 06 will cause a single sub-pixel unit to have different luminous intensities in different directions, thereby causing a large viewing angle color deviation of the display panel. For example, the display panel will appear red at one viewing angle and blue at another viewing angle.

[0050] Based on this, the present exemplary embodiment provides a display panel such as Figure 3 , 4 , 5, and 6, Figure 3 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Figure 4 for Figure 3 The structural layout of the third conductive layer in Figure 5 for Figure 3 The structural layout of the fourth conductive layer in Figure 6 for Figure 3 The display panel may include multiple Figure 3The display panel may include: a base substrate, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the third conductive layer is located at one side of the base substrate, and the third conductive layer may include a plurality of first signal lines 31, and the orthographic projections of the plurality of first signal lines 31 on the base substrate may extend along a first direction Y and be spaced apart along a second direction X, and the first direction Y and the second direction X may intersect, for example, the first direction may be perpendicular to the second direction. The fourth conductive layer may be located on a side of the third conductive layer away from the base substrate, and the fourth conductive layer may include a plurality of second signal lines 42, and the orthographic projections of the plurality of second signal lines 42 on the base substrate may extend along the first direction Y and be spaced apart along the second direction X; wherein, the plurality of second signal lines 42 may be arranged one-to-one with the plurality of first signal lines 31, and the second signal line 42 may include a plurality of second signal line segments 421, and the orthographic projections of the plurality of second signal line segments 421 in the same second signal line on the base substrate may be spaced apart along the first direction Y, and the orthographic projections of the second signal line segments 421 on the base substrate may extend along the first direction Y; each second signal line segment 421 may at least partially overlap with the orthographic projection of the first signal line 41 corresponding thereto (i.e., the first signal line corresponding to the second signal line to which the second signal line segment is located) on the base substrate, so that each second signal line segment 421 may be electrically connected to the first signal line 41 corresponding thereto through the via B. The fifth conductive layer may be located on a side of the fourth conductive layer away from the base substrate, and the fifth conductive layer may include a plurality of electrode portions 51 and a plurality of electrode portions 52, and the electrode portions 51 and 52 may be used to form electrodes of the light-emitting unit. The orthographic projections of the electrode portions 51 and 52 on the base substrate may be partially located in the gap between the orthographic projections of two adjacent second signal line segments 421 in the same second signal line on the base substrate.

[0051] The display panel provided by this exemplary embodiment sets the second signal line to be a plurality of second signal line segments spaced apart along the first direction Y, so that the orthographic projection of the electrode portion on the substrate substrate can be located in the gap between the orthographic projections of two adjacent second signal line segments 421 in the same second signal line on the substrate substrate. When the orthographic projection of the electrode portion on the substrate substrate is located in the gap between the orthographic projections of two adjacent second signal line segments 421 in the same second signal line on the substrate substrate, the area where the electrode portion overlaps with the first signal line and the second signal line at the same time can be reduced, thereby reducing or avoiding the tilting effect on the electrode portion caused by the repeated action of the first signal line and the second signal line, thereby improving the display effect of the display panel. In addition, the display panel can also transmit the same signal through the first signal line and the second signal line, thereby reducing the attenuation of the signal during transmission due to the voltage drop of the signal line itself.

[0052] In this exemplary embodiment, Figure 3 As shown, the orthographic projection of the electrode portion 51 on the substrate substrate does not overlap with the orthographic projection of the second signal line on the substrate substrate, so that the electrode portion 51 has good flatness. The orthographic projection of the electrode portion 52 on the substrate substrate partially overlaps with the orthographic projection of the second signal line on the substrate substrate, so that the electrode portion 52 has good flatness to a certain extent, and the flatness of the electrode portion 52 is relatively lower than that of the electrode portion 51. Figure 3 As shown, each second signal line segment 421 may be connected to the corresponding first signal line 31 through a via.

[0053] It should be understood that in other exemplary embodiments, only some of the multiple electrode portions in the display panel may have their orthographic projections on the substrate located in the gap between the orthographic projections of two adjacent second signal line segments 421 on the substrate substrate in the same second signal line. In other exemplary embodiments, the orthographic projections of all electrode portions on the substrate substrate may not overlap with the orthographic projections of the second signal line on the substrate substrate. Each second signal line segment 421 may be connected to the corresponding first signal line 31 through multiple vias. For example, each second signal line segment 421 may be connected to the corresponding first signal line 31 through two vias, and the two vias may be located at both ends of the second signal line segment.

[0054] In this exemplary embodiment, the first signal line and the second signal line can be used to provide the same power signal. It should be understood that in other exemplary embodiments, the first signal line and the second signal line can also transmit other signals, for example, the first signal line and the second signal line can also be used to provide data signals.

[0055] In this exemplary embodiment, Figure 3 , 5 As shown in , 6, the fourth conductive layer may further include a plurality of third signal lines 43, the orthographic projection of the third signal line 43 on the substrate may be located between the orthographic projections of two adjacent second signal lines on the substrate. The fifth conductive layer may further include a plurality of connecting portions 53, the connecting portions 53 may respectively connect two adjacent second signal lines through vias, thereby connecting two adjacent first signal lines. For example, Figure 3As shown, from left to right, the first first signal line can be connected to the second first signal line, and the third first signal line can be connected to the fourth first signal line. This arrangement can make some adjacent first signal lines form a parallel structure, thereby further reducing the impedance of the first signal line in other extension directions. It should be understood that in other exemplary embodiments, adjacent first signal lines in the display panel can also be connected in other ways, for example, every two adjacent first signal lines in the display panel are connected to each other, or at least some of the adjacent two first signal lines are electrically connected. Among them, the connection part for connecting the same group of two adjacent first signal lines can be one or more.

[0056] In this exemplary embodiment, Figure 7 , 8 , 9, 10, Figure 7 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Figure 8 for Figure 7 The structural layout of the third conductive layer in Fig. 9 for Figure 7 The structural layout of the fourth conductive layer in Fig.10 for Figure 7 The display panel may include multiple Figure 7 The structure shown. Figure 7 The structural layout of the display panel shown is similar to Figure 3 The structure layout of the display panel shown is the same. Figure 7 right Figure 3 Some structures in the middle have been renamed and annotated. The first direction Y can be a column direction, and the second direction X can be a row direction; the multiple electrode parts can include: an R electrode part, a G electrode part, and a B electrode part, and the R electrode part, the G electrode part, and the B electrode part are alternately distributed in sequence along the same electrode row; and in the same electrode row, two G electrode parts distributed along the column direction are arranged between the R electrode part and the B electrode part, and in adjacent electrode rows, electrode parts of the same color are located in different columns, and in two electrode rows separated by one electrode row, electrode parts of the same color are located in the same column. In this exemplary embodiment, Figure 7 , 10As shown, the multiple R electrode parts include multiple first R electrode parts R1 and multiple second R electrode parts R2, and the multiple first R electrode parts R1 are located in the same electrode column, and the multiple second R electrode parts R2 are located in the same electrode column. The multiple B electrode parts include multiple first B electrode parts B1 and multiple second B electrode parts B2, and the multiple first B electrode parts B1 are located in the same electrode column, and the multiple second B electrode parts B2 are located in the same electrode column. The multiple G electrode parts include multiple first G electrode parts G1 and multiple second G electrode parts G2, and the multiple first G electrode parts G1 are located in the same electrode column, and the multiple second G electrode parts G2 are located in the same electrode column. Among them, the electrode column where the first R electrode part R1 is located, the electrode column where the first B electrode part B1 is located, the electrode column where the first G electrode part G1 is located, the electrode column where the second R electrode part R2 is located, the electrode column where the second B electrode part B2 is located, and the electrode column where the second G electrode part G2 is located are distributed in sequence in the second direction X.

[0057] In this exemplary embodiment, Figure 7 , 9 As shown, the plurality of second signal lines may include a first power line, a second power line, a third power line, and a fourth power line. The first power line may include a plurality of first power line segments 421 spaced apart along the first direction; the second power line is disposed adjacent to the first power line, and the second power line may include a plurality of second power line segments 422 and a plurality of third power line segments 423 spaced apart along the first direction, and the second power line segments 422 and the third power line segments 423 are alternately distributed in sequence in the first direction Y; the third power line is disposed adjacent to the second power line, and the third power line may include a plurality of fourth power line segments 424 spaced apart along the first direction; the fourth power line is disposed adjacent to the third power line, and the fourth power line may include a plurality of fifth power line segments 425 and a plurality of sixth power line segments 426 spaced apart along the first direction Y, and the fifth power line segments 425 and the sixth power line segments 426 are alternately distributed in sequence in the first direction Y. Wherein, any one of the first power line, the second power line, the third power line, and the fourth power line may be used to form Figure 3 The second signal line shown in FIG. 1 , any one of the first power line segment, the second power line segment, the third power line segment, the fourth power line segment, the fifth power line segment, and the sixth power line segment can be used to form Figure 3The second signal line segment shown. The plurality of connection parts may be multiple, and the plurality of connection parts include: multiple first connection parts 531, multiple second connection parts 532, and multiple third connection parts 533. The first power line segment 421 may be connected to the third power line segment 423 through the first connection part 531, the fourth power line segment 424 may be connected to the fifth power line segment 425 through the second connection part 532, and the fourth power line segment 424 may be connected to the sixth power line segment 426 through the third connection part 533.

[0058] In this exemplary embodiment, Figure 7 As shown, the orthographic projection of the first R electrode portion R1 on the substrate is located in the gap between the orthographic projections of two adjacent first power line segments 421 on the substrate, and the two adjacent first power line segments 421 are located on the same first power line. The orthographic projection of the first B electrode portion B1 on the substrate is located in the gap between the orthographic projections of the adjacent second power line segment 422 and the third power line segment 423 on the substrate, and the adjacent second power line segment 422 and the third power line segment 423 are located on the same second power line. The orthographic projection of the first G electrode portion G1 on the substrate is located in the gap between the orthographic projections of the adjacent second power line segment 422 and the third power line segment 423 on the substrate, and the adjacent second power line segment 422 and the third power line segment 423 are located on the same second power line. The orthographic projection of the second R electrode portion R2 on the substrate is located in the gap between the orthographic projections of the adjacent two fourth power line segments 424 on the substrate, and the adjacent two fourth power line segments 424 are located on the same third power line. The second B electrode portion B2 is located at the gap between the orthographic projections of the fifth power line segment 425 and the sixth power line segment 426 on the substrate substrate, and the adjacent fifth power line segment 425 and the sixth power line segment 426 are located on the same fourth power line. The second G electrode portion G2 is located at the gap between the orthographic projections of the fifth power line segment 425 and the sixth power line segment 426 on the substrate substrate, and the adjacent fifth power line segment 425 and the sixth power line segment 426 are located on the same fourth power line.

[0059] In this exemplary embodiment, Figure 7 , 9As shown, the fourth conductive layer may further include: a plurality of first extension portions 441, a plurality of second extension portions 442, and a plurality of third extension portions 443. The first extension portion 441 is connected to the first power line segment 421. In the second direction X, the orthographic projection of the first extension portion 441 on the substrate may be located between the orthographic projection of the first power line segment 421 on the substrate and the orthographic projection of the third power line segment 423 on the substrate. The first extension portion 441 may be connected to the third power line segment 423 via the first connection portion 531. The second extension portion 442 may be connected to the fourth power line segment 424. In the second direction X, the orthographic projection of the second extension portion 442 on the substrate may be located between the orthographic projection of the fourth power line segment 424 on the substrate and the orthographic projection of the fifth power line segment 425 on the substrate. The second extension portion 442 may be connected to the fifth power line segment 425 via the second connection portion 532. The third extension portion 443 can be connected to the fourth power line segment 424. In the second direction X, the orthographic projection of the third extension portion 443 on the substrate can be located between the orthographic projection of the fourth power line segment 424 on the substrate and the orthographic projection of the sixth power line segment 426 on the substrate. The third extension portion 443 can be connected to the sixth power line segment 426 via the third connection portion 533.

[0060] In this exemplary embodiment, Figure 7 As shown, the orthographic projection of the third power line segment 423 on the substrate can be located between the orthographic projections of two adjacent first G electrode portions G1 on the substrate, and the two adjacent first G electrode portions G1 are located in the same electrode column and in different electrode rows. The orthographic projection of the fifth power line segment 425 on the substrate can be located between the orthographic projections of two adjacent second G electrode portions G2 on the substrate, and the two adjacent second G electrode portions G2 are located in the same electrode column and in different electrode rows. The orthographic projection of the sixth power line segment 426 on the substrate can be located between the orthographic projections of two adjacent second G electrode portions G2 on the substrate, and the two adjacent second G electrode portions are located in the same electrode column and in different electrode rows.

[0061] The design of the power line segment, connecting portion, electrode portion, and extending portion can realize the connection of adjacent first signal lines in a limited display panel layout space. At the same time, this arrangement can also greatly reduce the area where the electrode portion overlaps with the first signal line and the second signal line at the same time.

[0062] In this exemplary embodiment, the display panel may further include a pixel driving circuit such as Fig.11As shown, it is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure. The pixel driving circuit may include: a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C. Among them, the gate of the driving transistor DT is connected to the node N; the first electrode of the first transistor T1 is connected to the node N, and the second electrode is connected to the first electrode of the driving transistor DT; the first electrode of the second transistor T2 is connected to the second electrode of the driving transistor DT, the second electrode is connected to the data signal terminal, and the gate is connected to the gate driving signal terminal; the first electrode of the third transistor T3 is connected to the initial signal terminal Vinit, the second electrode is connected to the node N, and the gate is connected to the reset signal terminal Re; the first electrode of the fourth transistor T4 is connected to the first power supply terminal VDD, the second electrode is connected to the second electrode of the driving transistor DT, and the gate is connected to the enable signal terminal EM; the first electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor DT, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the initialization signal terminal Vinit, the second electrode is connected to the second electrode of the fifth transistor T5, and the gate is connected to the reset signal terminal Re, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the fifth transistor T5 and the second power supply terminal VSS. Among them, the transistors T1-T6 and DT can all be P-type transistors or N-type transistors. This exemplary embodiment takes N-type transistors as an example for description.

[0063] like Figure 12-20 As shown, Fig.12 is a structural diagram of another exemplary embodiment of the display panel disclosed in the present invention, Fig.13 for Fig.12 The structural layout of the active layer, Fig.14 for Fig.12 The structural layout of the first conductive layer in Fig.15 for Fig.12 The structural layout of the second conductive layer in Fig.16 for Fig.12 The structural layout of the third conductive layer in Fig.17 for Fig.12 The structural layout of the fourth conductive layer in Fig.18 for Fig.12 The structure of the fifth conductive layer in the figure is as follows: Fig.19 for Fig.12 The structure layout of the active layer, the first conductive layer and the second conductive layer, Fig. 20 for Fig.12 The structure layout of the active layer, the first conductive layer, the second conductive layer and the third conductive layer, Fig.21 for Fig.12The display panel may include an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. Fig.11 The pixel driving circuit shown in FIG. Fig.12 The display panel may include Figure 3 , 7 All technical features of the display panel are shown.

[0064] In this exemplary embodiment, the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer which are sequentially stacked. Fig.12 , 13 As shown in Figures 19, the active layer may include a first active portion 61, a second active portion 62, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, an eighth active portion 68, a ninth active portion 69, a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, a thirteenth active portion 613, and a fourteenth active portion 614. The first active portion 61 may be used to form a first channel region of the first transistor T1; the second active portion 62 may be used to form a second channel region of the first transistor T1; the third active portion 63 may be connected between the first active portion 61 and the second active portion 62; the fourth active portion 64 may be connected to the second active portion 62, and used to connect the first electrode of the first transistor T1; and the fifth active portion 65 is used to connect the second electrode of the second transistor T2. The fifth active portion 65 is spaced apart from the orthographic projection of the substrate and the orthographic projection of the fourth active portion 64 on the substrate in the second direction X; the sixth active portion 66 is used to form the channel region of the driving transistor DT; the seventh active portion 67 is used to form the channel region of the second transistor T2; the eighth active portion 68 is used to form the channel region of the third transistor T3; the ninth active portion 69 is used to form the channel region of the fifth transistor T5; the tenth active portion 610 is used to form the channel region of the sixth transistor T6; and the eleventh active portion 611 is used to form the channel region of the fourth transistor T4.

[0065] like Fig.12 , 14 As shown in FIG. 19 , the first conductive layer may include a first gate line Gate, a second gate line Re, a third gate line EM, a first conductive portion 11, and a sixth protrusion 12. The sixth protrusion 12 is connected to the first gate line Gate. The orthographic projections of the first gate line Gate, the second gate line Re, and the third gate line EM on the substrate may extend along the second direction X. The first gate line Gate may be used to provide Fig.11 The gate drive signal terminal Gate in the second gate line Re can provide Fig.11 The reset signal terminal Re in the third gate line EM can be used to provide Fig.11 The enable signal terminal EM in the substrate. The orthographic projection of the first gate line Gate on the substrate covers the orthographic projection of the first active portion 61 on the substrate, so that a partial structure of the first gate line is used to form the first gate of the first transistor T1; the orthographic projection of the sixth protrusion 12 on the substrate covers the orthographic projection of the second active portion 62 on the substrate, so that the sixth protrusion 12 is used to form the second gate of the first transistor T1. The orthographic projection of the first gate line Gate on the substrate also covers the orthographic projection of the seventh active portion 67 on the substrate, so that a partial structure of the first gate line is used to form the gate of the second transistor T2. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the sixth active portion 66 on the substrate, which is used to form the gate and Fig.11 An electrode of the capacitor C in the middle. The orthographic projection of the second gate line Re on the substrate covers the orthographic projection of the eighth active portion 68 on the substrate, so that a partial structure of the second gate line Re is used to form the gate of the third transistor T3. The orthographic projection of the third gate line EM on the substrate covers the orthographic projection of the ninth active portion 69 on the substrate, so that a partial structure of the third gate line EM is used to form the gate of the fifth transistor T5. The orthographic projection of the third gate line EM on the substrate covers the orthographic projection of the eleventh active portion 611 on the substrate, so that a partial structure of the third gate line EM is used to form the gate of the fourth transistor T4. The orthographic projection of the second gate line Re in the adjacent next row of pixel driving circuits on the substrate covers the orthographic projection of the tenth active portion 610 on the substrate, so that a partial structure of the second gate line Re can be used to form the gate of the sixth transistor T6.

[0066] like Fig.12 , 15 As shown in FIG. 19 , the second conductive layer may include a fourth gate line Vinit, a second conductive portion 22, a third conductive portion 23, and a fourth conductive portion 24. The orthographic projection of the fourth gate line Vinit on the substrate may extend along the second direction X, and is used to provide Fig.11 The initialization signal terminal Vinit in the third conductive part 23 and the fourth conductive part 24 can be multiple, and the multiple third conductive parts 23 can be distributed along the second direction X at intervals, and the multiple fourth conductive parts 24 can be distributed along the second direction X, and the multiple fourth conductive parts can be connected to each other, wherein the fourth conductive part 24 can be used to form Fig.11 The other electrode of capacitor C.

[0067] like Fig.12 , 16 As shown in FIG. 20 , the third conductive layer may include a first signal line 31, a conductive portion 32, a conductive portion 33, a conductive portion 34, and a conductive portion 35. The orthographic projection of the first signal line 31 on the substrate may extend along the first direction Y. The first signal line 31 may be used to provide Fig.11The first power supply terminal VDD is connected to the first conductive portion 612 through the via 106. The conductive portion 32 can be connected to the fourth gate line Vinit through the via 101, and connected to the fourteenth active portion 614 through the via 102 to connect the first pole of the third transistor T3 and the initial signal terminal Vinit. The conductive portion 33 can be connected to the fifth active portion 65 through the via 103 to connect the second pole of the second transistor T2. The conductive portion 34 can be connected to the fourth active portion 64 through the via 104 and connected to the first conductive portion 11 through the via 105 to connect the gate of the driving transistor DT and the first pole of the first transistor T1. The conductive portion 35 can be connected to the twelfth active portion 612 through the via 106 to connect the second pole of the fifth transistor T5. The first signal line 31 is also connected to the thirteenth active portion 613 through the via 107 to connect the first power supply terminal VDD and the first pole of the fourth transistor T4.

[0068] like Fig.12 , 17 As shown in 21, the fourth conductive layer of the display panel can be Figure 3 , Figure 7 The fourth conductive layer may include a third signal line 43, a second signal line, and a conductive portion 44. The orthographic projection of the third signal line 43 on the substrate may extend along the first direction Y. The third signal line 43 may be used to provide Fig.11 The data signal terminal Da in the middle. The second signal line can be arranged in a one-to-one correspondence with the first signal line 31, and the second signal line can include a plurality of second signal line segments 421 spaced apart along the first direction Y, and the second signal line segments 421 can be electrically connected to the corresponding first signal line 31 through the via 109. The conductive portion 44 can be electrically connected to the conductive portion 35 through the via 108 to connect the second electrode of the fifth transistor T5. The third signal line 43 can be connected to the conductive portion 33 through the via 111 to connect the second electrode of the second transistor T2.

[0069] like Fig.12 , 18 As shown, the fifth conductive part may include a plurality of R electrode parts R, a plurality of G electrode parts G, and a plurality of B electrode parts B, wherein the electrode parts may be connected to the conductive part 44 through the via 110 to connect the second electrode of the fifth transistor T5.

[0070] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel may have other structures.

[0071] In this exemplary embodiment, Fig.13 , 15As shown in FIG. 19 , the first transistor T1 is a dual-gate structure, the third active portion 63 is a conductor, and the third active portion 63 and the first gate line Gate can form a capacitor structure. The third active portion 63 is prone to voltage fluctuations under the action of the first gate line Gate voltage, thereby causing the third active portion 63 to leak to the source and drain of the first transistor T1. In this exemplary embodiment, Fig.19 As shown, the orthographic projection of the second conductive portion 22 on the substrate can be located on the side of the orthographic projection of the first gate line Gate on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. And the orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the third active portion 63 on the substrate. Since the second conductive portion 22 is connected to the first signal line 31 with a stable voltage, the third active portion 63 can reduce its voltage fluctuation under the coupling effect of the second conductive portion 22.

[0072] In this exemplary embodiment, Fig.13 , 15 As shown in FIG. 19 , the orthographic projection of the second conductive portion 22 on the substrate can also at least partially overlap with the orthographic projection of the fourth active portion 64 on the substrate. Similarly, the second conductive portion 22 can form a parallel plate capacitor with the fourth active portion 64, and the fourth active portion 64 can reduce its voltage fluctuation under the coupling effect of the second conductive portion 22, thereby ensuring that the light-emitting unit is in the light-emitting stage. Fig.11 The voltage at the middle node N is stable.

[0073] In this exemplary embodiment, Fig.19 As shown, the orthographic projection of the third conductive portion 23 on the substrate can be located between the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the fourth active portion 64 on the substrate. The third conductive portion 23 can form a lateral capacitor with the fourth active portion 64, and the fourth active portion 64 can reduce its voltage fluctuation under the coupling effect of the third conductive portion 23, thereby ensuring that the light-emitting unit is in the light-emitting stage. Fig.11 The voltage at the middle node N is stable.

[0074] In this exemplary embodiment, Fig.12 , 18The display panel shown includes a pixel driving circuit 81 and a pixel driving circuit 82 arranged adjacent to each other in the second direction, and the display panel also includes a light-emitting layer, which is located on the side of the fifth conductive layer away from the base substrate, and the light-emitting layer includes a plurality of light-emitting portions 71, and the light-emitting portions 71 are arranged one-to-one with the electrode portion. Among them, the light-emitting portion 71 can be formed in the opening of the pixel definition layer. The B electrode portion can include a B electrode body 513, a first protruding portion 511, and a second protruding portion 512, and the orthographic projection of the B electrode body 513 on the base substrate and the orthographic projection of the corresponding light-emitting portion 71 on the base substrate completely overlap; the first protruding portion 511 can be connected to the B electrode body 513, and the orthographic projection of the first protruding portion 511 on the base substrate can overlap at least partially with the orthographic projection of the sixth protruding portion 12 in the pixel driving circuit 81 on the base substrate. Since the voltage of the electrode portion is stable during the light-emitting stage of the pixel driving circuit, the arrangement can stabilize the voltage of the sixth protrusion 12 (the gate of the first transistor) through the first protrusion 511, so as to prevent the node N from leaking through the first transistor T1 at the light-emitting node. The second protrusion 512 is connected to the B electrode body 513, and the orthographic projection of the second protrusion 512 on the substrate can at least partially overlap with the orthographic projection of the sixth protrusion 12 in the pixel driving circuit on the substrate. Similarly, the arrangement can stabilize the voltage of the sixth protrusion 12 (the gate of the first transistor) through the first protrusion 511, so as to prevent the node N from leaking through the first transistor T1 at the light-emitting node.

[0075] In this exemplary embodiment, Fig.12 , 18 The R electrode portion R shown may include: an R electrode body 516, a third protrusion 517, wherein the orthographic projection of the R electrode body 516 on the substrate substrate may completely overlap with the orthographic projection of the corresponding light-emitting portion on the substrate substrate; the third protrusion 517 is connected to the R electrode body 516, and the orthographic projection of the third protrusion 517 on the substrate substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate substrate. This arrangement can stabilize the voltage of the first conductive portion 11 through the third protrusion 517, so as to reduce the voltage fluctuation of the node N in the pixel driving circuit during the light-emitting stage. Among them, the orthographic projection of the third protrusion 517 on the substrate substrate may at least partially overlap with the orthographic projection of the opening 241 on the substrate substrate.

[0076] In this exemplary embodiment, Fig.12 , 18As shown, the display panel may include a pixel driving circuit 82 and a pixel driving circuit 84 arranged adjacent to each other in the first direction Y. Part of the G electrode portion G may include a G electrode body 515, a fourth protrusion 514, and a fifth protrusion 518. The orthographic projection of the G electrode body 515 on the substrate may completely overlap with the orthographic projection of the corresponding light-emitting portion 71 on the substrate, and the orthographic projection of the G electrode body 515 on the substrate may not intersect with the orthographic projection of the first conductive portion 11 on the substrate. The fourth protrusion 514 may be connected to the G electrode body 515, and the orthographic projection of the fourth protrusion 514 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 in the pixel driving circuit 82 on the substrate. This arrangement can stabilize the voltage of the first conductive portion 11 through the fourth protrusion 514 during the light-emitting stage. The fifth protrusion 518 is connected to the G electrode body 515, and the orthographic projection of the fifth protrusion 518 on the substrate can at least partially overlap with the orthographic projection of the sixth protrusion 12 in the pixel driving circuit 84 on the substrate. This arrangement can stabilize the voltage of the sixth protrusion 12 through the fifth protrusion 518 during the light-emitting stage.

[0077] like Fig. 22 As shown, Fig.12 Partial cross-sectional view along dotted line C in FIG. The display panel may also include a buffer layer 91, a first gate insulating layer 92, a second gate insulating layer 93, a dielectric layer 94, a first flat layer 95, and a second flat layer 96. Among them, the substrate 0, the buffer layer 91, the active layer, the first gate insulating layer 92, the first conductive layer, the second gate insulating layer 93, the second conductive layer, the dielectric layer 94, the third conductive layer, the first flat layer 95, the fourth conductive layer, the second flat layer 96, and the fifth conductive layer are stacked in sequence. Among them, the gate insulating layer may be a silicon oxide layer, and the dielectric layer may be a silicon nitride layer. The material of the buffer layer may be silicon nitride or silicon oxide. The material of the active layer may be polysilicon, a metal oxide semiconductor, and the like. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may all be formed by at least one metal layer. For example, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may all be formed by stacking a first titanium layer, an aluminum layer, and a second titanium layer in sequence. The base substrate may be formed of an insulating material, for example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide (PI) layer, and a second silicon oxide layer arranged in sequence.

[0078] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, etc.

[0079] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0080] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: include: substrate substrate; A third conductive layer, located on one side of the base substrate, the third conductive layer comprising a plurality of first signal lines, wherein the orthographic projections of the plurality of first signal lines on the base substrate extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction intersect; a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising a plurality of second signal lines, wherein the orthographic projections of the plurality of second signal lines on the base substrate extend along the first direction and are spaced apart along the second direction; The plurality of second signal lines are arranged in one-to-one correspondence with the plurality of first signal lines, the second signal lines include a plurality of second signal line segments, the orthographic projections of the plurality of second signal line segments in the same second signal line on the substrate are spaced apart along the first direction, and the orthographic projections of the second signal line segments on the substrate extend along the first direction; The orthographic projection of each second signal line segment on the base substrate at least partially overlaps with the orthographic projection of the first signal line corresponding thereto on the base substrate, and each second signal line segment is electrically connected to the first signal line corresponding thereto through a via; a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer comprising a plurality of electrode portions, the electrode portions being used to form electrodes of the light-emitting unit; The orthographic projections of at least some of the electrode portions among the plurality of electrode portions on the base substrate are located in a gap between the orthographic projections of two adjacent second signal line segments in the same second signal line on the base substrate.

2. The display panel according to claim 1, wherein: The first signal line and the second signal line are used to provide power signals.

3. The display panel according to claim 2, wherein: At least two adjacent portions of the first signal lines are electrically connected.

4. The display panel according to claim 3, wherein: The fourth conductive layer further comprises: A plurality of third signal lines, wherein the orthographic projections of the third signal lines on the substrate are located between the orthographic projections of two adjacent second signal lines on the substrate; The fifth conductive layer further comprises: The connecting portion connects two adjacent second signal lines through via holes to connect two adjacent first signal lines.

5. The display panel according to claim 4, wherein: The first direction is a column direction, and the second direction is a row direction; The plurality of electrode portions include: an R electrode portion, a G electrode portion, and a B electrode portion, and the R electrode portion, the G electrode portion, and the B electrode portion are alternately distributed along the same electrode row; In the same electrode row, two G electrode portions distributed along the column direction are arranged between the R electrode portion and the B electrode portion. In adjacent electrode rows, electrode portions of the same color are located in different columns. In two electrode rows separated by one electrode row, electrode portions of the same color are located in the same column.

6. The display panel according to claim 5, wherein: The plurality of second signal lines include: A first power line, comprising a plurality of first power line segments spaced apart along the first direction; a second power line, arranged adjacent to the first power line, the second power line comprising a plurality of second power line segments and a plurality of third power line segments spaced apart along the first direction, the second power line segments and the third power line segments being alternately arranged in sequence in the first direction; a third power line, disposed adjacent to the second power line, the third power line comprising a plurality of fourth power line segments spaced apart along the first direction; a fourth power line, arranged adjacent to the third power line, the fourth power line comprising a plurality of fifth power line segments and a plurality of sixth power line segments spaced apart along the first direction, the fifth power line segments and the sixth power line segments being alternately arranged in sequence in the first direction; Wherein, any one of the first power line, the second power line, the third power line, and the fourth power line is used to form the second signal line, and any one of the first power line segment, the second power line segment, the third power line segment, the fourth power line segment, the fifth power line segment, and the sixth power line segment is used to form the second signal line segment; There are multiple connecting parts, including: multiple first connecting parts, multiple second connecting parts, and multiple third connecting parts. The first power line segment is connected to the third power line segment through the first connecting part, the fourth power line segment is connected to the fifth power line segment through the second connecting part, and the fourth power line segment is connected to the sixth power line segment through the third connecting part.

7. The display panel according to claim 6, wherein: The plurality of R electrode portions include: A plurality of first R electrode portions, wherein the plurality of first R electrode portions are located in the same electrode column; A plurality of second R electrode portions, wherein the plurality of second R electrode portions are located in the same electrode column; The plurality of B electrode portions include: A plurality of first B electrode portions, wherein the plurality of first B electrode portions are located in the same electrode column; A plurality of second B electrode portions, wherein the plurality of second B electrode portions are located in the same electrode column; The plurality of G electrode portions include: A plurality of first G electrode portions, wherein the plurality of first G electrode portions are located in the same electrode column; A plurality of second G electrode portions, wherein the plurality of second G electrode portions are located in the same electrode column; The electrode column where the first R electrode portion is located, the electrode column where the first B electrode portion is located, the electrode column where the first G electrode portion is located, the electrode column where the second R electrode portion is located, the electrode column where the second B electrode portion is located, and the electrode column where the second G electrode portion is located are sequentially distributed in the second direction; The orthographic projection of the first R electrode portion on the base substrate is located in a gap between two adjacent first power line segments on the base substrate, and the two adjacent first power line segments are located on the same first power line; The orthographic projection of the first B electrode portion on the base substrate is located in a gap between the orthographic projections of the adjacent second power line segment and the third power line segment on the base substrate, and the adjacent second power line segment and the third power line segment are located on the same second power line; The first G electrode portion is located at a gap between the orthographic projections of the second power line segment and the third power line segment adjacent to the substrate on the orthographic projection portion of the substrate, and the adjacent second power line segment and the third power line segment are located on the same second power line; The orthographic projection of the second R electrode portion on the base substrate is located in a gap between the orthographic projections of two adjacent fourth power line segments on the base substrate, and the two adjacent fourth power line segments are located on the same third power line; The orthographic projection of the second B electrode portion on the base substrate is located in a gap between the orthographic projections of the adjacent fifth power line segment and the sixth power line segment on the base substrate, and the adjacent fifth power line segment and the sixth power line segment are located on the same fourth power line; The second G electrode portion is located in a gap between the orthographic projections of the fifth and sixth power line segments adjacent to the base substrate, and the adjacent fifth and sixth power line segments are located on the same fourth power line.

8. The display panel according to claim 6, wherein: The fourth conductive layer further comprises: a first extension portion connected to the first power line segment, wherein in the second direction, the orthographic projection of the first extension portion on the substrate is located between the orthographic projection of the first power line segment on the substrate and the orthographic projection of the third power line segment on the substrate, and the first extension portion is connected to the third power line segment via the first connection portion; a second extension portion connected to the fourth power line segment, wherein in the second direction, the orthographic projection of the second extension portion on the substrate is located between the orthographic projection of the fourth power line segment on the substrate and the orthographic projection of the fifth power line segment on the substrate, and the second extension portion is connected to the fifth power line segment via the second connection portion; The third extension portion is connected to the fourth power line segment. In the second direction, the orthographic projection of the third extension portion on the substrate is located between the orthographic projection of the fourth power line segment on the substrate and the orthographic projection of the sixth power line segment on the substrate. The third extension portion is connected to the sixth power line segment via the third connection portion.

9. The display panel according to claim 7, wherein: The orthographic projection of the third power line segment on the base substrate is located between the orthographic projections of two adjacent first G electrode portions on the base substrate, and the two adjacent first G electrode portions are located in the same electrode column and in different electrode rows; The orthographic projection of the fifth power line segment on the base substrate is located between the orthographic projections of two adjacent second G electrode portions on the base substrate, and the two adjacent second G electrode portions are located in the same electrode column and in different electrode rows; The orthographic projection of the sixth power line segment on the base substrate is located between the orthographic projections of two adjacent second G electrode portions on the base substrate, and the two adjacent second G electrode portions are located in the same electrode column and in different electrode rows.

10. The display panel according to any one of claims 1 to 9, wherein: The second signal line segment is connected to the corresponding first signal line through a plurality of vias.

11. The display panel according to claim 5, wherein: The display panel further includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a first transistor, the first electrode of the first transistor is connected to the gate of the driving transistor, the second electrode of the first transistor is connected to the first electrode of the driving transistor, and the display panel further includes: An active layer is located between the substrate and the third conductive layer, and the active layer includes: a first active portion, used to form a first channel region of the first transistor; a second active portion, used to form a second channel region of the first transistor; a third active portion connected between the first active portion and the second active portion; A first conductive layer is located between the active layer and the third conductive layer, and the first conductive layer includes: A first conductive portion, used to form a gate of the driving transistor; a first gate line, wherein the first gate line covers the first active portion in an orthographic projection on the substrate, and a portion of the first gate line is used to form a first gate of the first transistor; A second conductive layer is located between the first conductive layer and the third conductive layer, and the second conductive layer includes: A second conductive portion is connected to the first signal line through a via, the orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the third active portion on the substrate, and the orthographic projection of the second conductive portion on the substrate is located on a side of the orthographic projection of the first gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate.

12. The display panel according to claim 11, wherein: The active layer further includes a fourth active portion, the fourth active portion is connected to the second active portion and is used to connect to the first electrode of the first transistor; The orthographic projection of the second conductive portion on the base substrate at least partially overlaps with the orthographic projection of the fourth active portion on the base substrate.

13. The display panel according to claim 12, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to a second electrode of the driving transistor, and the second electrode receives a data signal, and the active layer further includes: a fifth active portion, used for connecting the second electrode of the second transistor, wherein the orthographic projection of the fifth active portion on the substrate and the orthographic projection of the fourth active portion on the substrate are spaced apart from each other in the second direction; The second conductive layer further comprises: The third conductive portion is connected to the second conductive portion, and the orthographic projection of the third conductive portion on the base substrate is located between the orthographic projection of the fifth active portion on the base substrate and the orthographic projection of the fourth active portion on the base substrate.

14. The display panel according to claim 11, wherein: The display panel includes a first pixel driving circuit and a second pixel driving circuit adjacently arranged in the second direction, and the first conductive layer further includes: a sixth protruding portion, connected to the first gate line, covering the second active portion in an orthographic projection on the base substrate, and used to form a second gate of the first transistor; The display panel further includes: a light-emitting layer, located on a side of the fifth conductive layer away from the base substrate, the light-emitting layer comprising a plurality of light-emitting portions, the light-emitting portions being arranged in one-to-one correspondence with the electrode portions; The B electrode portion comprises: A B electrode body, wherein the orthographic projection of the B electrode body on the base substrate completely overlaps with the orthographic projection of the corresponding light-emitting portion on the base substrate; A first protrusion is connected to the B electrode body, wherein an orthographic projection of the first protrusion on the base substrate at least partially overlaps with an orthographic projection of a sixth protrusion in the first pixel driving circuit on the base substrate; A second protrusion is connected to the B electrode body, and an orthographic projection of the second protrusion on the base substrate at least partially overlaps with an orthographic projection of a sixth protrusion in the second pixel driving circuit on the base substrate.

15. The display panel according to claim 11, wherein: The display panel further includes: a light-emitting layer, located on a side of the fifth conductive layer away from the base substrate, the light-emitting layer comprising a plurality of light-emitting portions, the light-emitting portions being arranged in one-to-one correspondence with the electrode portions; The R electrode portion includes: An R electrode body, wherein the orthographic projection of the R electrode body on the base substrate and the orthographic projection of the corresponding light-emitting portion on the base substrate completely overlap; A third protrusion is connected to the R electrode body, and an orthographic projection of the third protrusion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate.

16. The display panel according to claim 11, wherein: The display panel includes a third pixel driving circuit and a fourth pixel driving circuit arranged adjacent to each other in the first direction, The first conductive layer further comprises: a sixth protruding portion, connected to the first gate line, covering the second active portion in an orthographic projection on the base substrate, and used to form a second gate of the first transistor; The display panel further includes: a light-emitting layer, located on a side of the fifth conductive layer away from the base substrate, the light-emitting layer comprising a plurality of light-emitting portions, the light-emitting portions being arranged in one-to-one correspondence with the electrode portions; Part of the G electrode portion includes: A G electrode body, wherein the orthographic projection of the G electrode body on the base substrate and the orthographic projection of the corresponding light-emitting portion on the base substrate completely overlap; a fourth protrusion connected to the G electrode body, wherein an orthographic projection of the fourth protrusion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion in the third pixel driving circuit on the base substrate; A fifth protrusion is connected to the G electrode body, and an orthographic projection of the fifth protrusion on the base substrate at least partially overlaps with an orthographic projection of the sixth protrusion in the fourth pixel driving circuit on the base substrate.

17. A display device, wherein: A display panel comprising any one of claims 1-16.

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