Integrated circuit, monitoring system and its monitoring method

Abstract

The present invention provides an integrated circuit, a monitoring system and a monitoring method thereof. The integrated circuit includes at least one input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module and a direct memory access (DMA). The controller provides a first control signal corresponding to an instruction from the input pin. The timer periodically provides a trigger signal according to the first control signal. The processor is coupled to the first memory and stores a first data in the first memory. The output module is coupled to the output pin. The direct memory access is coupled between the output module and the first memory, obtains the first data from the first memory corresponding to the trigger signal, and transmits the first data to the output module. The output module provides the first data to the output pin according to a transmission rate.

Description

Technical Field

[0001] The present invention relates to an integrated circuit, a monitoring system and a monitoring method thereof, and particularly to a monitoring system for monitoring a memory of an integrated circuit. Background Art

[0002] Microcontroller Units (MCUs) or microprocessors are widely used in various industrial, household electrical products or devices. Currently, the program development of microcontrollers / microprocessors must use a chip simulation system and utilize breakpoints to monitor the execution status of the program in order to debug the program. Summary of the Invention

[0003] The present invention provides an integrated circuit. The integrated circuit includes at least one input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module, and a direct memory access (DMA) unit. The controller is coupled to the input pin and provides a first control signal in response to an instruction from the input pin. The timer periodically provides a trigger signal according to the first control signal. The processor is coupled to the first memory and is used to store a first data into the first memory. The output module is coupled to the output pin. The DMA unit is coupled between the output module and the first memory, and obtains the first data from the first memory in response to the trigger signal and transfers the first data to the output module. The output module provides the first data to the output pin according to a transfer rate.

[0004] Furthermore, the present invention provides a monitoring system. The monitoring system includes a bridge and an integrated circuit. The integrated circuit includes at least one input pin, a controller, a timer, a first memory, at least one first output pin, a first output module, and a DMA unit. The input pin is coupled to the bridge and is used to receive an instruction from the bridge. The controller is directly coupled to the input pin and provides a first control signal in response to the instruction. The timer periodically provides a trigger signal according to the first control signal. The first output module is coupled to the first output pin. The DMA unit is coupled between the first output module and the first memory, and obtains a first data from the first memory in response to the trigger signal and transfers the first data to the first output module. The first output module provides the first data to the first output pin according to a first transfer rate.

[0005] Furthermore, the present invention provides a monitoring method applicable to a memory of an integrated circuit. When a bridge is connected to the above-mentioned integrated circuit, an instruction is obtained from the above-mentioned bridge. According to the above-mentioned instruction, a first transfer rate of a first output module of the above-mentioned integrated circuit is set. According to the above-mentioned instruction, a timer of the above-mentioned integrated circuit is set to periodically provide a trigger signal. In response to the above-mentioned trigger signal, a first data is obtained from the above-mentioned first memory via a direct memory access of the above-mentioned integrated circuit. According to the above-mentioned first transfer rate, the above-mentioned first data is provided to the outside of the above-mentioned integrated circuit via the above-mentioned first output module. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. shows a monitoring system for memory content according to some embodiments of the present invention.

[0007] Figure 2 FIG. shows a monitoring system for memory content according to some embodiments of the present invention.

[0008] Figure 3 FIG. shows a monitoring method according to some embodiments of the present invention for instantaneously monitoring a memory in an integrated circuit.

[0009] REFERENCE NUMERALS:

[0010] 10a, 10b: integrated circuits

[0011] 15a - 15n: blocks

[0012] 20: bridge

[0013] 21 - 22, 31 - 33: pins

[0014] 30a, 30b: adapters

[0015] 40: display

[0016] 100A, 100B: monitoring systems

[0017] 110: controller

[0018] 120a, 120b: output modules

[0019] 130: timer

[0020] 140: direct memory access

[0021] 150, 160: memories

[0022] 170: processor

[0023] 180: functional circuit

[0024] Ctrl1 - Ctrl4: Control signals

[0025] DAT, DAT1: Data

[0026] ICE_CLK: Clock signal

[0027] ICE_DAT: Instruction

[0028] S310 - S350: Steps

[0029] Trig: Trigger signal Detailed implementation manners

[0030] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following provides preferred embodiments and, in conjunction with the accompanying drawings, detailed descriptions are as follows:

[0031] To debug a microcontroller / microprocessor, an In Circuit Emulator (ICE) can be used. The microcontroller / microprocessor to be tested can be set in an integrated circuit on a printed circuit board, and the in - circuit emulator can be coupled between the printed circuit board and a processing device. The processing device can be a computer / electronic device such as a personal computer, a tablet, or a mobile phone, and the above - mentioned processing device has an Integrated Development Environment (IDE). Therefore, engineers can simulate the behavior of the microcontroller / microprocessor on the chip through the integrated development system software to shorten the time for program development and debugging.

[0032] Figure 1Monitoring system 100A for displaying the memory content according to some embodiments of the present invention. The monitoring system 100A includes an integrated circuit 10a, a bridge 20, an adapter 30a, and a display 40. In some embodiments, the integrated circuit 10a is a chip under test disposed on a printed circuit board and having a plurality of pins. In some embodiments, the integrated circuit 10a can be a microcontroller or a microprocessor. In some embodiments, the display 40 can be a personal computer with integrated development system software (IDE). The bridge 20 can be an emulator used in an integrated development system software environment, such as ULink, J-Link, or Nu-Link, etc. In some embodiments, through the integrated development system software, the bridge 20 can access the registers and memories within the integrated circuit 10a, and control the controller 110 within the integrated circuit 10a to execute different programs and obtain the execution results. At the same time, in the integrated development system software environment, the user can diagnose the operating state of the integrated circuit 10a through the bridge 20. In some embodiments, the operation of the bridge 20 is set by a personal computer (such as the display 40) with integrated development system software. In some embodiments, the bridge 20 has a memory, and the bridge 20 performs corresponding operations according to the debug mode or program stored in the memory.

[0033] Integrated circuit 10a includes a controller 110, an output module 120a, a timer 130, a Direct Memory Access (DMA) 140, a memory 150, a processor 170, and a functional circuit 180. In this embodiment, the Direct Memory Access 140 may be a Peripheral Direct Memory Access (PDMA). The controller 110 is coupled to the bridge 20 via pins 21 and 22. Pins 21 and 22 are input pins, and the controller 110 is directly coupled to pins 21 and 22. In integrated circuit 10a, pin 21 is used to receive the clock signal ICE_CLK from the bridge 20, and pin 22 is used to receive the instruction ICE_DAT from the bridge 20. In some embodiments, integrated circuit 10a receives the instruction ICE_DAT from the bridge 20 via multiple pins. The controller 110 is coupled to the output module 120a, the timer 130, and the Direct Memory Access 140. According to the instruction ICE_DAT from the bridge 20, the controller 110 provides control signals Ctrl1, Ctrl2, and Ctrl3 to the timer 130, the output module 120a, and the Direct Memory Access 140, respectively. In this embodiment, the output module 120a is a universal asynchronous receiver / transmitter (UART) output module, hereinafter simply referred to as the UART output module 120a. The UART output module 120a is coupled to the adapter 30a via pin 31. In this embodiment, the adapter 30a is a universal serial bus (USB)-to-universal asynchronous receiver / transmitter (USB-to-UART) connector, which is used to convert the UART signal from pin 31 into a USB signal and transmit the USB signal to the display 40. In some embodiments, the display 40 may be a processing device such as a personal computer, a tablet, or a mobile phone.

[0034] In an embodiment of the present invention, the direct memory access (DMA) controller 140 can be used for data transfer. In addition, the DMA controller 140 can transfer data from one device (or address) to another device (or address) without going through the processor 170 (or controller). As a result, the workload of the processor 170 can be reduced, enabling the processor 170 to execute other applications. In some embodiments, the DMA controller 140 can set up a transfer channel to transfer data between a memory and a device or between different memories. In some embodiments, the processor 170 can be a central processing unit (CPU). In some embodiments, the functional circuit 180 can perform specific functions. For example, the functional circuit 180 can be a controller, converter, receiver, transmitter, transceiver, etc. of a peripheral device.

[0035] In Figure 1 , according to the control signal Ctrl1 from the controller 110, the timer 130 periodically provides a trigger signal Trig to the DMA controller 140. In some embodiments, the timer 130 can be implemented within the controller 110, so the controller 110 periodically provides the trigger signal Trig to the DMA controller 140. In addition, according to the control signal Ctrl2 from the controller 110, the DMA controller 140 sets up a transfer channel to access the memory 150 in response to the trigger signal Trig and obtain data DAT. Then, after obtaining the data DAT, the DMA controller 140 transfers the data DAT to the UART output module 120a. The memory 150 includes multiple blocks 15a - 15n. In some embodiments, the block accessed by the DMA controller 140 is determined by the control signal Ctrl2, i.e., the transfer channel. Furthermore, according to the control signal Ctrl3 from the controller 110, the UART output module 120a transmits the data DAT to the adapter 30a via pin 31 according to the UART communication protocol. In this embodiment, the UART output module 120a sets the transfer rate of the data DAT according to the control signal Ctrl3. As a result, the data DAT is transmitted to the display 40 via the adapter 30a for the user to perform real-time monitoring of the memory 150. Therefore, in some embodiments, the user can simultaneously use the bridge 20 to debug the integrated circuit 10a and monitor the data in the memory 150 through the UART output module 120a. In some embodiments, the UART output module 120a is an output module that is idle during the detection operation.

[0036] In some embodiments, the integrated circuit 10a includes more memory, such as memory 160. Similarly, according to the control signal Ctrl2 from the controller 110, the direct memory accessor 140 accesses the memory 160 in response to the trigger signal Trig to obtain the data DAT1. Then, after obtaining the data DAT from the memory 150 and the data DAT1 from the memory 160, the direct memory accessor 140 sequentially transmits the data DAT and DAT1 to the UART output module 120a. Next, according to the control signal Ctrl3 from the controller 110, the UART output module 120a transmits the data DAT and DAT1 to the adapter 30a via the pin 31 according to the UART communication protocol. In some embodiments, the order of transmission of the data DAT and DAT1 is determined by the control signal Ctrl3.

[0037] In the integrated circuit 10a, when the direct memory accessor 140 transmits the data DAT externally, the processor 170 controls the operation of the functional circuit 180 and does not participate in transmitting the data DAT. In some embodiments, the data in the memory 150 is stored by the processor 170. In some embodiments, the processor 170 stores the data DD of the functional circuit 180 in the memory 150, and the data DD can be debug data or arithmetic data generated during operation. In addition, compared with the controller 110, the processor 170 is not coupled to the pin 21 and the pin 22. In some embodiments, the processor 170 stores the data DD of other circuits (not shown) or operations in the memory 150.

[0038] Figure 2A monitoring system 100B for displaying the memory content according to some embodiments of the present invention is shown. The monitoring system 100B includes an integrated circuit 10b, a bridge 20, adapters 30a and 30b, and a display 40. In some embodiments, the integrated circuit 10b is a chip under test disposed on a printed circuit board and having a plurality of pins. The integrated circuit 10b includes a controller 110, a UART output module 120a, a timer 130, a direct memory accessor 140, a memory 150, an output module 120b, a processor 170, and a functional circuit 180. Similarly, the controller 110 is coupled to the bridge 20 via pins 21 and 22. The controller 110 is coupled to the UART output module 120a, the timer 130, the direct memory accessor 140, and the output module 120b. According to the instruction ICE_DAT from the bridge 20, the controller 110 provides control signals Ctrl1, Ctrl2, Ctrl3, and Ctrl4 to the timer 130, the UART output module 120a, the direct memory accessor 140, and the output module 120b, respectively. In this embodiment, the output module 120b is a serial peripheral bus (SPI), hereinafter simply referred to as the SPI output module 120b. The SPI output module 120b is coupled to the adapter 30b via pins 32 and 33. In this embodiment, the adapter 30b is a universal serial bus to serial peripheral bus interface adapter (USB-to-SPI connector) for converting SPI-related signals from pins 32 and 33 into USB signals and transmitting the USB signals to the display 40. In some embodiments, the display 40 may be a processing device such as a personal computer, a tablet, or a mobile phone.

[0039] In Figure 2 , according to the control signal Ctrl1 from the controller 110, the timer 130 periodically provides a trigger signal Trig to the direct memory accessor 140. In addition, according to the control signal Ctrl2 from the controller 110, the direct memory accessor 140 sets up a transfer channel to access the memory 150 corresponding to the trigger signal Trig to obtain data DAT.

[0040] In some embodiments, according to the first transmission channel, after the direct memory accessor 140 obtains the data DAT from the first block (e.g., block 15a), it transmits the data DAT from the first block to the UART output module 120a. Then, according to the control signal Ctrl3 from the controller 110, the UART output module 120a transmits the data DAT from the first block to the adapter 30a via the pin 31 according to the UART communication protocol. In addition, according to the second transmission channel, after the direct memory accessor 140 obtains the data DAT from the second block (e.g., block 15b), it transmits the data DAT from the second block to the SPI output module 120b. Then, according to the control signal Ctrl4 from the controller 110, the SPI output module 120b transmits the data DAT from the second block to the adapter 30b via the pins 32 and 33 according to the SPI communication protocol. The UART output module 120a sets the transmission rate of the data DAT from the first block according to the control signal Ctrl3. In addition, the SPI output module 120b sets the transmission rate of the data DAT from the second block according to the control signal Ctrl4. Thus, the data DAT from different blocks are respectively transmitted to the display 40 via the adapters 30a and 30b for the user to monitor in real time. In some embodiments, the user can simultaneously use the bridge 20 to detect the integrated circuit 10b and instantaneously monitor the data in different blocks in the memory 150 through the UART output module 120a and the SPI output module 120b. In some embodiments, the UART output module 120a and the SPI output module 120b are output modules that are idle during the detection operation.

[0041] In some embodiments, the integrated circuit 10b includes more memory, such as the memory 160. Similarly, according to the control signal Ctrl2 from the controller 110, the direct memory accessor 140 accesses the memory 160 corresponding to the trigger signal Trig to obtain the data DAT1. Then, according to the third transmission channel and the fourth transmission channel, after obtaining the data DAT of the memory 150 and the data DAT1 of the memory 160, the direct memory accessor 140 transmits the data DAT and DAT1 to the UART output module 120a and the SPI output module 120b respectively. Next, according to the control signal Ctrl3 from the controller 110, the UART output module 120a sequentially transmits the data DAT to the adapter 30a via the pin 31 according to the UART communication protocol. In addition, according to the control signal Ctrl4 from the controller 110, the SPI output module 120b sequentially transmits the data DAT1 to the adapter 30b via the pins 32 and 33 according to the SPI communication protocol. Thus, the data DAT and DAT1 from different memories are transmitted to the display 40 via the adapters 30a and 30b respectively for the user to monitor in real time. In some embodiments, the user can simultaneously use the bridge 20 to detect the integrated circuit 10b and monitor the data of different memories in real time through the UART output module 120a and the SPI output module 120b.

[0042] In the embodiments of the present invention, the UART output module 120a and the SPI output module 120b are output modules using different communication protocols. In some embodiments, the output module 120a and the output module 120b can be output modules using the same communication protocol. In some embodiments, the output module 120a and the output module 120b can use the same transmission rate. In some embodiments, the output module 120a and the output module 120b can use different transmission rates. In addition, each output module can be coupled to the corresponding adapter according to the actual application using the corresponding pins. In some embodiments, the output module 120a and / or the output module 120b can be a UART output module, an SPI output module, an inter-integrated circuit (I2C) output module, a general-purpose input / output (GPIO) output module, etc. In some embodiments, the display 40 can directly receive the data from the output module 120a and / or the output module 120b, so the adapters 30a and / or 30b can be omitted.

[0043] Figure 3Disclosed is a monitoring method according to some embodiments of the present invention for instantaneously monitoring memories (such as memory 150 and / or memory 160) within an integrated circuit (such as integrated circuit 10a and / or integrated circuit 10b). First, in step S310, when a bridge (such as bridge 20) is connected to the integrated circuit, an instruction (such as instruction ICE_DAT) is obtained from the bridge. Next, in step S320, according to the instruction of the bridge, relevant output modules (such as output modules 120a and / or 120b) are set, for example, the transmission rate is set according to the corresponding communication protocol. Then, in step S330, according to the instruction of the bridge, the time or period for a timer (such as timer 130) to provide a trigger signal Trig is set. Next, in step S340, according to the instruction of the bridge, the transfer task and the corresponding transfer channel of a direct memory accessor (such as direct memory accessor 140) are set to transfer data between the memory and the output module. Then, in step S350, corresponding to the periodic trigger signal Trig, the direct memory accessor transfers data from the specified block or specified memory to the corresponding output module according to the transfer channel, so as to provide the data of the memory to an external electronic device (such as display 40), enabling the user to instantaneously monitor the memory. In some embodiments, the direct memory accessor can transfer the contents of different blocks of the memory to the same or different output modules. In addition, the direct memory accessor can transfer the contents of different memories to the same or different output modules.

[0044] According to an embodiment of the present invention, without affecting the normal operation of the processor of the integrated circuit and without occupying the operation of the bridge, the data of the memory can be transferred to the specified output module by using a direct memory accessor, so that the memory can be instantaneously monitored or debugged through an external electronic device (such as display 40).

[0045] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the spirit and scope of the present invention, may make some modifications and refinements. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. An integrated circuit, characterized in that, Comprising: At least one input pin; A controller, coupled to the input pin, configured to provide a first control signal in response to an instruction from the input pin; A timer, configured to periodically provide a trigger signal according to the first control signal; A first memory; A processor, coupled to the first memory, configured to store a first data in the first memory; At least one output pin; An output module, coupled to the output pin; And A direct memory accessor, coupled between the output module and the first memory, configured to obtain the first data from the first memory in response to the trigger signal and transfer the first data to the output module; Wherein the output module provides the first data to the output pin according to a transfer rate.

2. The integrated circuit according to claim 1, wherein, The timer is implemented in the controller.

3. The integrated circuit according to claim 1, wherein, The controller further provides a second control signal to the output module to set the transfer rate, and the controller further provides a third control signal to the direct memory accessor, and the direct memory accessor obtains the first data from a specific block of the first memory according to the third control signal.

4. The integrated circuit according to claim 1, wherein Further comprising: A second memory; Wherein the direct memory accessor further obtains a second data from the second memory in response to the trigger signal and transfers the second data to the output module; Wherein the output module provides the second data to the output pin according to the transfer rate.

5. A monitoring system, characterized in that, Comprising: A bridge; And An integrated circuit, comprising: At least one input pin, coupled to the bridge, configured to receive an instruction from the bridge; A controller, directly coupled to the input pin, configured to provide a first control signal in response to the instruction; A timer, configured to periodically provide a trigger signal according to the first control signal; A first memory; At least one first output pin; A first output module, coupled to the first output pin; and A direct memory accessor, coupled to the first output module and the first memory, configured to obtain a first data from the first memory in response to the trigger signal and transfer the first data to the first output module; Wherein the first output module provides the first data to the first output pin according to a first transfer rate.

6. The monitoring system according to claim 5, wherein The controller further provides a second control signal to the first output module respectively to set the first transfer rate.

7. The monitoring system according to claim 5, wherein The timer is implemented in the controller.

8. A monitoring method, characterized in that, A memory applicable to an integrated circuit, comprising: When a bridge is connected to the integrated circuit, obtaining an instruction from the bridge via a controller of the integrated circuit; According to the instruction, setting a first transfer rate of a first output module of the integrated circuit; In response to the instruction from the bridge, setting a timer of the integrated circuit via the controller so as to periodically provide a trigger signal; In response to the trigger signal, a first data is obtained from the memory via a direct memory accessor of the integrated circuit; and According to the first transfer rate, the first data is provided to the outside of the integrated circuit via the first output module.

9. The monitoring method according to claim 8, characterized in that The integrated circuit is coupled to an electronic device via an adapter, and the first output module provides the first data to the electronic device via the adapter.

10. The monitoring method according to claim 8, characterized in that, The step of obtaining the first data from the memory via the direct memory accessor of the integrated circuit in response to the trigger signal further includes: According to the instruction, the first data is obtained from a specific block of the memory via the direct memory accessor.

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