Information transmission method and device, storage medium and electronic equipment

Abstract

The application discloses an information transmission method applied to an information transmission system, wherein the information transmission system comprises a first control chip, a second control chip and a storage chip; the first control chip is connected with the storage chip through a first communication interface; the second control chip is connected with the storage chip through a second communication interface; the method comprises the following steps: when the first control chip monitors that a target pin corresponding to the first communication interface is in a non-occupied state, the first control chip performs information transmission with the storage chip; and when the second control chip monitors that a target pin corresponding to the second communication interface is in a non-occupied state, the second control chip performs information transmission with the storage chip. According to the application, the communication effect between the first control chip and the second control chip is avoided from being affected.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an information transmission method, apparatus, storage medium, and electronic device. Background Technology

[0002] The main control chip and the microprocessor unit can communicate via an I2C serial bus (Inter-Integrated Circuit) or a universal serial data bus (UART). Summary of the Invention

[0003] This application provides an information transmission method, apparatus, storage medium, and electronic device, which allows information to be transmitted between a first control chip and a second control chip without using an I2C serial bus or UART. Instead, a storage chip acts as a bridge between the two chips to store the information. Even with a large amount of information to be transmitted, it will not affect instruction transmission or cause congestion on the communication channel between the two chips, thus preventing any impact on the communication performance between them. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide an information transmission method applied to an information transmission system. The information transmission system includes a first control chip, a second control chip, and a storage chip. The first control chip and the storage chip are connected via a first communication interface, and the second control chip and the storage chip are connected via a second communication interface. The method includes:

[0005] When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip transmits information to the memory chip.

[0006] When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip transmits information with the memory chip.

[0007] Secondly, embodiments of this application provide an information transmission device applied to an information transmission system. The information transmission system includes a first control chip, a second control chip, and a storage chip. The first control chip and the storage chip are connected via a first communication interface, and the second control chip and the storage chip are connected via a second communication interface. The device includes:

[0008] The first information transmission module is used to transmit information between the first control chip and the memory chip when the first control chip monitors that the target pin corresponding to the first communication interface is in an unoccupied state.

[0009] The second information transmission module is used to transmit information between the second control chip and the memory chip when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state.

[0010] Thirdly, embodiments of this application provide an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to execute the method steps of the first aspect described above.

[0011] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0012] In this embodiment, by adding a storage chip to the information transmission system cooperating between the first and second control chips, when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the storage chip transmit information; when the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the storage chip transmit information. This allows the information to be transmitted between the first and second control chips to be stored without using an I2C serial bus or UART. Even if the amount of information transmitted is large, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication performance between them. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of an information transmission system provided in an embodiment of this application;

[0015] Figure 2 This is a schematic diagram of the structure of an information transmission system provided in an embodiment of this application;

[0016] Figure 3 This is a flowchart illustrating an information transmission method provided in an embodiment of this application;

[0017] Figure 4 This is a flowchart illustrating an information transmission method provided in an embodiment of this application;

[0018] Figure 5 This is a flowchart illustrating an information transmission method provided in an embodiment of this application;

[0019] Figure 6 This is a flowchart illustrating an information transmission method provided in an embodiment of this application;

[0020] Figure 7 This is an example schematic diagram of an information transmission system provided in an embodiment of this application;

[0021] Figure 8 This is a flowchart illustrating an information transmission method provided in an embodiment of this application;

[0022] Figure 9 This is a schematic diagram of the structure of an information transmission device provided in an embodiment of this application;

[0023] Figure 10 This is a schematic diagram of the structure of an information transmission device provided in an embodiment of this application;

[0024] Figure 11 This is a schematic diagram of the structure of an information transmission device provided in an embodiment of this application;

[0025] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0027] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0029] This method can be implemented using a computer program and can run on information transmission devices based on the von Neumann architecture. The computer program can be integrated into applications or run as a standalone utility application.

[0030] In this application embodiment, the information transmission system can be a mobile terminal, tablet computer, handheld device, wearable device, computing device, smart interactive flat panel, or other processing device.

[0031] The present application will now be described in detail with reference to specific embodiments.

[0032] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of this application. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.

[0033] The communication between the main control chip and the microcontroller unit is mainly used to transmit control, alarm, and active reporting commands. If it is used to transmit Log information, when the amount of Log information transmitted between the two is large, it will cause congestion in the communication channel and affect the communication effect between the main control chip and the microprocessor unit.

[0034] Please see Figure 1 This is a schematic diagram of an information transmission system, which includes a first control chip, a second control chip, and a storage chip.

[0035] The first control chip can be the main control chip, which is a core component of the motherboard or hard drive. The second control chip can be a microcontroller unit, which appropriately reduces the frequency and specifications of the central processing unit (CPU) and integrates peripheral interfaces such as memory, counters, Universal Serial Bus (USB), and even the liquid crystal display (LCD) driver circuit onto a single chip.

[0036] Memory chips can be implemented using Application Specific Integrated Circuit (ASIC) technology or Field Programmable Gate Array (FPGA) technology. Among these, memory chips can be Flash chips, a type of memory chip where data can be modified through a specific program. In the electronics and semiconductor fields, Flash often refers to Flash Memory, or more precisely, Flash EEPROM Memory, which is independent of both the first and second control chips.

[0037] The first control chip may include a first communication interface, and the second control chip may include a second communication interface. The first communication interface may include at least one interface, and the specific number of interfaces in the communication interface is not limited; it can be a Serial Peripheral Interface (SPI) communication interface or a Secure Digital Input and Output (SDIO) interface. Similarly, the number of interfaces in the second communication interface may be the same as or different from the number of interfaces in the first communication interface. The first communication interface corresponds to the first control chip, and the second communication interface corresponds to the second control chip. Correspondingly, the memory chip includes connection interfaces corresponding to both the first and second communication interfaces.

[0038] Specifically, such as Figure 2As shown, for example, if the first and second communication interfaces use an SPI communication interface, then the target pins corresponding to the first and second communication interfaces can be chip select (CS) pins, and other pins corresponding to the first and second communication interfaces can be clock signal (CLK) pins, master output / slave input (MOSI) pins, and master input / slave output (MISO) pins. Therefore, the first control chip is connected to the memory chip through the first communication interface, and the second control chip is connected to the memory chip through the second communication interface. This can be achieved by connecting each pin of the first communication interface to the corresponding pin of the second communication interface before connecting to the memory chip.

[0039] All of the following embodiments are implemented based on the information transmission system described above.

[0040] Please see Figure 3 This is a flowchart illustrating an information transmission method provided in an embodiment of this application. The information transmission method is applied to an information transmission system and may include the following steps:

[0041] S101, when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the memory chip transmit information.

[0042] The target pin can be a chip select pin, also known as an enable pin, which indicates whether the chip containing the target pin is selected and whether it is independently transmitting data, addresses, or commands with a particular chip. The target pin can have two voltage levels: occupied and unoccupied. When the target pin is occupied, it indicates that the memory chip is currently transmitting information; when the target pin is unoccupied, it indicates that the memory chip is not currently transmitting information. The target pin can be in a high voltage level state when it is occupied and in a low voltage level state when it is unoccupied.

[0043] The first control chip can monitor the level status of the target pin corresponding to the first communication interface in real time. The monitored level status of the target pin can be high or low. When the first control chip monitors the target pin as high, it means that the first control chip and the second control chip are not transmitting information with the memory chip. That is, the first control chip can start transmitting information with the memory chip.

[0044] The information transmission between the first control chip and the memory chip can store information in the memory chip or read information stored in the memory chip.

[0045] S102, when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the storage chip transmit information.

[0046] The second control chip can monitor the level status of the target pin corresponding to the second communication interface in real time. The monitored level status of the target pin can be high or low. When the second control chip monitors the target pin as high, it means that the first and second control chips are not transmitting information with the memory chip. That is, the second control chip can start transmitting information with the memory chip.

[0047] The information transmission between the second control chip and the memory chip can store information in the memory chip or read information stored in the memory chip.

[0048] In this embodiment, by adding a storage chip to the information transmission system cooperating between the first and second control chips, when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the storage chip transmit information; when the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the storage chip transmit information. This allows the information to be transmitted between the first and second control chips to be stored without using an I2C serial bus or UART. Even if the amount of information transmitted is large, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication performance between them.

[0049] Please see Figure 4 This is a flowchart illustrating an information transmission method provided in an embodiment of this application. The information transmission method is applied to an information transmission system and may include the following steps:

[0050] S201, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, the first control chip writes first information to the storage chip; or; when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, the first control chip reads the first information and / or second information from the storage chip, wherein the second information is information written to the storage chip by the second control chip;

[0051] The first information is the information that the first control chip needs to store in the storage chip. The first information can be log information, which is used to record the system's operating information.

[0052] Currently, the memory chip may store first information previously written to the memory chip by the first control chip, or second information stored to the memory chip by the second control chip. The first control chip can read both this information and the second information, or it can read only one type of information as needed.

[0053] The first control chip transmits information with the memory chip, and at the same time, the first control chip sets the target pin corresponding to the first communication interface to a low level.

[0054] Based on the characteristic that the target pin is a chip select pin, when the first control chip and the memory chip are transmitting information, the level state needs to be set to a low level state to inform the outside world that there is currently a chip and the memory chip transmitting information.

[0055] S202, the first control chip sets the target pin corresponding to the first communication interface to a high level.

[0056] After the first control chip and the memory chip have completed the information transmission, the control over the memory chip should be released. The first control chip can set the level of the target pin to a high level to indicate to the external first control chip that the information transmission between the first control chip and the memory chip has ended.

[0057] In this embodiment, by adding a storage chip to the information transmission system cooperating between the first and second control chips, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, if the first control chip needs to write information to the storage chip, it can choose to write the first information to the storage chip. If the first control chip needs to read information stored in the storage chip, it can also read the first information previously written to the storage chip by the first control chip or the second information previously written to the storage chip by the second control chip. After the information transmission between the first control chip and the storage chip is completed, the first control chip can set the target pin corresponding to the first communication interface to a high level to inform the external system that the information transmission process between the first control chip and the storage chip has ended, and other chips can begin information transmission with the storage chip. This allows the information to be transmitted between the first and second control chips to be stored without using the I2C serial bus or UART. The storage chip acts as a bridge between the first and second control chips, ensuring that even with a large amount of information transmitted, it will not affect instruction transmission or cause congestion on the communication channel between the first and second control chips, thus preventing any impact on the communication effect between them.

[0058] Please see Figure 5 This is a flowchart illustrating an information transmission method provided in an embodiment of this application. The information transmission method is applied to an information transmission system and may include the following steps:

[0059] S301, when the second control chip monitors that the target pin corresponding to the second communication interface is in a high-level state, the second control chip writes second information to the storage chip; or; when the second control chip monitors that the target pin corresponding to the second communication interface is in a high-level state, the second control chip reads first information or second information from the storage chip, wherein the first information is the information written by the first control chip to the storage chip;

[0060] Currently, the memory chip may store first information previously written to the memory chip by the first control chip, or second information stored to the memory chip by the second control chip. The second control chip can read both the first and second information, or read only one of them.

[0061] The second control chip transmits information with the memory chip, and at the same time, the second control chip sets the target pin corresponding to the second communication interface to a low level.

[0062] Based on the characteristic that the target pin is a chip select pin, when the second control chip and the memory chip are transmitting information, the level state needs to be set to a low level state to inform the outside world that there is currently a chip and the memory chip transmitting information.

[0063] S302, the second control chip sets the target pin corresponding to the second communication interface to a high level.

[0064] After the second control chip and the memory chip have completed the information transmission, the control over the memory chip should be released. The second control chip can set the level of the target pin to a high level to indicate to the external second control chip that the information transmission process between the second control chip and the memory chip has ended.

[0065] It should be noted that, in practical applications, the method embodiments in this application may only perform the process of information transmission between the first control chip and the memory chip, or only perform the process of information transmission between the second control chip and the memory chip, or the processes of information transmission between the two and the memory chip may be executed alternately.

[0066] In this embodiment, by adding a storage chip to the information transmission system of the first and second control chips, when the second control chip monitors that the target pin corresponding to the second communication interface is in a high-level state, if the second control chip needs to write information to the storage chip, it can choose to write second information to the storage chip. If the second control chip needs to read information stored in the storage chip, it can also read the second information previously written to the storage chip or the first information previously written to the storage chip by the first control chip. After the information transmission between the second control chip and the storage chip is completed, the second control chip can set the target pin corresponding to the second communication interface to a high level to inform the external chip that the information transmission process between the second control chip and the storage chip has ended, and other chips can start information transmission with the storage chip. This allows the information to be transmitted between the first and second control chips to be stored without using the I2C serial bus or UART. The storage chip acts as a bridge between the first and second control chips, ensuring that even if the amount of information transmitted is large, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication effect between the first and second control chips.

[0067] Please see Figure 6 This is a flowchart illustrating an information transmission method provided in an embodiment of this application. The information transmission method is applied to an information transmission system, which may further include at least one fixed memory. For example, please refer to... Figure 7The first control chip can be connected to a fixed memory, and the second control chip can be connected to another fixed memory. The connection method is not limited. The information transmission method may include the following steps:

[0068] 401. When the first control chip detects that the target pin corresponding to the first communication interface is in a low-level state, and the second control chip is transmitting information with the storage chip, the first control chip stores the corresponding information in the fixed memory and continuously monitors the level state of the target pin.

[0069] The first control chip and the second control chip use the same file system format.

[0070] The software component in an operating system responsible for managing and storing file information is called the file management system, or simply the file system. A file system is the method and data structure used by the operating system to define files on a storage device or partition; in other words, it's the method by which files are organized on a storage device.

[0071] The file system specifies rules for naming files. These rules include the maximum number of characters in a filename, which characters can be used, and the length of filename extensions on some systems. The file system also includes a format for locating specified paths to files using the directory structure. Therefore, using a file system with the same format facilitates file searching on the storage chip and allows for faster retrieval of the required files.

[0072] When the first control chip detects that the target pin is in a low-level state, there are two possibilities: first, the first control chip is transmitting information with the memory chip; second, the second control chip is currently transmitting information with the memory chip. When the second control chip is transmitting information with the memory chip, the first control chip cannot transmit information with the memory chip. Therefore, when the first control chip needs to store information to the memory chip, it can temporarily store this information in a fixed-function memory. When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, it then retrieves this information from the fixed-function memory and stores it in the memory chip.

[0073] Fixed memory can be any type of memory that can perform storage functions, such as Random Access Memory (RAM), Read Only Memory (ROM), etc.

[0074] 402. When the first control chip detects that the level state of the target pin changes from a low level state to a high level state, the first control chip reads the corresponding information from the fixed memory and writes the information to the memory chip.

[0075] When the first control chip detects that the level of the target pin changes from low to high, it indicates that the memory chip is not currently transmitting information with any chip. Therefore, the first control chip can read the corresponding information from the fixed memory and store it in the memory chip.

[0076] In this embodiment, when necessary, the information corresponding to the first control chip is stored in a fixed memory. When the first control chip monitors the target pin's level state switching from a low level to a high level, the first control chip reads the corresponding information from the fixed memory and writes the information to the memory chip. This makes the information transmission process more flexible and convenient. It also allows the information that the first and second control chips need to transmit to each other without needing to be transmitted through an I2C serial bus or UART. The memory chip acts as a bridge between the first and second control chips for information storage. Even if the amount of information transmitted is large, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication effect between them.

[0077] Please see Figure 8 This is a flowchart illustrating an information transmission method provided in an embodiment of this application. The information transmission method is applied to an information transmission system, which may further include at least one fixed memory. For example, please refer to... Figure 7 The first control chip can be connected to a fixed memory, and the second control chip can be connected to another fixed memory. The connection method is not limited. The information transmission method may include the following steps:

[0078] S501, when the second control chip monitors that the target pin corresponding to the second communication interface is in a low-level state, and the first control chip and the storage chip are transmitting information, the second control chip stores the corresponding information in the fixed memory and continuously monitors the level state of the target pin;

[0079] When the second control chip detects that the target pin is in a low-level state, there are two possibilities: first, the second control chip is transmitting information with the memory chip; second, the first control chip is currently transmitting information with the memory chip. When the first control chip is transmitting information with the memory chip, the second control chip cannot transmit information with the memory chip. Therefore, when the second control chip needs to store information to the memory chip, it can temporarily store this information in a fixed-function memory. When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, it then retrieves this information from the fixed-function memory and stores it in the memory chip.

[0080] It should be noted that, as Figure 8 As shown, the information corresponding to the first control chip and the information corresponding to the second control chip can be stored in different memories. Of course, the information corresponding to the first control chip and the information corresponding to the second control chip can be stored in the same memory.

[0081] S502, when the second control chip monitors that the level state of the target pin changes from the low level state to the high level state, the second control chip reads the corresponding information from the fixed memory and writes the information to the memory chip.

[0082] When the second control chip detects that the level of the target pin changes from low to high, it indicates that the memory chip is not currently transmitting information with any chip. Therefore, the second control chip can read the corresponding information from the fixed memory and store it in the memory chip.

[0083] In this embodiment, the information corresponding to the first control chip is stored in a fixed memory. When the second control chip detects that the level of the target pin has switched from a low level to a high level, the second control chip reads the corresponding information from the fixed memory and writes the information to the memory chip. This makes the information transmission process more flexible and convenient. It also allows the information to be transmitted between the first and second control chips to be stored without using an I2C serial bus or UART. The memory chip acts as a bridge between the two chips, ensuring that even with a large amount of information transmitted, it does not affect instruction transmission or cause congestion on the communication channel between the two chips, thus preventing any impact on the communication performance between them.

[0084] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0085] Please see Figure 9 This illustration shows a schematic diagram of an information transmission device provided in an exemplary embodiment of this application. The information transmission device can be implemented as all or part of a terminal through software, hardware, or a combination of both. The information transmission device is applied to an information transmission system, which includes a first control chip, a second control chip, and a storage chip. The first control chip and the storage chip are connected via a first communication interface, and the second control chip and the storage chip are connected via a second communication interface. The information transmission device 1 includes a first information transmission module 11 and a second information transmission module 12.

[0086] The first information transmission module 11 is used to transmit information between the first control chip and the memory chip when the first control chip monitors that the target pin corresponding to the first communication interface is in an unoccupied state.

[0087] The second information transmission module 12 is used to transmit information between the second control chip and the memory chip when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state.

[0088] Optionally, the unoccupied state includes the target pin corresponding to the first communication interface being in a high-level state.

[0089] Optionally, the first information transmission module 11 is specifically used for:

[0090] When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip writes the first information to the memory chip.

[0091] or;

[0092] When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip reads the first information and / or the second information from the storage chip, wherein the second information is the information written by the second control chip to the storage chip.

[0093] Optionally, the second information transmission module 12 is specifically used for:

[0094] When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip writes the second information to the memory chip.

[0095] or;

[0096] When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip reads either the first information or the second information from the storage chip, wherein the first information is the information written by the first control chip to the storage chip.

[0097] Optionally, the first information transmission module 12 is further specifically used for:

[0098] The first control chip transmits information with the memory chip, and at the same time, the first control chip sets the target pin corresponding to the first communication interface to a low level.

[0099] The second information transmission module 12 is also specifically used for:

[0100] The second control chip transmits information with the memory chip, and at the same time, the second control chip sets the target pin corresponding to the second communication interface to a low level.

[0101] Optional, such as Figure 10 As shown, the device 1 further includes:

[0102] The first state setting module 13 is used for the first control chip to set the target pin corresponding to the first communication interface to a high level state.

[0103] The second state setting module 14 is used by the second control chip to set the target pin corresponding to the second communication interface to a high level.

[0104] Optional, such as Figure 11 As shown, the device 1 further includes:

[0105] The first storage module 15 is used to store the corresponding information in a fixed memory and continuously monitor the level state of the target pin when the first control chip monitors that the target pin corresponding to the first communication interface is in a low level state and the second control chip and the storage chip are transmitting information.

[0106] The first information transmission module 11 is further configured to, when the first control chip monitors that the level state of the target pin switches from the low level state to the high level state, read the corresponding information from the fixed memory and write the information to the memory chip;

[0107] The second storage module 16 is used to store the corresponding information in a fixed memory when the second control chip monitors that the target pin corresponding to the second communication interface is in a low-level state, and when the first control chip and the storage chip are transmitting information, and continuously monitors the level state of the target pin.

[0108] The second information transmission module 12 is further configured to, when the second control chip monitors that the level state of the target pin switches from the low level state to the high level state, read the corresponding information from the fixed memory and write the information to the memory chip.

[0109] Optionally, in the device 1, the first control chip is connected to the memory chip via a first communication interface, and the second control chip is connected to the memory chip via a second communication interface;

[0110] The first control chip and the second control chip use the same file system format.

[0111] It should be noted that the information transmission device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the information transmission method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the information transmission device and the information transmission method embodiments provided in the above embodiments belong to the same concept, and the implementation process can be found in the method embodiments, which will not be repeated here.

[0112] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] In this embodiment, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, if the first control chip needs to write information to the storage chip, the first control chip can choose to write the first information to the storage chip. If the first control chip needs to read the information stored in the storage chip, it can also read the first information previously written to the storage chip by the first control chip or the second information previously written to the storage chip by the second control chip. After the information transmission between the first control chip and the storage chip is completed, the first control chip can set the target pin corresponding to the first communication interface to a high level to inform the external first control chip that the information transmission process between the first control chip and the storage chip has ended, and other chips can start transmitting information with the storage chip. When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, if the second control chip needs to write information to the memory chip, it can choose to write the second information to the memory chip. If the second control chip needs to read information stored in the memory chip, it can also read the second information previously written to the memory chip or the first information previously written to the memory chip by the first control chip. After the information transmission between the second control chip and the memory chip is completed, the second control chip can set the target pin corresponding to the second communication interface to a high level to inform the external chip that the information transmission process between the second control chip and the memory chip has ended, and other chips can start information transmission with the memory chip. The first and second control chips use the same file system format, which facilitates file searching in the memory chip and allows for faster retrieval of the required files. This allows the information to be transmitted between the first and second control chips to be stored without using the I2C serial bus or UART. The memory chip acts as a bridge between the first and second control chips, ensuring that even with a large amount of information transmitted, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication effect between them.

[0114] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0115] Please see Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 12As shown, the electronic device 1000 may include: at least one processor 1001, at least one network interface 1004, a user interface 1003, a memory 1005, and at least one communication bus 1002.

[0116] The communication bus 1002 is used to realize the connection and communication between these components.

[0117] The user interface 1003 may include a display screen and a camera. Optionally, the user interface 1003 may also include a standard wired interface and a wireless interface.

[0118] The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0119] The processor 1001 may include one or more processing cores. The processor 1001 connects to various parts within the electronic device 1000 using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1005, and by calling data stored in the memory 1005. Optionally, the processor 1001 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1001 may integrate one or more of the following: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content to be displayed on the screen; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor 1001.

[0120] The memory 1005 may include random access memory (RAM) or read-only memory. Optionally, the memory 1005 may include a non-transitory computer-readable storage medium. The memory 1005 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 1005 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 1005 may also be at least one storage device located remotely from the aforementioned processor 1001. Figure 12 As shown, the memory 1005, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an information transmission method application program.

[0121] exist Figure 12 In the illustrated electronic device 1000, the user interface 1003 is mainly used to provide an input interface for the user and to acquire user input data; while the processor 1001 can be used to call the information transmission method application stored in the memory 1005. The information transmission method is applied to an information transmission system, which includes a first control chip, a second control chip, and a storage chip. The first control chip and the storage chip are connected through a first communication interface, and the second control chip and the storage chip are connected through a second communication interface, and specifically perform the following operations:

[0122] When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip transmits information to the memory chip.

[0123] When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip transmits information with the memory chip.

[0124] In one embodiment, the unoccupied state includes the target pin corresponding to the first communication interface being in a high-level state.

[0125] In one embodiment, when the processor 1001 performs information transmission with the memory chip when the first control chip monitors that the target pin corresponding to the first communication interface is in an unoccupied state, the processor 1001 specifically performs the following operations:

[0126] When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip writes the first information to the memory chip.

[0127] or;

[0128] When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip reads the first information and / or the second information from the storage chip, wherein the second information is the information written by the second control chip to the storage chip.

[0129] In one embodiment, when the processor 1001 performs information transmission with the memory chip when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state, the processor 1001 specifically performs the following operations:

[0130] When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip writes the second information to the memory chip.

[0131] or;

[0132] When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip reads either the first information or the second information from the storage chip, wherein the first information is the information written by the first control chip to the storage chip.

[0133] In one embodiment, when the processor 1001 performs information transmission between the first control chip and the memory chip, it specifically performs the following operations:

[0134] The first control chip transmits information with the memory chip, and at the same time, the first control chip sets the target pin corresponding to the first communication interface to a low level.

[0135] The information transmission between the second control chip and the memory chip includes:

[0136] The second control chip transmits information with the memory chip, and at the same time, the second control chip sets the target pin corresponding to the second communication interface to a low level.

[0137] In one embodiment, after the processor 1001 performs information transmission between the first control chip and the memory chip, it specifically performs the following operations:

[0138] The first control chip sets the target pin corresponding to the first communication interface to a high level.

[0139] After the second control chip and the memory chip transmit information, the system further includes:

[0140] The second control chip sets the target pin corresponding to the second communication interface to a high level.

[0141] In one embodiment, the processor 1001 performs the following operations:

[0142] When the first control chip detects that the target pin corresponding to the first communication interface is in a low-level state, and the second control chip is transmitting information with the storage chip, the first control chip stores the corresponding information in the fixed memory.

[0143] When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, and the first control chip transmits information with the memory chip, the following operations are performed:

[0144] When the first control chip detects that the level state of the target pin changes from the low level state to the high level state, the first control chip reads the corresponding information from the fixed memory and writes the information to the memory chip;

[0145] Alternatively, the processor 1001 may perform the following operations:

[0146] When the second control chip detects that the target pin corresponding to the second communication interface is in a low-level state, and the first control chip is transmitting information with the storage chip, the second control chip stores the corresponding information in the fixed memory and continuously monitors the level state of the target pin.

[0147] When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, and the second control chip transmits information with the memory chip, the following operations are performed:

[0148] When the second control chip detects that the level state of the target pin changes from the low level state to the high level state, the second control chip reads the corresponding information from the fixed memory and writes the information to the memory chip.

[0149] When the second control chip detects that the target pin corresponding to the second communication interface is in a low-level state, and the first control chip is transmitting information with the storage chip, the second control chip stores the corresponding information in the fixed memory.

[0150] In this embodiment, when the first control chip monitors that the target pin corresponding to the first communication interface is in a high-level state, if the first control chip needs to write information to the storage chip, the first control chip can choose to write the first information to the storage chip. If the first control chip needs to read the information stored in the storage chip, it can also read the first information previously written to the storage chip by the first control chip or the second information previously written to the storage chip by the second control chip. After the information transmission between the first control chip and the storage chip is completed, the first control chip can set the target pin corresponding to the first communication interface to a high level to inform the external first control chip that the information transmission process between the first control chip and the storage chip has ended, and other chips can start transmitting information with the storage chip. When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, if the second control chip needs to write information to the memory chip, it can choose to write the second information to the memory chip. If the second control chip needs to read information stored in the memory chip, it can also read the second information previously written to the memory chip or the first information previously written to the memory chip by the first control chip. After the information transmission between the second control chip and the memory chip is completed, the second control chip can set the target pin corresponding to the second communication interface to a high level to inform the external chip that the information transmission process between the second control chip and the memory chip has ended, and other chips can start information transmission with the memory chip. The first and second control chips use the same file system format, which facilitates file searching in the memory chip and allows for faster retrieval of the required files. This allows the information to be transmitted between the first and second control chips to be stored without using the I2C serial bus or UART. The memory chip acts as a bridge between the first and second control chips, ensuring that even with a large amount of information transmitted, it will not affect the transmission of instructions or cause congestion on the communication channel between the first and second control chips, thus avoiding any impact on the communication effect between them.

[0151] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0152] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

[0153] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0154] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service ports; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0158] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0159] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0160] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. An information transmission method, characterized in that, The method is applied to an information transmission system, which includes a first control chip, a second control chip, and a storage chip. The first control chip and the storage chip are connected via a first communication interface, and the second control chip and the storage chip are connected via a second communication interface. The first control chip and the second control chip use the same file system format. When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip transmits information with the memory chip; when the target pin is in an unoccupied state, it indicates that the memory chip is not currently transmitting information. When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip transmits information with the memory chip. When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the memory chip perform information transmission, including: When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip writes first information to the storage chip, and at the same time sets the target pin corresponding to the first communication interface to an occupied state through the first control chip; the first information is the information that the first control chip needs to store in the storage chip. After the information transmission between the first control chip and the memory chip is completed, the first control chip sets the target pin corresponding to the first communication interface to an unoccupied state. When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the memory chip perform information transmission, including: When the second control chip detects that the target pin is in an unoccupied state, the second control chip reads the first information from the memory chip.

2. The method according to claim 1, characterized in that, The unoccupied state includes the target pin corresponding to the first communication interface being in a high-level state.

3. The method according to claim 2, characterized in that, When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the memory chip perform information transmission, including: When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip writes the first information to the memory chip. or; When the first control chip detects that the target pin corresponding to the first communication interface is in a high-level state, the first control chip reads the first information and / or the second information from the storage chip, wherein the second information is the information written by the second control chip to the storage chip.

4. The method according to claim 2, characterized in that, When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the memory chip perform information transmission, including: When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip writes the second information to the memory chip. or; When the second control chip detects that the target pin corresponding to the second communication interface is in a high-level state, the second control chip reads either the first information or the second information from the storage chip, wherein the first information is the information written by the first control chip to the storage chip.

5. The method according to claim 2, characterized in that, The first control chip and the memory chip transmit information, including: The first control chip transmits information with the memory chip, and at the same time, the first control chip sets the target pin corresponding to the first communication interface to a low level. The second control chip transmits information to the memory chip, including: The second control chip transmits information with the memory chip, and at the same time, the second control chip sets the target pin corresponding to the second communication interface to a low level.

6. The method according to claim 2 or 5, characterized in that, After the first control chip and the memory chip exchange information, the system further includes: The first control chip sets the target pin corresponding to the first communication interface to a high level. After the second control chip and the memory chip transmit information, the system further includes: The second control chip sets the target pin corresponding to the second communication interface to a high level.

7. The method according to claim 2, characterized in that, The method further includes: When the first control chip detects that the target pin corresponding to the first communication interface is in a low-level state, and the second control chip is transmitting information with the storage chip, the first control chip stores the corresponding information in the fixed memory and continuously monitors the level state of the target pin. When the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip and the memory chip perform information transmission, including: When the first control chip detects that the level state of the target pin changes from the low level state to the high level state, the first control chip reads the corresponding information from the fixed memory and writes the information to the memory chip; or; When the second control chip detects that the target pin corresponding to the second communication interface is in a low-level state, and the first control chip is transmitting information with the storage chip, the second control chip stores the corresponding information in the fixed memory and continuously monitors the level state of the target pin. When the second control chip detects that the target pin corresponding to the second communication interface is in an unoccupied state, the second control chip and the memory chip perform information transmission, including: When the second control chip detects that the level state of the target pin has switched from the low level state to the high level state, the second control chip reads the corresponding information from the fixed memory and writes the information to the memory chip.

8. The method according to claim 1, characterized in that, The first control chip is connected to the memory chip via a first communication interface, and the second control chip is connected to the memory chip via a second communication interface, including: The first control chip is connected to the memory chip via a first communication interface, and the second control chip is connected to the memory chip via a second communication interface.

9. An information transmission device, characterized in that, An application in an information transmission system, the information transmission system including a first control chip, a second control chip, and a storage chip, wherein the first control chip and the storage chip are connected via a first communication interface, and the second control chip and the storage chip are connected via a second communication interface, and the first control chip and the second control chip use the same file system format, the device comprising: The first information transmission module is used to transmit information between the first control chip and the memory chip when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state. When the target pin is in an unoccupied state, it indicates that the memory chip is not currently transmitting information. The transmission of information between the first control chip and the memory chip when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state includes: when the first control chip detects that the target pin corresponding to the first communication interface is in an unoccupied state, the first control chip writes first information to the memory chip, and simultaneously sets the target pin corresponding to the first communication interface to an occupied state through the first control chip; the first information is information that the first control chip needs to store in the memory chip; after the information transmission between the first control chip and the memory chip is completed, the first control chip sets the target pin corresponding to the first communication interface to an unoccupied state through the first control chip. The second information transmission module is used to transmit information between the second control chip and the storage chip when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state; the transmission of information between the second control chip and the storage chip when the second control chip monitors that the target pin corresponding to the second communication interface is in an unoccupied state includes: when the second control chip monitors that the target pin is in an unoccupied state, the second control chip reads first information from the storage chip.

10. An electronic device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed the method steps as claimed in any one of claims 1 to 8.

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