An artificial neural network method for transistor modeling

Abstract

The application relates to a method for predicting the drain-source current of a three-terminal transistor, comprising receiving the actual gate-source voltage of the transistor, and generating a first drain-source current value when the drain-source voltage of the transistor is equal to a first reference value by using a first artificial neural network; receiving the actual drain-source voltage of the transistor, and extending a straight line formed by the first drain-source current value and the origin to obtain a second drain-source current; receiving the actual gate-source voltage and the actual drain-source voltage, and generating a first ratio by using a second artificial neural network; and obtaining a predicted value of the drain-source current of the transistor under a current bias condition based on the second drain-source current and the first ratio; the application also relates to an artificial neural network system for predicting the drain-source current of a three-terminal transistor and a method for establishing the same, and two computer-readable storage media.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic device simulation model design, in particular to an artificial neural network method for transistor modeling. BACKGROUND

[0002] With the development of integrated circuit technology beyond Moore's Law, more and more new devices are developed. In order to better use new devices and add them to the application of complex circuits, a model close to the actual working state of the new device in the simulation software is needed for circuit simulation. Therefore, the compact model of the new device directly affects the circuit simulation results and performance evaluation, and further affects the production of the device by the foundry.

[0003] The traditional device model building method is mostly based on the physical mechanism of the device, so the establishment of the device model not only needs a large amount of time cost, but also requires researchers to have theoretical knowledge in many professional fields such as solid state physics, circuit design, model calibration and numerical fitting. In addition, in the process of building a compact model of a device based on physical mechanism, in order to reduce the complexity of the model, some simplifications are made in some aspects, resulting in errors in the compact model.

[0004] Compared with traditional integrated circuit devices, new devices such as tunneling field effect transistors have some index parameters that describe their physical characteristics, or specific limiting relationships. For the model building of new devices, a new model is usually developed based on its physical mechanism, and the model building requires a large amount of time cost and research cost. Therefore, a simulation model generation method that can quickly model new devices and has better simulation effect is needed. SUMMARY

[0005] In view of the technical problems existing in the prior art, the present application provides a method for predicting the drain-source current of a three-terminal transistor, which comprises receiving the actual gate-source voltage of the transistor, and using a first artificial neural network to generate a first drain-source current value when the drain-source voltage of the transistor is equal to a first reference value; receiving the actual drain-source voltage of the transistor, and extending a straight line formed by the first drain-source current value and the origin to obtain a second drain-source current; receiving the actual gate-source voltage and the actual drain-source voltage, and using a second artificial neural network to generate a first ratio; and obtaining a prediction value of the drain-source current of the transistor under the current bias condition based on the second drain-source current and the first ratio.

[0006] In particular, the first reference value is 0.01V.

[0007] In particular, the second artificial neural network and the first artificial neural network are artificial neural networks of the same type.

[0008] In particular, the second artificial neural network and the first artificial neural network are artificial neural networks of the same type.

[0009] The present application provides an artificial neural network system for predicting the drain-source current of a three-terminal transistor, comprising a first artificial neural network configured to receive an actual gate-source voltage of the transistor when the drain-source voltage is equal to a first reference value, thereby obtaining a first drain-source current value of the transistor; a processing unit having an input coupled to an output of the first artificial neural network and configured to receive the first drain-source current and an actual drain-source voltage, and to extend a straight line formed by the first drain-source current value and the origin, thereby obtaining a second drain-source current; a second artificial neural network configured to receive the actual gate-source voltage and the actual drain-source voltage, and to generate a first ratio; and a fusion unit configured to receive the second drain-source current and the first ratio, and to output a predicted value of the drain-source current of the transistor under a current bias condition.

[0010] In particular, the first reference value is 0.01 V.

[0011] In particular, the fusion unit is configured to output a product of the second drain-source current and the first ratio as the predicted value of the drain-source current.

[0012] The present application provides a method for establishing an artificial neural network system for predicting the drain-source current of a three-terminal transistor, comprising using the gate-source voltage of the transistor in the training data set when the drain-source voltage is equal to a first reference value as the input of a first artificial neural network, and using the third drain-source current of the transistor under the same bias in the data set as the output of the first artificial neural network to train the first artificial neural network; using the corresponding drain-source voltage of the transistor in the training data set to extend a straight line formed by the third drain-source current value and the origin while keeping the slope unchanged, thereby obtaining a fourth drain-source current; and using the gate-source voltage and the drain-source voltage in the training data set, the reference drain-source current in the test data of the transistor under the same bias, and the corresponding fourth drain-source current as the training data of a second artificial neural network, using the gate-source voltage and the drain-source voltage in the training data set as the input of the second artificial neural network, and using the ratio of the reference drain-source current to the fourth drain-source current as the output of the second artificial neural network to train the second artificial neural network.

[0013] In particular, the first reference value is 0.01 V.

[0014] The application provides a computer readable storage medium, comprising a memory storing a computer program, wherein the computer program is executed to complete the method for predicting the drain-source current of the three-terminal transistor.

[0015] The application also provides a computer readable storage medium, comprising a memory storing a computer program, wherein the computer program is executed to complete the method for establishing an artificial neural network system for predicting the drain-source current of the three-terminal transistor.

[0016] By adopting the scheme of the application, the process collaborative design flow can be accelerated, the distortion problem caused by the traditional artificial neural network model violating the physical mechanism can be solved, a set of accurate model is provided for circuit designers, the simulation accuracy is improved, and the cost of tape-out caused by the simulation model is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0017] Hereinafter, the preferred embodiments of the application will be further described in detail with reference to the accompanying drawings, in which:

[0018] Figure 1 is the conductance characteristic curve output by the existing artificial neural network algorithm for modeling the three-terminal transistor;

[0019] Figure 2 is a method flowchart for predicting the drain-source current of the three-terminal transistor according to an embodiment of the application;

[0020] Figure 3 is a framework schematic diagram of an artificial neural network system for predicting the drain-source current of the three-terminal transistor;

[0021] Figure 4 is a method flowchart for establishing an artificial neural network system for predicting the drain-source current of the three-terminal transistor according to an embodiment of the application;

[0022] Figure 5 is the current characteristic curve after training of the first artificial neural network according to an embodiment of the application;

[0023] Figure 6 (a) to (b) are the optimized ratio curves generated in the application process of the method for predicting the drain-source current of the three-terminal transistor according to an embodiment of the application;

[0024] Figure 7 (a) to (b) are the transistor model parameter curves established by the method for predicting the drain-source current of the three-terminal transistor according to an embodiment of the application;

[0025] Figure 8 is the transistor model conductance curve established by the method for predicting the drain-source current of the three-terminal transistor according to an embodiment of the application;

[0026] Figure 9 (a) is a schematic diagram of a structure of an inverter circuit to which a transistor model established according to a method of predicting a drain-source current of a three-terminal transistor according to an embodiment of the present application is applied;

[0027] Figure 9 (b) is a voltage transfer characteristic curve of the inverter circuit shown in Figure 9 (a);

[0028] Figure 10 (a) is a schematic diagram of a structure of a five-stage oscillator circuit to which a transistor model established according to a method of predicting a drain-source current of a three-terminal transistor according to an embodiment of the present application is applied; and

[0029] Figure 10 (b) is a voltage output characteristic curve of the five-stage oscillator circuit shown in Figure 10 (a). DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0031] In the following detailed description, reference will be made to the accompanying drawings, which form a part of this description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The embodiments of the present application will be described in sufficient detail to enable those skilled in the art to make and use the embodiments of the application. It is to be understood that other embodiments can be utilized and that structural, logical, and electrical changes can be made without departing from the scope of the present application.

[0032] The detailed description and specific examples provided above are not intended to limit the scope of the application, but rather to exemplify the application. Those skilled in the art will recognize that the application is not limited to the embodiments disclosed, and that changes and modifications can be practiced within the scope of the application. The present application includes all alternatives, modifications and equivalents falling within the scope of the claims.

[0033] The transistor can refer to any structure of transistor, such as field effect transistor (FET) or bipolar transistor (BJT). When the transistor is a field effect transistor, it can be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc. according to different channel materials. According to whether the carrier is an electron or a hole, it can be divided into N type transistor and P type transistor, the control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor. The transistor can be manufactured by using amorphous silicon, polysilicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0034] As a new technology that has developed rapidly in recent years, artificial neural network algorithm has also been applied to modeling of new devices. Due to the existence of high-performance hardware-GPU and efficient open-source software-Pytorch and tensorflow, the efficient operation of artificial neural network is laid a foundation. Compared with the traditional modeling method based on physical mechanism, the artificial neural network modeling method does not need to establish a physical-based equation and use an empirical parameter to perfect the physical model, and the difficulty of parameter extraction of the artificial neural network modeling method is greatly reduced, and the theoretical basis requirement of the research field of the scientific researchers is lower, which can greatly reduce the time period of model establishment, so that the model establishment process is more efficient.

[0035] The existing artificial neural network algorithm at least includes a training process and an application process when solving a problem. In the training process, the artificial neural network first trains the training set data, after the training is completed, the artificial neural network can establish a relationship between the input and the output of the network, and obtain an artificial neural network model. In the application process, the artificial neural network model receives the initial data set by the user, calculates by using the model obtained in the training process, outputs the calculation value based on the initial data, and completes the application process.

[0036] Figure 1 is the conductance characteristic curve output by the existing artificial neural network algorithm for modeling of the three-terminal transistor. The existing artificial neural network algorithm can train the training data of the gate-source voltage V GS and the drain-source voltage V DS and the drain-source current I DS of the three-terminal transistor, and establish a trained model between the three. In the application, the artificial neural network can receive the gate-source voltage V GS and the drain-source voltage V DSAfterwards, the drain-source current I DS .

[0037] However, the three-terminal transistor model trained by the existing artificial neural network algorithm relies only on the algorithm itself to train data, without considering the establishment of physical equations or using empirical parameters to improve the physical model process. Therefore, in some working regions of the three-terminal transistor, the model may violate the physical mechanism. Using such a model for circuit simulation may cause simulation results and accuracy errors, resulting in a large difference between the test results and simulation results of the circuit designed by the circuit design researcher after the circuit is taped out.

[0038] According to an embodiment of the present application, the three-terminal transistor can be a new device such as a full-ring gate field effect transistor (GAA-FET), or a common MOSFET transistor. Those skilled in the art know that the solution in the present application can be applied to other types of transistors without going beyond the scope of the present application.

[0039] As shown in Figure 1 , the conductivity of the three-terminal transistor model generated by the existing artificial neural network algorithm is distorted in the subthreshold region and the saturation region, respectively. Specifically, when the drain-source voltage V DS is close to 0V, the conductance G DS will suddenly rise and then drop, which is inconsistent with the actual situation. For example, when the drain-source voltage is about 0.75-1V, i.e., the transistor is in the saturation region, the conductance G DS may be less than zero, which is a negative conductance problem. These distortions are all against the physical mechanism of the device. If the transistor model is not modified, it will have a great impact on the accuracy of the results in subsequent circuit simulation, ultimately leading to a large difference between the simulation results and the test results of the actual circuit, and the simulation results cannot be normally used.

[0040] The present application proposes a method for generating a three-terminal transistor simulation model based on an artificial neural network, which effectively solves the distortion problem of inconsistent simulation results and actual results, improves the accuracy of the simulation model, and has important significance for the development of design technology co-optimization (DTCO) and circuit simulation. Specifically, the solution of the present application overcomes the distortion of the three-terminal transistor generated by the existing artificial neural network algorithm in the subthreshold region and the saturation region, respectively, thereby forming an artificial neural network algorithm model or system that is closer to reality or closer to a model based on physical principles.

[0041] Figure 2 is a flowchart of a method for predicting the drain-source current of a three-terminal transistor according to an embodiment of the present application. Figure 3This is a schematic diagram of the framework of an artificial neural network system for predicting the drain-source current of a three-terminal transistor.

[0042] According to one embodiment of this application, the system may include a first artificial neural network (hereinafter referred to as the first network) 301, configured to receive data in practical applications where the drain-source voltage of a transistor is equal to a first reference value V. DS1 Gate-source voltage V at time GS Thus, we obtain this V DS1 The first drain-source current I of the transistor is... DS1 .

[0043] According to one embodiment, this first reference value V DS1 The value can be V, which is as close to 0V as possible to ensure that the transistor is in the subthreshold region. DS1 The value, or rather the conductance G, during the process of obtaining the transistor drain-source current using the first network 301. DS A certain V before the anomaly occurs in the subthreshold region DS1 value.

[0044] According to one embodiment, the system may further include a processing unit 310, the input of which is coupled to the output of the first network 301, configured to receive I DS1 And the drain-source voltage V of a transistor in practical applications DS And based on V DS to I DS1 Extending the straight line, we obtain the second drain-source current I. DS2 .

[0045] According to one embodiment, the system may further include a second artificial neural network (hereinafter referred to as the second network) 302, such as... Figure 3 As shown. The second network 302 is configured to receive V from the transistor in the actual application. GS V DS The reference drain-source current I in the test data generated under the same bias voltage conditions. DS_Simulation With the second drain-source current I DS2 The ratio Rs between them is output.

[0046] According to one embodiment, this application also includes a fusion unit 320 configured to receive I DS2 And Rs, and output the drain-source current I of the transistor under the current bias conditions. DS For example, according to one embodiment, the fusion unit can combine Rs with I DS2 Multiplication, theoretically speaking, I DS The reference drain-source current I of the transistor under the same bias voltage DS_Simulation They are basically the same.

[0047] In the fusion process, the Rs is mainly based on the reference drain-source current I DS_Simulation with the second drain-source current I DS2 , Rs can be based on the reference current to the final drain-source current I DS predicted value I DS2 , Rs and the second drain-source current I DS fusion of drain-source current I GS can effectively improve the drift of the above-mentioned sub-threshold region conductance, and the subsequent negative conductance problem.

[0048] According to an embodiment of the application, the first network 301 and the second network 302 can be based on V DS , V DS directly obtained I GS artificial neural network, according to the actual need to decide.

[0049] According to an embodiment, the method for obtaining the drain-source current of the three-terminal transistor based on the artificial neural network system described above can include the following steps. The meaning of the actual gate-source or drain-source voltage in the following description is the voltage actually received in the prediction of the drain-source current, rather than the voltage data in the data set when the system is trained.

[0050] Step 201: receive the actual gate-source voltage V DS1 , using the first network 301 to generate the first drain-source current I DS1 when the drain-source voltage is equal to the first reference value.

[0051] According to an embodiment, this first reference value can be a V DS value as close to 0V as possible to ensure that the transistor is in the sub-threshold region, or in other words, a V DS1 value before the conductance G DS1 abnormal in the sub-threshold region during the process of obtaining the transistor drain-source current using the first network 301. According to an embodiment, V DS may be 0.01V.

[0052] Step 202: receive the actual drain-source voltage V DS1 , extend the straight line formed by the first drain-source current I DS2 value and the origin to obtain the second drain-source current I DS2 . For example, the straight line formed between the first drain-source current value and the origin can be extended within the range of 0-VDD, and according to an embodiment of the application, VDD is 1V.

[0053] According to an embodiment of the application, I DS2 satisfies the following relationship:

[0054]

[0055] Step 203: receive the actual gate-source voltage V GS and the actual drain-source voltage V DS , use the second network 302 to generate the ratio Rs between the reference drain-source current I DS_Simulation and the second drain-source current I DS2 of the transistor under the same bias voltage condition based on the test data:

[0056]

[0057] Step 204: obtain the predicted value of the drain-source current I DS2 of the transistor under the current bias condition based on the second drain-source current I DS and the ratio Rs.

[0058] According to one embodiment of the present application, the product of R S and I DS2 can be used as the predicted value of I DS :

[0059] I DS = I DS2 x R S (3)

[0060] Figure 4 Fig. 4 shows a flow chart of a method for establishing an artificial neural network system for predicting the drain-source current of a three-terminal transistor according to one embodiment of the present application.

[0061] Step 401: use the gate-source voltage V DSt1 of the transistor in the training data set when the transistor drain-source voltage is equal to the first reference value V GSt as the input of the first network 301, and use the third drain-source current I DSt1 of the transistor under the same bias in the data set as the output of the first network to train the first network.

[0062] According to one embodiment of the present application, V DSt1 may be the V DS value of the transistor in the training set in the sub-threshold region as close to 0V as possible. According to one embodiment, V DS1 may be 0.01V. According to one embodiment, when V DSt1 is fixed at 0.01V in the training set, different gate-source voltages V GSt will also affect the value of I DSt1 , and the gate-source voltage V GSt may vary between 0 and VDD. According to one embodiment of the present application, VDD is 1V. For different VGSt There can be multiple I DSt1 According to an embodiment of the present application, the first network 301 is trained on the multiple I DSt1 in the training set.

[0063] According to an embodiment of the present application, the data in the training data set can be simulation results of TCAD on three-terminal transistors such as GAA-FET.

[0064] Step 402: using the different drain-source voltages V DSt of the transistor in the training data set, the corresponding third drain-source current values I DSt1 of the transistor are obtained. DSt The straight line formed by the origin and the third drain-source current values I DSt2 of the transistor varying with the drain-source voltage V DSt2 is extended under the premise of keeping its slope unchanged to obtain the fourth drain-source current I DSt value. I GSt satisfies the following relationship:

[0065]

[0066] wherein V DSt can be a voltage value between 0 and VDD, and is the different drain-source voltage of the transistor when it is in each working zone. According to an embodiment of the present application, VDD is 1V.

[0067] Step 403: using the transistor gate-source voltage V DS_Simluation , the drain-source voltage V DSt2 in the training data set, the reference drain-source current I GSt in the test data under the same bias, and the corresponding fourth drain-source current I DSt as the training data of the second network, the transistor gate-source voltage V DS_Simulation , the drain-source voltage V DSt2 as the input of the second network, and the ratio R St of I St and I DSt2 as the output of the second network, the second network is trained.

[0068] According to an embodiment of the present application, R DS_Simulation is mainly related to I DSt2 and the reference drain-source current I DSt1 . I DS_Simulation is obtained by processing the drain-source current I DSt2The ratio of I DS_Simulation to I St can adjust this deviation, and since I DS_Simulation is the current value obtained based on TCAD simulation or actual test, there is no negative conductance, so the generated ratio R St can effectively improve the negative conductance problem generated by the artificial neural network in the saturation region.

[0069] Figure 5 is the current characteristic curve of the first artificial neural network after training according to an embodiment of the present application. As shown in Figure 5 , the points in the curve represent the test data generated by the TCAD software, and the curve represents the predicted value generated by the transistor model constructed by the first artificial neural network after training. As shown in Figure 5 , the points of the test data are all on the curve, and the output third drain-source current I DSt1 matches the actual characteristics of the device.

[0070] Figure 6 (a) to (b) are the optimized ratio curves generated in the application process of the method for predicting the drain-source current of the three-terminal transistor according to an embodiment of the present application. Figure 6 (a) is the generated R S and the change curve of the input data V GS .

[0071] As shown in Figure 6 (a), R S increases with the increase of V GS , when V i is in the range of 0-0.5V, the device is in the sub-threshold region, the initial ratio R S tends to 1, and R GS also tends to 1; when V S gradually increases, the optimized ratio R S increases according to the working region of the device corresponding to different voltage values.

[0072] Figure 6 (b) is the change curve of the generated optimized ratio R S and the input data V DS . As shown in Figure 6 (b), with the increase of V DS , the drain-source current I DS of the transistor also changes from rapid increase to stable maintenance due to the different working states of the transistor. Since the actual transistor works in the saturation region, I DS maintains a relatively stable value, resulting in that the optimized ratio R DS_Simulation gradually decreases and tends to 0 as the ratio of I S to I DS_Simulation increases. While the increase of V DSt2 causes I GS toDS The increase of the ratio R S The value of the ratio R is also relatively increased.

[0073] According to one embodiment of the present application, if the current model formed by the trained generation method does not meet the actual production requirements, the training process in the generation method can be repeated multiple times until the formed current model meets the user's requirements, including the accuracy of the model.

[0074] Figure 7 (a) and (b) are the transistor model parameter curves established by the method for predicting the drain-source current of a three-terminal transistor according to one embodiment of the present application. Specifically, Figure 7 (a) is the generated drain-source current I DS The change curve of V GS , Figure 7 (b) is the simulated drain-source current I DS The curve of V DS . Wherein, the points refer to the data generated by the TCAD software, and the lines refer to the predicted values generated by the model constructed by the generation method. As Figure 7 (a) and (b) show, each point is on the curve, which means that the transistor model established based on the method for predicting the drain-source current of a three-terminal transistor disclosed in the embodiments of the present application matches the test data, and the accuracy of the model is high.

[0075] Figure 8 is the transistor model conductance curve established by the method for predicting the drain-source current of a three-terminal transistor according to one embodiment of the present application. As Figure 8 shown, the transistor formed by the method disclosed in the present application does not appear distortion phenomena such as oscillation when it is in the sub-threshold region; when V DS is 0.75-1V, it also does not appear negative conductance phenomenon, which conforms to the physical mechanism.

[0076] Figure 9 (a) is a structure schematic diagram of the transistor model established by the method for predicting the drain-source current of a three-terminal transistor according to one embodiment of the present application applied to an inverter circuit; Figure 9 (b) is the voltage transfer characteristic curve of the inverter circuit as Figure 9 (a) shows. As Figure 9 (b) shows, the voltage transfer curve of the inverter circuit changes with the change of the input voltage Vin, the simulation model conforms to the physical mechanism, and the inverting effect meets the actual production requirements.

[0077] Figure 10 (a) is a structure schematic diagram of the transistor model established by the method for predicting the drain-source current of a three-terminal transistor according to one embodiment of the present application applied to a five-order oscillator circuit; Figure 10 (b) is a structure schematic diagram of the five-order oscillator circuit asFigure 10 (a) the voltage output characteristic curve of the five-stage oscillator circuit shown. As Figure 10 (b) the model of the five-stage oscillator is consistent with the physical mechanism, and the output effect meets the actual production needs.

[0078] The embodiment of the present application also provides a simulation tool, including a model card and a Verilog-A model. According to an embodiment of the present application, the artificial neural network system for predicting the drain-source current of the three-terminal transistor is converted into a model card with other parameters by using the three-terminal transistor model generated by steps 201-204, and the formed three-terminal transistor model is converted into a Verilog-A model.

[0079] According to an embodiment of the present application, the model card can be generated by writing a Python script.

[0080] According to an embodiment of the present application, the generated model card and Verilog-A model can be applied to the simulation software of the simulation tool, such as SPICE, to simulate and test a single device or an entire module circuit.

[0081] The embodiment of the present application also provides a computer readable storage medium, such as a memory including a computer program stored therein, which can be executed to complete the method steps for predicting the drain-source current of the three-terminal transistor provided by any embodiment of the present application. The computer storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disc, or CD ROM; or various devices including one or any combination of the above memories.

[0082] By using the scheme of the present application, the process collaborative design flow can be accelerated, the distortion problem caused by the traditional artificial neural network model violating the physical mechanism can be solved, a set of accurate model is provided for circuit designers, the simulation accuracy is improved, and the cost of tape-out caused by the simulation model is greatly reduced.

[0083] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also belong to the scope of the present application.

Claims

1. A method for predicting transistor drain-source current, comprising: The first artificial neural network is trained by using the gate-source voltage of the transistor when the drain-source voltage in the training dataset is equal to the second reference value, and the third drain-source current of the transistor under the same bias in the dataset as the output of the first artificial neural network. Using the corresponding drain-source voltages of the transistors in the training dataset, the straight line formed by the third drain-source current value and the origin is extended while keeping its slope unchanged to obtain the fourth drain-source current corresponding to the drain-source voltages in the training dataset. as well as, The gate-source voltage, drain-source voltage, and reference drain-source current and corresponding fourth drain-source current in the test data of the transistor under the same bias in the training dataset are used as training data for the second artificial neural network. The gate-source voltage and drain-source voltage in the training dataset are used as input to the second artificial neural network. The ratio of the reference drain-source current to the fourth drain-source current is used as the output of the second artificial neural network to train the second artificial neural network. The actual gate-source voltage of the transistor under test is received, and the first artificial neural network is used to generate a first drain-source current value when the drain-source voltage of the transistor under test is equal to a first reference value. The actual drain-source voltage of the transistor under test is received, and the straight line formed by the first drain-source current value of the transistor under test and the origin is extended to obtain the second drain-source current. Based on the actual gate-source voltage and the actual drain-source voltage of the transistor under test, a first ratio is generated using the second artificial neural network; as well as, The predicted value of the drain-source current of the transistor under test is obtained based on the second drain-source current of the transistor under test and the first ratio; wherein the first reference value and the second reference value are values ​​that ensure the transistor is in the subthreshold region and are as close as possible to 0V.

2. The method according to claim 1, wherein, The first reference value is 0.01V. The second reference value is 0.01V.

3. The method according to claim 1, wherein, The predicted value of the drain-source current of the transistor under test under the current bias condition is obtained by multiplying the second drain-source current and the first ratio.

4. The method according to claim 1, wherein, The second artificial neural network and the first artificial neural network are artificial neural networks of the same type.

5. An artificial neural network system for predicting transistor drain-source current, comprising: The first artificial neural network is configured to receive the actual gate-source voltage of the transistor under test when the drain-source voltage is equal to the first reference value, thereby obtaining the first drain-source current value of the transistor under test. The processing unit, whose input terminal is coupled to the output terminal of the first artificial neural network, is configured to receive the first drain-source current and the actual drain-source voltage of the transistor under test, and to extend the straight line formed by the first drain-source current value and the origin to obtain the second drain-source current. The second artificial neural network is configured to receive the actual gate-source voltage and the actual drain-source voltage of the transistor under test, and generate a first ratio. as well as, A fusion unit is configured to receive the second drain-source current and the first ratio, and output a predicted value of the drain-source current of the transistor under test under the current bias condition. Specifically, the gate-source voltage when the transistor drain-source voltage in the training dataset is equal to the second reference value is used as the input of the first artificial neural network, and the third drain-source current of the transistor under the same bias in the dataset is used as the output of the first artificial neural network for training. Using the corresponding drain-source voltages of the transistors in the training dataset, the straight line formed by the third drain-source current value and the origin is extended while maintaining its slope to obtain a fourth drain-source current corresponding to the drain-source voltages in the training dataset; and... The gate-source voltage, drain-source voltage, and reference drain-source current and corresponding fourth drain-source current in the test data of the transistor under the same bias in the training dataset are used as training data for the second artificial neural network. The gate-source voltage and drain-source voltage in the training dataset are used as inputs to the second artificial neural network. The ratio of the reference drain-source current to the fourth drain-source current is used as the output of the second artificial neural network to train the second artificial neural network. The first reference value and the second reference value are values ​​that ensure the transistor is in the subthreshold region and as close to 0V as possible.

6. The artificial neural network system according to claim 5, wherein, The first reference value is 0.01V. The second reference value is 0.01V.

7. The artificial neural network system according to claim 5, wherein, The fusion unit is configured to output the product of the second drain-source current and the first ratio as a predicted value of the drain-source current of the transistor under test.

8. A method for establishing an artificial neural network system for predicting transistor drain-source current, comprising: The first artificial neural network is trained by using the gate-source voltage of the transistor when the drain-source voltage in the training dataset is equal to the second reference value, and the third drain-source current of the transistor under the same bias in the dataset as the output of the first artificial neural network. Using the corresponding drain-source voltages of the transistors in the training dataset, the straight line formed by the third drain-source current value and the origin is extended while keeping its slope unchanged to obtain the fourth drain-source current corresponding to the drain-source voltages in the training dataset. as well as, The gate-source voltage, drain-source voltage, and reference drain-source current and corresponding fourth drain-source current in the test data of the transistor under the same bias in the training dataset are used as training data for the second artificial neural network. The gate-source voltage and drain-source voltage in the training dataset are used as input to the second artificial neural network. The ratio of the reference drain-source current to the fourth drain-source current is used as the output of the second artificial neural network to train the second artificial neural network. The second reference value is a value that ensures the transistor is in the subthreshold region and is as close to 0V as possible.

9. The method for establishing according to claim 8, wherein, The second reference value is 0.01V.

10. A computer-readable storage medium comprising a memory storing a computer program that is executed to perform the method for predicting transistor drain-source current according to any one of claims 1-4.

11. A computer-readable storage medium comprising a memory storing a computer program, said computer program being executed to perform a method for establishing an artificial neural network system for predicting transistor drain-source current as described in any one of claims 8-9.

Images