Display circuit device, display device, and electronic equipment

Abstract

A display circuit device, a display device, and an electronic device are provided. The display circuit device includes a CPU, a display control circuit, and a drive signal generation circuit. The drive signal generation circuit includes: a generation circuit that generates a first CRC value as a CRC value of command data input from the CPU; a sending circuit that sends the first CRC value to the CPU. The CPU includes: an expectation value generation circuit that generates a second CRC value as a CRC value of command data before being input to the drive signal generation circuit; a receiving circuit that receives the first CRC value; a comparison circuit that compares the first CRC value and the second CRC value; and a control circuit that performs control based on the comparison result of the comparison circuit.

Description

Technical Field

[0001] The invention relates to a display circuit device, a display device and an electronic device. Background Art

[0002] As shown in Patent Document 1, when image data is sent from an upstream circuit to a downstream circuit, a technology is becoming popular that uses CRC (Cyclic Redundancy Check) to detect whether image data received by a downstream circuit has errors with respect to the image data sent by the upstream circuit.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-35677

[0004] However, in the technology described in Patent Document 1, although it is possible to detect errors in image data, it is not possible to detect errors in command data sent from the upstream circuit to the downstream circuit. Therefore, even if an error occurs in the command data, the error will be missed, which may cause malfunction of the downstream circuit. Summary of the invention

[0005] The display circuit device includes a processing device, a display control circuit and a driving circuit, wherein the driving circuit receives command data from the processing device and image data from the display control circuit, and drives a display panel based on the image data and the command data, wherein the driving circuit includes: a first generating circuit that generates a first CRC value as a CRC value of the command data input from the processing device; and a first sending circuit that sends the first CRC value to the processing device, wherein the processing device includes: a first expectation value generating circuit that generates a first CRC expectation value as a CRC value of the command data before being input to the driving circuit; a first receiving circuit that receives the first CRC value sent by the first sending circuit; a first comparing circuit that compares the first CRC expectation value generated by the first expectation value generating circuit with the first CRC value received by the first receiving circuit; and a control circuit that performs control based on the comparison result of the first comparing circuit between the first CRC expectation value and the first CRC value.

[0006] The display circuit device includes a processing device, a display control circuit and a driving circuit, wherein the driving circuit receives command data from the processing device and image data from the display control circuit, and drives a display panel based on the image data and the command data, wherein the driving circuit includes: a first generating circuit that generates a first CRC value as a CRC value of the command data input from the processing device; and a first sending circuit that sends the first CRC value to the display control circuit, wherein the display control circuit includes: a first expectation value generating circuit that generates a first CRC expectation value as a CRC value of the command data before being input to the driving circuit; a first receiving circuit that receives the first CRC value sent by the first sending circuit; and a first comparing circuit that compares the first CRC expectation value generated by the first expectation value generating circuit with the first CRC value received by the first receiving circuit, wherein the processing device includes a control circuit that performs control based on the comparison result of the first comparing circuit between the first CRC expectation value and the first CRC value.

[0007] A display device includes the above-mentioned display circuit device and the display panel.

[0008] An electronic device includes the above-mentioned display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing the structure of an electro-optical device.

[0010] Figure 2 is a circuit diagram of a pixel circuit.

[0011] Figure 3 This is a block diagram showing the structure of the display circuit device according to the first embodiment.

[0012] Figure 4 This is a timing chart showing an example of the operation of the display circuit device.

[0013] Figure 5 This is a block diagram showing the structure of a display circuit device according to a second embodiment.

[0014] Figure 6 This is a block diagram showing the structure of a display circuit device according to a third embodiment.

[0015] Figure 7 This is a block diagram showing the structure of a display circuit device according to a fourth embodiment.

[0016] Figure 8 is a block diagram showing a structure of a display circuit device according to another embodiment.

[0017] Fig. 9is a block diagram showing a structure of a display circuit device according to another embodiment.

[0018] Fig.10 is a block diagram showing a structure of a display circuit device according to another embodiment.

[0019] Fig.11 It is a schematic diagram of a projection type display device as an application example.

[0020] Fig.12 It is a perspective view of a personal computer as an application example.

[0021] Fig.13 It is a diagram showing a configuration example of a portable information terminal as an application example.

[0022] Fig.14 It is a diagram showing a configuration example of a moving object as an application example.

[0023] Description of symbols

[0024] 1, 1R, 1G, 1B: electro-optical device; 10: electro-optical panel; 21: scan line; 22: data line; 24: pixel electrode; 25: liquid crystal; 30: common electrode; 100: scan line driving circuit; 200: data line driving circuit; 201: image data receiving circuit; 202: data signal generating circuit; 300: voltage supply circuit; 400: drive signal generating circuit; 401: command register; 402: first data selecting circuit; 403: first generating circuit; 404: first transmitting circuit; 413: second generating circuit; 414: second transmitting circuit; 500: display control circuit; 501: data receiving circuit circuit; 502: data buffer; 503: data transmission circuit; 504, 602: second data selection circuit; 505, 603: first expectation value generation circuit; 506, 604: first receiving circuit; 507, 605: first error detection circuit; 507a, 605a: first comparison circuit; 508, 606: error signal transmission circuit; 515, 613: second expectation value generation circuit; 516, 614: second receiving circuit; 517, 615: second error detection circuit; 517a, 615a: second comparison circuit; 600: CPU; 601: control circuit; 1000: display circuit device; 3100: projection display device; 3101: illumination optical system; 3102: illumination device; 3103: projection optical system; 3104: projection surface; 3200: personal computer; 3201: power switch; 3202: keyboard; 3210: main body; 3300: portable information terminal; 3301: operation button; 3302: power switch; 3400: automobile; 3401: vehicle body; 3402: wheel; Px: pixel circuit; CL: liquid crystal element; Tr: write transistor; Vcom: common voltage; Vsync: vertical synchronization signal; Hsync: horizontal synchronization signal; G: scanning signal; Vd: Data signal; Cda, CDb, CDc, CDd, Cca, CCb, CCc, CCd, Cpa, CPb, CPc, CPd: code; CLK0, CLK0c, CLK0p, CLK1, CLK1c, CLK1p: clock; DE: data enable signal; Da: input image data; Dc0, Dc1, Dc2: command data; Do1, Do2: object data; Dp0, Dp1: image data; Err, Err1, Err1c, Err1p: error signal; Tcc1, Tcc2, Tcp, Tec, Tep, Toc1, Toc2, Top: period. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments will be described with reference to the accompanying drawings. However, in each figure, the size and scale of each part are appropriately different from the actual size and scale. In addition, the embodiments described below are added with various technically preferred limitations, but the embodiments are not limited to these modes.

[0026] A. First embodiment

[0027] Figure 1 1 is a block diagram showing the structure of an electro-optical device 1 as a display device. The electro-optical device 1 includes an electro-optical panel 10 and a display circuit device 1000 for causing the electro-optical panel 10 to display an image. The electro-optical panel 10 is a display panel using an electro-optical material that changes optical properties by electric energy. Examples of the electro-optical material include liquid crystal, organic electroluminescence, and charged materials used in electrophoretic elements. In this embodiment, the electro-optical panel 10 using liquid crystal as the electro-optical material is described.

[0028] In the electro-optical panel 10, the axis along the scanning line 21 is set as the x-axis, and the axis orthogonal to the x-axis is set as the y-axis. The electro-optical panel 10 is formed with M scanning lines 21 extending from the first row to the Mth row along the x-axis and N data lines 22 extending from the first column to the Nth column along the y-axis. Here, M and N are natural numbers. In the electro-optical panel 10, corresponding to each intersection of the scanning line 21 and the data line 22, the pixel circuits Px constituting the pixels are arranged in a matrix of M rows in the vertical direction and N columns in the horizontal direction.

[0029] like Figure 1As shown, the display circuit device 1000 includes a CPU 600 as a processing device, a display control circuit 500, and a drive signal generating circuit 400 as a driving circuit. In the display circuit device 1000, the CPU 600 supplies the display control circuit 500 with input image data Da, a control signal, and command data Dc0. Here, the input image data Da includes data that specifies the grayscale to be displayed by each pixel circuit Px. For example, the input image data Da can also be digital data that specifies the grayscale to be displayed in each pixel in 8 bits. In addition, the control signal includes synchronization signals such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync. In addition, the command data Dc0 is data for setting the action of the drive signal generating circuit 400, and is output to the drive signal generating circuit 400 via the display control circuit 500. The drive signal generating circuit 400 implements, for example, display on / off, color tone adjustment, drive power setting, display timing setting, etc. according to the supplied command data Dc0. In addition, the command data Dc0 may be directly supplied from the CPU 600 to the drive signal generating circuit 400 without passing through the display control circuit 500. In the present embodiment, the CPU 600 has a function of detecting errors in various data supplied to the drive signal generating circuit 400 by CRC (Cyclic Redundancy Check). The details of this error detection function will be described later.

[0030] The vertical synchronization signal Vsync is a synchronization signal indicating the start of a vertical scanning period, and is a vertical start pulse signal having one pulse at the start of a vertical scanning period. In addition, the horizontal synchronization signal Hsync is a synchronization signal indicating the start of a horizontal scanning period, and is a horizontal start pulse signal having one pulse at the start of a horizontal scanning period.

[0031] The display control circuit 500 generates various control signals based on the synchronization signal supplied from the CPU 600, and controls the drive signal generation circuit 400. In addition, the display control circuit 500 generates image data Dp0 representing an image to be displayed on the electro-optical panel 10 based on the input image data Da supplied from the CPU 600, and outputs the image data Dp0 to the drive signal generation circuit 400.

[0032] The drive signal generation circuit 400 is a circuit that performs a signal generation process for generating a drive signal for driving the electro-optical panel 10. The drive signal generation circuit 400 generates a drive signal based on the image data Dp0 input from the display control circuit 500 and the command data Dc0 input from the CPU 600, and supplies the generated drive signal to the electro-optical panel 10, thereby driving the electro-optical panel 10 to display an image. The drive signal generation circuit 400 includes a scan line drive circuit 100, a data line drive circuit 200, and a voltage supply circuit 300.

[0033] The voltage supply circuit 300 is a circuit that supplies various voltages as drive signals, such as a common voltage Vcom for the common electrode 30 of the electro-optical panel 10 , a power supply voltage for the scanning line driving circuit 100 , and a power supply voltage for the data line driving circuit 200 .

[0034] The scanning line driving circuit 100 is a circuit for driving the M scanning lines 21 in the electro-optical panel 10. The display control circuit 500 provides the scanning line driving circuit 100 with the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync received from the CPU 600. Whenever the vertical synchronization signal Vsync is provided, the scanning line driving circuit 100 sequentially selects the M scanning lines 21 in synchronization with the horizontal synchronization signal Hsync, and sets the scanning signal G[i] for the selected scanning line 21 to an effective level. Here, i is a natural number from 1 to M.

[0035] The data line driving circuit 200 is a circuit for driving the N data lines 22 in the electro-optical panel 10. The display control circuit 500 provides the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync received from the CPU 600 to the data line driving circuit 200. The data line driving circuit 200 receives one frame of image data Dp0 from the display control circuit 500 each time the vertical synchronization signal Vsync is provided. In addition, the data line driving circuit 200 repeatedly performs the following operation: in the process of receiving one frame of image data Dp0, each time the horizontal synchronization signal Hsync is provided, the data line driving circuit 200 performs D / A conversion on one line of image data among the M lines of image data constituting one frame of image data Dp0, and outputs the D / A conversion to the N data lines 22 as an analog data signal Vd[n]. Here, n is a natural number from 1 to N.

[0036] Figure 21 is a circuit diagram of each pixel circuit Px provided in the electro-optical panel 10. As shown in the figure, each pixel circuit Px includes a liquid crystal element CL and a write transistor Tr. The liquid crystal element CL includes a common electrode 30, a pixel electrode 24, and a liquid crystal 25 provided between the common electrode 30 and the pixel electrode 24. Here, the common electrode 30 is opposite to the pixel electrodes 24 of all pixels on the electro-optical panel 10. A common voltage Vcom supplied from a voltage supply circuit 300 is applied to the common electrode 30. The liquid crystal 25 of the liquid crystal element CL changes its transmittance according to the voltage applied to the liquid crystal element CL, more precisely, according to the voltage applied between the common electrode 30 and the pixel electrode 24.

[0037] In this embodiment, the write transistor Tr is an N-channel transistor whose gate is connected to the scan line 21, and is provided between the liquid crystal element CL and the data line 22 to control the electrical connection between the two. In other words, it controls whether the liquid crystal element CL and the data line 22 are conductive or non-conductive. When the scan signal G[i] as a drive signal is set to an effective level, the write transistors Tr in each pixel circuit Px of the i-th row are simultaneously turned into a conductive state.

[0038] When the scanning line 21 corresponding to the pixel circuit Px is selected and the write transistor Tr of the pixel circuit Px is controlled to be in the on state, the data signal Vd[n] as the driving signal is supplied to the pixel circuit Px from the data line 22. As a result, the liquid crystal 25 of the pixel circuit Px is set to a transmittance corresponding to the data signal Vd[n], so that the pixel corresponding to the pixel circuit Px displays the grayscale corresponding to the data signal Vd[n].

[0039] Figure 3 1 is a block diagram showing a configuration of a display circuit device 1000 according to Embodiment 1. In this figure, illustration of the scanning line driving circuit 100 and the voltage supply circuit 300 included in the driving signal generating circuit 400 is omitted.

[0040] The CPU 600 includes a control circuit 601. The control circuit 601 sends input image data Da, vertical synchronization signal Vsync and horizontal synchronization signal Hsync to the display control circuit 500, and sends command data Dc0 to the drive signal generation circuit 400 via the display control circuit 500. Configurations other than the control circuit 601 will be described later.

[0041] The display control circuit 500 includes a data receiving circuit 501, a data buffer 502, and a data sending circuit 503. The data receiving circuit 501 receives input image data Da from the CPU 600 and stores it in the data buffer 502. The data sending circuit 503 takes out image data of one frame from the data buffer 502 each time a vertical synchronization signal Vsync is generated, and sends it to the drive signal generating circuit 400 as image data Dp0 representing a display object of the electro-optical panel 10. In addition, the display control circuit 500 sends the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the drive signal generating circuit 400.

[0042] The drive signal generating circuit 400 includes, in addition to the above-mentioned scanning line driving circuit 100, the data line driving circuit 200, and the voltage supply circuit 300, a command register 401, a first data selecting circuit 402, a first generating circuit 403, and a first transmitting circuit 404. In addition, the data line driving circuit 200 includes an image data receiving circuit 201 and a data signal generating circuit 202. Whenever a vertical synchronization signal Vsync is generated, the image data receiving circuit 201 receives one frame of image data Dp0 from the display control circuit 500. In the case where the electro-optical panel 10 is composed of M rows and N columns of pixels, the image data Dp0 of one frame is image data of M rows representing the grayscale displayed in each pixel corresponding to each of the M scanning lines 21. In addition, the image data of one row is image data of N pixels representing the grayscale displayed by N pixels corresponding to one scanning line 21.

[0043] The data signal generating circuit 202 repeatedly generates the data signal Vd[n] output to the N data lines 22 in synchronization with the horizontal synchronization signal Hsync. In more detail, each time the horizontal synchronization signal Hsync is generated, the data signal generating circuit 202 performs D / A conversion on the image data of the latest line, that is, the image data of N pixels, in the image data Dp0 received by the image data receiving circuit 201, and generates the data signal Vd[n] output to the N data lines 22.

[0044] The command register 401 stores the command data Dc0 input from the control circuit 601. The drive signal generation circuit 400 performs various settings according to the command data Dc0 stored in the command register 401.

[0045] The first data selection circuit 402 receives one frame of image data Dp0 received by the image data receiving circuit 201 , command data Dc0 output from the control circuit 601 and before being stored in the command register 401 , and command data Dc0 read from the command register 401 after being stored in the command register 401 .

[0046] In addition, the image data Dp0 input to the first data selection circuit 402 is originally the same data as the image data Dp0 read from the data buffer 502, but sometimes an error occurs and the data is different. Therefore, in order to distinguish between the two, the image data Dp0 input to the first data selection circuit 402 will be referred to as image data Dp1. Similarly, the command data Dc0 input to the first data selection circuit 402 is also originally the same data as the command data Dc0 output from the control circuit 601, but sometimes an error occurs and the data is different. Therefore, in order to distinguish between them, the command data Dc0 before being stored in the command register 401 will be referred to as command data Dc1, and the command data Dc0 read from the command register 401 will be referred to as command data Dc2. The first data selection circuit 402 selects one of the image data Dp1, command data Dc1, and command data Dc2 according to the elapsed time from the generation of the vertical synchronization signal Vsync, and outputs it to the first generation circuit 403 as the object data Do1. The command data Dc1 is equivalent to the first command data, and the command data Dc2 is equivalent to the second command data. The first data selection circuit 402 corresponds to a first selection circuit that selects and outputs one of the command data Dc1 and the command data Dc2 , and corresponds to a second selection circuit that selects and outputs any one of the command data Dc1 , Dc2 and the image data Dp1 .

[0047] The first generation circuit 403 generates a code CDb, which is a CRC value for error detection, based on the object data Do1 output from the first data selection circuit 402. That is, when the first data selection circuit 402 selects the command data Dc1, the first generation circuit 403 generates a CRC value of the command data Dc1 as the code CDb, and when the first data selection circuit 402 selects the command data Dc2, the first generation circuit 403 generates a CRC value of the command data Dc2 as the code CDb, and when the first data selection circuit 402 selects the image data Dp1, the first generation circuit 403 generates a CRC value of the image data Dp1 as the code CDb. In addition, when the first generation circuit 403 generates CRC values ​​of the command data Dc1 and Dc2, the generated code CDb is equivalent to the first CRC value, and when the first generation circuit 403 generates a CRC value of the image data Dp1, the generated code CDb is equivalent to the second CRC value.

[0048] Whenever the first generation circuit 403 generates a code CDb, the first transmission circuit 404 converts the code CDb into a code CDc as a serial bit string, and transmits each bit constituting the code CDc to the CPU 600 in synchronization with the clock CLK0. Alternatively, the code CDc and the clock CLK0 may be transmitted to the CPU 600 via the display control circuit 500.

[0049] Next, we return to the description of the structure of the CPU 600. The CPU 600 includes a second data selection circuit 602, a first expectation value generation circuit 603, a first receiving circuit 604, a first error detection circuit 605, and an error signal transmission circuit 606 in addition to the control circuit 601. The second data selection circuit 602 receives image data Dp0 for one frame as a transmission target from the data buffer 502 of the display control circuit 500, and receives command data Dc0 output to the drive signal generation circuit 400. The second data selection circuit 602 selects one of the image data Dp0 and the command data Dc0 based on the elapsed time from the generation of the vertical synchronization signal Vsync, and outputs it as the object data Do2 to the first expectation value generation circuit 603. The second data selection circuit 602 is equivalent to a third selection circuit that selects and outputs one of the command data Dc0 and the image data Dp0.

[0050] The first expectation value generation circuit 603 generates a code CDa as a CRC value based on the object data Do2 input from the second data selection circuit 602. That is, the first expectation value generation circuit 603 generates a CRC value of the command data Dc0 as the code CDa when the second data selection circuit 602 selects the command data Dc0, and generates a CRC value of the image data Dp0 as the code CDa when the second data selection circuit 602 selects the image data Dp0. In addition, when the first expectation value generation circuit 603 generates a CRC value of the command data Dc0, the generated code CDa is equivalent to the first CRC expectation value, and when the first expectation value generation circuit 603 generates a CRC value of the image data Dp0, the generated code CDa is equivalent to the second CRC expectation value.

[0051] The first receiving circuit 604 receives the code CDc by taking in each bit constituting the code CDc synchronously with the clock CLK0, converts it into a code CDd as parallel data, and outputs it. The code CDd output by the first receiving circuit 604 is obtained by performing parallel-serial conversion on the code CDb obtained in the drive signal generating circuit 400, and then performing serial-parallel conversion, and its content should be consistent with the code CDb. That is, the code CDb and the code CDd represent the same CRC value. In addition, although the data form of the code CDc is different, it is also a code that represents the same CRC value as the code CDb and the code CDd.

[0052] In this embodiment, the algorithm for generating the code CDa by the first expected value generating circuit 603 is the same as the algorithm for generating the code CDb by the first generating circuit 403. Therefore, when the data for generating the code CDb is the same as the data for generating the code CDa, that is, when the drive signal generating circuit 400 receives the data without error, the codes CDb and CDd are consistent with the code CDa. On the other hand, when an abnormality occurs in the input terminal of the drive signal generating circuit 400, an abnormality occurs in the image data receiving circuit 201, an abnormality occurs in the signal line from the display control circuit 500 to the data line driving circuit 200, an abnormality occurs in the command register 401, etc., the codes CDb and CDd are inconsistent with the code CDa.

[0053] The first error detection circuit 605 includes a first comparison circuit 605a. The first comparison circuit 605a compares the code CDa generated by the first expectation value generation circuit 603 and the code CDd output from the first receiving circuit 604, and detects an error based on the comparison result. More specifically, the first comparison circuit 605a compares the code CDa and the code CDd based on the clock CLK1 generated at a timing when a predetermined time has passed since the timing when the code CDd is output from the first receiving circuit 604, and outputs an error signal Err1 when the two do not match. In this way, the first comparison circuit 605a compares the CRC value of the command data Dc0 generated by the first expectation value generation circuit 603 with the CRC values ​​of the command data Dc1 and Dc2 output from the first receiving circuit 604, and further compares the CRC value of the image data Dp0 generated by the first expectation value generation circuit 603 with the CRC value of the image data Dp1 output from the first receiving circuit 604.

[0054] The error signal transmission circuit 606 generates a comprehensive error signal Err based on the error signal Err1 generated by the first error detection circuit 605 and other error signals generated by the drive signal generation circuit 400, and transmits it to the control circuit 601. In a preferred embodiment, the error signal transmission circuit 606 transmits a logical sum of the error signal Err1 and other error signals as the comprehensive error signal Err. In another preferred embodiment, the error signal transmission circuit 606 transmits a signal obtained by time-multiplexing the error signal Err1 and other error signals as the comprehensive error signal Err. In addition, in this embodiment, the detailed description of other error signals is omitted.

[0055] In the control circuit 601, based on the error signal Err, an abnormality generated in the drive signal generation circuit 400 and the like is detected, and a process corresponding to the abnormality is performed. Various methods can be considered for the process corresponding to the abnormality. For example, the frequency of generation of the error signal Err per unit time can also be obtained. When the frequency of generation exceeds a predetermined threshold value, the control circuit 601 controls the display of an error message indicating that an abnormality has occurred in the drive signal generation circuit 400 on the electro-optical panel 10. In this way, the abnormality of the drive signal generation circuit 400 can be notified to the user, so that the user can perform the required operations such as repairing and replacing the circuit. In this way, the control circuit 601 controls the operation of the display circuit device 1000 based on the comparison result of the first comparison circuit 605a and the like.

[0056] Figure 4 is a timing chart showing an example of the operation of the display circuit device 1000 according to this embodiment. Figure 3 as well as Figure 4 , the operation of this embodiment is described.

[0057] In the display control circuit 500, whenever a negative pulse, i.e., a vertical synchronization signal Vsync, is generated, the data transmission circuit 503 reads out image data for one frame from the data buffer 502 and transmits it as image data Dp0 to the data line driving circuit 200. In addition, while transmitting the image data Dp0 for one frame, the data transmission circuit 503 transmits a data enable signal DE of an H level indicating that the image data Dp0 is valid to the data line driving circuit 200. In addition, in the display control circuit 500, whenever a vertical synchronization signal Vsync is generated, the image data Dp0 is transmitted from the data buffer 502 to the CPU 600.

[0058] In the CPU 600, the command data Dc0 sent from the control circuit 601 and the image data Dp0 sent from the data buffer 502 are input to the second data selection circuit 602. The second data selection circuit 602 sequentially selects the command data Dc0 and the image data Dp0 according to the elapsed time from the generation of the vertical synchronization signal Vsync, and sends the selected data as the object data Do2 to the first expectation value generation circuit 603. The first expectation value generation circuit 603 sequentially generates the code CDa according to the sent object data Do2.

[0059] exist Figure 4In the example shown, in synchronization with the generation of the first vertical synchronization signal Vsync, the second data selection circuit 602 selects the image data Dp0, and the first expectation value generation circuit 603 generates FFFFh as the code CDa of the image data Dp0 for one frame. Then, the second data selection circuit 602 selects the command data Dc0, and the first expectation value generation circuit 603 generates 000Fh as the code CDa of the command data Dc0. Here, h represents a hexadecimal notation. In addition, the code CDa is 16-bit parallel data. Furthermore, in synchronization with the generation of the second vertical synchronization signal Vsync, the second data selection circuit 602 selects the image data Dp0 again, and the first expectation value generation circuit 603 generates 0F0Fh as the code CDa of the image data Dp0 for the next one frame. Then, the second data selection circuit 602 selects the command data Dc0, and the first expectation value generation circuit 603 generates 000Fh as the code CDa of the command data Dc0. The above-mentioned operation is repeated thereafter.

[0060] In addition, Figure 4 In the above, the period Tec is a period during which the first expected value generation circuit 603 generates the CRC value of the command data Dc0 as the code CDa. In addition, the period Tep is a period during which the first expected value generation circuit 603 generates the CRC value of the image data Dp0 as the code CDa.

[0061] In the drive signal generation circuit 400, whenever the vertical synchronization signal Vsync is generated, the image data reception circuit 201 receives one frame of image data Dp0 sent from the display control circuit 500 while the data enable signal DE is at H level. In addition, the command register 401 receives command data Dc0 from the CPU 600 via the display control circuit 500.

[0062] The first data selection circuit 402 sequentially selects the image data Dp1 from the image data receiving circuit 201, the command data Dc1 previously stored in the command register 401, and the command data Dc2 read from the command register 401, based on the elapsed time from the generation of the vertical synchronization signal Vsync, and transmits them as the object data Do1 to the first generation circuit 403. The first generation circuit 403 generates the code CDb each time it receives the object data Do1 from the first data selection circuit 402. Like the code CDa, the code CDb is 16-bit parallel data.

[0063] Every time the first generation circuit 403 generates a code CDb, the first transmission circuit 404 converts the code CDb into a 16-bit serial bit string, ie, a code CDc, and transmits each bit of the code CDc to the CPU 600 in synchronization with the clock CLK0 .

[0064] exist Figure 4 In the example shown, in synchronization with the generation of the first vertical synchronization signal Vsync, the command data Dc1 is selected by the first data selection circuit 402, and 000Fh is generated as the code CDb by the first generation circuit 403. Next, the image data Dp1 is selected by the first data selection circuit 402, and FFFFh is generated as the code CDb of the image data Dp1 for one frame by the first generation circuit 403. Thereafter, the command data Dc2 is selected by the first data selection circuit 402, and 000Fh is generated as the code CDb by the first generation circuit 403. Similarly, in synchronization with the generation of the second vertical synchronization signal Vsync, the command data Dc1 is selected by the first data selection circuit 402, and 00FFh is generated as the code CDb by the first generation circuit 403. Next, the image data Dp1 is selected by the first data selection circuit 402, and 0F0Fh is generated as the code CDb of the image data Dp1 for the next one frame by the first generation circuit 403. After that, the command data Dc2 is selected by the first data selection circuit 402, and 000Fh is generated as the code CDb by the first generation circuit 403. The above operation is repeated thereafter. The code CDb generated by the first generation circuit 403 is converted by the first transmission circuit 404 into a code CDc which is a serial bit string.

[0065] In addition, Figure 4 In the period Toc1, Toc2 is a period during which the first generation circuit 403 generates the CRC value of the command data Dc1, Dc2 as the code CDb. In addition, the period Top is a period during which the first generation circuit 403 generates the CRC value of the image data Dp1 as the code CDb. In addition, the period Toc1 of the periods Toc1 and Toc2 is a period during which the first generation circuit 403 generates the CRC value of the command data Dc1 before being stored in the command register 401 as the code CDb, and the period Toc2 is a period during which the first generation circuit 403 generates the CRC value of the command data Dc2 stored in the command register 401 as the code CDb.

[0066] In CPU 600 , first receiving circuit 604 receives code CDc by taking in bits constituting code CDc in synchronization with clock CLK0 , and outputs code CDd as 16-bit parallel data. This code CDd corresponds to code CDb generated by first generating circuit 403 of drive signal generating circuit 400 .

[0067] exist Figure 4In the example shown, in synchronization with the generation of the first vertical synchronization signal Vsync, 000Fh as the CRC value of the command data Dc1 is output from the first receiving circuit 604 as the code CDd, and then FFFFh as the CRC value of the image data Dp1 is output, and then 000Fh as the CRC value of the command data Dc2 is output. Similarly, in synchronization with the generation of the second vertical synchronization signal Vsync, 00FFh as the CRC value of the command data Dc1 is output from the first receiving circuit 604 as the code CDd, and then 0F0Fh as the CRC value of the image data Dp1 is output, and then 000Fh as the CRC value of the command data Dc2 is output. The above-mentioned operation is repeated thereafter.

[0068] The first comparison circuit 605a of the first error detection circuit 605 is supplied with the clock CLK1, compares the code CDa output from the first expected value generation circuit 603 and the code CDd output from the first reception circuit 604, and outputs an H-level error signal Err1 when the two do not match.

[0069] exist Figure 4 In the example shown, the first comparison circuit 605a compares the code CDa of the command data Dc0 with the code CDd of the command data Dc1 in the period Tcc1 from the output of the code CDd of the command data Dc1, and then compares the code CDa of the image data Dp0 with the code CDd of the image data Dp1 in the period Tcp from the output of the code CDd of the image data Dp1. Furthermore, the first comparison circuit 605a compares the code CDa of the command data Dc0 with the code CDd of the command data Dc2 in the period Tcc2 from the output of the code CDd of the command data Dc2. In the comparison in the second period Tcc1, the code CDa output by the first expected value generation circuit 603 is 000Fh, while the code CDd output by the first receiving circuit 604 is 00FFh, and the two do not match, so the first comparison circuit 605a outputs the error signal Err1 of the H level. The content of the error signal Err1 is notified to the control circuit 601 through the error signal Err from the error signal transmission circuit 606. As described above, in this embodiment, when an error occurs in the image data Dp1 and the command data Dc1 and Dc2 received by the drive signal generation circuit 400, the error is notified to the control circuit 601, and the control circuit 601 performs control corresponding to the content of the error.

[0070] As described above, according to the display circuit device 1000 of the present embodiment, since errors in the command data Dc1 and Dc2 are detected using CRC, malfunctions due to errors in the command data Dc1 and Dc2 can be suppressed.

[0071] In addition, according to the display circuit device 1000 of this embodiment, errors are detected in both command data Dc1 stored before command register 401 and command data Dc2 stored in command register 401, so that abnormalities in the path from command data Dc0 to command register 401 and abnormalities in command register 401 itself can be distinguished.

[0072] Furthermore, according to the display circuit device 1000 of the present embodiment, since errors are also detected using CRC for the image data Dp1 , it is possible to suppress display disturbances caused by errors in the image data Dp1 .

[0073] Furthermore, according to the display circuit device 1000 of the present embodiment, since error detection of the command data Dc1 and Dc2 and error detection of the image data Dp1 are performed using a common circuit, it is possible to suppress an increase in the size of the circuit.

[0074] B. Second Implementation

[0075] The display circuit device 1000 of the second embodiment is different from that of the first embodiment in that the structure for detecting an error is not the CPU 600 but the structure possessed by the display control circuit 500 .

[0076] Figure 5 : is a block diagram showing the structure of a display circuit device 1000 according to the second embodiment.

[0077] like Figure 5 As shown, the display control circuit 500 of this embodiment includes a second data selection circuit 504, a first expectation value generation circuit 505, a first receiving circuit 506, a first error detection circuit 507, and an error signal transmission circuit 508 in addition to a data receiving circuit 501, a data buffer 502, and a data transmission circuit 503. These circuits have the same functions as the second data selection circuit 602, the first expectation value generation circuit 603, the first receiving circuit 604, the first error detection circuit 605, and the error signal transmission circuit 606 in the first embodiment, respectively. In addition, the first error detection circuit 507 includes a first comparison circuit 507a, and the first comparison circuit 507a has the same function as the first comparison circuit 605a in the first embodiment.

[0078] Even with such a configuration, the same effects as those of the first embodiment can be obtained.

[0079] C. Third Implementation

[0080] The display circuit device 1000 of the third embodiment is similar to the first embodiment in that the CPU 600 has a structure for detecting errors, but differs from the first embodiment in that different circuits are used for generating a CRC value in the drive signal generating circuit 400 and detecting errors in the CPU 600, the image data Dp1 and the command data Dc1, Dc2.

[0081] Figure 6 : is a block diagram showing the structure of a display circuit device 1000 according to the third embodiment.

[0082] like Figure 6 As shown, in the drive signal generating circuit 400 of the present embodiment, in addition to the command register 401, the first data selecting circuit 402, the first generating circuit 403 and the first transmitting circuit 404 in the first embodiment, a second generating circuit 413 and a second transmitting circuit 414 are further provided. The image data Dp1 received by the image data receiving circuit 201 is input to the second generating circuit 413. The second generating circuit 413 generates a CRC value for error detection, that is, a code CPb based on the image data Dp1. Whenever the second generating circuit 413 generates a code CPb, the second transmitting circuit 414 converts the code CPb into a code CPc as a serial bit string, and transmits each bit constituting the code CPc to the CPU 600 in synchronization with the clock CLK0p. The code CPb generated by the second generating circuit 413 is equivalent to the second CRC value.

[0083] In addition, in the first data selection circuit 402 of the present embodiment, the command data Dc1 stored before the command register 401 and the command data Dc2 stored in the command register 401 and read from the command register 401 are input, and the image data Dp1 is not input. Then, the first data selection circuit 402 selects one of the command data Dc1 and the command data Dc2 according to the elapsed time from the generation of the vertical synchronization signal Vsync, and outputs it to the first generation circuit 403 as the object data Do1. The first generation circuit 403 generates a CRC value for error detection, that is, a code CCb based on the object data Do1 output from the first data selection circuit 402. Whenever the first generation circuit 403 generates a code CCb, the first transmission circuit 404 converts the code CCb into a code CCc as a serial bit string, and transmits each bit constituting the code CCc to the CPU 600 in synchronization with the clock CLK0c. The code CCb generated by the first generation circuit 403 is equivalent to the first CRC value.

[0084] The CPU 600 of this embodiment includes a second expectation value generating circuit 613, a second receiving circuit 614, and a second error detecting circuit 615 in addition to the control circuit 601, the first expectation value generating circuit 603, the first receiving circuit 604, the first error detecting circuit 605, and the error signal transmitting circuit 606. The CPU 600 does not include the second data selecting circuit 602.

[0085] The second expected value generation circuit 613 obtains one frame of image data Dp0 from the data buffer 502 and generates a code CPa as a CRC value. The second receiving circuit 614 receives the code CPc by taking in each bit constituting the code CPc synchronously with the clock CLK0p, converts it into a code CPd as parallel data, and outputs it. The code CPd is obtained by performing parallel-serial conversion on the code CPb obtained in the drive signal generation circuit 400, and then performing serial-parallel conversion, and its content should be consistent with the code CPb. In addition, the code CPa generated by the second expected value generation circuit 613 is equivalent to the second CRC expected value.

[0086] The second error detection circuit 615 includes a second comparison circuit 615a. The second comparison circuit 615a compares the code CPa generated by the second expected value generation circuit 613 and the code CPd output from the second receiving circuit 614, and detects an error based on the comparison result. More specifically, the second comparison circuit 615a compares the code CPa and the code CPd based on the clock CLK1p generated at a timing when a predetermined time has passed since the timing when the code CPd is output from the second receiving circuit 614, and outputs an error signal Err1p when the two do not match.

[0087] In addition, the first expected value generation circuit 603 of the present embodiment obtains the command data Dc0 output to the drive signal generation circuit 400, and generates a code CCa as a CRC value. The code CCa is equivalent to the first CRC expected value. The first receiving circuit 604 receives the code CCc by taking in each bit constituting the code CCc synchronously with the clock CLK0c, converts it into a code CCd as parallel data, and outputs it. The code CCd is obtained by performing parallel-serial conversion on the code CCb obtained in the drive signal generation circuit 400, and then performing serial-parallel conversion, and its content should originally be consistent with the code CCb.

[0088] The first error detection circuit 605 includes a first comparison circuit 605a. The first comparison circuit 605a compares the code CCa generated by the first expected value generation circuit 603 with the code CCd output from the first receiving circuit 604, and detects an error based on the comparison result. More specifically, the first comparison circuit 605a compares the code CCa and the code CCd based on the clock CLK1c generated at a timing when a predetermined time has passed since the timing when the code CCd is output from the first receiving circuit 604, and outputs an error signal Err1c when the two do not match.

[0089] The error signal transmission circuit 606 generates a comprehensive error signal Err based on the error signal Err1c generated by the first error detection circuit 605, the error signal Err1p generated by the second error detection circuit 615, and other error signals generated by the drive signal generation circuit 400, and transmits it to the control circuit 601. The control circuit 601 detects an abnormality generated in the drive signal generation circuit 400 and the like based on the error signal Err, and performs processing corresponding to the abnormality. In this way, the control circuit 601 controls the operation of the display circuit device 1000 based on the comparison result of the first comparison circuit 605a and the comparison result of the second comparison circuit 615a, etc.

[0090] Even with such a configuration, the same effects as those of the first embodiment can be obtained.

[0091] D. Fourth Implementation

[0092] The display circuit device 1000 of the fourth embodiment generates CRC values ​​and detects errors for the image data Dp1 and the command data Dc1 and Dc2 using different circuits as in the third embodiment, but differs from the third embodiment in that the display control circuit 500 has a structure for detecting errors.

[0093] Figure 7 : is a block diagram showing the structure of a display circuit device 1000 according to a fourth embodiment.

[0094] like Figure 7 As shown in FIG. 2 , the drive signal generating circuit 400 of this embodiment has the same structure as the drive signal generating circuit 400 of the third embodiment.

[0095] In addition, the display control circuit 500 of this embodiment includes a first expectation value generation circuit 505, a first receiving circuit 506, a first error detection circuit 507, an error signal transmission circuit 508, a second expectation value generation circuit 515, a second receiving circuit 516, and a second error detection circuit 517 in addition to the data receiving circuit 501, the data buffer 502, and the data transmitting circuit 503. These circuits have the same functions as the first expectation value generation circuit 603, the first receiving circuit 604, the first error detection circuit 605, the error signal transmission circuit 606, the second expectation value generation circuit 613, the second receiving circuit 614, and the second error detection circuit 615 in the third embodiment. In addition, the first error detection circuit 507 includes a first comparison circuit 507a, and the second error detection circuit 517 includes a second comparison circuit 517a. Moreover, the first comparison circuit 507a and the second comparison circuit 517a have the same functions as the first comparison circuit 605a and the second comparison circuit 615a in the third embodiment.

[0096] Even with such a configuration, the same effects as those of the first embodiment can be obtained.

[0097] E. Other Implementation Methods

[0098] Although the embodiments have been described above, other embodiments are possible. For example, the following are described.

[0099] (1) In the above embodiment, regarding the generation of the CRC value in the drive signal generation circuit 400, a common circuit may be used for the image data Dp1 and the command data Dc1 and Dc2, while regarding the detection of errors, different circuits may be used for the image data Dp1 and the command data Dc1 and Dc2. Figure 8 , the display control circuit 500 includes both a circuit for detecting an error in the image data Dp1 and a circuit for detecting an error in the command data Dc1 and Dc2. Although not shown in the figure, the CPU 600 may also include both a circuit for detecting an error in the image data Dp1 and a circuit for detecting an error in the command data Dc1 and Dc2. Fig. 9 , a circuit for detecting an error in the image data Dp1 is provided in the display control circuit 500, and a circuit for detecting an error in the command data Dc1 and Dc2 is provided in the CPU 600. In addition, although not shown in the figure, it is also possible that different circuits are used for the image data Dp1 and the command data Dc1 and Dc2 in generating the CRC value in the drive signal generating circuit 400, while a common circuit is used for the image data Dp1 and the command data Dc1 and Dc2 in detecting an error.

[0100] (2) In the above embodiment, the CRC value of the command data Dc1 and the CRC value of the command data Dc2 are generated by the common first generation circuit 403 and transmitted by the common first transmission circuit 404. However, it is also possible to configure the command data Dc1 and the command data Dc2 to have a generation circuit and a transmission circuit respectively. If this configuration is adopted in the third and fourth embodiments in which different generation circuits are used for the command data Dc1, Dc2 and the image data Dp1, the first data selection circuit 402 is not required.

[0101] (3) In the above embodiment, a structure capable of detecting errors in both the command data Dc1 and the command data Dc2 is shown, but a structure capable of detecting errors in only one of the two may be used. Fig.10 2 shows a configuration in which, in the display circuit device 1000 of the third embodiment, only an error in the command data Dc2 read from the command register 401 can be detected. Thus, if this configuration is adopted in the third and fourth embodiments, the first data selection circuit 402 is not required.

[0102] (4) In the above embodiment, the configuration for detecting an error in the image data Dp1 is not essential, and any configuration may be used as long as an error in the command data Dc1 and Dc2 can be detected.

[0103] (5) In the above embodiment, the drive signal generation circuit 400 may not store the command data Dc0 input from the control circuit 601 in the command register 401, but may perform various settings based on the input command data Dc0. In this case, the command register 401 is unnecessary.

[0104] (6) In the above embodiment, the CRC value is generated from the image data Dp0, Dp1 in units of one frame, but the unit of the image data Dp0, Dp1 for generating the CRC value is arbitrary, and the CRC value may be generated from the image data Dp0, Dp1 in units of one line.

[0105] (7) In the above embodiment, the algorithm for generating the code CDa by the first expected value generating circuit 603 is made the same as the algorithm for generating the code CDb by the first generating circuit 403, and the first comparison circuit 605a detects errors in the image data Dp1 and the command data Dc1 and Dc2 received by the drive signal generating circuit 400 by comparing the code CDa with the code CDd corresponding to the code CDb. However, the algorithm for generating the code CDa and the algorithm for generating the code CDb may be different. For example, the algorithm for generating the code CDb may be determined in such a way as to generate the code CDb having the same absolute value as the code CDa and the opposite sign. In this case, in the first error detection circuit 605, when the sum of the code CDa and the code CDd corresponding to the code CDb is a value other than 0, the error signal Err1 is generated. In this way, the first error detection circuit 605 only needs to detect errors in the image data Dp1 and the command data Dc1 and Dc2 received by the drive signal generating circuit 400 based on the code CDa and the code CDd.

[0106] (8) In the above embodiment, a liquid crystal display panel is used as the electro-optical panel 10, but the embodiment is not limited to this. For example, it can also be applied to an electro-optical device 1 having an electro-optical panel 10 other than a liquid crystal display panel, such as a display panel composed of a light-emitting element such as an OLED (Organic Light-Emitting Diode) or a display panel composed of an electrophoretic element.

[0107] In addition, by appropriately combining the first to fourth embodiments and the other embodiments (1) to (8), various display circuit devices 1000 can be implemented. For example, an embodiment may be adopted in which error detection of the image data Dp1 is not performed and none of the command register 401, the first data selection circuit 402, and the second data selection circuits 504 and 602 is provided.

[0108] F. Application Examples

[0109] The electro-optical device 1 illustrated in each of the above embodiments can be used in various electronic devices. Figures 11 to 14 Specific embodiments of electronic equipment using the electro-optical device 1 are illustrated.

[0110] Fig.11Schematic diagram of a projection display device 3100 using electro-optical devices 1R, 1G, and 1B having the same structure as the electro-optical device 1 described above. The projection display device 3100 includes three electro-optical devices 1R, 1G, and 1B corresponding to different display colors, specifically, red, green, and blue. The illumination optical system 3101 supplies the red component r of the output light from the illumination device 3102 to the electro-optical device 1R, supplies the green component g to the electro-optical device 1G, and supplies the blue component b to the electro-optical device 1B. The electro-optical devices 1R, 1G, and 1B function as light modulators that modulate the monochromatic light supplied from the illumination optical system 3101 according to the display image. The projection optical system 3103 synthesizes the output light from the electro-optical devices 1R, 1G, and 1B and projects it onto a projection surface 3104. The observer visually recognizes the image projected onto the projection surface 3104.

[0111] Fig.12 It is a perspective view of a portable personal computer 3200 that uses the electro-optical device 1. The personal computer 3200 includes the electro-optical device 1 that displays various images, and a main body 3210 provided with a power switch 3201 and a keyboard 3202.

[0112] Fig.13 1 is a diagram showing a configuration example of a portable information terminal (PDA: Personal Digital Assistants) 3300 to which the electro-optical device 1 is applied. The portable information terminal 3300 includes a plurality of operation buttons 3301, a power switch 3302, and the electro-optical device 1 as a display unit. When the power switch 3302 is operated, various information such as an address book and a schedule are displayed on the electro-optical device 1.

[0113] In addition, as electronic equipment to which the electro-optical device 1 is applied, Figures 11 to 13 In addition to the devices listed above, there may be mentioned digital still cameras, televisions, video cameras, electronic notebooks, electronic paper, calculators, word processors, workstations, videophones, POS (Point of Sale system) terminals, printers, scanners, copiers, video players, devices with touch panels, etc.

[0114] Fig.14 1 is a diagram showing a structural example of a mobile body to which the electro-optical device 1 is applied. The mobile body is, for example, a device or apparatus that includes a driving mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices and moves on the ground, in the sky, or on the sea. As the mobile body, for example, a car, an airplane, a motorcycle, a ship, or a robot can be envisioned. Fig.14A car 3400 is schematically shown as a specific example of a mobile body. The car 3400 has a body 3401 and wheels 3402. An electro-optical device 1 having an electro-optical panel 10 and a display circuit device 1000 is assembled in the car 3400. The display circuit device 1000 may include, for example, an ECU (electronic control unit) or the like. The electro-optical panel 10 is, for example, a panel device such as an instrument panel. The display circuit device 1000 generates an image for prompting a user and displays the image on the electro-optical panel 10. For example, information such as vehicle speed, remaining fuel, driving distance, and settings of various devices is displayed as an image.

Claims

1. A display circuit device, characterized in that: A processing device, a display control circuit, and a driving circuit are provided. The driving circuit receives command data from the processing device and receives image data and a control signal from the display control circuit, and drives a display panel based on the image data and the command data. The driving circuit comprises: a first generating circuit that generates a first CRC value as a CRC value of the command data input from the processing device; and a first sending circuit, which sends the first CRC value to the processing device, The processing device has: a first expected value generating circuit that generates a first CRC expected value as a CRC value of the command data before being input to the driving circuit; a first receiving circuit, configured to receive the first CRC value sent by the first sending circuit; a first comparison circuit, configured to compare the first CRC expected value generated by the first expected value generation circuit with the first CRC value received by the first receiving circuit; as well as a control circuit that performs control based on a comparison result of the first comparison circuit between the first CRC expected value and the first CRC value, The command data is data for setting the operation of the drive circuit, the image data includes data that specifies the grayscale to be displayed by each pixel circuit of the display panel, and the control signal includes a synchronization signal.

2. The display circuit device according to claim 1, characterized in that: The driving circuit comprises: a command register storing the command data input from the processing device; and a first selection circuit that selects and outputs one of first command data that is command data previously stored in the command register and second command data that is command data already stored in the command register, The first generation circuit generates a CRC value of the first command data as the first CRC value when the first selection circuit selects the first command data, and generates a CRC value of the second command data as the first CRC value when the first selection circuit selects the second command data.

3. The display circuit device according to claim 1 or 2, characterized in that: The driving circuit comprises: a second generation circuit that generates a second CRC value as a CRC value of the image data input from the display control circuit; and a second sending circuit, which sends the second CRC value to the processing device, The processing device has: a second expected value generating circuit which receives the image data from the display control circuit and generates a second CRC expected value as a CRC value of the image data; a second receiving circuit, configured to receive the second CRC value sent by the second sending circuit; as well as a second comparison circuit for comparing the second CRC expected value generated by the second expected value generation circuit with the second CRC value received by the second receiving circuit; The control circuit performs control based on a comparison result of the second comparison circuit between the second CRC expected value and the second CRC value.

4. The display circuit device according to claim 1 or 2, characterized in that: The drive circuit includes a second selection circuit that selects and outputs one of the command data input from the processing device and the image data input from the display control circuit. The processing device includes a third selection circuit that selects and outputs one of the command data before being input to the drive circuit and the image data input from the display control circuit. The first generating circuit generates the first CRC value as the CRC value of the command data output from the second selecting circuit when the second selecting circuit selects the command data, and generates the second CRC value as the CRC value of the image data output from the second selecting circuit when the second selecting circuit selects the image data, The first sending circuit sends the first CRC value or the second CRC value to the processing device, The first receiving circuit receives the first CRC value or the second CRC value sent by the first sending circuit, The first expectation value generating circuit generates the first CRC expectation value as the CRC value of the command data output from the third selection circuit when the third selection circuit selects the command data, and generates the second CRC expectation value as the CRC value of the image data output from the third selection circuit when the third selection circuit selects the image data. The first comparison circuit compares the first CRC expectation value generated by the first expectation value generation circuit with the first CRC value received by the first receiving circuit, and compares the second CRC expectation value generated by the first expectation value generation circuit with the second CRC value received by the first receiving circuit. The control circuit performs control based on a comparison result of the first comparison circuit between the first CRC expected value and the first CRC value and a comparison result of the first comparison circuit between the second CRC expected value and the second CRC value.

5. A display circuit device, characterized in that: A processing device, a display control circuit, and a driving circuit are provided. The driving circuit receives command data from the processing device and receives image data and a control signal from the display control circuit, and drives a display panel based on the image data and the command data. The driving circuit comprises: a first generating circuit that generates a first CRC value as a CRC value of the command data input from the processing device; and a first sending circuit, which sends the first CRC value to the display control circuit, The display control circuit comprises: a first expected value generating circuit that generates a first CRC expected value as a CRC value of the command data before being input to the driving circuit; a first receiving circuit, configured to receive the first CRC value sent by the first sending circuit; as well as a first comparison circuit that compares the first CRC expected value generated by the first expected value generation circuit with the first CRC value received by the first receiving circuit, The processing device includes a control circuit that performs control based on a comparison result of the first comparison circuit between the first CRC expected value and the first CRC value. The command data is data for setting the operation of the drive circuit, the image data includes data that specifies the grayscale to be displayed by each pixel circuit of the display panel, and the control signal includes a synchronization signal.

6. The display circuit device according to claim 5, characterized in that: The driving circuit comprises: a command register storing the command data input from the processing device; and a first selection circuit that selects and outputs one of first command data that is command data previously stored in the command register and second command data that is command data already stored in the command register, The first generation circuit generates a CRC value of the first command data as the first CRC value when the first selection circuit selects the first command data, and generates a CRC value of the second command data as the first CRC value when the first selection circuit selects the second command data.

7. The display circuit device according to claim 5 or 6, characterized in that: The driving circuit comprises: a second generation circuit that generates a second CRC value as a CRC value of the image data input from the display control circuit; and a second sending circuit, which sends the second CRC value to the display control circuit, The display control circuit comprises: a second expected value generating circuit for generating a second CRC expected value as a CRC value of the image data output to the driving circuit; a second receiving circuit, configured to receive the second CRC value sent by the second sending circuit; as well as a second comparison circuit for comparing the second CRC expected value generated by the second expected value generation circuit with the second CRC value received by the second receiving circuit; The control circuit performs control based on a comparison result of the second comparison circuit between the second CRC expected value and the second CRC value.

8. The display circuit device according to claim 5 or 6, characterized in that: The drive circuit includes a second selection circuit that selects and outputs one of the command data input from the processing device and the image data input from the display control circuit. The display control circuit includes a third selection circuit that selects and outputs one of the command data before being input to the drive circuit and the image data output to the drive circuit. The first generating circuit generates the first CRC value as the CRC value of the command data output from the second selecting circuit when the second selecting circuit selects the command data, and generates the second CRC value as the CRC value of the image data output from the second selecting circuit when the second selecting circuit selects the image data, The first sending circuit sends the first CRC value or the second CRC value to the display control circuit, The first receiving circuit receives the first CRC value or the second CRC value sent by the first sending circuit, The first expectation value generating circuit generates the first CRC expectation value as the CRC value of the command data output from the third selection circuit when the third selection circuit selects the command data, and generates the second CRC expectation value as the CRC value of the image data output from the third selection circuit when the third selection circuit selects the image data. The first comparison circuit compares the first CRC expectation value generated by the first expectation value generation circuit with the first CRC value received by the first receiving circuit, and compares the second CRC expectation value generated by the first expectation value generation circuit with the second CRC value received by the first receiving circuit. The control circuit performs control based on a comparison result of the first comparison circuit between the first CRC expected value and the first CRC value and a comparison result of the first comparison circuit between the second CRC expected value and the second CRC value.

9. A display device, characterized in that: The display device comprises the display circuit device according to any one of claims 1 to 8 and the display panel. 10 . An electronic device comprising the display device according to claim 9 .

Images