Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a substrate, the substrate is provided with a plurality of bit lines arranged at intervals and parallel to each other, and the bit lines extend along a first direction; sequentially forming a conductive layer and a first sacrificial layer on the substrate; forming a plurality of groups of first grooves and second grooves which are staggered with each other on the first sacrificial layer through two photoetching processes, and the overlapping positions of the first grooves and the second grooves form overlapping grooves; wherein the first grooves extend along the first direction, and the second grooves extend along a second direction; removing at least part of the first sacrificial layer exposed in the overlapping grooves to form a contact hole; filling the contact hole with an insulating column, and etching the conductive layer with the insulating column as a mask to form a contact pad. The semiconductor structure preparation method provided by the application can reduce the formation defects of the contact pad, increase the product yield, improve the packing density of the capacitor, and increase the data storage capacity of the DRAM.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or apparatuses.

[0003] DRAM comprises multiple repeating memory cells, each including a capacitor and a transistor. The gate of the transistor is connected to the word line (WL), the drain to the bit line (BL), and the source to the capacitor. Capacitor contacts are located on the active region of the transistor, and the capacitor is electrically connected to these contacts via contact pads, enabling conduction between the capacitor and the active region.

[0004] However, as the size of capacitors in DRAM continues to shrink, the manufacturing of contact pads becomes increasingly difficult, and the defects in the contact pads are becoming more and more numerous, resulting in a decrease in product yield. At the same time, the storage capacity of DRAM also needs to be increased. Summary of the Invention

[0005] To address at least one of the problems mentioned in the background art, this application provides a method for fabricating a semiconductor structure and a semiconductor structure that can reduce contact pad formation defects and improve product yield; at the same time, it can increase the stacking density of capacitors and increase the data storage capacity of DRAM.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] On one hand, this application provides a method for fabricating a semiconductor structure, comprising:

[0008] A substrate is provided, in which multiple bit lines are arranged at intervals and parallel to each other, and the bit lines extend along a first direction;

[0009] A conductive layer and a first sacrificial layer are sequentially formed on the substrate;

[0010] Multiple sets of intersecting first and second trenches are formed on the first sacrificial layer through two photolithography processes, and the overlapping positions of the first and second trenches form overlapping trenches; wherein, the first trenches extend along a first direction and the second trenches extend along a second direction.

[0011] Remove at least part of the first sacrificial layer exposed in the overlapping trenches to form contact holes;

[0012] Insulating pillars are filled into the contact holes, and the conductive layer is etched using the insulating pillars as a mask to form a contact pad.

[0013] In the semiconductor structure fabrication method described above, optionally, the second direction is perpendicular to the first direction.

[0014] The semiconductor structure fabrication method described above, optionally, involves forming multiple sets of interlocking first trenches and second trenches on the first sacrificial layer through two photolithography processes, specifically including:

[0015] A first mask layer is formed on the first sacrificial layer, and the first sacrificial layer is removed along the first mask layer to form a plurality of first trenches;

[0016] A second sacrificial layer is formed on the first sacrificial layer, and the second sacrificial layer partially fills the first trench;

[0017] A second mask layer is formed on the second sacrificial layer, and the second sacrificial layer is removed along the second mask layer to form a plurality of second trenches; wherein the opening of the second trench is flush with the opening of the first trench.

[0018] The semiconductor structure fabrication method described above optionally includes sequentially forming a conductive layer and a first sacrificial layer on a substrate, specifically comprising:

[0019] A conductive layer is formed on the substrate;

[0020] At least one dielectric layer is formed on the conductive layer.

[0021] In the semiconductor structure fabrication method described above, optionally, at least one dielectric layer is formed on the conductive layer, specifically including:

[0022] A first dielectric layer is formed on the conductive layer;

[0023] A second dielectric layer is formed on the first dielectric layer.

[0024] The semiconductor structure fabrication method described above, optionally, involves forming a first mask layer on the first sacrificial layer and removing the first sacrificial layer along the first mask layer, specifically including:

[0025] A first mask layer is formed on the second dielectric layer; wherein the first mask layer has a plurality of first mask openings extending along a first direction, and the plurality of first mask openings are spaced apart along a direction perpendicular to the first direction;

[0026] The second dielectric layer is removed along the opening of the first mask, exposing a portion of the surface of the first dielectric layer.

[0027] In the semiconductor structure fabrication method described above, optionally, a first dielectric layer is formed on the conductive layer, specifically including:

[0028] A first oxide layer and a first barrier layer are sequentially formed on the conductive layer.

[0029] In the semiconductor structure fabrication method described above, optionally, a second dielectric layer is formed on the first dielectric layer, specifically including:

[0030] A second oxide layer and a second barrier layer are sequentially formed on the first barrier layer.

[0031] In the semiconductor structure fabrication method described above, optionally, both the first barrier layer and the second barrier layer include a stacked hard mask layer and an anti-reflection layer.

[0032] The semiconductor structure fabrication method described above, optionally, involves forming a second mask layer on the second sacrificial layer and removing the second sacrificial layer along the second mask layer, specifically including:

[0033] A second mask layer is formed on the second sacrificial layer; wherein the second mask layer has a plurality of second mask openings extending in a direction perpendicular to the first direction, and the plurality of second mask openings are spaced apart along the first direction;

[0034] The second sacrificial layer is removed along the opening of the second mask, exposing the first trench.

[0035] In the semiconductor structure fabrication method described above, optionally, a second sacrificial layer is formed on the first sacrificial layer, and the second sacrificial layer partially fills the first trench, specifically including:

[0036] A third hard mask layer is formed on the first sacrificial layer, and the third hard mask layer partially fills the first trench;

[0037] A third anti-reflective layer is formed on the third hard mask layer.

[0038] The semiconductor structure fabrication method described above, optionally, involves filling the contact hole with an insulating pillar and using the insulating pillar as a mask to etch a conductive layer to form a contact pad, specifically including:

[0039] Part of the first sacrificial layer was removed, exposing a portion of the insulating pillar;

[0040] A protective layer is formed to enclose the insulating pillars, and the protective layer forms small holes spaced between the insulating pillars;

[0041] Fill the small hole with an insulating column;

[0042] The first sacrificial layer and the conductive layer exposed outside the insulating pillar are etched away to form a contact pad.

[0043] Optionally, in the method for fabricating the semiconductor structure as described above, before filling the insulating pillars into the vias, the method further includes:

[0044] The protective layer and insulating pillars are etched until the via is formed into a round hole;

[0045] Fill the circular hole with an insulating column.

[0046] In the semiconductor structure fabrication method described above, optionally, a protective layer encapsulating the insulating pillars is formed, specifically including:

[0047] A protective layer is deposited using atomic layer deposition (ALD).

[0048] The semiconductor structure fabrication method described above, optionally, involves removing a portion of the first sacrificial layer and exposing the insulating pillar, specifically including:

[0049] The first sacrificial layer, which is 1 / 5 to 1 / 4 thick, is removed by etching.

[0050] In the semiconductor structure fabrication method described above, optionally, the projections of the contact pads and bit lines on the substrate surface overlap.

[0051] On the other hand, this application provides a semiconductor structure, which is prepared by the preparation method described above.

[0052] This application provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes: providing a substrate with multiple spaced and parallel bit lines extending along a first direction; sequentially forming a conductive layer and a first sacrificial layer on the substrate; forming multiple sets of intersecting first trenches and second trenches on the first sacrificial layer through two photolithography processes, with the overlapping positions of the first trenches and second trenches forming overlapping trenches; wherein the first trenches extend along the first direction and the second trenches extend along a second direction; removing at least a portion of the first sacrificial layer exposed in the overlapping trenches to form contact holes; filling the contact holes with insulating pillars and using the insulating pillars as a mask to etch the conductive layer to form contact pads. The contact pad formation method provided in this application can reduce contact pad formation defects and increase product yield; simultaneously, it can increase the capacitor stacking density and increase the data storage capacity of DRAM. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A schematic flowchart illustrating the method for fabricating the semiconductor structure provided in Embodiment 1 of this application;

[0055] Figure 2 A cross-sectional view of a substrate having a conductive layer and a first sacrificial layer formed on it, provided in Embodiment 1 of this application;

[0056] Figure 3 for Figure 2 A three-dimensional schematic diagram of the conductive layer and the first sacrificial layer in the middle;

[0057] Figure 4 This is a projection image of the contact pad in the substrate provided in Embodiment 1 of this application;

[0058] Figure 5 A flowchart illustrating the formation of a first trench and a second trench on a first sacrificial layer, provided in Embodiment 1 of this application;

[0059] Figure 6 This is a structural diagram showing the first mask layer formed on the first sacrificial layer.

[0060] Figure 7 for Figure 6 A three-dimensional view of the structure of each layer above the middle conductive layer;

[0061] Figure 8 This is a structural diagram of the first trench formed in the first sacrificial layer according to Embodiment 1 of this application;

[0062] Figure 9 for Figure 8 A three-dimensional view of the structure of each layer above the middle conductive layer;

[0063] Figure 10 This is a structural diagram of a second sacrificial layer and a second mask layer formed on a first sacrificial layer, as provided in Embodiment 1 of this application.

[0064] Figure 11 for Figure 10 A three-dimensional view of the structure of each layer above the middle conductive layer;

[0065] Figure 12 This is a structural diagram of a second trench formed on a first sacrificial layer, provided in Embodiment 1 of this application.

[0066] Figure 13 for Figure 12 A three-dimensional view of the structure of each layer above the middle conductive layer;

[0067] Figure 14 This is a structural diagram of a contact hole formed on the first sacrificial layer according to Embodiment 1 of this application;

[0068] Figure 15 for Figure 14 A three-dimensional view of the intermediate conductive layer and the first sacrificial layer;

[0069] Figure 16 for Figure 15 A structural diagram showing the filling of insulating pillars within the contact holes;

[0070] Figure 17This is a flowchart of etching to form contact pads using an insulating pillar as a mask;

[0071] Figure 18 for Figure 16 A structural diagram showing the removal of part of the first oxide layer;

[0072] Figure 19 for Figure 18 A structural diagram showing the protective layer forming around the insulating column;

[0073] Figure 20 for Figure 19 A structural diagram showing the removal of part of the protective layer and insulating pillars;

[0074] Figure 21 for Figure 20 A structural diagram showing the formation of small holes between insulating pillars;

[0075] Figure 22 for Figure 21 Structural diagram of insulating pillars filling small and medium-sized holes;

[0076] Figure 23 This is a structural diagram of the contact pad.

[0077] Explanation of reference numerals in the attached figures:

[0078] 100-Semiconductor structure;

[0079] 1-Substrate; 2-Conductive layer; 3-First sacrificial layer; 4-First mask layer; 5-Second sacrificial layer; 6-Second mask layer;

[0080] 11-Bit line; 12-Active region; 13-Shallow trench isolation structure; 14-Contact plug; 15-Insulating structure; 16-Contact barrier layer; 17-Isolation structure; 18-Word line; 21-Contact pad; 3a-First trench; 3b-Second trench; 3c-Overlapping trench; 3d-Contact hole; 3e-Insulating post; 31-First dielectric layer; 32-Second dielectric layer; 33-Protective layer; 41-First mask opening; 51-Third hard mask layer; 52-Third anti-reflection layer; 61-Second mask opening;

[0081] 111 - First bit line layer; 112 - Second bit line layer; 113 - Bit line blocking layer; 311 - First oxide layer; 312 - First blocking layer; 321 - Second oxide layer; 322 - Second blocking layer; 331 - Orifice;

[0082] 3311 - Round hole;

[0083] A - Hard mask layer; B - Anti-reflective layer. Detailed Implementation

[0084] DRAM is composed of multiple sets of perpendicularly intersecting word lines and bit lines, forming multiple repeating memory cells. Each memory cell includes a capacitor and a transistor. The transistor includes a gate, a drain, and a source. The gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The transistor is turned on or off by a voltage signal on the word line. Data information stored in the capacitor is read through the bit line, or data information is written to the capacitor for storage through the bit line.

[0085] In this configuration, the source of the transistor is connected to the capacitor via a capacitor contact plug and a contact pad. The capacitor contact plug is connected to the source, and the contact pad is in contact with the capacitor contact plug. The capacitor and the contact pad are connected in a one-to-one correspondence.

[0086] This application provides a method for preparing a semiconductor structure and the semiconductor structure itself. The method for preparing the semiconductor structure can be used to form contact pads with high density, while reducing contact pad formation defects and increasing product yield.

[0087] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0088] Example 1

[0089] This embodiment provides a method for fabricating a semiconductor structure, which can be, for example, a DRAM. It is understood that the semiconductor structure is not limited to DRAM.

[0090] Figure 1 A schematic flowchart illustrating the method for fabricating the semiconductor structure provided in Embodiment 1 of this application; Figure 2 A cross-sectional view of a substrate having a conductive layer and a first sacrificial layer formed on it, provided in Embodiment 1 of this application; Figure 3 for Figure 2 A three-dimensional schematic diagram of the conductive layer and the first sacrificial layer in the middle; Figure 4 This is a projection of the contact pad in the substrate provided in Embodiment 1 of this application.

[0091] like Figure 1 As shown, the method for fabricating the semiconductor structure 100 provided in this embodiment includes:

[0092] S100. A substrate 1 is provided, wherein a plurality of bit lines 11 are arranged at intervals and parallel to each other, and the bit lines 11 extend along a first direction.

[0093] like Figure 2 As shown, a plurality of shallow trench isolation structures 13 are spaced apart on the substrate 1, and an active region 12 of a transistor is formed between adjacent shallow trench isolation structures 13. For example, the material constituting the shallow trench isolation structure 13 may include silicon oxide, silicon nitride, etc., and the material constituting the active region 12 may include silicon, etc.

[0094] The substrate 1 also contains a plurality of parallel bit lines 11 extending along a first direction, and the plurality of bit lines 11 are arranged at intervals. In addition, the substrate 1 also contains a plurality of parallel word lines (not shown in the figure), the plurality of word lines are arranged at intervals, and the word lines extend along a direction perpendicular to the bit lines 11.

[0095] The bit line 11 may include a first bit line layer 111 and a second bit line layer 112 stacked together, with the first bit line layer 111 located near the active region 12 and the shallow trench isolation structure 13. For example, the material constituting the first bit line layer 111 may be polysilicon, and the material constituting the second bit line layer 112 may be tungsten.

[0096] In addition, a bit line blocking layer 113 may be provided between the first bit line layer 111 and the second bit line layer 112. The bit line blocking layer 113 can prevent the materials between the first bit line layer 111 and the second bit line layer 112 from penetrating each other, and the bit line blocking layer 113 can realize the electrical connection between the first bit line layer 111 and the second bit line layer 112. The material constituting the bit line blocking layer 113 is, for example, titanium nitride.

[0097] like Figure 2 As shown, a plurality of contact plugs 14 are also disposed at intervals within the substrate 1. The contact plugs 14 are located between adjacent bit lines 11, and each contact plug 14 is correspondingly engaged with each active region 12. The contact plugs 14 are used to connect the active region 12 to the capacitor. For example, the material constituting the contact plug 14 may include conductive materials such as polysilicon.

[0098] To achieve an insulated connection between the contact plug 14 and the bit line 11, an insulating structure 15 may be provided between the contact plug 14 and the bit line 11. For example, the material constituting the insulating structure 15 may include silicon nitride, silicon oxide, etc., such as the insulating structure 15 comprising a stacked silicon nitride-silicon oxide-silicon nitride three-layer composite structure connected between the contact plug 14 and the bit line 11.

[0099] S200, a conductive layer 2 and a first sacrificial layer 3 are sequentially formed on the substrate 1.

[0100] In practical applications, such as Figure 2 and Figure 4As shown, a capacitor (not shown) is located above the substrate. The capacitor is connected to the active region 12 via a contact pad 21. For example, the capacitor is connected to the source via the contact pad 21. A conductive layer 2 is deposited on the substrate 1, and the contact pad 21 is formed through the conductive layer 2. The contact pad 21 contacts the contact plug 14 located below it, so that the capacitor and the active region 12 are electrically connected through the contact pad 21 and the contact plug 14.

[0101] By forming a first sacrificial layer 3 on the conductive layer 2, etching the first sacrificial layer 3 to form a mask pattern, and using the etched first sacrificial layer 3 as a mask to etch the conductive layer 2, the conductive layer 2 is finally formed into multiple spaced contact pads 21, and the contact pads 21 are at least partially in contact with the contact plugs 14.

[0102] For example, the conductive layer 2 and the first sacrificial layer 3 can be deposited on the substrate 1 in sequence by physical vapor deposition or chemical vapor deposition.

[0103] like Figure 2 As shown, before depositing the conductive layer 2 on the substrate 1, a contact barrier layer 16 can be deposited on the substrate 1 first. The contact barrier layer 16 is located between the contact plug 14 and the conductive layer 2, and is used to prevent the interpenetration of materials between the contact plug 14 and the conductive layer 2. The contact barrier layer 16 can also realize the electrical connection between the contact plug 14 and the conductive layer 2. For example, the material constituting the contact barrier layer 16 can be titanium nitride.

[0104] In this embodiment, the first sacrificial layer 3 includes at least one dielectric layer. The conductive layer 2 and the first sacrificial layer 3 are sequentially formed on the substrate 1. Specifically, the conductive layer 2 is first formed on the substrate 1, and then at least one dielectric layer is formed on the conductive layer 2. For example, at least one dielectric layer is deposited on the conductive layer 2 by physical vapor deposition or chemical vapor deposition.

[0105] like Figure 2 and Figure 3 As shown, in some embodiments, the first sacrificial layer 3 may include a stacked first dielectric layer 31 and a second dielectric layer 32. Forming the first sacrificial layer 3 on the conductive layer 2 specifically involves: forming a first dielectric layer 31 on the conductive layer 2, for example, depositing the first dielectric layer 31 on the conductive layer 2; and then forming a second dielectric layer 32 on the first dielectric layer 31, for example, depositing the second dielectric layer 32 on the first dielectric layer 31.

[0106] In this embodiment, the first dielectric layer 31 may include a first oxide layer 311 and a first barrier layer 312, and the second dielectric layer 32 may include a second oxide layer 321 and a second barrier layer 322. The formation of the first dielectric layer 31 and the second dielectric layer 32 on the conductive layer 2 specifically involves sequentially forming the first oxide layer 311, the first barrier layer 312, the second oxide layer 321, and the second barrier layer 322 on the conductive layer 2.

[0107] The first barrier layer 312 and the second barrier layer 322 both include a stacked hard mask layer A and an anti-reflection layer B. By sequentially stacking the hard mask layer A and the anti-reflection layer B, the standing wave effect in the photolithography process can be improved, and the adjustment space of the etching process can be increased, thereby improving the etching accuracy of the subsequent etching process on the first dielectric layer 31 and the second dielectric layer 32, and ultimately improving the positional accuracy of the etched contact pad 21.

[0108] like Figure 2 and Figure 3 As shown, forming the first sacrificial layer 3 on the conductive layer 2 includes: sequentially forming a first oxide layer 311, a hard mask layer A, an anti-reflection layer B, a second oxide layer 321, a hard mask layer A, and an anti-reflection layer B on the conductive layer 2. Specifically, the hard mask layer A can be a spin-coated hard mask composition layer, such as an SOH layer; the anti-reflection layer B can be a silicon oxynitride layer.

[0109] S300, Multiple sets of intersecting first trenches 3a and second trenches 3b are formed on the first sacrificial layer 3 through two photolithography processes, and the overlapping position of the first trenches 3a and the second trenches 3b forms an overlapping trench 3c; wherein, the first trenches 3a extend along a first direction, and the second trenches 3b extend along a second direction.

[0110] After two photolithography processes on the first sacrificial layer 3, multiple sets of spaced first trenches 3a and multiple sets of spaced second trenches 3b are formed, with the first trenches 3a and second trenches 3b intersecting each other. The overlapping positions of the first trenches 3a and second trenches 3b can form overlapping trenches 3c. Subsequently, by processing the areas where the overlapping trenches 3c are located, multiple spaced contact pads 21 are formed in the conductive layer 2.

[0111] The first trench 3a extends along the first direction, that is, the extension direction of the first trench 3a is parallel to the extension direction of the bit line 11. This facilitates the positioning of the first trench 3a. Consequently, the position of the overlapping trench 3c formed by the first trench 3a and the second trench 3b is more accurate, thereby improving the position accuracy of the contact pad 21 and ensuring the performance of the electrical connection between the capacitor and the active region 12.

[0112] Furthermore, to further improve the positioning accuracy of the contact pad 21, the second direction can be perpendicular to the first direction, that is, the extension direction of the second groove 3b is perpendicular to the extension direction of the first groove 3a. For example, the extension direction of the second groove 3b is parallel to the extension direction of the letter line.

[0113] like Figure 2 As shown, it should be noted that, in order to insulate the contact pads 21 from each other, an isolation structure 17 can be formed on the substrate 1 before depositing the conductive layer 2 on the substrate 1. Adjacent contact pads 21 are insulated from each other by the isolation structure 17. For example, the material constituting the isolation structure 17 can be silicon nitride.

[0114] Alternatively, an isolation structure 17 can be formed on substrate 1 first, and then a contact barrier layer 16 can be deposited on substrate 1, with the contact barrier layer 16 covering the isolation structure 17.

[0115] Figure 5 A flowchart illustrating the formation of a first trench and a second trench on a first sacrificial layer, provided in Embodiment 1 of this application;

[0116] Figure 6 This is a structural diagram showing the first mask layer formed on the first sacrificial layer. Figure 7 for Figure 6 A three-dimensional view of the structure of each layer above the middle conductive layer; Figure 8 This is a structural diagram of the first trench formed in the first sacrificial layer according to Embodiment 1 of this application; Figure 9 for Figure 8 A three-dimensional view of the structure of each layer above the middle conductive layer.

[0117] Figure 10 This is a structural diagram of a second sacrificial layer and a second mask layer formed on a first sacrificial layer, as provided in Embodiment 1 of this application. Figure 11 for Figure 10 A three-dimensional view of the structure of each layer above the middle conductive layer; Figure 12 This is a structural diagram of a second trench formed on a first sacrificial layer, provided in Embodiment 1 of this application. Figure 13 for Figure 12 A three-dimensional view of the structure of each layer above the middle conductive layer.

[0118] like Figure 5 As shown, specifically, multiple sets of intersecting first trenches 3a and second trenches 3b are formed on the first sacrificial layer 3 through two photolithography processes, including the following steps:

[0119] S310. A first mask layer 4 is formed on the first sacrificial layer 3, and the first sacrificial layer 3 is removed along the first mask layer 4 to form a plurality of first trenches 3a.

[0120] like Figures 6 to 9As shown, a first mask layer 4 is first formed on the first sacrificial layer 3. The first mask layer 4 has a first mask pattern. By using the first mask pattern as a mask, the area on the first sacrificial layer 3 exposed outside the first mask pattern is etched to form the first trench 3a.

[0121] For example, the first mask layer 4 may be a first photoresist layer formed on the first sacrificial layer 3, the first photoresist layer having a first mask pattern, so that a portion of the surface of the first sacrificial layer 3 is exposed outside the first mask pattern. After etching to form the first trench 3a, the first photoresist layer is removed.

[0122] Specifically, S310 may include:

[0123] A first mask layer 4 is formed on the second dielectric layer 32; wherein the first mask layer 4 has a plurality of first mask openings 41 extending along a first direction, and the plurality of first mask openings 41 are arranged at intervals along a direction perpendicular to the first direction.

[0124] like Figure 6 and Figure 7 As shown, a first mask layer 4 is formed on the anti-reflection layer B on the top layer of the second dielectric layer 32. For example, a first photoresist layer with a first mask pattern is formed on the anti-reflection layer B. The first photoresist layer has a plurality of first mask openings 41. The first mask openings 41 extend along a first direction, and the plurality of first mask openings 41 are spaced apart along a direction perpendicular to the first direction.

[0125] like Figure 8 and Figure 9 As shown, after the first mask layer 4 is formed on the second dielectric layer 32, the first mask layer 4 is used as a mask to etch the second dielectric layer 32, that is, to etch the second dielectric layer 32 exposed within the first mask opening 41. The etching removes the anti-reflective layer B, the hard mask layer A, and the portion of the second oxide layer 321 exposed within the first mask opening 41 of the second dielectric layer 32. The second oxide layer 321 forms a plurality of first trenches 3a extending along the first direction and spaced apart along the second direction. The portion of the surface of the first dielectric layer 31 corresponding to the opening of the first trenches 3a is exposed outside the patterned second oxide layer 321, that is, a portion of the surface of the anti-reflective layer B located on the top layer of the first dielectric layer 31 is exposed.

[0126] S320, A second sacrificial layer 5 is formed on the first sacrificial layer 3, and the second sacrificial layer 5 partially fills the first trench 3a.

[0127] like Figure 10 and Figure 11As shown, after etching the second dielectric layer 32 to form the first trench 3a on the surface of the first dielectric layer 31, the second sacrificial layer 5 is formed on the surface of the first sacrificial layer 3 (i.e. the first dielectric layer 31). For example, the second sacrificial layer 5 is deposited on the first dielectric layer 31 and is formed on the surface of the first dielectric layer 31 and filled into the first trench 3a.

[0128] Specifically, the second sacrificial layer 5 may include a third hard mask layer 51 and a third anti-reflection layer 52. The functions of the third hard mask layer 51 and the third anti-reflection layer 52 are the same as those of the hard mask layer A and the anti-reflection layer B in the first dielectric layer 31 and the second dielectric layer 32, and will not be repeated here.

[0129] Forming the second sacrificial layer 5 on the first sacrificial layer 3 includes: forming a third hard mask layer 51 on the surface of the first sacrificial layer 3 (i.e., the first dielectric layer 31), the third hard mask layer 51 partially filling the first trench 3a, and then forming a third anti-reflection layer 52 on the third hard mask layer 51.

[0130] S330, a second mask layer 6 is formed on the second sacrificial layer 5, and the second sacrificial layer 5 is removed along the second mask layer 6 to form a plurality of second trenches 3b; wherein the opening of the second trench 3b is flush with the opening of the first trench 3a.

[0131] like Figure 10 and Figure 11 As shown, after the second sacrificial layer 5 is formed on the first sacrificial layer 3, the second mask layer 6 is formed on the second sacrificial layer 5, that is, the second mask layer 6 is formed on the third anti-reflection layer 52.

[0132] The second mask layer 6 is, for example, a second photoresist layer, which has a second mask pattern, exposing a portion of the surface of the third anti-reflective layer 52 outside the second mask layer 6. Specifically, the second mask layer 6 has a plurality of second mask openings 61 extending in a direction perpendicular to the first direction, and the plurality of second mask openings 61 are spaced apart along the first direction.

[0133] like Figure 12 and Figure 13 As shown, the second mask layer 6 is used as a mask, and the second sacrificial layer 5 is etched at the second mask opening 61 to the third hard mask layer 51, so that the third hard mask layer 51 is patterned to form multiple second trenches 3b and exposes the first trench 3a.

[0134] The extension direction of the second trench 3b is perpendicular to the extension direction of the first trench 3a. The second trench 3b and the first trench 3a together form multiple overlapping trenches 3c arranged in an array along the first and second directions. Furthermore, by controlling the etching rate and etching time, the opening of the second trench 3b is made flush with the opening of the first trench 3a, thereby improving the etching quality in the subsequent overlapping trenches 3c formed by the first trench 3a and the second trench 3b, reducing the risk of collapse, and improving the uniformity of etching.

[0135] S400, Remove at least part of the first sacrificial layer 3 exposed in the overlapping trench 3c to form a contact hole 3d.

[0136] Figure 14 This is a structural diagram of a contact hole formed on the first sacrificial layer according to Embodiment 1 of this application; Figure 15 for Figure 14 A three-dimensional view of the intermediate conductive layer and the first sacrificial layer.

[0137] like Figure 14 and Figure 15 As shown, after forming the first trench 3a and the second trench 3b on the first sacrificial layer 3 (i.e., the first dielectric layer 31), the pattern formed by the first trench 3a and the second trench 3b is used as a mask to etch the first sacrificial layer 3 (i.e., the first dielectric layer 31). Specifically, the first dielectric layer 31 exposed in the overlapping trench 3c formed at the intersection of the first trench 3a and the second trench 3b is etched.

[0138] The etching process begins from the anti-reflective layer B at the top of the first dielectric layer 31 and extends down to the bottom first oxide layer 311. As the etching progresses, it removes a portion of the trench walls of the first trench 3a and the second trench 3b on the outer periphery of the overlapping trench 3c, causing the contact hole 3d to gradually transition from a square corner to a rounded corner. This process continues until the first oxide layer 311 is reached, at which point the contact hole 3d formed within the first oxide layer 311 is approximately a circular hole 3311.

[0139] Among them, such as Figure 14 and Figure 15 As shown, etching proceeds to the first oxide layer 311, removing the hard mask layer A and the anti-reflection layer B above the first oxide layer 311, forming a contact hole 3d in the first oxide layer 311. It should be noted that by controlling the etching rate and etching time, the contact hole 3d can extend to the middle of the first oxide layer 311, or the contact hole 3d can penetrate through the first oxide layer 311.

[0140] S500, fill the contact hole 3d with insulating pillar 3e, and use the insulating pillar 3e as a mask to etch the conductive layer 2 to form the contact pad 21.

[0141] Figure 16 for Figure 15A structural diagram showing the filling of insulating pillars within the contact holes; Figure 17 This is a flowchart of etching to form contact pads using an insulating pillar as a mask; Figure 18 for Figure 16 A structural diagram showing the removal of part of the first oxide layer; Figure 19 for Figure 18 A structural diagram showing the protective layer forming around the insulating column; Figure 20 for Figure 19 A structural diagram showing the removal of part of the protective layer and insulating pillars; Figure 21 for Figure 20 A structural diagram showing the formation of small holes between insulating pillars; Figure 22 for Figure 21 Structural diagram of insulating pillars filling small and medium-sized holes; Figure 23 This is a structural diagram of the contact pad.

[0142] like Figure 16 As shown, after forming a contact hole 3d in the first oxide layer 311, an insulating material is filled into the contact hole 3d to form an insulating pillar 3e. For example, the insulating material can be silicon nitride. The filled insulating material can be higher than the surface of the first oxide layer 311 to ensure that the insulating material completely fills the contact hole 3d in the first oxide layer 311. After filling with the insulating material, the insulating pillar 3e above the surface of the first oxide layer 311 is etched or ground to make the insulating pillar 3e flush with the upper surface of the first oxide layer 311.

[0143] like Figure 17 As shown, in S500, the conductive layer 2 is etched using the insulating pillar 3e as a mask to form the contact pad 21, specifically including:

[0144] S510, Remove part of the first sacrificial layer 3 and expose part of the insulating pillar 3e.

[0145] like Figure 18 As shown, a portion of the first sacrificial layer 3 (i.e., the first oxide layer 311) is etched away, exposing a portion of the insulating pillar 3e. Exemplarily, the etching can be performed using dry etching or wet etching, by selectively etching the etching gas or etchant to remove a portion of the first oxide layer 311 while retaining the insulating pillar 3e.

[0146] The thickness of the removed first oxide layer 311 can be 1 / 5 to 1 / 4 of its total thickness, so that the height of the exposed insulating pillar 3e is 1 / 5 to 1 / 4 of the total thickness of the first oxide layer 311. This facilitates the subsequent formation of a protective layer 33 outside the exposed insulating pillar 3e and ensures sufficient redundancy for subsequent etching of the first oxide layer 311 through the gaps between the protective layers 33, reducing the difficulty of subsequently etching the gaps into circular holes.

[0147] S520, a protective layer 33 is formed to enclose the insulating pillars 3e, and the protective layer 33 forms small holes 331 spaced between the insulating pillars 3e.

[0148] like Figure 19 As shown, specifically, an atomic layer deposition (ALD) process can be used to deposit a protective layer 33 on the first oxide layer 311. The protective layer 33 formed by the ALD process surrounds the outside of the insulating pillars 3e, and small holes 331 are formed between the protective layers 33 outside the adjacent insulating pillars 3e. Furthermore, the insulating pillars 3e can be further filled into the small holes 331 to increase the density of the insulating pillars 3e, thereby increasing the density of the formed contact pads 21, increasing the density of the capacitors corresponding to the contact pads 21, thereby increasing the storage capacity of the DRAM and improving the utilization rate of the DRAM.

[0149] For example, the material constituting the protective layer 33 can be the same as the material constituting the first oxide layer 311, for example, the protective layer 33 is a silicon oxide layer.

[0150] It is understood that the thickness of the protective layer 33 surrounding the insulating post 3e determines the size of the aperture 331. Therefore, the thickness of the protective layer 33 can be controlled by controlling the rate and duration of the ALD process, so that the cross-sectional area of ​​the aperture 331 is slightly smaller than that of the contact hole 3d. With further etching of the aperture 331, the aperture 331 is formed into a circular hole 3311 that is almost the same size as the contact hole 3d.

[0151] S530, fill the small hole 331 with insulating post 3e.

[0152] like Figure 20 and Figure 21 As shown, specifically, before filling the small hole 331 with the insulating pillar 3e, the insulating pillar 3e is exposed by etching the protective layer 33 and the first oxide layer 311. Then, the protective layer 33, the first oxide layer 311 and the insulating pillar 3e are simultaneously etched. Due to the higher etching rate at the angular parts of the outer periphery of the small hole 331 between the protective layers 33, as the etching progresses, more material is etched from the angular parts of the outer edge of the small hole 331, and the size of the small hole 331 gradually increases until the small hole 331 is formed into a circular hole 3311 of the same size as the contact hole 3d.

[0153] As etching proceeds, the thicknesses of the protective layer 33, the insulating pillar 3e, and the first oxide layer 311 all decrease. For example... Figure 21 As shown, when the small hole 331 is formed into a circular hole 3311 of the same size as the contact hole 3d, for example, both the insulating post 3e and the circular hole 3311 are flush with the surface of the first oxide layer 311. Figure 22As shown, after etching to form the small hole 331 into a round hole 3311 of the same size as the contact hole 3d, the round hole 3311 is then filled with an insulating post 3e.

[0154] S540, etch away the first sacrificial layer 3 and the conductive layer 2 exposed outside the insulating pillar 3e to form a contact pad 21.

[0155] like Figure 23 As shown, after the insulating pillar 3e is filled in the circular hole 3311, the first sacrificial layer 3 is etched away. Then, using the insulating pillar 3e in the contact hole 3d and the insulating pillar 3e in the circular hole 3311 as a mask, the conductive layer 2 exposed outside the insulating pillar 3e is etched away so that the conductive layer 2 forms a plurality of spaced contact pads 21.

[0156] It is understandable that by filling the circular holes 3311 with insulating pillars 3e, the spacing between each insulating pillar 3e is increased on the basis of the original array arrangement of insulating pillars 3e, thus increasing the density of insulating pillars 3e, thereby increasing the density of contact pads 21, increasing the density of capacitors corresponding to contact pads 21, and thus increasing the storage capacity of DRAM and improving the utilization rate of DRAM.

[0157] In addition, such as Figure 4 As shown, in this embodiment, based on the addition of contact pads 21 in the array arrangement and gaps of each contact pad 21 formed by etching the conductive layer 2, the projections of the contact pads 21 and the bit lines 11 on the surface of the substrate 1 may overlap.

[0158] In practical applications, the contact plugs 14 are typically located within the gaps formed between the vertically intersecting word lines 18 and bit lines 11. In this embodiment, the projections of the contact pads 21 and bit lines 11 onto the surface of the substrate 1 overlap, and the contact pads 21 and contact plugs 14 are not completely aligned; rather, the contact pads 21 are offset relative to the contact plugs 14. Thus, the capacitors corresponding to the contact pads 21 do not need to be directly opposite the contact plugs 14, which increases the capacitor density.

[0159] The method for fabricating the semiconductor structure 100 provided in this embodiment involves sequentially forming a conductive layer 2 and a first sacrificial layer 3 on a substrate 1. Multiple sets of intersecting first trenches 3a and second trenches 3b are formed on the first sacrificial layer 3 through two photolithography processes. Overlapping trenches 3c are formed at the overlapping positions of the first trenches 3a and the second trenches 3b. At least a portion of the first sacrificial layer 3 exposed in the overlapping trenches 3c is removed by etching to form contact holes 3d. Insulating pillars 3e are filled into the contact holes 3d. The conductive layer 2 is etched using the insulating pillars 3e as a mask to form contact pads 21. Specifically, by extending the first trench 3a along a first direction parallel to the bit line 11 in the substrate 1, and the second trench 3b along a second direction, with the second direction intersecting the first direction, an array of overlapping trenches 3c can be formed, thereby forming an array of contact holes 3d. By filling the contact holes 3d with insulating pillars 3e and using the self-aligned circular holes 3311 formed by the insulating pillars 3e, not only is the arrangement accuracy of the contact holes 3d and the circular holes 3311 improved, reducing the short-circuit risk of the subsequently formed contact pads, but the density of the contact pads and the density of the capacitors are also increased, thus increasing the data storage capacity of the DRAM. In addition, the staggered arrangement of the contact holes 3d and the circular holes 3311 facilitates the realization of the hexagonal stacking method of the capacitors, further increasing the stacking density of the capacitors.

[0160] Example 2

[0161] This embodiment provides a semiconductor structure 100, which is prepared using the preparation method of semiconductor structure 100 in Embodiment 1.

[0162] Specifically, the semiconductor structure 100 includes a substrate 1, which includes an active region 12 and a shallow trench isolation structure 13. Contact plugs 14 are provided on the surface of the active region 12, and bit lines 11 are provided between adjacent contact plugs 14. The bit lines 11 and contact plugs 14 are isolated by an insulating structure 15. Contact pads 21 are provided on the surface of the contact plugs 14, and each contact pad 21 corresponds to a contact plug 14. The contact pads 21 and contact plugs 14 are isolated by an isolation structure 17. Additionally, the semiconductor structure 100 may also include a capacitor located above the substrate 1, with the capacitor and contact pads 21 connected in a corresponding manner.

[0163] In this embodiment, the contact pad 21 is formed by etching the conductive layer 2 on the substrate 1. Specifically, a first sacrificial layer 3 is formed on the conductive layer 2, and two intersecting first trenches 3a and second trenches 3b are formed on the first sacrificial layer 3 through two photolithography processes. The overlapping position of the first trenches 3a and the second trenches 3b forms an overlapping trench 3c. By etching the overlapping trench 3c, a portion of the contact pad 21 is finally formed on the conductive layer 2. Furthermore, by filling the contact hole 3d with insulating pillars 3e and using the self-aligned circular holes 3311 formed by the insulating pillars 3e, not only is the arrangement accuracy of the contact hole 3d and the circular holes 3311 improved, reducing the short-circuit risk of the subsequently formed contact pads, but the density of the contact pads and the density of the capacitors are also increased, thereby increasing the data storage capacity of the DRAM. In addition, the staggered arrangement of the contact hole 3d and the circular holes 3311 is conducive to the realization of the hexagonal stacking method of the capacitors, further increasing the stacking density of the capacitors.

[0164] Furthermore, the extension direction of the first trench 3a is the same as the extension direction of the bit line 11 in the substrate 1, which can improve the positioning accuracy of the contact pad 21. In some embodiments, the extension direction of the second trench 3b can be perpendicular to the extension direction of the bit line 11. For example, the extension direction of the second trench 3b is the same as the extension direction of the word line 18, to further improve the positional accuracy of the contact pad 21. Thus, the positional accuracy of the capacitor is improved.

[0165] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0166] In the description of this application, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.

[0167] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the connection within two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0168] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a plurality of bit lines are arranged at intervals and parallel to each other, the bit lines extending along a first direction; A conductive layer and a first sacrificial layer are sequentially formed on the substrate; Multiple sets of intersecting first trenches and second trenches are formed on the first sacrificial layer through two photolithography processes, and the overlapping positions of the first trenches and the second trenches form overlapping trenches; wherein, the first trenches extend along the first direction, and the second trenches extend along the second direction; Remove at least part of the first sacrificial layer exposed in the overlapping trench to form a contact hole; An insulating pillar is filled into the contact hole, and the conductive layer is etched using the insulating pillar as a mask to form a contact pad.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second direction is perpendicular to the first direction.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of forming multiple sets of interlocking first and second trenches on the first sacrificial layer through two photolithography processes specifically includes: A first mask layer is formed on the first sacrificial layer, and the first sacrificial layer is removed along the first mask layer to form a plurality of the first trenches; A second sacrificial layer is formed on the first sacrificial layer, and the second sacrificial layer partially fills the first trench; A second mask layer is formed on the second sacrificial layer, and the second sacrificial layer is removed along the second mask layer to form a plurality of second trenches; wherein the opening of the second trench is flush with the opening of the first trench.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The formation of a conductive layer and a first sacrificial layer sequentially on the substrate specifically includes: A conductive layer is formed on the substrate; At least one dielectric layer is formed on the conductive layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The formation of at least one dielectric layer on the conductive layer specifically includes: A first dielectric layer is formed on the conductive layer; A second dielectric layer is formed on the first dielectric layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The step of forming a first mask layer on the first sacrificial layer and removing the first sacrificial layer along the first mask layer specifically includes: A first mask layer is formed on the second dielectric layer; wherein the first mask layer has a plurality of first mask openings extending along the first direction, and the plurality of first mask openings are spaced apart along a direction perpendicular to the first direction; The second dielectric layer is removed along the opening of the first mask, exposing a portion of the surface of the first dielectric layer.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, The formation of the first dielectric layer on the conductive layer specifically includes: A first oxide layer and a first barrier layer are sequentially formed on the conductive layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming a second dielectric layer on the first dielectric layer specifically includes: A second oxide layer and a second barrier layer are sequentially formed on the first barrier layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, Both the first barrier layer and the second barrier layer include a stacked hard mask layer and an anti-reflective layer.

10. The method for preparing a semiconductor structure according to any one of claims 3-9, characterized in that, The step of forming a second mask layer on the second sacrificial layer and removing the second sacrificial layer along the second mask layer specifically includes: A second mask layer is formed on the second sacrificial layer; wherein the second mask layer has a plurality of second mask openings extending in a direction perpendicular to the first direction, and the plurality of second mask openings are spaced apart along the first direction; The second sacrificial layer is removed along the opening of the second mask, exposing the first trench.

11. The method for preparing a semiconductor structure according to any one of claims 3-9, characterized in that, The process of forming a second sacrificial layer on the first sacrificial layer, wherein the second sacrificial layer partially fills the first trench, specifically includes: A third hard mask layer is formed on the first sacrificial layer, and the third hard mask layer partially fills the first trench; A third anti-reflective layer is formed on the third hard mask layer.

12. The method for preparing a semiconductor structure according to any one of claims 1-9, characterized in that, The step of filling the contact hole with insulating pillars and using the insulating pillars as a mask to etch the conductive layer to form a contact pad specifically includes: Remove a portion of the first sacrificial layer, exposing a portion of the insulating pillar; A protective layer is formed to enclose the insulating pillars, and the protective layer has small holes spaced between the insulating pillars; The insulating column is filled into the small hole; The first sacrificial layer and the conductive layer exposed outside the insulating pillar are etched away to form a contact pad.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Before filling the small hole with the insulating post, the method further includes: The protective layer and the insulating pillar are etched down to form a circular hole; The insulating post is filled into the circular hole.

14. The method for preparing a semiconductor structure according to claim 12, characterized in that, The protective layer forming the insulating pillar specifically includes: The protective layer is deposited using atomic layer deposition (ALD).

15. The method for preparing a semiconductor structure according to claim 12, characterized in that, The removal of a portion of the first sacrificial layer, exposing the portion of the insulating pillar, specifically includes: The first sacrificial layer, which is 1 / 5 to 1 / 4 thick, is removed by etching.

16. The method for preparing a semiconductor structure according to claim 12, characterized in that, The projections of the contact pad and the bit line on the substrate surface overlap.

17. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method according to any one of claims 1-16.

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