A package structure of a semiconductor device and a packaging method

Abstract

The application discloses a packaging structure and a packaging method of a semiconductor device. The packaging structure comprises a driving module and a power module arranged oppositely. The power module comprises a first packaging substrate and a power unit arranged on a side of the first packaging substrate facing the driving module. The driving module comprises a second packaging substrate and a driving unit arranged on a side of the second packaging substrate facing away from the power module. The second packaging substrate is provided with a connecting circuit which is used for connecting the power unit and the driving unit through a through hole penetrating the second packaging substrate. The packaging structure reduces the loop parasitic inductance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and more particularly to a packaging structure and a packaging method of a semiconductor device. BACKGROUND

[0002] With the continuous progress of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work and becomes an indispensable important tool for people today. The main component of electronic devices to realize various functions is chip. In order to ensure the reliability and service life of the chip and avoid damage from external factors, the chip needs to be packaged and protected.

[0003] In the field of semiconductor devices, power units have always been the core of promoting the development of power electronics technology, and their performance determines the efficiency of electric energy conversion. The existing power units and their driving units are generally packaged separately to form two independent packaging structures, and then interconnected through a circuit board, which may result in a large loop parasitic inductance. SUMMARY

[0004] Therefore, the present application provides a packaging structure and a packaging method of a semiconductor device to reduce the loop parasitic inductance, and the scheme is as follows:

[0005] A packaging structure of a semiconductor device, the packaging structure comprising:

[0006] a driving module and a power module arranged oppositely;

[0007] the power module comprising a first packaging substrate and a power unit located on a side of the first packaging substrate facing the driving module;

[0008] the driving module comprising a second packaging substrate and a driving unit located on a side of the second packaging substrate facing away from the power module;

[0009] wherein the second packaging substrate has a connection circuit, and the connection circuit is used at least to connect the power unit and the driving unit through a via hole penetrating through the second packaging substrate.

[0010] Preferably, in the packaging structure, the power unit comprises a silicon carbide MOS power device, and the first packaging substrate is a first silicon carbide plate.

[0011] Preferably, in the packaging structure, the second packaging substrate comprises a sub-packaging substrate connected with the driving unit and a second silicon carbide plate located on a side of the sub-packaging substrate facing away from the driving unit.

[0012] Preferably, in the above packaging structure, the through-hole includes: a first through-hole penetrating the sub-package substrate and a second through-hole penetrating the second silicon carbide plate; the first through-hole and the second through-hole are disposed opposite to each other;

[0013] The connection circuit includes: a first rewiring layer located on the side of the sub-package substrate away from the driving unit; a second rewiring layer located on the side of the second silicon carbide plate facing the driving unit; a third rewiring layer located on the side of the second silicon carbide plate away from the driving unit; the first rewiring layer and the second rewiring layer are connected; the third rewiring layer is connected to the power unit;

[0014] The first redistribution layer is connected to the drive unit through the first via; the second redistribution layer and the third redistribution layer are connected through the second via.

[0015] Preferably, in the above packaging structure, a positive electrode connection component and a negative electrode connection component are provided between the first packaging substrate and the second packaging substrate;

[0016] The power unit is connected to the positive terminal connection component and the negative terminal connection component respectively, and the positive terminal connection component and the negative terminal connection component are connected to an external power source through the connection circuit.

[0017] Preferably, in the above-described packaging structure, the second packaging substrate has a positive terminal and a negative terminal on one side for arranging the driving unit.

[0018] The connection circuit connects the positive terminal and the positive terminal through the corresponding through hole, and connects the negative terminal and the negative terminal through the corresponding through hole. The positive terminal and the negative terminal are connected to the external power supply.

[0019] Preferably, in the above packaging structure, the power unit includes: a first power device and a second power device;

[0020] The drive unit includes: a first drive device connected to the first power device and a second drive device connected to the second power device.

[0021] Preferably, in the above packaging structure, both the first power device and the second power device include a first electrode, a second electrode, and a control terminal;

[0022] An output component is also provided between the first packaging substrate and the second packaging substrate, and the output component is connected to an external load through the connection circuit;

[0023] The first electrode of the first power device is connected to the positive electrode connection component; the second electrode of the second power device is connected to the negative electrode connection component; the second electrode of the first power device and the first electrode of the second power device are connected to the output component.

[0024] Preferably, in the above-described packaging structure, a heat-insulating medium is filled between the first packaging substrate and the second packaging substrate.

[0025] Preferably, in the above packaging structure, the surface of the first packaging substrate facing away from the power unit has a metal layer, and the metal layer is used to connect heat dissipation components.

[0026] The present invention also provides a method for packaging a semiconductor device, the packaging method comprising:

[0027] Fabrication of a power module; the power module includes a first packaging substrate and a power unit located on one side of the first packaging substrate;

[0028] A drive module is provided on one side of the power module having the power unit. The drive module includes a second packaging substrate and a drive unit located on the side of the second packaging substrate opposite to the power module.

[0029] The second packaging substrate has a connection circuit, which connects the power unit and the drive unit through a through-hole penetrating the second packaging substrate.

[0030] Preferably, in the above packaging method, the method for preparing the power module includes:

[0031] Provide the first packaging substrate;

[0032] A power unit, a positive electrode connection component, a negative electrode connection component, and an output component are disposed on the same side of the first packaging substrate, and the power unit is respectively connected to the positive electrode connection component, the negative electrode connection component, and the output component;

[0033] The positive terminal connection component and the negative terminal connection component are connected to an external power source through the connection circuit, and the output component is connected to an external load through the connection circuit.

[0034] Preferably, in the above encapsulation method, the driver module includes:

[0035] A second silicon carbide plate is disposed on one side of the power module having the power unit;

[0036] A sub-package substrate on the side of the second silicon carbide plate away from the power module is provided with the drive unit bonded thereon; the drive unit is located on the side of the sub-package substrate away from the second silicon carbide plate.

[0037] As described above, in the semiconductor device packaging structure and packaging method provided by the present invention, the power unit and the driving unit are connected through the connection circuit, and the connection circuit passes through a through-hole in the second packaging substrate. For the packaging structure, the loop between the power unit and the driving unit is much shorter than the corresponding loop in existing packaging structures, reducing parasitic inductance. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0040] Figure 1 This is a schematic diagram of a semiconductor device packaging structure provided in an embodiment of the present invention;

[0041] Figure 2 An equivalent circuit diagram of a semiconductor device provided in an embodiment of the present invention;

[0042] Figures 3-7 This is a flowchart illustrating an encapsulation method provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Reference Figure 1 ,Figure 1 This is a schematic diagram of a semiconductor device packaging structure provided in an embodiment of the present invention. The packaging structure includes:

[0046] The drive module and power module are configured relative to each other.

[0047] The power module includes a first packaging substrate 3 and a power unit 1 located on the side of the first packaging substrate 3 facing the drive module.

[0048] The drive module includes a second packaging substrate 4 and a drive unit 2 located on the side of the second packaging substrate 4 opposite to the power module.

[0049] The second packaging substrate 4 has a connection circuit, which is used at least to connect the power unit 1 and the drive unit 2 through a through hole penetrating the second packaging substrate 4.

[0050] In terms of the packaging structure, the power unit 1 and the driving unit 2 are connected through the connection circuit, which passes through a through-hole in the second packaging substrate 4. This shortens the loop distance between the driving unit 2 and the power unit 1, reduces the parasitic loop inductance between them, and thus improves the switching speed of the semiconductor device, thereby reducing switching losses. Furthermore, in the above packaging structure, the power unit 1 and the driving unit 2 are stacked and packaged through the first packaging substrate 3 and the second packaging substrate 4, achieving three-dimensional high-density packaging of the semiconductor device, improving integration, and reducing the area of ​​the packaging structure.

[0051] The power unit 1 includes a silicon carbide MOS power device; the first packaging substrate 3 is a first silicon carbide plate.

[0052] Since both the silicon carbide power device substrate and the first silicon carbide plate contain silicon carbide substrate, and their coefficients of thermal expansion are the same, the thermomechanical stress between them is reduced, avoiding problems such as warping of the MOS power device due to mechanical stress when the two are connected and fixed, thus ensuring the reliability of the connection.

[0053] Meanwhile, the silicon carbide plate has a high heat dissipation coefficient, and the main heat in the power unit 1 is discharged through the first silicon carbide plate, which improves the heat dissipation efficiency of the power unit 1.

[0054] The second packaging substrate 4 includes: a sub-packaging substrate 41 connected to the driving unit 2; and a second silicon carbide plate 42 located on the side of the sub-packaging substrate 41 opposite to the driving unit 2.

[0055] A small portion of the heat from the power unit 1 can be transferred to the second packaging substrate 4 through the metal connection structure between the power unit 1 and the drive unit 2. The second silicon carbide plate 42, which has good heat dissipation performance, can dissipate this heat as quickly as possible, thus avoiding any impact on the drive unit 2 and ensuring its normal operation.

[0056] Meanwhile, the second silicon carbide plate 42 has good insulation properties, ensuring the safe operation of the drive unit 2, the power unit 1, and related circuits.

[0057] The through-hole includes a first through-hole 411 penetrating the sub-package substrate 41 and a second through-hole 421 penetrating the second silicon carbide plate 42; the first through-hole 411 and the second through-hole 421 are disposed opposite to each other.

[0058] like Figure 1 As shown, the connection circuit connects the drive unit 2 and the power unit 1 through the first through hole 411 and the second through hole 421. The axis of the first through hole 411 and the axis of the second through hole 421 are on the same straight line, which shortens the length of the loop between the drive unit 2 and the power unit 1 and reduces the parasitic inductance of the loop.

[0059] The connection circuit includes: a first redistribution layer 51 located on the side of the sub-package substrate 41 away from the driving unit 2; a second redistribution layer 52 located on the side of the second silicon carbide plate 42 facing the driving unit 2; a third redistribution layer 53 located on the side of the second silicon carbide plate 42 away from the driving unit 2; the first redistribution layer 51 and the second redistribution layer 52 are connected; and the third redistribution layer 53 is connected to the power unit 1.

[0060] The first redistribution layer 51 and the second redistribution layer 52 have solder balls 7 for connecting the first redistribution layer 51 and the second redistribution layer 52.

[0061] The first redistribution layer 51 is connected to the drive unit 2 through the first through-hole 411; the second redistribution layer 52 and the third redistribution layer 53 are connected through the second through-hole 421.

[0062] By setting up the first redistribution layer 51, the second redistribution layer 52, and the third redistribution layer 53, the power unit 1 and the driving unit 2 are stacked and packaged, reducing the packaging area of ​​the semiconductor device, optimizing the circuit connection, and reducing the inductance between the circuits.

[0063] The first packaging substrate 3 and the second packaging substrate 4 have a positive electrode connection component 61 and a negative electrode connection component 63.

[0064] The power unit 1 is connected to the positive terminal connection component 61 and the negative terminal connection component 63 respectively. The positive terminal connection component 61 and the negative terminal connection component 63 are connected to an external power source through the connection circuit.

[0065] The second packaging substrate 4 is used to set the driving unit 2 on one side, which also has a positive terminal and a negative terminal.

[0066] The connection circuit connects the positive terminal connection component 61 and the positive terminal connection end through the corresponding through holes, and connects the negative terminal connection component 63 and the negative terminal connection end through the corresponding through holes. The positive terminal connection end and the negative terminal connection end are connected to the external power supply.

[0067] The power unit 1 includes: a first power device 11 and a second power device 12.

[0068] The drive unit 2 includes a first drive device 21 connected to the first power device 11 and a second drive device 22 connected to the second power device 12.

[0069] Both the first power device 11 and the second power device 12 include a first electrode, a second electrode, and a control terminal.

[0070] An output component 62 is also provided between the first packaging substrate 3 and the second packaging substrate 4, and the output component 62 is connected to an external load through the connection circuit.

[0071] The first electrode of the first power device 11 is connected to the positive electrode connection component 61; the second electrode of the second power device 12 is connected to the negative electrode connection component 63; the second electrode of the first power device 11 and the first electrode of the second power device 12 are connected to the output component 62.

[0072] Wherein, the first power device 11 and the second power device 12 are both silicon carbide MOS power devices. The first power device 11 is a first silicon carbide MOS power device, and the second power device 12 is a second silicon carbide MOS power device; when the first power device 11 and the second power device 12 are MOS power devices, the first electrode is the drain of the MOS power device, the second electrode is the source of the MOS power device, and the control terminal is the gate of the MOS power device.

[0073] The first silicon carbide MOS power device includes a first source 111, a first drain 112, and a first gate 113; the second silicon carbide MOS power device includes a second source 121, a second drain 122, and a second gate 123.

[0074] The first source 111 and the first gate 113 are located on the surface of the first silicon carbide MOS power device away from the first packaging substrate 3, and the first drain 112 is located on the surface of the first silicon carbide MOS power device facing the first packaging substrate 3; the first drain 112 is fixedly connected to the first packaging substrate 3.

[0075] The second source 121 and the second gate 123 are located on the surface of the second silicon carbide MOS power device away from the first packaging substrate 3, and the second drain 122 is located on the surface of the second silicon carbide MOS power device facing the first packaging substrate 3; the second drain 122 is fixedly connected to the first packaging substrate 3.

[0076] The second source 121 is connected to the negative terminal connection component 63; the first drain 112 is connected to the positive terminal connection component 61; the first source 111 and the second drain 122 are connected to the output component 62.

[0077] The first gate 113 is connected to the first driving device 21 through the connection circuit, and the second gate 123 is connected to the second driving device 22 through the connection circuit.

[0078] The positive electrode connection component 61, the negative electrode connection component 63, and the output component 62 are all copper pillars. The copper pillars are located on the surface of the first packaging substrate 3 and are fixedly connected to the second packaging substrate 4.

[0079] The copper pillars not only connect the circuitry but also support the second packaging substrate 4, increasing the stability of the packaging structure. In addition to the copper pillars, a retaining ring can be added to support the second packaging substrate 4 and further enhance stability.

[0080] A thermally insulating medium is filled between the first packaging substrate 3 and the second packaging substrate 4, forming a temperature gradient from the second packaging substrate 4 to the first packaging substrate 3. The temperature gradient increases sequentially from the second packaging substrate 4 to the first packaging substrate 3. Simultaneously, the thermally insulating medium isolates heat transfer between power devices, ensuring normal device operation.

[0081] The first packaging substrate 3 has a metal layer 9 on the surface opposite to the power unit 1, and the metal layer 9 is used to connect heat dissipation components. Connecting heat dissipation components further improves the heat dissipation efficiency of the semiconductor device.

[0082] Reference Figure 2 , Figure 2 This is an equivalent circuit diagram of a semiconductor device provided in an embodiment of the present invention, for comparison. Figure 1In the figure, MOSFET Q H Equivalent to the first power device 11 mentioned above, MOSFET Q L Equivalent to the second power device 12, R GH R is the gate drive resistor of the first power device 11 mentioned above. GL The gate drive resistor of the second power device 12 is defined as follows: DC+ is the positive terminal, DC- is the negative terminal, M is the external load, Hdriver IC is the first driver device 21, Ldriver IC is the second driver device 22, and the two diodes are the body diodes of the first power device 11 and the second power device 12, respectively.

[0083] The MOS transistor Q described in the prior art H The circuit between the Hdriver IC and the MOS transistor Q L The loop between the circuit and the Ldriver IC is relatively long, resulting in a significant parasitic inductance. The embodiment provided by this invention shortens the length of the MOS transistor Q by modifying the chip packaging structure. H The circuit between the Hdriver IC and the MOS transistor Q L The loop between the circuit and the LdriverIC reduces the parasitic inductance of the loop.

[0084] Based on the above embodiments, another embodiment of the present invention provides a packaging method for packaging the packaging structure described in the above embodiments, the packaging method being as follows: Figures 3-7 As shown, Figures 3-7 A flowchart illustrating a packaging method provided in an embodiment of the present invention includes:

[0085] Step 1: Fabricating a power module; the power module includes a first packaging substrate 3 and a power unit 1 located on one side of the first packaging substrate 3; wherein, the method for fabricating the power module includes:

[0086] Step 1.1: Provide a first packaging substrate 3, the first packaging substrate 3 having interconnect circuitry.

[0087] Step 1.2: As Figure 3 As shown, a power unit 1, a positive electrode connection component 61, a negative electrode connection component 63, and an output component 62 are disposed on the same side of the first packaging substrate 3. The power unit 1 is connected to the positive electrode connection component 61, the negative electrode connection component 63, and the output component 62 respectively. The positive electrode connection component 61 and the negative electrode connection component 63 are connected to an external power supply through the connection circuit, and the output component 62 is connected to an external load through the connection circuit.

[0088] The positive electrode connection component 61, the negative electrode connection component 63, and the output component 62 are all copper pillars, which are sintered onto the surface of the first packaging substrate 3 using nano-silver sintering technology.

[0089] The power unit 1 includes: a first power device 11 and a second power device 12; the first power device 11 includes a first silicon carbide MOS power device, and the second power device 12 includes a second silicon carbide MOS power device.

[0090] The first silicon carbide MOS power device includes a first source 111, a first drain 112, and a first gate 113; the second silicon carbide MOS power device includes a second source 121, a second drain 122, and a second gate 123.

[0091] The first source 111 and the first gate 113 are located on the surface of the first silicon carbide MOS power device away from the first packaging substrate 3, and the first drain 112 is located on the surface of the first silicon carbide MOS power device facing the first packaging substrate 3.

[0092] The second source 121 and the second gate 123 are located on the surface of the second silicon carbide MOS power device away from the first packaging substrate 3, and the second drain 122 is located on the surface of the second silicon carbide MOS power device facing the first packaging substrate 3.

[0093] The first silicon carbide MOS power device and the second silicon carbide power device are disposed on the same side of the first packaging substrate 3 where the positive electrode connection component 61, the negative electrode connection component 63 and the output component 62 are disposed by flip-chip bonding. The specific method includes: firstly performing surface metallization treatment on the surface where the first drain 112 is located and the surface where the second drain 122 is located, and then sintering the surface metallized surface onto one side of the first packaging substrate 3 by nano-silver sintering technology.

[0094] The positive terminal connection component 61 is connected to the first drain 112 through the interconnection circuit, and the output component 62 is connected to the second drain 122 through the interconnection circuit.

[0095] Step 2: A drive module is provided on the side of the power module having the power unit 1. The drive module includes a second packaging substrate 4 and a drive unit 2 located on the side of the second packaging substrate 4 away from the power module.

[0096] The second packaging substrate 4 has a connection circuit, which can connect the power unit 1 and the drive unit 2 through a through hole penetrating the second packaging substrate 4.

[0097] The driving module includes: a second silicon carbide plate 42 disposed on the side of the power module having the power unit 1; a sub-package substrate 41 on the side of the second silicon carbide plate 42 opposite to the power module, on which the driving unit 2 is bonded; the driving unit 2 is located on the side of the sub-package substrate 41 opposite to the second silicon carbide plate 42.

[0098] The specific steps for manufacturing the drive module and setting the drive module on one side of the power module include:

[0099] Step 2.1: As Figure 4 As shown, the second packaging substrate 4 is etched with through holes using deep reactive ion etching, and then the through holes are filled with copper by electroplating to form solid through holes.

[0100] The second packaging substrate 4 includes a sub-packaging substrate 41 and a second silicon carbide plate 42. When drilling holes in the second packaging substrate 4, through holes can be integrally etched into the sub-packaging substrate 41 and the second silicon carbide plate 42, ensuring that the axis of the first through hole 411 of the sub-packaging substrate 41 and the axis of the second through hole 421 of the second silicon carbide plate 42 are on the same straight line after etching. This method only requires drilling once, avoiding separate drilling of the sub-packaging substrate 41 and the second silicon carbide plate 42, thus reducing process steps. Alternatively, through holes can be etched separately at corresponding positions on the sub-packaging substrate 41 and the second silicon carbide plate 42. This separate etching of through holes results in a shallower etching depth and less process difficulty compared to integral etching of through holes on both plates.

[0101] Step 2.2: As Figure 5 As shown, an electroplating technique is used to form a first redistribution layer 51 on the side of the sub-package substrate 41 away from the driving unit 2, a second redistribution layer 52 on the side of the second silicon carbide plate 42 facing the driving unit 2, and a third redistribution layer 53 on the side of the second silicon carbide plate 42 away from the driving unit 2.

[0102] Step 2.3: As Figure 6 As shown, the driving unit 2 and the sub-package substrate 41 are integrated into a system in-package (SIP) using a ball grid array (BGA) package.

[0103] Step 2.4: As Figure 7 As shown, the second silicon carbide plate 42 is connected and fixed to the first silicon carbide MOS power device, the second silicon carbide MOS power device, the output component 62, the positive electrode connection component 61 and the negative electrode connection component 63, and a high-temperature heat insulation medium 8 is filled between the second silicon carbide plate 42 and the first packaging substrate 3.

[0104] The output component 62, the positive electrode connection component 61, and the negative electrode connection component 63 are respectively connected to the corresponding third redistribution layer 53 through a nano-silver sintering process; the first source 111, the first drain 112, the second source 121, and the second drain 122 are respectively connected to the corresponding third redistribution layer 53 after surface metallization treatment through a nano-silver sintering process.

[0105] The negative terminal connection component 63 is connected to the second source 121 through the third redistribution layer 53; the output component 62 is connected to the first source 111 through the third redistribution layer 53, thereby realizing the interconnection between the first source 111 and the second drain 122.

[0106] Step 2.5: Microbump pads and solder balls 7 are fabricated on the side of the sub-package substrate 41 facing away from the driving unit 2 and the side of the second silicon carbide plate 42 facing the driving unit 2, respectively. The sub-package substrate 41 and the second silicon carbide plate 42 are then flip-chip interconnected via the solder balls 7 and the microbump pads to form a structure as shown in the figure. Figure 1 The packaging structure shown.

[0107] The packaging structure and method provided in this embodiment of the invention shorten the loop distance between the drive unit 2 and the power unit 1, reduce the parasitic inductance of the loop, improve the switching speed of the power device, and thus reduce switching losses, enabling the power device to achieve high-frequency applications. Simultaneously, this packaging structure achieves vertical interconnection between the drive unit 2 and the power unit 1, reducing the packaging area and achieving high-density packaging. Furthermore, this packaging structure uses a first silicon carbide plate and a second silicon carbide plate 42 with the same coefficient of thermal expansion as the silicon carbide power device, reducing thermomechanical stress and improving the heat dissipation efficiency of the semiconductor device. A high-temperature insulating medium 8 is filled between the first silicon carbide plate and the second silicon carbide plate 42, forming a temperature gradient from top to bottom. Moreover, due to the good insulation properties of the second silicon carbide substrate 42, good isolation is achieved between the high-voltage device below it (including the power unit 1) and the low-voltage device above it (including the drive unit 2 and the circuitry on the second packaging substrate 4), i.e., high-low voltage isolation is achieved, further improving the heat dissipation efficiency of the semiconductor device.

[0108] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0109] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0110] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0111] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging structure for a semiconductor device, characterized in that, include: The drive module and power module are configured relative to each other; The power module includes a first packaging substrate and a power unit located on the side of the first packaging substrate facing the drive module. The drive module includes a second packaging substrate and a drive unit located on the side of the second packaging substrate opposite to the power module. The second packaging substrate has a connection circuit, which is at least used to connect the power unit and the drive unit through a through-hole penetrating the second packaging substrate. The second packaging substrate includes: a sub-packaging substrate connected to the driving unit; a second silicon carbide plate located on the side of the sub-packaging substrate opposite to the driving unit; the through hole includes: a first through hole penetrating the sub-packaging substrate and a second through hole penetrating the second silicon carbide plate; the first through hole and the second through hole are disposed opposite to each other.

2. The packaging structure according to claim 1, characterized in that, The power unit includes a silicon carbide MOS power device; the first packaging substrate is a first silicon carbide plate.

3. The packaging structure according to claim 1, characterized in that, The connection circuit includes: a first rewiring layer located on the side of the sub-package substrate away from the driving unit; a second rewiring layer located on the side of the second silicon carbide plate facing the driving unit; a third rewiring layer located on the side of the second silicon carbide plate away from the driving unit; the first rewiring layer and the second rewiring layer are connected; the third rewiring layer is connected to the power unit; The first redistribution layer is connected to the drive unit through the first via; the second redistribution layer and the third redistribution layer are connected through the second via.

4. The packaging structure according to claim 1, characterized in that, The first packaging substrate and the second packaging substrate have a positive electrode connection component and a negative electrode connection component; The power unit is connected to the positive terminal connection component and the negative terminal connection component respectively, and the positive terminal connection component and the negative terminal connection component are connected to an external power source through the connection circuit.

5. The packaging structure according to claim 4, characterized in that, The second packaging substrate is used to set the driving unit on one side, which also has a positive terminal and a negative terminal. The connection circuit connects the positive terminal and the positive terminal through the corresponding through hole, and connects the negative terminal and the negative terminal through the corresponding through hole. The positive terminal and the negative terminal are connected to the external power supply.

6. The packaging structure according to claim 4, characterized in that, The power unit includes: a first power device and a second power device; The drive unit includes: a first drive device connected to the first power device and a second drive device connected to the second power device.

7. The packaging structure according to claim 6, characterized in that, Both the first power device and the second power device include a first electrode, a second electrode, and a control terminal; An output component is also provided between the first packaging substrate and the second packaging substrate, and the output component is connected to an external load through the connection circuit; The first electrode of the first power device is connected to the positive electrode connection component; the second electrode of the second power device is connected to the negative electrode connection component; the second electrode of the first power device and the first electrode of the second power device are connected to the output component.

8. The packaging structure according to claim 1, characterized in that, A heat-insulating medium is filled between the first packaging substrate and the second packaging substrate.

9. The packaging structure according to claim 1, characterized in that, The first packaging substrate has a metal layer on the surface opposite to the power unit, and the metal layer is used to connect heat dissipation components.

10. A packaging method, characterized in that, The encapsulation method includes: Fabrication of a power module; the power module includes a first packaging substrate and a power unit located on one side of the first packaging substrate; A drive module is provided on one side of the power module having the power unit. The drive module includes a second packaging substrate and a drive unit located on the side of the second packaging substrate opposite to the power module. The second packaging substrate has a connection circuit, which can connect the power unit and the drive unit through a through hole penetrating the second packaging substrate. The driving module includes: a second silicon carbide plate disposed on one side of the power module having the power unit; a sub-package substrate on the side of the second silicon carbide plate opposite to the power module to which the driving unit is bonded; the driving unit is located on the side of the sub-package substrate opposite to the second silicon carbide plate; the through hole includes: a first through hole penetrating the sub-package substrate and a second through hole penetrating the second silicon carbide plate; the first through hole and the second through hole are disposed opposite to each other.

11. The packaging method according to claim 10, characterized in that, The method for preparing the power module includes: Provide the first packaging substrate; A power unit, a positive electrode connection component, a negative electrode connection component, and an output component are disposed on the same side of the first packaging substrate, and the power unit is respectively connected to the positive electrode connection component, the negative electrode connection component, and the output component; The positive terminal connection component and the negative terminal connection component are connected to an external power source through the connection circuit, and the output component is connected to an external load through the connection circuit.

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