Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same, wherein the semiconductor device comprises a first substrate; a first device located on the first substrate; a first dielectric layer and a first conductive plug located on the first device; a first metal layer located on the first dielectric layer and the first conductive plug, a first dielectric layer located on the surface of the first metal layer, a first ferroelectric insulating layer located on the surface of the first dielectric layer, and a second metal layer located on the surface of the first ferroelectric insulating layer; a negative capacitor is formed between two conductor layers (the first metal layer and the second metal layer) by using the ferroelectric insulating layer, and a positive capacitor can be formed between the two conductor layers (the first metal layer and the second metal layer) due to the presence of the first dielectric layer, and the capacitance density finally formed is improved by matching the positive and negative capacitances, thereby reducing the risk of leakage of the finally formed semiconductor device and greatly improving the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of wireless communications, the requirements for integrated capacitors in mixed signal chips, chip systems (Soc) and radio frequency circuits (RF) are becoming increasingly higher.

[0003] Capacitor components are often used as electronic passive devices in integrated circuits such as radio frequency ICs and monolithic microwave ICs. In traditional semiconductor manufacturing processes, common capacitor components include metal oxide semiconductor (MOS) capacitors, PN junction capacitors, and MIM (Metal-Insulation-Metal) capacitors. Among them, MIM capacitors can provide electrical properties that are superior to MOS capacitors or PN junction capacitors in some special applications. This is because MOS capacitors and PN junction capacitors are limited by their own structures, and the electrodes are prone to produce hole layers during operation, resulting in reduced frequency characteristics. MIM capacitors can provide better frequency and temperature-related characteristics.

[0004] However, as the size of devices decreases, the usable area becomes smaller and smaller. Therefore, it is necessary to achieve sufficient capacitance in a limited usable area while ensuring the reliability of the formed capacitance. This is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, thereby ensuring that the formed semiconductor device has higher quality and reliability.

[0006] To solve the above problems, the present invention provides a semiconductor device, comprising: a first substrate; a first device located on the first substrate; a first dielectric layer and a first conductive plug located on the first device; a first metal layer located on the first dielectric layer and the first conductive plug; a first dielectric layer located on the surface of the first metal layer; a first ferroelectric insulating layer located on the surface of the first dielectric layer; and a second metal layer located on the surface of the first ferroelectric insulating layer.

[0007] Optionally, it also includes: a third metal layer, wherein the third metal layer is located between the first dielectric layer and the first ferroelectric insulating layer.

[0008] Optionally, the sum of the thickness of the first ferroelectric insulating layer and the thickness of the first dielectric layer is 5 nanometers to 30 nanometers.

[0009] Optionally, the material of the first ferroelectric insulating layer is HfO2 or HfZrO.

[0010] The present invention also provides a semiconductor device, comprising: a second substrate; a second device located on the second substrate; a second dielectric layer and a second conductive plug located on the second device; a fourth metal layer located on the second dielectric layer and the second conductive plug; a second dielectric layer and a second ferroelectric insulating layer located on the surface of the fourth metal layer, the second dielectric layer and the second ferroelectric insulating layer being located on the same surface of the fourth metal layer and not in contact with each other; a fifth metal layer located on the surface of the second dielectric layer; and a sixth metal layer located on the surface of the second ferroelectric insulating layer.

[0011] Optionally, the material of the second ferroelectric insulating layer is HfO2 or HfZrO.

[0012] Optionally, the sum of the thickness of the second ferroelectric insulating layer and the thickness of the second dielectric layer is 5 nanometers to 30 nanometers.

[0013] The present invention provides a method for forming a semiconductor device, comprising: providing an initial first metal layer; forming an initial first dielectric layer on the initial first metal layer; forming an initial first ferroelectric insulating layer on the initial first dielectric layer; forming an initial second metal layer on the initial first ferroelectric insulating layer; forming a first patterned layer on the initial second metal layer; using the first patterned layer as a mask, sequentially etching the initial second metal layer, the initial first ferroelectric insulating layer and the initial first dielectric layer, and sequentially forming a first dielectric layer, a first ferroelectric insulating layer and a second metal layer on the surface of the initial first metal layer; forming a second patterned layer after forming the first dielectric layer, the first ferroelectric insulating layer and the second metal layer; using the second patterned layer as a mask, etching the initial first metal layer to form a first metal layer.

[0014] Optionally, after forming the initial first ferroelectric insulating layer and before forming the initial second metal layer, the method further includes: performing heat treatment.

[0015] Optionally, after forming the initial second metal layer and before forming the first patterned layer, the method further includes forming a first protective layer on the initial second metal layer.

[0016] Optionally, after forming the first dielectric layer, the first ferroelectric insulating layer and the second metal layer, and before forming the second patterned layer, it also includes forming a second protective layer on the first protective layer, the side wall of the second metal layer, the side wall of the first ferroelectric insulating layer and the side wall of the first dielectric layer.

[0017] Optionally, after forming an initial first dielectric layer on the initial first metal layer and before forming the initial first ferroelectric insulating layer, it also includes: forming an initial third metal layer on the initial first dielectric layer, using the first patterned layer as a mask, sequentially etching the initial second metal layer, the initial first ferroelectric insulating layer, the initial third metal layer and the initial first dielectric layer, and sequentially forming a first dielectric layer, a first ferroelectric insulating layer, a third metal layer and a second metal layer on the surface of the initial first metal layer.

[0018] Optionally, before providing the initial first metal layer, the method further includes providing a first substrate, forming a first device on the first substrate, and forming a first dielectric layer and a first conductive plug on the first device.

[0019] The present invention also provides a method for forming a semiconductor device, comprising: providing an initial fourth metal layer; forming an initial second dielectric layer on the initial fourth metal layer; forming an initial fifth metal layer on the initial second dielectric layer; forming a third patterned layer on the initial fifth metal layer; using the third patterned layer as a mask, sequentially etching the initial fifth metal layer, the initial second dielectric layer to form a fifth metal layer, and the second dielectric layer to expose a portion of the surface of the initial fourth metal layer; forming an initial second ferroelectric insulating layer on the exposed surface of the initial fourth metal layer; forming an initial sixth metal layer on the initial second ferroelectric insulating layer; forming a fourth patterned layer on the initial sixth metal layer; using the fourth patterned layer as a mask, etching the initial sixth metal layer and the initial second ferroelectric insulating layer to form a sixth metal layer and a second ferroelectric insulating layer; removing the fourth patterned layer to form a fifth patterned layer on the sixth metal layer and the fifth metal layer; using the fifth patterned layer as a mask, etching the initial fourth metal layer to form a fourth metal layer.

[0020] Optionally, after forming the initial second ferroelectric insulating layer and before forming the initial sixth metal layer on the initial second ferroelectric insulating layer, the method further includes performing a heat treatment.

[0021] Optionally, after forming the initial fifth metal layer and before forming the third patterned layer, the method further includes: forming a third protective layer on the initial fifth metal layer.

[0022] Optionally, after forming the initial sixth metal layer and before forming the fourth patterned layer, the method further includes: forming a fourth protective layer on the initial sixth metal layer.

[0023] Optionally, after forming the sixth metal layer and the second ferroelectric insulating layer and before forming the fifth patterned layer, the method further includes: forming a fifth protective layer on the third protective layer and the fourth protective layer.

[0024] Optionally, before providing the initial fourth metal layer, the method further includes providing a second substrate, forming a second device on the second substrate, and forming a second dielectric layer and a second conductive plug on the second device.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] The first ferroelectric insulating layer is introduced into the semiconductor device of the present invention. Due to the existence of the ferroelectric insulating layer, a negative capacitor is formed between the two conductor layers (the first metal layer and the second metal layer), and due to the existence of the first dielectric layer, a positive capacitor can be formed between the two conductor layers (the first metal layer and the second metal layer). In the structure where the positive and negative capacitors are matched, the relationship between the positive capacitor and the negative capacitor satisfies: (where C represents the final capacitance value; C1 represents one of the capacitance values; C2 represents the other capacitance value). When positive capacitance and negative capacitance exist at the same time, Infinitely small, so C is infinitely large, which increases the final capacitance density, reduces the risk of leakage, improves the reliability of semiconductor devices, and expands the scope of use of semiconductor devices.

[0027] In the formation method of the present invention, a first ferroelectric insulating layer is formed between two metal layers. On the one hand, the ferroelectric insulating layer can be used to form a negative capacitor between the two conductors (the first metal layer and the second metal layer). Due to the existence of the first dielectric layer, a positive capacitor can be formed between the two conductors (the first metal layer and the second metal layer). By matching the positive and negative capacitors, the capacitance density finally formed is improved. On the other hand, based on the introduction of the first ferroelectric insulating layer, there is no need to additionally change the thickness of the first dielectric layer, which reduces the process difficulty and does not cause defects such as leakage current due to the thin thickness of the first dielectric layer. The risk of leakage of the finally formed semiconductor device is reduced, and the reliability of the semiconductor device is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a semiconductor device in one embodiment;

[0029] Figures 2 to 12 is a structural schematic diagram of a semiconductor device forming process in a first embodiment of the present invention;

[0030] Figure 13 to Figure 14 is a schematic structural diagram of a semiconductor device forming process according to a second embodiment of the present invention;

[0031] Figures 15 to 19 It is a structural schematic diagram of the semiconductor device forming process in the third embodiment of the present invention. DETAILED DESCRIPTION

[0032] The conventional structure of MIM (Metal-Insulation-Metal) capacitors is to form a dielectric layer between two metal layers, and the metal layer serves as an electrode to form an electrical connection with an external circuit. However, in the process of forming MIM capacitors, the area in which MIM capacitors can be formed is becoming smaller and smaller due to the continuous reduction in device size. In the case of this continuous reduction in size, it is also necessary to ensure the formation of MIM capacitors with high capacitance density to ensure effective capacitance. The commonly used means is to reduce the thickness of the dielectric layer to increase the capacitance density. However, the thinner the thickness of the dielectric layer, the greater the risk of leakage of the MIM capacitor, thereby limiting the use of semiconductor devices and reducing reliability.

[0033] Please refer to Figure 1 The MIM capacitor 100 includes: a first metal layer 101 , a dielectric layer 102 located on the first metal layer 101 , and a second metal layer 103 located on the dielectric layer 102 .

[0034] The inventors have found that in order to ensure the capacitance density of the formed MIM capacitor, the thickness of the dielectric layer 102 needs to be reduced, thereby ensuring the capacitance of the MIM capacitor. However, as the thickness of the dielectric layer 102 decreases, leakage current occurs more and more in the MIM capacitor, thereby reducing the reliability of the MIM capacitor and limiting the application of the MIM capacitor.

[0035] The inventors have found that by forming a first ferroelectric insulating layer between two metal layers, on the one hand, the ferroelectric insulating layer can be used to form a negative capacitor between the two conductors (the first metal layer and the second metal layer), and due to the presence of the first dielectric layer, a positive capacitor can be formed between the two conductors (the first metal layer and the second metal layer). By matching the positive and negative capacitors, the capacitance density finally formed is improved. On the other hand, based on the introduction of the first ferroelectric insulating layer, there is no need to additionally change the thickness of the first dielectric layer, which reduces the process difficulty and does not cause defects such as leakage current due to the thin thickness of the first dielectric layer, thereby reducing the risk of leakage of the finally formed semiconductor device and greatly improving the reliability of the semiconductor device.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] First embodiment

[0038] Figures 2 to 12 It is a structural schematic diagram of the semiconductor device forming process in the first embodiment of the present invention.

[0039] First reference Figure 2, providing an initial first metal layer 200.

[0040] In this embodiment, the material of the initial first metal layer 200 is aluminum; in other embodiments, the material of the initial first metal layer 200 is one or more of aluminum, titanium, tantalum, titanium nitride, and tantalum nitride.

[0041] The initial first metal layer 200 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the initial first metal layer 200 is formed by a physical vapor deposition process.

[0042] In this embodiment, the initial first metal layer 200 is electrically connected to an external circuit as an electrode layer, and can be connected to the positive electrode of a power source or to the negative electrode of a power source.

[0043] In this embodiment, before providing the initial first metal layer, the process further includes providing a first substrate, forming a first device on the first substrate, and forming a first dielectric layer and a first conductive plug on the first device. For the convenience of illustration, the first substrate, the first device, the first dielectric layer, and the first conductive plug are not shown in the figure.

[0044] refer to Figure 3 , forming an initial first dielectric layer 201 on the initial first metal layer 200 .

[0045] The material of the initial first dielectric layer 201 is a high-k dielectric material.

[0046] In this embodiment, the material of the initial first dielectric layer 201 is silicon dioxide; in other embodiments, the material of the initial first dielectric layer 201 may also be silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxide silicate, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate or zirconium oxide silicate.

[0047] In this embodiment, the initial first dielectric layer 201 is used as a dielectric material of a capacitor.

[0048] The initial first dielectric layer 201 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0049] In this embodiment, the initial first dielectric layer 201 is formed by a chemical vapor deposition process.

[0050] The process for planarizing the initial first dielectric layer 201 includes: a chemical mechanical polishing process, a wet etching process or a dry etching process; in this embodiment, the process for planarizing the initial first dielectric layer 201 adopts a chemical mechanical polishing process.

[0051] refer to Figure 4 , an initial first ferroelectric insulating layer 202 is formed on the initial first dielectric layer 201 .

[0052] In this embodiment, the material of the initial first ferroelectric insulating layer 202 is HfZrO; in other embodiments, the initial first ferroelectric insulating layer may also be one or a combination of HfO2 or HfZrO.

[0053] In this embodiment, the initial first ferroelectric insulating layer 202 is used as a dielectric material to form a negative capacitor.

[0054] In this embodiment, the preparation method of the initial first ferroelectric insulating layer 202 includes one or a combination of atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process.

[0055] In this embodiment, the initial first ferroelectric insulating layer 202 is formed on the initial first dielectric layer 201, so that two capacitors connected in series can be formed between the first metal layer and the second metal layer later.

[0056] refer to Figure 5 , for heat treatment.

[0057] The arrows in the figure indicate the heat treatment process.

[0058] In this embodiment, the heat treatment temperature is 450° C. to 1000° C., and the heat treatment time is 20 seconds to 10 minutes, wherein the heat treatment time is determined according to the thickness of the formed ferroelectric insulating layer.

[0059] In this embodiment, after the initial first ferroelectric insulating layer 202 is formed, the purpose of performing heat treatment is to improve the quality and ferroelectricity of the first ferroelectric insulating layer and make it more stable.

[0060] refer to Figure 6 , forming an initial second metal layer 203 on the initial first ferroelectric insulating layer 202 .

[0061] In this embodiment, the material of the initial second metal layer 203 is aluminum; in other embodiments, the material of the initial second metal layer 203 is one or more of aluminum, titanium, tantalum, titanium nitride, and tantalum nitride.

[0062] The initial second metal layer 203 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the initial second metal layer 203 is formed by a physical vapor deposition process.

[0063] In this embodiment, the initial second metal layer 203 is used as an electrode layer to form an electrical connection with an external circuit, and is connected to the positive electrode of a power source or to the negative electrode of a power source.

[0064] In this embodiment, when the initial second metal layer 203 is used to connect to the positive electrode of the power supply, the initial first metal layer 200 is used to connect to the negative electrode of the power supply.

[0065] refer to Figure 7 , forming a first protective layer 204 on the initial second metal layer 203 .

[0066] In this embodiment, the material of the first protection layer 204 is silicon oxide.

[0067] In other embodiments, the material of the first protective layer 204 may also be one or a combination of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0068] The first protection layer 204 is formed by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process or a combination thereof.

[0069] In this embodiment, the first protection layer 204 is formed by a chemical vapor deposition process.

[0070] In this embodiment, the purpose of forming the first protective layer 204 is: the initial second metal layer 203, the initial first ferroelectric insulating layer and the initial first dielectric layer need to be etched subsequently to form a final second metal layer, a first ferroelectric insulating layer and a first dielectric layer. Due to the existence of the protective layer 204, the surface quality of the formed second metal layer can be guaranteed, thereby improving the quality and reliability of the formed semiconductor device, and at the same time playing a role of isolating from other devices.

[0071] refer to Figure 8 , forming a first patterned layer 205 on the first protective layer 204.

[0072] In this embodiment, the material of the first patterned layer 205 is a photoresist layer, and the material used is krypton fluoride (KrF); in other embodiments, the material of the first patterned layer 205 may also be argon fluoride (ArF).

[0073] In this embodiment, the first patterned layer 205 has a pattern structure required by the design, so that the required pattern structure can be formed by using the first patterned layer 205 as a mask.

[0074] refer to Fig. 9, using the first patterned layer 205 as a mask, the initial second metal layer 203, the initial first ferroelectric insulating layer 202 and the initial first dielectric layer 201 are etched in sequence, and a first dielectric layer 206, a first ferroelectric insulating layer 207 and a second metal layer 208 are formed in sequence on the surface of the initial first metal layer 200.

[0075] In this embodiment, the etching process is a wet etching process; in other embodiments, the etching process may also be one or more of a dry etching process and a wet etching process.

[0076] In this embodiment, after the first dielectric layer 206 , the first ferroelectric insulating layer 207 , and the second metal layer 208 are formed, a cleaning process is used to remove the first patterned layer 205 .

[0077] In this embodiment, the first protective layer 204 located on the initial second metal layer 203 is etched while the initial second metal layer 203, the initial first ferroelectric insulating layer 202 and the initial first dielectric layer 201 are etched in sequence. The first protective layer after etching is still denoted by the number 204.

[0078] In other embodiments, the first patterned layer 205 may be removed by an etching process.

[0079] In this embodiment, the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is in the range of 5 nanometers to 30 nanometers; when the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is less than 5 nanometers, due to the formed thickness being too thin, defects such as leakage may occur, thereby reducing the reliability of the performance of the semiconductor device; when the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is greater than 30 nanometers, at this time, due to the formed thickness being too thick, the difficulty of processes such as annealing increases, and the process is difficult to control.

[0080] Please refer to Fig.10 A second protective layer 209 is formed on the first protective layer 204 , the sidewalls of the second metal layer 208 , the sidewalls of the first ferroelectric insulating layer 207 , and the sidewalls of the first dielectric layer 206 .

[0081] In this embodiment, the second protective layer 209 adopts a laminated structure; in other embodiments, the second protective layer 209 may also adopt a single-layer structure.

[0082] In this embodiment, the second protection layer 209 is made of a stacked material of silicon oxide and silicon nitride.

[0083] In other embodiments, the second protective layer 209 may also be made of any two of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or a combination of any two of silicon carbon oxynitride.

[0084] In this embodiment, the second protective layer 209 is formed by a chemical vapor deposition process; in other embodiments, the second protective layer 209 may be formed by an atomic layer deposition process or a physical vapor deposition process.

[0085] In this embodiment, the purpose of forming the second protective layer 209 is: in the subsequent etching process, it plays a role in protecting the quality of the side walls of the first dielectric layer 206, the first ferroelectric insulating layer 207 and the second metal layer 208; and in the subsequent process of etching the initial first metal layer 200 to form the first metal layer, it can ensure the surface quality of the first metal layer formed, thereby ensuring the quality of the semiconductor device finally formed; at the same time, due to the existence of the second protective layer 209, it serves as an isolation layer between MIM capacitors, isolating other circuits on the second protective layer 209, and playing a role in protecting the MIM capacitors.

[0086] After forming the first dielectric layer, the first ferroelectric insulating layer and the second metal layer, a second patterning layer is formed.

[0087] Please refer to Figure 11 to Figure 12 , forming the second patterned layer on the second protective layer 209 , and etching the initial first metal layer 200 using the second patterned layer as a mask to form a first metal layer 210 .

[0088] Fig.12 yes Fig.11 The cross-section view at the AA section line, where Fig.12 The first protection layer 204 and the second protection layer 209 located on the second metal layer 208 are not shown.

[0089] In this embodiment, the material of the second patterned layer is a photoresist layer, and the material used is argon fluoride (ArF); in other embodiments, the material of the second patterned layer may also be krypton fluoride (KrF).

[0090] In this embodiment, the second patterned layer has a pattern structure required by the design, so that the required pattern structure can be formed by using the second patterned layer as a mask.

[0091] In this embodiment, after the first metal layer 210 is formed, the second patterned layer is removed.

[0092] In this embodiment, after the first metal layer 210 is formed by etching the initial first metal layer 200, a final MIM capacitor structure is formed (the first protective layer 204 and the second protective layer 209 are omitted), including a first metal layer 210, a first dielectric layer 206 located on the first metal layer 210, a first ferroelectric insulating layer 207 located on the first dielectric layer 206, and a second metal layer 208 located on the first ferroelectric insulating layer 207, wherein the first metal layer 210 and the second metal layer 208 are respectively connected to the positive and negative electrodes of a power supply.

[0093] In this embodiment, since there are the first dielectric layer 206 and the first ferroelectric insulating layer 207 between the first metal layer 210 and the second metal layer 208, the first dielectric layer 206 forms a positive capacitor between the first metal layer 210 and the second metal layer 208, and the first ferroelectric insulating layer 207 forms a negative capacitor between the first metal layer 210 and the second metal layer 208, the relationship between the positive capacitor and the negative capacitor satisfies: (where C represents the final capacitance value; C1 represents one of the capacitance values; C2 represents the other capacitance value). Since positive capacitance and negative capacitance exist at the same time, Infinitely small, so C is infinitely large, thereby improving the final capacitance density, and on the other hand, based on the introduction of the first ferroelectric insulating layer, there is no need to additionally change the thickness of the first dielectric layer, thereby reducing the process difficulty and there will be no defects such as leakage current caused by the thickness of the first dielectric layer being too thin, thereby reducing the risk of leakage of the final semiconductor device and greatly improving the reliability of the semiconductor device.

[0094] Correspondingly, the present invention also provides a semiconductor device, including a first substrate, a first device located on the first substrate, a first dielectric layer and a first conductive plug located on the first device, a first metal layer 210 located on the first dielectric layer and the first conductive plug, a first dielectric layer 206 located on the surface of the first metal layer 210, a first ferroelectric insulating layer 207 located on the surface of the first dielectric layer 206, and a second metal layer 208 located on the surface of the first ferroelectric insulating layer 207.

[0095] In this embodiment, the first ferroelectric insulating layer 207 is introduced. Due to the presence of the first ferroelectric insulating layer 207, a negative capacitor is formed between the first metal layer 210 and the second metal layer 208; and due to the presence of the first dielectric layer 206, a positive capacitor can be formed between the first metal layer 210 and the second metal layer 208. In the structure where the positive and negative capacitors are matched, the relationship between the positive capacitor and the negative capacitor satisfies (where C represents the final capacitance value; C1 represents one of the capacitance values; C2 represents the other capacitance value). When positive capacitance and negative capacitance exist at the same time, Infinitely small, so C is infinitely large, which increases the final capacitance density, reduces the risk of leakage, improves the reliability of semiconductor devices, and expands the scope of use of semiconductor devices.

[0096] In this embodiment, the material of the first ferroelectric insulating layer 207 is HfO 2 ; in other embodiments, the material of the first ferroelectric insulating layer 207 may also be HfZrO.

[0097] In this embodiment, the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is 5 nanometers to 30 nanometers. When the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is less than 5 nanometers, the thickness is too thin, resulting in defects such as leakage, reducing the reliability of the performance of the semiconductor device; when the sum of the thickness of the first ferroelectric insulating layer 207 and the thickness of the first dielectric layer 206 is greater than 30 nanometers, the thickness is too thick, resulting in increased difficulty in annealing and other processes, and the process is difficult to control.

[0098] Second embodiment

[0099] The second embodiment differs from the first embodiment only in that, before forming the initial first ferroelectric insulating layer 202 , the method further comprises: forming an initial third metal layer 211 on the initial first dielectric layer 201 .

[0100] For the step of forming the initial first dielectric layer 201 on the initial first metal layer 200, please refer to the first embodiment. Figures 2 to 3 .

[0101] Please refer to Fig.13 , forming an initial third metal layer 211 on the initial first dielectric layer 201 .

[0102] In this embodiment, the material of the initial third metal layer 211 is aluminum; in other embodiments, the material of the initial third metal layer 211 is one or more of aluminum, titanium, tantalum, titanium nitride, and tantalum nitride.

[0103] In this embodiment, the purpose of forming the initial third metal layer 211 is to provide a MIM capacitor structure, wherein the initial third metal layer 211 serves as a series layer of the capacitor and isolates the subsequently formed dielectric layer from the ferroelectric insulating layer; it helps to form more stable upper and lower interface layers between the dielectric layer and the ferroelectric insulating layer.

[0104] After forming the initial third metal layer 211, the initial first ferroelectric insulating layer 202 is formed on the initial third metal layer, and the initial second metal layer 203 is formed on the initial first ferroelectric insulating layer 202. Using the first patterned layer as a mask, the initial second metal layer 203, the initial first ferroelectric insulating layer 202, the initial third metal layer 211 and the initial first dielectric layer 201 are sequentially etched. The steps of sequentially forming the first dielectric layer 206, the third metal layer 212, the first ferroelectric insulating layer 207, and the second metal layer 208 on the surface of the initial first metal layer 200 are the same as those of the first embodiment. Please refer to Figures 4 to 11 .

[0105] After forming the first dielectric layer 206 , the first ferroelectric insulating layer 207 , the third metal layer 212 and the second metal layer 208 , the initial first metal layer 200 is patterned to form the first metal layer 210 .

[0106] Correspondingly, the present invention provides a semiconductor device, please refer to Fig.14 , including a first metal layer 210, a first dielectric layer 206 located on the surface of the first metal layer 210, a third metal layer 212 located on the surface of the first dielectric layer 206, a first ferroelectric insulating layer 207 located on the surface of the third metal layer 212, and a second metal layer 208 located on the surface of the first ferroelectric insulating layer 207.

[0107] Fig.14 The viewing direction and Fig.12 The viewing direction is consistent.

[0108] In this embodiment, the first dielectric layer 206 forms a positive capacitor between the first metal layer 210 and the third metal layer 212, and the first ferroelectric insulating layer 207 forms a negative capacitor between the third metal layer and the second metal layer 208. The positive capacitor and the negative capacitor are connected in series, and the capacitance density finally formed is improved by matching the positive and negative capacitors. On the other hand, based on the introduction of the first ferroelectric insulating layer, there is no need to additionally change the thickness of the first dielectric layer, which reduces the process difficulty and does not cause defects such as leakage current due to the thin thickness of the first dielectric layer, thereby reducing the risk of leakage of the finally formed semiconductor device and greatly improving the reliability of the semiconductor device.

[0109] Third embodiment

[0110] The difference between this embodiment and the first embodiment is that the ferroelectric insulating layer and the dielectric layer are distributed in parallel on the fourth metal layer. Figures 15 to 19 .

[0111] First, please refer to Fig.15, providing an initial fourth metal layer 300.

[0112] In this embodiment, the material of the initial fourth metal layer 300 is aluminum, which is also used as an electrode plate to achieve electrical connection with an external circuit.

[0113] In this embodiment, before providing the initial fourth metal layer, a second substrate is provided, a second device is formed on the second substrate, and a second dielectric layer and a second conductive plug are formed on the second device. For the convenience of illustration, the second substrate, the second device, the second dielectric layer and the second conductive plug are not shown in the figure.

[0114] Please refer to Fig.16 , forming an initial second dielectric layer 301 on the initial fourth metal layer 300 .

[0115] The material of the initial second dielectric layer 301 is a high-k dielectric material.

[0116] In this embodiment, the material of the initial second dielectric layer 301 is silicon dioxide; in other embodiments, the material of the initial second dielectric layer 301 may also be silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxide silicate, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate or zirconium oxide silicate.

[0117] In this embodiment, the initial second dielectric layer 301 is used as a dielectric material of a capacitor.

[0118] Please refer to Fig.17 , an initial fifth metal layer 302 is formed on the initial second dielectric layer 301 .

[0119] In this embodiment, the material of the initial fifth metal layer 302 is aluminum, which is also used as an electrode plate to achieve electrical connection with an external circuit and can be connected to the positive electrode of a power source.

[0120] Please refer to Fig.18 , a third protective layer 303 is formed on the initial fifth metal layer 302, and a third patterned layer (not shown in the figure) is formed on the third protective layer 303. Using the third patterned layer as a mask, the initial fifth metal layer 302 and the initial second dielectric layer 301 are etched in sequence to form a fifth metal layer 304 and the second dielectric layer 305, exposing a portion of the surface of the initial fourth metal layer 300.

[0121] After forming the fifth metal layer 304 and the second dielectric layer 305 , the third patterned layer is removed.

[0122] Please refer to Fig.19, an initial second ferroelectric insulating layer (not shown in the figure) is formed on the exposed surface of the initial fourth metal layer 300, and a heat treatment is performed. After the heat treatment, an initial sixth metal layer (not shown in the figure) is formed on the initial second ferroelectric insulating layer, a fourth protective layer 306 is formed on the initial sixth metal layer, a fourth graphic layer (not shown in the figure) is formed on the fourth protective layer 306, and the fourth graphic layer is used as a mask to etch the fourth protective layer 306, the initial sixth metal layer, and the initial second ferroelectric insulating layer to form a sixth metal layer 307 and a second ferroelectric insulating layer 308; the fourth graphic layer is removed, and a fifth protective layer 309 is formed on the third protective layer and the fourth protective layer, and a fifth graphic layer is formed on the fifth protective layer 309, and the initial fourth metal layer is etched using the fifth graphic layer as a mask to form a fourth metal layer 310.

[0123] After forming the fourth metal layer 310 , the fifth patterned layer is removed.

[0124] In this embodiment, the material of the second ferroelectric insulating layer 308 is HfO 2 ; in other embodiments, the material of the second ferroelectric insulating layer 308 may also be HfZrO.

[0125] In this embodiment, the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is 5 nanometers to 30 nanometers. When the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is less than 5 nanometers, the thickness is too thin, resulting in defects such as leakage, reducing the reliability of the performance of the semiconductor device; when the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is greater than 30 nanometers, the thickness is too thick, resulting in increased difficulty in annealing and other processes, and the process is difficult to control.

[0126] Before forming the initial third ferroelectric insulating layer, the third patterned layer is removed.

[0127] Compared with the first embodiment and the second embodiment, this embodiment has an additional masking process, so a patterning layer needs to be formed.

[0128] Correspondingly, the present invention also provides a semiconductor device, including a second substrate; a second device located on the second substrate; a second dielectric layer and a second conductive plug located on the second device; a fourth metal layer 310 located on the second dielectric layer and the second conductive plug; a second dielectric layer 305 and a second ferroelectric insulating layer 308 located on the surface of the fourth metal layer 310, the second dielectric layer 305 and the second ferroelectric insulating layer 308 being located on the same surface of the fourth metal layer 310 and not in contact; a fifth metal layer 304 located on the surface of the second dielectric layer 305; and a sixth metal layer 307 located on the surface of the second ferroelectric insulating layer 308.

[0129] In this embodiment, the material of the second ferroelectric insulating layer 308 is HfO 2 ; in other embodiments, the material of the second ferroelectric insulating layer 310 may also be HfZrO.

[0130] In this embodiment, the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is 5 nanometers to 30 nanometers. When the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is less than 5 nanometers, the thickness is too thin, resulting in defects such as leakage, reducing the reliability of the performance of the semiconductor device; when the sum of the thickness of the second ferroelectric insulating layer 308 and the thickness of the second dielectric layer 305 is greater than 30 nanometers, the thickness is too thick, resulting in increased difficulty in annealing and other processes, and the process is difficult to control.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: a first substrate; a first device located on the first substrate; a first dielectric layer and a first conductive plug located on the first device; a first metal layer located on the first dielectric layer and the first conductive plug; a first dielectric layer located on a surface of the first metal layer; a first ferroelectric insulating layer located on the surface of the first dielectric layer, wherein the first ferroelectric insulating layer is heat-treated; a second metal layer located on the surface of the first ferroelectric insulating layer; a second protective layer located on the sidewalls of the second metal layer, the sidewalls of the first ferroelectric insulating layer and the sidewalls of the first dielectric layer; The invention also includes: a third metal layer, wherein the third metal layer is located between the first dielectric layer and the first ferroelectric insulating layer.

2. The semiconductor device according to claim 1, wherein: The sum of the thickness of the first ferroelectric insulating layer and the thickness of the first dielectric layer is 5 nanometers to 30 nanometers.

3. The semiconductor device according to claim 1, wherein: The material of the first ferroelectric insulating layer is HfO2 or HfZrO.

4. A semiconductor device, characterized in that: include: a second substrate; a second device located on the second substrate; a second dielectric layer and a second conductive plug located on the second device; a fourth metal layer located on the second dielectric layer and the second conductive plug; A second dielectric layer and a second ferroelectric insulating layer located on the surface of the fourth metal layer, wherein the second dielectric layer and the second ferroelectric insulating layer are located on the same surface of the fourth metal layer and are not in contact with each other; a fifth metal layer located on a surface of the second dielectric layer; A sixth metal layer is located on a surface of the second ferroelectric insulating layer.

5. The semiconductor device according to claim 4, characterized in that: The material of the second ferroelectric insulating layer is HfO2 or HfZrO.

6. The semiconductor device according to claim 4, characterized in that The sum of the thickness of the second ferroelectric insulating layer and the thickness of the second dielectric layer is 5 nanometers to 30 nanometers.

7. A method for forming a semiconductor device, characterized in that: include providing an initial first metal layer; forming an initial first dielectric layer on the initial first metal layer; forming an initial third metal layer on the initial first dielectric layer; forming an initial first ferroelectric insulating layer on the initial third metal layer, and performing heat treatment on the initial first ferroelectric insulating layer; forming an initial second metal layer on the initial first ferroelectric insulating layer; forming a first patterned layer on the initial second metal layer; Using the first patterned layer as a mask, sequentially etching the initial second metal layer, the initial first ferroelectric insulating layer, the initial third metal layer and the initial first dielectric layer, and sequentially forming a first dielectric layer, a first ferroelectric insulating layer, a third metal layer and a second metal layer on the surface of the initial first metal layer; forming a second protective layer on the sidewalls of the second metal layer, the sidewalls of the first ferroelectric insulating layer, and the sidewalls of the first dielectric layer; After forming the first dielectric layer, the first ferroelectric insulating layer and the second metal layer, forming a second patterned layer; The initial first metal layer is etched using the second patterned layer as a mask to form a first metal layer.

8. The method for forming a semiconductor device according to claim 7, wherein: After forming the initial first ferroelectric insulating layer and before forming the initial second metal layer, the method further includes: performing a heat treatment.

9. The method for forming a semiconductor device according to claim 8, wherein: After forming the initial second metal layer and before forming the first patterned layer, the method further includes forming a first protective layer on the initial second metal layer.

10. The method for forming a semiconductor device according to claim 9, wherein: After forming the first dielectric layer, the first ferroelectric insulating layer and the second metal layer, and before forming the second patterned layer, the method further includes forming a second protective layer on the first protective layer, the side wall of the second metal layer, the side wall of the first ferroelectric insulating layer and the side wall of the first dielectric layer.

11. The method for forming a semiconductor device according to claim 7, wherein: Before providing the initial first metal layer, the method further includes providing a first substrate, forming a first device on the first substrate, and forming a first dielectric layer and a first conductive plug on the first device.

12. A method for forming a semiconductor device, characterized in that: include providing an initial fourth metal layer; forming an initial second dielectric layer on the initial fourth metal layer; initializing a fifth metal layer on the initial second dielectric layer; forming a third patterned layer on the initial fifth metal layer; Using the third patterned layer as a mask, sequentially etching the initial fifth metal layer and the initial second dielectric layer to form a fifth metal layer and the second dielectric layer, exposing a portion of the surface of the initial fourth metal layer; forming an initial second ferroelectric insulating layer on the exposed surface of the initial fourth metal layer; forming an initial sixth metal layer on the initial second ferroelectric insulating layer; forming a fourth patterned layer on the initial sixth metal layer; Using the fourth patterned layer as a mask, etching the initial sixth metal layer and the initial second ferroelectric insulating layer to form a sixth metal layer and a second ferroelectric insulating layer; removing the fourth patterned layer, and forming a fifth patterned layer on the sixth metal layer and the fifth metal layer; The initial fourth metal layer is etched using the fifth patterned layer as a mask to form a fourth metal layer, wherein the second dielectric layer and the second ferroelectric insulating layer are located on the same surface of the fourth metal layer and are not in contact with each other.

13. The method for forming a semiconductor device according to claim 12, wherein: After forming the initial second ferroelectric insulating layer and before forming the initial sixth metal layer on the initial second ferroelectric insulating layer, the method further includes performing a heat treatment.

14. The method for forming a semiconductor device according to claim 12, wherein: After forming the initial fifth metal layer and before forming the third patterned layer, the method further includes: forming a third protective layer on the initial fifth metal layer.

15. The method for forming a semiconductor device according to claim 14, wherein: After forming the initial sixth metal layer and before forming the fourth patterned layer, the method further includes: forming a fourth protective layer on the initial sixth metal layer.

16. The method for forming a semiconductor device according to claim 15, wherein: After forming the sixth metal layer and the second ferroelectric insulating layer and before forming the fifth patterned layer, the method further includes: forming a fifth protective layer on the third protective layer and the fourth protective layer.

17. The method for forming a semiconductor device according to claim 12, wherein: Before providing the initial fourth metal layer, the method further includes providing a second substrate, forming a second device on the second substrate, and forming a second dielectric layer and a second conductive plug on the second device.

Images