Infrared detector, imaging chip and preparation method thereof

Abstract

The present invention relates to an infrared detector, an imaging chip, and methods for fabricating the same. The invention provides a method for fabricating a large-scale InGaAsOI substrate with a vertical NIPI / PINI structure. The method involves bonding an acceptor substrate and a donor substrate together to form a single InGaAsOI substrate. A short-wave infrared InGaAs photodetector and a fully depleted InGaAs transistor are then formed on the InGaAsOI substrate. The invention integrates the short-wave infrared InGaAs photodetector and the fully depleted InGaAs transistor on the same substrate. Leveraging the high mobility and excellent optoelectronic properties of the InGaAs material, the invention provides a monolithic optoelectronic integration solution for a short-wave infrared imaging chip on an InGaAsOI substrate, simplifying the manufacturing process and reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to an infrared detector, an imaging chip, and a method for manufacturing the same. Background Art

[0002] The detection principle of infrared detectors is that infrared light excites the detector chip, increasing the number of conduction electrons and thus the conductivity. Under an applied bias, this increases the current, which is proportional to the number of photons. Photoconductivity detectors are commonly known as photoresistors. Photoconductivity is categorized into two types: intrinsic excitation and extrinsic (impurity) excitation. Intrinsic excitation occurs when infrared photons excite electrons from the valence band to the conduction band, generating electron-hole pairs. This means that electrons are added to the conduction band and holes are generated in the valence band. Impurity excitation occurs when infrared photons excite bound electrons (or holes) at a higher energy level into the conduction band (or valence band), adding electrons to the conduction band (or holes to the valence band). The most commonly used intrinsic photoconductivity detectors include lead sulfide, lead selenide, indium antimonide, and mercury cadmium telluride. Impurity-type photoconductivity detectors primarily include mercury-doped germanium and gallium-doped silicon.

[0003] Optoelectronic integration combines the advantages of both photonic and electronic circuits, breaking the power consumption and information transmission limitations of traditional microelectronics and promoting the development of the information industry. Among optoelectronic integration solutions, silicon-based monolithic optoelectronic integration (optoelectronic integrated chips) offers the advantages of integrating most photonic devices (including lasers, photodiodes, detectors, etc.) and electronic devices (including amplifiers, signal conditioners, readout circuits, etc.) on the same substrate, being compatible with traditional microelectronics manufacturing processes and amenable to large-scale mass production. These advantages hold great promise for research and application.

[0004] The existing integration process for photonic and electronic devices involves separately fabricating them using different substrate materials, and then integrating these discrete devices to achieve photoelectric conversion. This method has complex process steps, is time-consuming, has a low degree of integration, and cannot be precisely aligned.

[0005] Compared to silicon, III-V semiconductor materials have higher carrier mobility and hold great promise for use in advanced CMOS devices. Currently, progress in III-V transistors is primarily focused on device performance and scalable 3D device architectures. Therefore, there is an urgent need to develop integrated solutions for silicon-based III-V transistors. III-VOI technology, as an extension of SOI, offers similar advantages, including dielectric isolation, low parasitic capacitance, high integration density, high speed, simple process flow, minimal short-channel effects, low voltage, low power consumption, and low leakage current. Fully depleted III-VOI technology, in particular, features thin buried oxide (BOX) and top III-V materials, resulting in devices with reduced parasitic capacitance, higher speed, lower power consumption, and superior radiation resistance (advantages of fully depleted InGaAs transistors). Therefore, developing (FD) III-VOI substrate fabrication processes is crucial for achieving high-performance field-effect transistors.

[0006] InGaAs material has extremely high electron mobility, making it a very important candidate for transistor channel materials. Furthermore, InGaAs possesses excellent optoelectronic properties, with an extremely high absorption coefficient in the shortwave infrared band, enabling the development of high-performance shortwave infrared imaging chips. Shortwave infrared detectors fabricated using the ternary alloy In0.53Ga0.47As, lattice-matched to InP, have a cutoff wavelength of 1.7μm and exhibit excellent device performance, finding widespread application in a wide range of fields. (FD)InGaAsOI readout circuitry and InGaAsOI shortwave infrared focal plane arrays enable monolithic optoelectronic integration, simplifying the manufacturing process and promising lower-cost, lower-power, and higher-resolution shortwave infrared cameras.

[0007] Currently commercially available InGaAs shortwave infrared cameras primarily consist of an optical system, a shortwave infrared focal plane array chip, a silicon readout circuit, and a signal processing system. The interconnection between the shortwave infrared focal plane array chip and the silicon readout circuit typically utilizes heterogeneous integration, which presents challenges such as complex manufacturing processes, high costs, low resolution, and difficulties in scalable production. Notably, the vast majority utilize silicon readout circuits to integrate, amplify, and multiplex the detector signals. Compared to silicon readout circuits, (FD)InGaAsOI readout circuits offer superior performance.

[0008] Most existing InGaAsOI substrates are small in size, with high manufacturing costs, and the resulting detector arrays are small in size. TMWhen manufacturing (FD)InGaAsOI substrates using this technology, large-sized InGaAs substrates are required, which has problems such as high manufacturing cost and thin layer structure. It is impossible to achieve monolithic optoelectronic integration of InGaAs short-wave infrared detectors and (FD)InGaAsOI field-effect transistors. There is an urgent need to develop new (FD)InGaAsOI substrate manufacturing solutions.

[0009] References: 1. "An InGaAs on Si platform for CMOS with 200 mm InGaAs-OIsubstrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch";

[0010] 2. “300 mm InGaAsOI substrate fabrication using the Smart Cut TMtechnology”;

[0011] 3. "Advances in InGaAs / InP single-photon detector systems for quantum communication";

[0012] 4. "An InGaAs detector for the 1.0–1.7μm wavelength range";

[0013] 5. "High performance InGaAs-on-insulator MOSFETs on Si by novel directwafer bonding technology applicable to large wafer size Si". Summary of the Invention

[0014] In response to the above technical problems, the present invention provides a short-wave infrared imaging chip with monolithic optoelectronic integration on an InGaAsOI substrate and a method for preparing the same. The method involves bonding a substrate without a detector structure to an electronic circuit structure substrate, and then fabricating the detector structure. This simplifies the integration process, improves the integration level, and solves the problem of inability to accurately align the chip.

[0015] In order to achieve the above objectives, the present invention provides the following technical solutions:

[0016] A method for integrating a photodetector, comprising:

[0017] A buffer structure layer, a vertical stacking structure layer, and a high-mobility channel layer are sequentially formed on the surface of a first substrate from bottom to top, wherein the vertical stacking structure layer is a PINI vertical stacking structure or an NIPI vertical stacking structure, and then a first dielectric layer is formed on the surface of the high-mobility channel layer to obtain a donor substrate;

[0018] forming a second dielectric layer on the surface of the second substrate to obtain an acceptor substrate;

[0019] bonding the acceptor substrate and the donor substrate by using the first dielectric layer and the second dielectric layer as bonding surfaces;

[0020] After bonding, the first substrate and the buffer structure layer are removed to form a third substrate;

[0021] Then, vertical etching is performed from top to bottom in the third substrate until the high-mobility channel layer is exposed, thereby separating the third substrate into a photodetector region and a transistor region;

[0022] wherein the photodetector region forms a photodetector;

[0023] Etching away the buffer layer and the vertical stacking structure in the transistor area, forming a gate and a source and drain on the exposed high-mobility channel layer to form a transistor;

[0024] The transistor and the photodetector structure are electrically connected.

[0025] An integrated structure of a detector, comprising:

[0026] insulating substrate;

[0027] The insulating substrate includes a photodetector and a transistor;

[0028] The photodetector is a PINI vertical stacking structure or a NIPI vertical stacking structure, wherein the bottom layer is the first i-InGaAs layer;

[0029] A gate electrode and a source and drain electrode are provided on the second i-InGaAs layer on the insulating substrate to form a transistor;

[0030] The first i-InGaAs layer and the second i-InGaAs layer are electrically isolated by etching;

[0031] The transistor and the planar photodetector are electrically interconnected for reading out the photocurrent of the photodetector.

[0032] Compared with the prior art, the present invention achieves the following technical effects:

[0033] The present invention proposes a solution for integrating a double heterojunction detector and a low-power (FD) InGaAs transistor on the same InGaAsOI substrate. Leveraging the high mobility and excellent optoelectronic properties of InGaAs materials, this solution provides a monolithic optoelectronic integration solution for short-wave infrared imaging chips on an InGaAsOI substrate, simplifying the manufacturing process and reducing costs.

[0034] 1) Traditional InGaAs detector arrays are heterogeneously integrated with silicon readout circuits by bonding to form an imaging system. However, this patent uses FD-InGaAs transistors as the readout circuit of the InGaAs detector array. That is, the readout circuit and the detector array are integrated on the same substrate, which improves imaging effects and simplifies the manufacturing process.

[0035] 2) Traditional InP / InGaAs / InP detectors are directly formed by epitaxial growth on InP or Si substrates. The device has a large leakage current, no resonant cavity effect, and a slow operating speed. However, in this patent, a PINI or NIPI structure of InP / InGaAs / InP / InGaAs is formed on an insulator substrate by bonding. The performance of the resulting detector and transistor are both better than that of existing technologies, and they are integrated on the same substrate, resulting in faster imaging speed and lower power consumption.

[0036] 3) The multi-oxide layer structure used in the present invention has a strong resonant cavity effect, which helps to improve the performance indicators such as the responsiveness of the InGaAs detector; by reasonably controlling the InP / InGaAs / InP thickness, its resonant cavity effect can also be improved, and the device operates faster and consumes less power. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those skilled in the art by reading the following detailed description of the preferred embodiment.The accompanying drawings are only for the purpose of illustrating the preferred embodiment and are not to be considered as limiting the present invention.

[0038] Figure 1 is a schematic diagram of the donor substrate 100.

[0039] Figure 2 is a schematic diagram of the acceptor substrate 200.

[0040] Figure 3 Schematic diagram of the donor substrate 100 and the acceptor substrate 200 after bonding.

[0041] Figure 4 Schematic diagram of InGaAsOI substrate.

[0042] Figure 5 Schematic diagram of forming a SiO2 layer on an InGaAsOI substrate.

[0043] Figure 6 Schematic diagram of opening a hole in the SiO2 layer

[0044] Figure 7 Schematic diagram of forming the photodetector region and transistor region on the InGaAsOI substrate

[0045] Figure 8 Schematic diagram of forming a passivation film on the outer surface of the photodetector

[0046] Figure 9 Schematic diagram of forming N-type contact and P-type contact on the outer surface of the photodetector.

[0047] Figure 10 Schematic diagram of removing the NIPI / PINI structure from the transistor area and forming a metal gate.

[0048] Figure 11 Schematic diagram of the integrated structure of the photodetector of the present invention. DETAILED DESCRIPTION

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0050] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0051] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0052] The present invention provides a method for preparing a short-wave infrared imaging chip with monolithic optoelectronic integration on an InGaAsOI substrate, which specifically comprises the following steps:

[0053] Step 1: Forming a donor substrate 100

[0054] See also Figure 1 A 6° beveled Si substrate 101 is provided as an initial substrate, and then epitaxial growth is sequentially performed thereon to form a low-temperature Ge layer 102 and a high-temperature Ge layer 103, and then a chemical mechanical polishing (CMP) process is performed on the upper surface of the high-temperature Ge layer 103, and then epitaxial growth is sequentially performed to form a GaAs buffer layer 104, an n+-InP buffer layer 105, an i-InP buffer layer 106, and the like from bottom to top. 0.53 Ga 0.47 As layer 106, p+-InP layer 107, i-In 0.53 Ga 0.47 As buffer layer 108, Al2O3 layer 109, thus forming donor substrate 100. 0.53 Ga 0.47 As is perfectly lattice-matched, resulting in a defect-free material. Furthermore, the InP / InGaAs / InP double heterojunction structure provides stronger carrier confinement than a homojunction. Photodetectors fabricated using this double heterojunction structure offer high speed and sensitivity. In this embodiment, epitaxial growth is performed using molecular beam epitaxy (MBE).

[0055] The donor substrate formed above forms a NIPI structure in the subsequent steps of the detector vertical structure. In another embodiment, the formation order of the n+-InP buffer layer 105 and the p+-InP layer 107 can be interchanged, resulting in the positions of the two being interchanged, and the vertical structure of the detector subsequently formed is a PINI structure.

[0056] In another embodiment, Figure 1 The 6°-beveled Si substrate 101 , the low-temperature Ge layer 102 , the high-temperature Ge layer 103 , the GaAs buffer layer 104 , and the n + -InP buffer layer 105 in the middle dotted frame can be entirely replaced with an n + -InP substrate.

[0057] Step 2: Forming the acceptor substrate 200

[0058] See also Figure 2 A conventional Si substrate 201 is provided as an initial substrate, and a SiO2 layer 202 with a thickness of 10-500nm is formed thereon by a thermal oxidation process, which facilitates the subsequent increase in bonding strength; then a SiO2 layer or TEOS layer 203 with a thickness of 10-500nm is formed by a thermal oxidation process, which facilitates the increase in bonding strength and the increase in the resonant cavity effect of the detector, thereby forming an acceptor substrate 200.

[0059] The order of step 1 forming the donor substrate 100 and step 2 forming the acceptor substrate 200 can be reversed or performed simultaneously.

[0060] Step 3: Bond the donor substrate 100 and the acceptor substrate 200 to form an InGaAsOI substrate.

[0061] like Figure 3 As shown, first, the bonding surface of the donor substrate 100 is activated, that is, the upper surface of the Al2O3 layer 109 is activated. Plasma activation using O2 and / or N2 plasma is used to supplement the activation of the donor substrate. The upper surface of the Al2O3 layer 109 of the donor substrate 100 to be bonded is exposed to oxygen plasma or plasma containing O2.

[0062] Next, the activation of the acceptor substrate 200 includes: surface cleaning, for example, using SC1 for cleaning at 30°C to 80°C for about 10 minutes; under the same conditions as described above for activating the donor substrate 100, plasma activation of the bonding surface of the acceptor substrate 200, that is, plasma activation of the SiO2 layer or TEOS layer 203.

[0063] The purpose of the activation process step is to prepare the surface for bonding so that high bonding energies can be achieved.

[0064] Subsequently, the donor substrate 100 and the acceptor substrate 200 are placed in a bonding chamber, with the surface of the SiO2 layer or TEOS layer 203 on the acceptor substrate 200 facing the surface of the Al2O3 layer 109 on the donor substrate 100. Typically, the two substrates are aligned based on alignment marks on the two substrates. After the substrates are placed and aligned, the bonding chamber is sealed and evacuated to approximately 1-50 Torr, preferably 1-20 Torr. Typically, this process lasts approximately 2-3 minutes, but for the purposes of the present invention, this level of low vacuum increases the bonding energy in a moderate amount of time (e.g., compared to high vacuum or ultra-high vacuum).

[0065] The atmosphere in the bonding chamber of this embodiment primarily comprises a dry atmosphere (particularly an atmosphere containing less than 100 ppm of H₂O molecules) and / or, more preferably, a neutral atmosphere such as argon and / or nitrogen. The bonding chamber is maintained at room temperature, preferably within a temperature range of 18°C to 26°C.

[0066] When the required pressure level is reached, the surface of the SiO2 layer or TEOS layer 203 on the acceptor substrate 200 begins to contact the surface of the Al2O3 layer 109 on the donor substrate 100. Figure 3 As shown, bonding begins. Typically, bonding occurs at a single point and the bonding wave propagates, ultimately connecting the two surfaces via intermolecular forces (van der Waals forces) to form a donor-acceptor complex. In one embodiment, initial contact can be achieved by applying slight pressure to one side or the center using a mechanical finger.

[0067] Due to the advantageous synergistic effect of the surface activation step in combination with the contacting under low vacuum, it is possible to achieve a bonding speed of at least 700-1000 mJoule / m by means of the described bonding method. 2 The invention relates to a method for producing a bonding energy within a range of 100 nm and 100 nm, while at the same time reducing the degree of bonding defects or even eliminating bonding defects. Moreover, these results are achieved without requiring a post-bonding anneal at a high temperature greater than 500°C. It has been observed that, with the exception of voids arising from particles already present on one of the two surfaces before bonding, the occurrence of edge voids can be suppressed or limited (by at least an order of magnitude compared to existing bonding methods).

[0068] Then as Figure 4 As shown, the donor substrate 100 is thinned, and the top Si substrate 101 of the composite, which is beveled at a 6° angle, is thinned. The thinning process involves grinding and / or polishing steps, followed by chemical etching, which terminates at the low-temperature Ge layer 102. The low-temperature Ge layer 102, the high-temperature Ge layer 103, and the GaAs layer 105 are selectively etched using a TMAH solution, exposing the n+-InP buffer layer 106.

[0069] In one embodiment, the 6° beveled Si substrate 101, the low-temperature Ge layer 102, the high-temperature Ge layer 103, the GaAs buffer layer 104, and the n+-InP buffer layer 105 can be replaced as a whole with an n+-InP substrate. At this time, only the n+-InP substrate needs to be thinned to a suitable thickness, preferably to 100-2000nm.

[0070] Other finishing steps may then be performed, such as edge polishing and / or grinding, for example, chemical mechanical polishing (CMP) to obtain the InGaAsOI substrate 300 required by the present invention.

[0071] Step 4: Forming a vertically structured InGaAsOI detector

[0072] The upper surface of the InGaAsOI substrate 300 obtained in the above step 3, that is, the surface of the exposed n+-InP buffer layer 104, is formed into a SiO2 layer 301 by a thermal oxidation process. Figure 5 Then, the SiO2 layer 301 is physically or chemically etched to form a hole 302 on the SiO2 layer 301, with a diameter of 10-200 μm, as shown in FIG. Figure 6 shown.

[0073] See also Figure 7 Then, the remaining SiO2 layer 301 is used as a mask to etch the InGaAsOI substrate 300 to the upper surface of the Al2O3 layer 109, forming a mesa under the position of the hole 302. Figure 7 As can be seen from the longitudinal cross-sectional view, the InGaAsOI substrate 300 is now divided into three parts, namely, region A, region B, and region C from left to right. The mesa is located in the middle region B. The components of each layer of the mesa are the same as those of each layer of region A, and the step position of the mesa is formed in the P+-InP layer 107. In one embodiment, region A may not be retained; a vertical structure detector (referring to the setting direction of the PN structure) is formed in a subsequent step in region B, which is used to detect short-wave infrared rays in the present invention; a transistor is formed in a subsequent step in region C, and the transistor can be a readout circuit to read out the electrical signal in the detector, including but not limited to one or more integrated amplifiers and signal conditioners.

[0074] The structures from top to bottom in area B are n+-InP buffer layer 105, i-In 0.53 Ga 0.47 As layer 106, p+-InP layer 107, i-In 0.53 Ga 0.47 The As layer 108 forms an NIPI stacking structure, which constitutes the core NIPI junction of the photodetection device.

[0075] In one embodiment, the formation order of the n+-InP buffer layer 105 and the p+-InP layer 107 can be interchanged, resulting in the positions of the two being interchanged. In this case, the structure of the detector in area B from top to bottom is p+-InP layer 107, i-In 0.53 Ga 0.47 As layer 106, n+-InP buffer layer 105, i-In 0.53 Ga 0.47 The As layer 108 forms a PINI stack structure, constituting the core PIN junction of the photodetection device.

[0076] Then, a passivation layer 400 is formed on the surface of the mesa in area B. The passivation layer 400 can enhance the stability and reliability of the device and shield the device from harmful effects of external impurities, ionic charges, water vapor, etc. The passivation layer 400 can be formed by physical / chemical vapor deposition processes, including but not limited to LPCVD, RTCVD, PECVD or thermal oxidation. The material of the passivation layer 400 is SiO2, HfO2 or Al2O3, such as Figure 8 shown.

[0077] A hole is opened on the top of the passivation layer 400 to expose part of the p+-InP buffer layer 105. An n-type light absorbing layer 401 is formed at the position of the hole. In one embodiment, the n-type light absorbing layer 401 is an N-type InP layer, and the doping elements are S and Sn, with a doping concentration of 5e 18 -5e 19The formation process is in-situ doping, diffusion or ion implantation; the doping thickness is 100-2000nm; a hole is opened on the upper surface of the step to expose the p+-InP layer 107, and a p-type doped light absorption layer 402 is formed at the position of the hole. The p-type light absorption layer 402 is P-type InP, the doping element is Zn, and the doping concentration is 5e 18 -6e 19 ; The formation process is in-situ doping, diffusion or ion implantation, and the doping thickness is 100-2000nm, such as Figure 9 shown.

[0078] Step 5: Forming a fully depleted InGaAsOI transistor

[0079] See also Figure 10 , remove the NIP stack structure or PIN stack structure in the C area, that is, etch the n+-InP buffer layer 105, i-In 0.53 Ga 0.47 The As layer 106 and the p+-InP layer 107 can be etched by dry etching or wet etching. In one embodiment, reactive ion etching (RIE) can be used. 0.53 Ga 0.47 A high-K dielectric layer 501 and a gate metal layer 502 are sequentially deposited on the upper surface of the As layer 108. Then, the high-K dielectric layer 501 and the gate metal layer 502 are etched by an etching process. The high-K dielectric layer 501 and the gate metal layer 502 on both sides are etched away, and the high-K dielectric layer 501 and the gate metal layer 502 in the middle are retained. The i-In is exposed on both sides of the high-K dielectric layer 501 and the gate metal layer 502. 0.53 Ga 0.47 The source and drain electrodes 503 are deposited on the upper surface of the As layer 108, thereby forming a readout circuit. In this embodiment, the readout circuit is an amplifier circuit that amplifies the electrical signal from the detector in the B region.

[0080] Rapid thermal annealing is performed to allow the NIPI stacking structure in region B or the PI or NI layers in the PINI structure to mutually expand, thereby forming a NIPI structure or a PINI structure.

[0081] Finally, the readout circuit structure and the detector structure are interconnected through the TSV process to obtain the following Figure 11 The structure shown (the detailed circuit structure is not shown in the figure).

[0082] This method is applicable to any vertical (referring to the setting direction of the PN structure) optoelectronic device that needs to be integrated on a monolithic silicon chip. Therefore, there are no specific requirements for the readout circuit structure and the detector structure. The readout circuit structure can be replaced by other single-function or multi-function structures, such as one or more integrated amplifiers and signal conditioners.

[0083] The present invention proposes a solution for integrating InGaAsOI detectors and (FD)InGaAsOI transistors on the same substrate. Transistor types include but are not limited to planar (FD)InGaAsOI transistors, and may also include: planar partially depleted (PD) transistors, three-dimensional multi-gate transistors (for example, dual-gate transistors, Pi (П) gate transistors, Omega (Ω) gate transistors), fin field-effect transistors, etc.

[0084] Figure 11 A schematic longitudinal section of a first example of a photodetector 10 is shown, with a cut-off wavelength of 1.7 μm for detecting short-wave infrared rays.

[0085] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for integrating a photodetector, characterized in that: include: A buffer structure layer, a vertical stacking structure layer, and a high-mobility channel layer are sequentially formed on the surface of a first substrate from bottom to top, wherein the vertical stacking structure layer is a PINI vertical stacking structure or an NIPI vertical stacking structure, and then a first dielectric layer is formed on the surface of the high-mobility channel layer to obtain a donor substrate; The materials used in the vertical stacking structure are n+-InP, i-InGaAs, p+-InP, i-InGaAs; the high mobility channel layer is i-In 0.53 Ga 0.47 As buffer layer; forming a second dielectric layer on the surface of the second substrate to obtain an acceptor substrate; bonding the acceptor substrate and the donor substrate by using the first dielectric layer and the second dielectric layer as bonding surfaces; After bonding, the first substrate and the buffer structure layer are removed to form a third substrate; Then, vertical etching is performed from top to bottom in the third substrate until the high-mobility channel layer is exposed, thereby separating the third substrate into a photodetector region and a transistor region; wherein the photodetector region forms a photodetector; Etching away the buffer layer and the vertical stacking structure in the transistor area, forming a gate and a source and drain on the exposed high-mobility channel layer to form a transistor; The transistor and the photodetector structure are electrically connected.

2. The integration method according to claim 1, characterized in that The third substrate is an InGaAsOI substrate.

3. The integration method according to claim 1, characterized in that The first substrate is a 6° beveled Si substrate, and the second substrate is a Si substrate.

4. The integration method according to claim 1, characterized in that The first dielectric layer is Al2O3, and the second dielectric layer is a SiO2 layer, or a stack of a SiO2 layer and a TEOS layer.

5. The integration method according to claim 1, characterized in that The buffer structure layers are, from bottom to top, a low-temperature Ge layer, a high-temperature Ge layer, a GaAs buffer layer, and an n+-InP buffer layer.

6. The integration method according to claim 1, characterized in that The transistor is an integrated circuit of one or more of an amplifier, a signal conditioner, and a readout circuit.

7. The integration method according to claim 1, characterized in that: The transistor region is a fully depleted transistor with a planar structure, a partially depleted (PD) transistor with a planar structure, a multi-gate transistor with a three-dimensional structure, or a fin field effect transistor.

8. The integration method according to claim 1, characterized in that: The transistor is a fully depleted InGaAsOI transistor.

9. The integration method according to claim 1, characterized in that: The method for removing the first substrate is one or more combinations of grinding and polishing, wet etching, dry etching, and CMP; the method for removing the buffer structure layer is one or any combination of wet etching, dry etching, dry oxidation combined with wet etching, and wet oxidation combined with wet etching.

10. An integrated structure of a detector, characterized in that: It includes: insulating substrate; The insulating substrate includes a photodetector and a transistor; The photodetector is a PINI vertical stacking structure or an NIPI vertical stacking structure, and the material used in the vertical stacking structure is n+-InP, i-InGaAs, p+-InP, i-InGaAs; The bottom layer is the first i-InGaAs layer; A gate and a source and drain are arranged on the second i-InGaAs layer on the insulating substrate to form a transistor; the second i-InGaAs layer is a high-mobility channel layer; The first i-InGaAs layer and the second i-InGaAs layer are electrically isolated by etching; The transistor and the photodetector are electrically interconnected for reading out the photocurrent of the photodetector.

11. A monolithic optoelectronically integrated short-wave infrared imaging chip, characterized by: It comprises an integrated structure of a plurality of detectors according to claim 10.

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