Electronic device and method of manufacturing the same

Abstract

An electronic device including a semiconductor memory and a manufacturing method thereof are provided. The semiconductor memory includes a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region, second lines disposed above the first lines and extending in a second direction crossing the first direction, storage cells located at intersection regions between the first lines and the second lines in the cell region, a first insulating layer located between the first lines, between the second lines, or both in the first cell region, and a second insulating layer located between the first lines and the second lines in the second cell region, wherein a dielectric constant of the first insulating layer is less than a dielectric constant of the second insulating layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0065415, filed on May 21, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This patent document relates to memory circuits or storage devices and their applications in electronic devices or electronic systems. Background Technology

[0004] Recently, as electrical appliances have become increasingly miniaturized, low-power, high-performance, and multifunctional, there is a need in this field for semiconductor devices capable of storing information in various electrical appliances such as computers and portable communication devices, and research has been conducted on such semiconductor devices. These semiconductor devices can store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current; examples include RRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), and electric fuses. Summary of the Invention

[0005] The technologies disclosed in this patent document include various embodiments of electronic devices that can improve the operating characteristics of semiconductor memories and simplify the manufacturing process.

[0006] In one embodiment, an electronic device includes a semiconductor memory comprising: a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; a plurality of first lines disposed on the substrate and each extending in a first direction; a plurality of second lines disposed on the first lines and each extending in a second direction intersecting the first direction; a plurality of memory cells located at intersection regions between the first lines and the second lines in the cell region; a first insulating layer located between the plurality of first lines, between the plurality of second lines, or both between the plurality of first lines and the plurality of second lines in the first cell region; and a second insulating layer located between the plurality of first lines and between the plurality of second lines in the second cell region, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer.

[0007] In another embodiment, an electronic device includes a semiconductor memory comprising: a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; a plurality of first lines disposed on the substrate and each extending in a first direction; a plurality of second lines disposed on the first lines and each extending in a second direction intersecting the first direction; a plurality of memory cells located at intersection regions between the first lines and the second lines in the cell region; and a first insulating layer located between the plurality of first lines, between the plurality of second lines, or between the plurality of first lines and the plurality of second lines in the first cell region. The first insulating layer is located between the first wires and the second wires in the second unit region. When the first insulating layer is located between the first wires, the first capacitance is smaller than the second capacitance. The first capacitance is generated by a first adjacent portion of the first wires in the first unit region and a first portion of the first insulating layer. The second capacitance is generated by a second adjacent portion of the first wires in the second unit region and a first portion of the second insulating layer. Furthermore, when the first insulating layer is located between the second wires, the third capacitance is smaller than the fourth capacitance. The third capacitance is generated by a first adjacent portion of the second wires in the first unit region and a second portion of the first insulating layer. The fourth capacitance is generated by a second adjacent portion of the second wires in the second unit region and a second portion of the second insulating layer.

[0008] In one embodiment, a method for manufacturing an electronic device including a semiconductor memory includes: providing a substrate including a peripheral circuit region and a cell region, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; forming a plurality of stacked structures on the substrate, each of the plurality of stacked structures extending in a first direction, each of the stacked structures including a first line and an initial memory cell disposed on the first line; forming a first insulating material layer filling the spaces between the stacked structures; replacing one or more portions of the first insulating material layer in the first cell region with a second insulating material layer having a dielectric constant lower than that of the first insulating material layer; forming a plurality of second lines on the stacked structures, the first insulating material layer, and the second insulating layer, each of the plurality of second lines extending in a second direction; and forming the plurality of memory cells by etching the initial memory cells exposed by the second lines.

[0009] In one embodiment, a method for manufacturing an electronic device including a semiconductor memory includes: providing a substrate including a peripheral circuit region and a cell region, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; forming a plurality of stacked structures on the substrate, each of the plurality of stacked structures extending in a first direction, each of the stacked structures including a first line and an initial memory cell disposed on the first line; forming a first insulating material layer filling between the stacked structures; forming a plurality of second lines on the stacked structures and the first insulating material layer, each of the plurality of second lines extending in a second direction; forming a plurality of memory cells by etching the initial memory cells exposed by the second lines; forming a third insulating material layer filling between the second lines in the first direction and between the memory cells; and replacing one or more portions of the third insulating material layer in the first cell region with a fourth insulating material layer having a dielectric constant lower than that of the third insulating material layer. Attached Figure Description

[0010] Figure 1 This is a plan view illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2A It is along Figure 1 The cross-sectional view taken by line AA′. Figure 2B It is along Figure 1 The cross-sectional view taken from line BB′.

[0012] Figure 3A This is a view showing how the capacitance generated by the wires and the insulating material between them changes according to the dielectric constant of the insulating material.

[0013] Figure 3B This is a view showing the current supplied to the storage cell based on the capacitance generated by the wires and the insulating material therebetween.

[0014] Figure 3C This is a view showing the fault cell bit of the capacitance generated by the wires and the insulating material between them.

[0015] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B It shows the manufacturing process. Figure 1 , Figure 2A and Figure 2B A cross-sectional view of an example of a method for storing storage devices.

[0016] Figure 12A , 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a storage device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0017] Figure 18A and Figure 18B This is a cross-sectional view illustrating a storage device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0018] Figure 19A and Figure 19B This is a cross-sectional view showing a storage device according to another embodiment of the present disclosure.

[0019] Figure 20 This is an example of a configuration diagram of a microprocessor that implements a memory circuitry based on the disclosed technology.

[0020] Figure 21 This is an example of a processor configuration diagram that implements a storage circuit system based on the disclosed technology.

[0021] Figure 22 This is an example of a system configuration diagram for implementing a storage circuit system based on the disclosed technology.

[0022] Figure 23 This is an example of a configuration diagram of a storage system based on the disclosed technology that implements the storage circuit system. Detailed Implementation

[0023] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0024] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated to clearly show certain features of the described embodiments. When a specific example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positional relationship of these layers or the order in which these layers are arranged as shown reflects a specific implementation of the described or illustrated example, and different relative positioning relationships or orders of arrangement of these layers are possible. Furthermore, the example of a described or illustrated multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when a first layer in a described or illustrated multilayer structure is referred to as being "on" or "above" a second layer or "on" or "above" a substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0025] Figure 1 This is a plan view illustrating a storage device according to an embodiment of the present disclosure. Figure 2A It is along Figure 1 The cross-sectional view taken by line AA′, and Figure 2B It is along Figure 1 The cross-sectional view taken from line BB′.

[0026] refer to Figure 1 , Figure 2A and Figure 2B The storage device in this embodiment may include a substrate 100, a first line 120 disposed on the substrate 100 and extending in a first direction, a second line 150 disposed on the first line 120 and extending in a second direction intersecting the first direction, and a storage cell 130 located at each intersection region between the first line 120 and the second line 150.

[0027] The substrate 100 may include a semiconductor material such as silicon. Furthermore, the substrate 100 may include a cell region CA and peripheral circuit regions PA1 and PA2. The cell region CA may be a region in which a memory cell 130 is disposed, and the peripheral circuit regions PA1 and PA2 may be regions in which a driving circuit (not shown) for driving the memory cell 130 is disposed. Although the memory cell 130 is disposed on the substrate 100 of the cell region CA, the driving circuit may be formed in the substrate 100 of the peripheral circuit regions PA1 and PA2.

[0028] exist Figure 1In the embodiments described, in the plan view, the cell region CA can have a rectangular shape, and four cell regions CA can be arranged to be spaced apart from each other in a 2×2 shape along the first and second directions. Furthermore, in the plan view, peripheral circuit regions PA1 and PA2 can be located between these cell regions CA and can have a cross shape or a grid shape. However, the embodiments of this disclosure are not limited to this, and the number and arrangement of cell regions CA and peripheral circuit regions PA1 and PA2 can be modified in various ways. For ease of description, among the peripheral circuit regions PA1 and PA2, the region extending in the second direction and located between the two cell regions CA arranged along the first direction will be referred to as the first peripheral circuit region PA1, and the region extending in the first direction and located between the two cell regions CA arranged along the second direction will be referred to as the second peripheral circuit region PA2.

[0029] Additionally, the cell region CA may include: a first cell region CA1, which is relatively close to the peripheral circuit regions PA1 and PA2; and a second cell region CA2, which is relatively far from the peripheral circuit regions PA1 and PA2. Specifically, the first cell region CA1 may be configured to be closer to one or both of the peripheral circuit regions PA1 and PA2 than the second cell region CA2. In one embodiment, the first cell region CA1 may include: a first plurality of storage cells, each storage cell being spaced apart from a corresponding one of the first contact plugs 110 by a first distance in a first direction and spaced apart from a corresponding one of the second contact plugs 140 by a second distance in a second direction, such that the sum of the first distance and the second distance is equal to or less than a given distance. In this embodiment, the second cell region CA2 includes: a second plurality of storage cells, each storage cell being spaced apart from a corresponding one of the first contact plugs 110 by a third distance in a first direction and spaced apart from a corresponding one of the second contact plugs 140 by a fourth distance in a second direction, such that the sum of the third distance and the fourth distance exceeds a given distance. Therefore, the electrical path between the storage cell 130 of the first unit region CA1 and the driving circuit of the peripheral circuit regions PA1 and PA2 can be shorter than the electrical path between the storage cell 130 of the second unit region CA2 and the driving circuit of the peripheral circuit regions PA1 and PA2. In one embodiment, the virtual boundary line VL separating the first unit region CA1 and the second unit region CA2 can extend in a diagonal direction intersecting the first and second directions. For example, the first unit region CA1 may include: a first plurality of storage cells, each storage cell being spaced apart by a first distance in a first direction from a first boundary between the peripheral circuit region PA1 and the first unit region CA1 and by a second distance in a second direction from a second boundary between the peripheral circuit region PA2 and the first unit region CA1, such that the sum of the first distance and the second distance is equal to or less than a given distance. The second unit region CA2 may include: a second plurality of storage cells, each storage cell being spaced apart by a third distance in a first direction from a first boundary and by a fourth distance in a second direction from a second boundary, such that the sum of the third distance and the fourth distance exceeds a given distance. However, embodiments of this disclosure are not limited thereto, and the boundary line VL can be determined differently, taking into account the distance between the storage cell 130 and the peripheral circuit regions PA1 and PA2.

[0030] The first line 120 may extend along a first direction through the cell region CA and the first peripheral circuit region PA1. The first line 120 may serve as a word line or a bit line. The first line 120 may be electrically connected to a portion of the substrate 100 via a first contact plug 110, for example, electrically connected to a drive circuit formed in the substrate 100 within the first peripheral circuit region PA1, the first contact plug 110 being disposed in the first peripheral circuit region PA1 and connected below the first line 120. The first contact plug 110 may be formed to penetrate a first interlayer insulating layer 160 between the first line 120 and the substrate 100. The first interlayer insulating layer 160 may include various insulating materials, such as silicon oxide, silicon nitride, or combinations thereof. The first line 120 and the first contact plug 110 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof. Figure 1 , Figure 2A and Figure 2B In some embodiments, a plurality of first lines 120 and a plurality of first contact plugs 110 may be connected in a one-to-one correspondence. Furthermore, in a plan view, the first contact plugs 110 may be arranged in a zigzag shape along a second direction. This is to ensure a gap between adjacent first contact plugs 110 in the second direction. However, embodiments of this disclosure are not limited to this, and various modifications can be made to the number and arrangement of the first lines 120 and the first contact plugs 110.

[0031] The second line 150 may extend along a second direction through the cell region CA and the second peripheral circuit region PA2. When the first line 120 is used as a word line, the second line 150 may be used as a bit line. Alternatively, when the first line 120 is used as a bit line, the second line 150 may be used as a word line. The second line 150 may be electrically connected to a portion of the substrate 100 via a second contact plug 140, for example, to a drive circuit formed in the substrate 100 within the second peripheral circuit region PA2, the second contact plug 140 being disposed in the second peripheral circuit region PA2 and connected below the second line 150. The second contact plug 140 may be formed to penetrate a first interlayer insulating layer 160 and a second interlayer insulating layer 170 between the second line 150 and the substrate 100. The second interlayer insulating layer 170 may comprise various insulating materials, such as silicon oxide, silicon nitride, or combinations thereof. The second wire 150 and the second contact plug 140 may comprise various conductive materials, such as metals like platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof. Figure 1 , Figure 2A and Figure 2B In some embodiments, a plurality of second lines 150 and a plurality of second contact plugs 140 may be connected in a one-to-one correspondence. Furthermore, in a plan view, the second contact plugs 140 may be arranged in a zigzag pattern along a first direction. This is to ensure a gap between adjacent second contact plugs 140 in the first direction. However, embodiments of this disclosure are not limited thereto, and various modifications can be made to the number and arrangement of the second lines 150 and the second contact plugs 140.

[0032] exist Figure 1 , Figure 2A and Figure 2B In one embodiment, the second interlayer insulating layer 170 may include a first insulating layer 170-1 of the first cell region CA1 and a second insulating layer 170-2 of the second cell region CA2. The first insulating layer 170-1 may cover the side surfaces of the first line 120, the storage cell 130, and the second line 150 in the first cell region CA1. Therefore, the first insulating layer 170-1 may be located between adjacent first lines 120, adjacent storage cells 130, and adjacent second lines 150 in the first cell region CA1. Furthermore, the second insulating layer 170-2 may cover the side surfaces of the first line 120, the storage cell 130, and the second line 150 in the second cell region CA2. Therefore, the second insulating layer 170-2 may be located between adjacent first lines 120, adjacent storage cells 130, and adjacent second lines 150 in the second cell region CA2.

[0033] Here, the first insulating layer 170-1 may include an insulating material having a dielectric constant k lower than that of the second insulating layer 170-2. As an example, the first insulating layer 170-1 may include a low-k material whose dielectric constant is lower than that of standard silicon oxide (SiO2). The term "standard silicon oxide" as used herein may refer to silicon oxide (e.g., silicon dioxide) formed using various conventional processes in the semiconductor manufacturing field. The dielectric constant of the low-k material may be less than 3.9, or even less than 2.7.

[0034] Furthermore, as an example, the elements constituting the first insulating layer 170-1 can be the same as those constituting the second insulating layer 170-2. For example, when the second insulating layer 170-2 comprises standard silicon oxide, the first insulating layer 170-1 can also comprise silicon oxide. Through heat treatment, the k-value of the silicon oxide used to form the first insulating layer 170-1 can be lower than the k-value of the standard silicon oxide used to form the second insulating layer 170-2. This will be described later in the process of describing the method of manufacturing the memory device.

[0035] Alternatively, as another example, the elements constituting the first insulating layer 170-1 may be different from the elements constituting the second insulating layer 170-2. For example, when the second insulating layer 170-2 comprises standard silicon oxide, the first insulating layer 170-1 may comprise: SiCOH, silsesquioxane (HSQ), methylsilsesquioxane (MSQ), SiCH, SiCNH, or combinations thereof.

[0036] Storage cell 130 can be arranged in cell region CA at the intersection area between first line 120 and second line 150. Storage cell 130 can store different data depending on the voltage or current applied to first line 120 and second line 150. As an example, storage cell 130 may include a variable resistor element that stores different data by switching between different resistance states according to the voltage or current applied to first line 120 and second line 150. Furthermore, as an example, storage cell 130 may include a multilayer structure including a lower electrode layer 131, a selection element layer 133, an intermediate electrode layer 135, a variable resistor layer 137, and an upper electrode layer 139.

[0037] The lower electrode layer 131 and the upper electrode layer 139 may be located at the lower end and upper end of the memory cell 130, respectively, and serve to transmit the voltage or current required for the operation of the memory cell 130. The intermediate electrode layer 135 serves to electrically connect the select element layer 133 and the variable resistor layer 137 while physically separating them. The lower electrode layer 131, the intermediate electrode layer 135, or the upper electrode layer 139 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), or metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN), or combinations thereof. Alternatively, the lower electrode layer 131, the intermediate electrode layer 135, or the upper electrode layer 139 may include carbon electrodes.

[0038] The selector layer 133 can substantially prevent current leakage that may occur between memory cells 130 sharing the first line 120 or the second line 150. To this end, the selector layer 133 can have threshold switching characteristics, that is, it substantially blocks or limits current when the applied voltage is less than a predetermined threshold, and allows a sudden increase in current when the applied voltage is greater than the threshold. This threshold can be referred to as the threshold voltage, and the selector layer 133 can be implemented in an on or off state based on the threshold voltage. The selector layer 133 may include diodes, OTS (bidirectional threshold switching) materials such as chalcogenide materials, MIEC (mixed ionic electronic conduction) materials such as metal chalcogenide materials, MIT (metal-insulator transition) materials such as NbO2 or VO2, or tunneling insulating materials with a relatively wide gap such as SiO2 or Al2O3.

[0039] The variable resistance layer 137 may be a portion of the storage cell 130 that stores data. For this purpose, the variable resistance layer 137 may have variable resistance characteristics that switch between different resistance states according to the applied voltage. The variable resistance layer 137 may have a single-layer structure or a multi-layer structure, which includes at least one of the materials used in RRAM, PRAM, MRAM, or FRAM, namely, metal oxides such as perovskite-based oxides or transition metal oxides, and phase change materials such as chalcogenide-based materials, ferromagnetic materials, or ferroelectric materials.

[0040] However, embodiments of this disclosure are not limited to the memory cell 130 having a layered structure. When the memory cell 130 is a variable resistor device, as long as it includes the variable resistor layer 137 necessary for data storage, the stacking order of the layers included in the memory cell 130 can be changed or at least one of the stacked layers can be omitted. As an example, at least one of the lower electrode layer 131, the select element layer 133, the intermediate electrode layer 135, and the upper electrode layer 139 can be omitted. Alternatively, as an example, the positions of the select element layer 133 and the variable resistor layer 137 can be reversed. Alternatively, as an example, one or more layers (not shown) can be added to the memory cell 130 to improve the manufacturing process or characteristics of the memory cell 130.

[0041] The effects of the above-described storage device will be described below in comparison with a comparative example.

[0042] In the comparative example memory device, regardless of the distance between the memory cell and the peripheral circuitry area, an interlayer insulation layer containing the memory cell and its upper and lower traces can be formed from a single insulating material. In this comparative example, to drive the memory cell relatively far from the peripheral circuitry area, it may be necessary to reduce the resistance of the upper and lower traces or supply a large current through the upper and lower traces. However, there are limits to reducing the resistance of the upper and lower traces. Furthermore, when supplying a large current through the upper and lower traces, excessive overshooting current or spike current may flow into the memory cell relatively close to the peripheral circuitry area, causing the memory cell to fail to operate.

[0043] However, as in Figure 1 , Figure 2A and Figure 2B As in the embodiments described above, the problem of the comparative example can be solved when the first insulating layer 170-1 of the first cell region CA1 has a lower dielectric constant than the second insulating layer 170-2 of the second cell region CA2. Specifically, when the first insulating layer 170-1 with a low dielectric constant is located between adjacent first lines 120 in the first cell region CA1, the capacitance generated by the first lines 120 and the first insulating layer 170-1 can be reduced. For example, the capacitance defined by the adjacent first lines 120 and a portion of the first insulating layer 170-1 between the adjacent first lines 120 can be relatively smaller than the capacitance in the comparative example, thereby reducing the magnitude of overshoot current or spike current flowing through the memory cell relatively close to the peripheral circuit region, to substantially prevent memory cell malfunction. On the other hand, since the second insulating layer 170-2 with a higher dielectric constant than the first insulating layer 170-1 is located between adjacent first lines 120 in the second cell region CA2, the capacitance generated by the first lines 120 and the second insulating layer 170-2 can be increased compared to the first cell region CA1. Similarly, when a first insulating layer 170-1 with a low dielectric constant is located between adjacent second lines 150 in the first cell region CA1, the capacitance generated by the second lines 150 and the first insulating layer 170-1 can be reduced. For example, the capacitance defined by the adjacent second lines 150 and a portion of the first insulating layer 170-1 between the adjacent second lines 150 can be relatively small compared to the capacitance in the comparative example. On the other hand, since a second insulating layer 170-2 with a higher dielectric constant than the first insulating layer 170-1 is located between adjacent second lines 150 in the second cell region CA2, the capacitance generated by the second lines 150 and the second insulating layer 170-2 can be increased compared to the first cell region CA1. The reduction in capacitance due to the reduction in dielectric constant has been experimentally confirmed, which will be referred to below. Figure 3A Describe it.

[0044] Figure 3A This is a view showing how the capacitance generated by the wires and the insulating material between them changes according to the dielectric constant of the insulating material.

[0045] refer to Figure 3A Case 1 shows the capacitance when the insulating material is standard silicon oxide, and cases 2 through 6 show the capacitance when various low-k materials are used as the insulating material. The results show that the capacitance decreases as the dielectric constant of the insulating material decreases.

[0046] As described above, when the capacitance in the first cell region CA1 decreases, the current supplied to the memory cell 130 in the first cell region CA1 can be limited. On the other hand, the current supplied to the memory cell 130 in the second cell region CA2 can be greater than the current supplied to the first cell region CA1. The current limitation caused by the decrease in capacitance has been experimentally verified, and this will be referred to... Figure 3B Describe it.

[0047] Figure 3B This is a view showing the current supplied to the storage cell based on the capacitance generated by the wires and the insulating material therebetween. For example, Figure 3B The diagram illustrates the distribution of current magnitude, with the current supplied to cell regions relatively close to the peripheral circuit area (e.g., based on the capacitance defined by adjacent lines and the insulating material between them). Figure 1 The storage unit in the first unit region CA1).

[0048] Reference Figure 3B Case 1 shows the case where the insulating material is standard silicon dioxide, and cases 2 through 4 show the cases where various low-k materials are used as the insulating material. Therefore, it can be seen that the current supplied in case 1, which has a relatively large capacitance, is large, while the current supplied in cases 2 through 4, which have relatively small capacitance, is small.

[0049] As a result, while supplying sufficient current to the memory cell 130 in the second cell region CA2, the following phenomenon can be reduced / prevented: the memory cell 130 in the first cell region CA1 may fail due to excessive current flowing into it. Therefore, the operating characteristics of the memory device can be improved. The reduction in failure rate of the capacitor-based memory cell 130 has been experimentally verified, and will be referred to below. Figure 3C Describe it.

[0050] Figure 3CThis is a view showing the fault cell bits based on the capacitance generated by the wires and the insulating material between them.

[0051] refer to Figure 3C The first case, CASE 1, shows the case where the capacitance is at its maximum and the number of faulty cell bits is also at its maximum. The second case, CASE 2, shows the case where the capacitance is reduced compared to the first case, CASE 1, and the number of faulty cell bits is also reduced. The third case, CASE 3, shows the case where the capacitance is at its minimum and the number of faulty cell bits is also at its minimum. As a result, it can be seen that the number of faulty cell bits increases proportionally to the capacitance. Since the capacitance in the embodiment of this application is reduced compared to the capacitance in the comparative example, the operating characteristics of the memory device according to this embodiment of the application can be improved compared to the operating characteristics of the memory device in the comparative example.

[0052] Figures 4A to 11B It is a cross-sectional view that shows the process used in manufacturing. Figure 1 , Figure 2A and Figure 2B Examples of methods for storage devices. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A Based on along Figure 1 The cross section cut by line AA′ is shown, and Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B Based on along Figure 1 Another cross-section of line BB′ is shown.

[0053] refer to Figure 4A and Figure 4B A first interlayer insulating layer 160 can be formed on a substrate 100 including a first unit region CA1, a second unit region CA2, a first peripheral circuit region PA1, and a second peripheral circuit region PA2.

[0054] Subsequently, a first contact hole 105 exposing a portion of the substrate 100 can be formed by selectively etching the first interlayer insulating layer 160 of the first peripheral circuit region PA1. Then, the first contact plug 110 can be formed by depositing a conductive material having a thickness sufficient to fill the first contact hole 105, and performing a planarization process such as CMP (chemical mechanical polishing) until the upper surface of the first interlayer insulating layer 160 is exposed.

[0055] Subsequently, a stacked structure of a first line 120 and an initial memory cell 130A can be formed on the first interlayer insulating layer 160 on which the first contact plug 110 is formed. Multiple stacked structures can be formed. The stacked structure of the first line 120 and the initial memory cell 130A can be formed by depositing a conductive layer for forming the first line 120 and a material layer for forming the initial memory cell 130A, and etching the conductive layer and the material layer using a mask pattern (not shown) having a line shape extending in a first direction as an etch stop layer. Therefore, the first line 120 can have a line shape extending in a first direction when it overlaps and connects with the first contact plug 110, and the initial memory cell 130A can have a line shape extending in a first direction when it overlaps with the first line 120. The initial memory cell 130A may include a stacked structure of an initial lower electrode layer 131A, an initial select element layer 133A, an initial intermediate electrode layer 135A, an initial variable resistor layer 137A, and an initial upper electrode layer 139A.

[0056] refer to Figure 5A and Figure 5B A first insulating layer 172 may be formed over the first interlayer insulating layer 160 to fill the space between the stacked structure of the first line 120 and the initial memory cell 130A. The first insulating layer 172 may be formed by depositing an insulating material having a thickness sufficient to cover the initial memory cell 130A, and performing a planarization process until the upper surface of the initial memory cell 130A is exposed. The first insulating layer 172 may be formed by a spin-coating (SOC) method and may comprise standard silicon oxide. However, embodiments of this disclosure are not limited thereto, and various deposition methods and insulating materials may be used when forming the first insulating layer 172. Here, the first insulating layer 172 may include a material whose k-value decreases during heat treatment.

[0057] Subsequently, a second contact hole 145 exposing a portion of the substrate 100 can be formed by selectively etching the first insulating material layer 172 and the first interlayer insulating layer 160 in the second peripheral circuit region PA2. Then, a second contact plug 140 filling the second contact hole 145 can be formed.

[0058] refer to Figure 6A and Figure 6B The first mask pattern M1 can be formed in Figure 5A and Figure 5B The resulting structure is used to cover the second unit region CA2 while opening the first unit region CA1. Figure 6A and Figure 6BIn the embodiments shown, the first mask pattern M1 also covers the first peripheral circuit region PA1 and the second peripheral circuit region PA2. However, the embodiments of this disclosure are not limited thereto, and in another embodiment, the first peripheral circuit region PA1 and the second peripheral circuit region PA2 may be partially or completely exposed without being covered by the first mask pattern M1.

[0059] Subsequently, a heat treatment process can be performed on the first unit region CA1 exposed by the first mask pattern M1 (see arrow). As an example, the heat treatment process may include ultraviolet (UV) annealing. UV annealing can be performed for 2 to 5 minutes at a temperature range of 200°C to 300°C and a power range of 40% to 80% of the maximum power intensity. It has been experimentally confirmed that the k-value of the standard silicon oxide (SiO2) used to form the first insulating material layer 172 decreases during UV annealing, as will be described with reference to [Table 1] below.

[0060] [Table 1]

[0061] UV 200C2M40% 200C3M40% 200C4M40% 300C5M40% k 3.27 3.26 3.22 2.78

[0062] Referring to Table 1 above, when UV annealing was performed at 200°C for 2 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 3.27. Furthermore, when UV annealing was performed at 200°C for 3 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 3.26. Additionally, when UV annealing was performed at 200°C for 4 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 3.22. Furthermore, when UV annealing was performed at 300°C for 5 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film significantly decreased to approximately 2.78. As a result, it can be seen that the k-value of the SiO2 film decreases during UV annealing, and specifically, the k-value decreases with increasing annealing time or temperature, or both.

[0063] Furthermore, it has been confirmed in another experiment that the k value of the SiO2 film used to form the first insulating material layer 172 decreases during UV annealing, which will be described with reference to [Table 2] below.

[0064] [Table 2]

[0065] UV 200C4M40% 300C5M40% 300C5M60% 300C5M80% k 2.76 2.65 2.57 2.52

[0066] Referring to Table 2 above, when UV annealing was performed at 200°C for 4 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 2.76. Furthermore, when UV annealing was performed at 300°C for 5 minutes at approximately 40% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 2.65. Additionally, when UV annealing was performed at 300°C for 5 minutes at approximately 60% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 2.57. Furthermore, when UV annealing was performed at 300°C for 5 minutes at approximately 80% of the maximum power intensity, the k-value of the SiO2 film decreased to approximately 2.52. As a result, it can be seen that the k-value of the SiO2 film decreases during UV annealing, and specifically, the k-value decreases as one or more of the annealing time, temperature, and power increase.

[0067] However, the embodiments disclosed herein are not limited thereto, and any heat treatment process can be performed on the first cell region CA1 as long as the k value of the first insulating material layer 172 is reduced. For example, a baking process, a heat treatment process using a gas such as helium or nitrogen or plasma, or a heat treatment process involving ion implantation can be performed.

[0068] exist Figure 7A and Figure 7B The middle shows Figure 6A and Figure 6B The resulting structure.

[0069] refer to Figure 7A and Figure 7B The first insulating material layer 172 is subjected to Figure 6A and Figure 6B The UV annealing effect, resulting in one or more portions having different characteristics (e.g., a lower dielectric constant k), will be referred to as the second insulating layer 174. The remaining portion of the first insulating layer 172 that is not significantly affected by UV annealing is indicated by reference numeral 172A. The second insulating layer 174 may fill between the first line 120 and the memory cell 130 in the first cell region CA1, and may have a k value smaller than that of the first insulating layer 172A. The first insulating layer 172A may fill between the first line 120 and the memory cell 130 in the second cell region CA2. Because the initial upper electrode layer 139A is located at the top of the initial memory cell 130A during UV annealing, the initial variable resistance layer 137A can be unaffected by UV annealing, thereby maintaining its characteristics.

[0070] After UV annealing, the first mask pattern M1 can be removed.

[0071] refer to Figure 8A and Figure 8B The second line 150 can be formed in Figure 7A and Figure 7B The second line 150 can be formed by depositing a conductive layer for forming the second line 150, and etching the conductive layer using a linear mask pattern (not shown) extending in the second direction as an etch stop layer.

[0072] Subsequently, the memory cell 130 can be formed by etching the initial memory cell 130A exposed by the second line 150. As a result of this process, the memory cell 130 can have an island shape in the plan view at each intersection region between the first line 120 and the second line 150. In a first direction, the two sidewalls of the memory cell 130 can be aligned with the two sidewalls of the second line 150, and in a second direction, the two sidewalls of the memory cell 130 can be aligned with the two sidewalls of the first line 120. The memory cell 130 may include a stacked structure of a lower electrode layer 131, a select element layer 133, an intermediate electrode layer 135, a variable resistor layer 137, and an upper electrode layer 139.

[0073] In the process of forming the memory cell 130, the first insulating material layer 172A and the second insulating material layer 174 exposed by the second line 150 can also be etched to form a first insulating material pattern 172B and a second insulating material pattern 174A. The space between the first lines 120 in the first cell region CA1 can be filled with the second insulating material pattern 174A, and the space between the first lines 120 in the second cell region CA2 can be filled with the first insulating material pattern 172B. Furthermore, in the first cell region CA1, the space between the memory cells 130 in the second direction can be filled with the second insulating material pattern 174A, and the space between the memory cells 130 in the first direction can be empty. Furthermore, in the second cell region CA2, the space between the memory cells 130 in the second direction can be filled with the first insulating material pattern 172B, and the space between the memory cells 130 in the first direction can be empty.

[0074] refer to Figure 9A and Figure 9B The third insulating material layer 176 can be formed in Figure 8A and Figure 8BThe resulting structure is used to fill the space between the second lines 150 and the space between the storage cells 130 in the first direction. A third insulating layer 176 can be formed by depositing an insulating material with a thickness sufficient to cover the second lines 150, and performing a planarization process until the upper surface of the second lines 150 is exposed. The third insulating layer 176 can be formed by a spin-coating (SOC) method and can include standard silicon oxide. The third insulating layer 176 can be formed from the same material as the first insulating material pattern 172B. However, embodiments of this disclosure are not limited thereto, and various deposition methods and insulating materials can be used when forming the third insulating layer 176. Here, the third insulating layer 176 may include a material whose k-value decreases during heat treatment.

[0075] refer to Figure 10A and Figure 10B The second mask pattern M2 can be formed in Figure 9A and Figure 9B The resulting structure is used to cover the second unit region CA2 while opening the first unit region CA1. Figure 10A and Figure 10B In the embodiments shown, the second mask pattern M2 also covers the first peripheral circuit region PA1 and the second peripheral circuit region PA2. However, the embodiments of this disclosure are not limited thereto, and in another embodiment, the first peripheral circuit region PA1 and the second peripheral circuit region PA2 may be partially or completely exposed without being covered by the second mask pattern M2.

[0076] Subsequently, a heat treatment process (see arrow) can be performed on the first unit region CA1 exposed by the second mask pattern M2. As an example, the heat treatment process may include UV annealing. UV annealing can be performed for 2 to 5 minutes at a temperature range of 200°C to 300°C and a power range of 40% to 80% of the maximum power intensity. During UV annealing, the k-value of the third insulating material layer 176 in the first unit region CA1 can be reduced.

[0077] In Figure 11A and Figure 11B It shows Figure 10A and Figure 10B The resulting structure.

[0078] Reference Figure 11A and Figure 11B ,by Figure 10A and Figure 10BThe UV annealing effect on one or more portions of the third insulating layer 176, which have different properties (e.g., a lower dielectric constant k), will be referred to as the fourth insulating layer 178. The fourth insulating layer 178 may be formed of the same material as the second insulating pattern 174A. The remaining portion of the third insulating layer 176 that is not significantly affected by UV annealing is indicated by reference numeral 176A. In the first cell region CA1, the fourth insulating layer 178 may fill between the second line 150 and the memory cell 130 in a first direction and may have a k value smaller than that of the third insulating layer 176A. In the second cell region CA2, the third insulating layer 176A may fill between the second line 150 and the memory cell 130 in a first direction. Because the upper electrode layer 139 is located at the top of the memory cell 130 during UV annealing, the variable resistance layer 137 may be unaffected by UV annealing, thereby maintaining its properties.

[0079] After UV annealing, the second mask pattern M2 can be removed.

[0080] Through the above process, it is possible to obtain the same as Figure 1 , Figure 2A and Figure 2B The memory device described herein is substantially the same as the memory device described herein. The second insulating material pattern 174A and the fourth insulating material layer 178 of the first cell region CA1 can be with Figure 2A and Figure 2B The first insulating material layer 170-1 is basically the same, and the first insulating material pattern 172B and the third insulating material layer 176A of the second unit region CA2 can be the same as those of the first insulating material layer 170-1. Figure 2A and Figure 2B The second insulating material layer 170-2 is basically the same.

[0081] Figures 12A to 17B This is a cross-sectional view illustrating a storage device and a method of manufacturing the same according to another embodiment of the present disclosure. Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A Based on along Figure 1 The cross section cut by line AA′ is shown, and Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B Based on along Figure 1 Another cross-section of line BB′ is shown. The differences from the embodiment described above will be highlighted.

[0082] refer to Figure 12A and Figure 12B It can perform the above Figures 4A to 5B The process is essentially the same as that used in other processes. As a result, the following can be provided: a substrate 200 including a first cell region CA1, a second cell region CA2, a first peripheral circuit region PA1, and a second peripheral circuit region PA2; a first interlayer insulating layer 260 disposed on the substrate 200; a first contact plug 210 connected to a portion of the substrate 200 via the first interlayer insulating layer 260 in the first peripheral circuit region PA1; a stacked structure of a first line 220 and an initial memory cell 230A disposed on the first interlayer insulating layer 260 and extending in a first direction to connect to the first contact plug 210; a first insulating material layer 272 disposed on the first interlayer insulating layer 260 and filling the space between the stacked structure of the first line 220 and the initial memory cell 230A; and a second contact plug 240 connected to a portion of the substrate 200 via the first interlayer insulating layer 260 and the first insulating material layer 272 in the second peripheral circuit region PA2. Here, the initial memory cell 230A may include a stacked structure of an initial lower electrode layer 231A, an initial selection element layer 233A, an initial intermediate electrode layer 235A, an initial variable resistor layer 237A, and an initial upper electrode layer 239A.

[0083] Subsequently, a first mask pattern M1 can be formed on the above structure, which opens the first unit region CA1 while covering the second unit region CA2.

[0084] refer to Figure 13A and Figure 13B The first insulating material layer 272 exposed by the first mask pattern M1 can be removed. The removal of the first insulating material layer 272 can be performed using an etching method such as an etching gas, which selectively removes only the insulating material, and thus, the first line 220 and the initial memory cell 230A of the first cell region CA1 can be substantially maintained. The space formed by removing the first insulating material layer 272 in the first cell region CA1 will be referred to as the first space S1. Furthermore, the remaining portion of the first insulating material layer 272 that was not removed in this process and remains in the second cell region CA2 is indicated by reference numeral 272A.

[0085] After the first space S1 is formed, the first mask pattern M1 can be removed.

[0086] refer to Figure 14A and Figure 14B It can form a filler Figure 13A and Figure 13BThe first space S1 contains a second insulating material layer 274. The second insulating material layer 274 may have a lower k value than the first insulating material layer 272A. For example, when the first insulating material layer 272A comprises standard silicon oxide, the second insulating material layer 274 may comprise SiCOH, HSQ, MSQ, SiCH, SiCNH, or combinations thereof.

[0087] The second insulating material layer 274 can be formed by depositing material sufficient to cover... Figure 13A and Figure 13B The thickness of the insulating material of the resulting structure is increased, and a planarization process is performed until the upper surface of the initial memory cell 230A is exposed.

[0088] refer to Figure 15A and Figure 15B , can Figure 14A and Figure 14B A second line 250 is formed on top of the obtained structure.

[0089] Subsequently, the memory cell 230 can be formed by etching the initial memory cell 230A exposed by the second line 250. The memory cell 230 may include a stacked structure of a lower electrode layer 231, a select element layer 233, an intermediate electrode layer 235, a variable resistor layer 237, and an upper electrode layer 239.

[0090] In the process of forming the memory cell 230, the first insulating material layer 272A and the second insulating material layer 274 exposed by the second line 250 can also be etched to form the first insulating material pattern 272B and the second insulating material pattern 274A.

[0091] refer to Figure 16A and Figure 16B A third insulating material layer 276A can be formed to fill the space between the second lines 250 and the space between the storage cells 230 in the first direction. Then, the second space S2 can be formed by removing the third insulating material layer 276A using a second mask pattern M2 that covers the second cell region CA2 while opening the first cell region CA1.

[0092] refer to Figure 17A and Figure 17B It can form a filler Figure 16A and Figure 16B The fourth insulating material layer 278 is located in the second space S2. The fourth insulating material layer 278 may have a lower k value than the third insulating material layer 276A. For example, when the third insulating material layer 276A comprises standard silicon oxide, the fourth insulating material layer 278 may comprise SiCOH, HSQ, MSQ, SiCH, SiCNH, or combinations thereof.

[0093] Through the above process, it is possible to obtain the same as Figure 1 , Figure 2A and Figure 2B The memory device described herein is substantially the same as the memory device described herein. The second insulating material pattern 274A and the fourth insulating material layer 278 of the first cell region CA1 can be compared with... Figure 2A and Figure 2B The first insulating material layer 170-1 is basically the same, and the first insulating material pattern 272B and the third insulating material layer 276A of the second unit region CA2 can be the same as those of the first insulating material layer 170-1. Figure 2A and Figure 2B The second insulating material layer 170-2 is basically the same.

[0094] Furthermore, in the above embodiments, the following situation has been described: in the first unit region CA1, the low-k material is located between the first line (e.g., Figure 11A and Figure 11B The first line 120 and Figure 17A and Figure 17B The first line 220) between the second line (e.g., Figure 11A and Figure 11B The second line 150 and Figure 17A and Figure 17B Between the second lines 250 in the first cell region CA1. For example, in the above embodiment, the low-k material may be located between the first portions of the first lines or between the second portions of the plurality of second lines in the first cell region CA1, or both between the first portions of the first lines and between the second portions of the plurality of second lines. Adjacent pairs of the first portions of the first lines may be arranged to be spaced apart from each other in a second direction, and adjacent pairs of the second portions of the plurality of second lines may be arranged to be spaced apart from each other in a first direction. As a result, a relatively low capacitance associated with the low-k material may be formed between adjacent pairs of the first lines or between adjacent pairs of the second lines, or both between adjacent pairs of the first lines and between adjacent pairs of the second lines. In some cases, even if the low-k material is located between the first lines and / or between the second lines, the current supplied to the memory cells 130 or 230 of the first cell region CA1 can be limited to a desired extent. Reference will be made below. Figures 18A to 19B Describe these examples.

[0095] Figure 18A and Figure 18B This is a cross-sectional view illustrating a storage device and a method of manufacturing the same according to another embodiment of the present disclosure. Figure 18A Based on along Figure 1 The cross section intercepted by line AA′ is shown, and Figure 18B Based on along Figure 1 Another cross-section of line BB′ is shown. The differences from the embodiment described above will be highlighted.

[0096] refer to Figure 18A and Figure 18B The storage device may include: a substrate 300, which includes a first cell region CA1, a second cell region CA2, a first peripheral circuit region PA1, and a second peripheral circuit region PA2; a first line 320 extending over the substrate 300 in a first direction; a second line 350 extending over the first line 320 in a second direction; and storage cells 330 located at the intersection of the first line 320 and the second line 350. The storage cells 330 may include a multilayer structure, comprising a lower electrode layer 331, a selection element layer 333, an intermediate electrode layer 335, a variable resistor layer 337, and an upper electrode layer 339.

[0097] The first interlayer insulating layer 360 may be located between the substrate 300 and the first line 320 in the vertical direction. The first line 320 may be connected to a portion of the substrate 300 via a first contact plug 310 that penetrates the first interlayer insulating layer 360 in the first peripheral circuit region PA1.

[0098] Furthermore, in the vertical direction, the first insulating material layer 372, the second insulating material layer 374, and the third insulating material layer 376 may be located between the first line 320 and the second line 350. The second line 350 may be connected to a portion of the substrate 300 via a second contact plug 340 that penetrates the first insulating material layer 372 and the first interlayer insulating layer 360 in the second peripheral circuit region PA2.

[0099] Here, the first insulating material layer 372 can be filled between the storage cells 330 in the second direction, and simultaneously between the first lines 320 in the second cell region CA2. The second insulating material layer 374 can be filled between the storage cells 330 in the second direction, and simultaneously between the first lines 320 in the first cell region CA1. The third insulating material layer 376 can be filled between the storage cells 330 in the first direction, and simultaneously between the second lines 350 in the first cell region CA1 and the second cell region CA2. The k-value of the second insulating material layer 374 can be lower than the k-values ​​of the first insulating material layer 372 and the third insulating material layer 376.

[0100] It can be done in the above Figures 4A to 11B The manufacturing method of the embodiment is omitted Figures 10A to 11B The first insulating material layer to the third insulating material layers 372, 374 and 376 are formed using a specific process. Alternatively, the first insulating material layer to the third insulating material layer 372, 374 and 376 are formed using a specific process. Figures 12A to 17B The manufacturing method of the embodiment is executed Figures 12A to 16BThe process can form a first insulating material layer to a third insulating material layer 372, 374 and 376 without forming a second space S2.

[0101] according to Figure 18A and Figure 18B In one embodiment, a low-k material can be present between the first lines 320 in the first cell region CA1, and thus the capacitance caused by the low-k material can be reduced. For example, the first capacitance can be smaller than the second capacitance, the first capacitance being defined by a pair of first adjacent portions of the first line 320 in the first cell region CA1 and a portion of the second insulating material layer 374 disposed between the first adjacent portions of the first line 320, and the second capacitance being defined by a pair of second adjacent portions of the first line 320 in the second cell region CA2 and a portion of the first insulating material layer 372 disposed between the second adjacent portions of the first line 320.

[0102] Figure 19A and Figure 19B This is a cross-sectional view illustrating a storage device and a method of manufacturing the same according to another embodiment of the present disclosure. Figure 19A Based on along Figure 1 The cross section intercepted by line AA′ is shown, and Figure 19B Based on along Figure 1 Another cross-section of line BB′ is shown. The differences from the embodiment described above will be highlighted.

[0103] refer to Figure 19A and Figure 19B The storage device may include: a substrate 400, which includes a first cell region CA1, a second cell region CA2, a first peripheral circuit region PA1, and a second peripheral circuit region PA2; a first line 420 extending over the substrate 400 in a first direction; a second line 450 extending over the first line 420 in a second direction; and storage cells 430 located at the intersection of the first line 420 and the second line 450. The storage cells 430 may include a multilayer structure comprising a lower electrode layer 431, a selection element layer 433, an intermediate electrode layer 435, a variable resistor layer 437, and an upper electrode layer 439.

[0104] The first interlayer insulating layer 460 may be located vertically between the substrate 400 and the first line 420. The first line 420 may be connected to a portion of the substrate 400 via a first contact plug 410 that penetrates the first interlayer insulating layer 460 in the first peripheral circuit region PA1.

[0105] Furthermore, in the vertical direction, the first insulating material layer 472, the second insulating material layer 476, and the third insulating material layer 478 may be located between the first line 420 and the second line 450. The second line 450 may be connected to a portion of the substrate 400 via a second contact plug 440 that penetrates the first insulating material layer 472 and the first interlayer insulating layer 460 in the second peripheral circuit region PA2.

[0106] Here, the first insulating material layer 472 can be filled between the storage cells 430 in the second direction, and simultaneously between the first lines 420 in the first cell region CA1 and the second cell region CA2. The second insulating material layer 476 can be filled between the storage cells 430 in the first direction, and simultaneously between the second lines 450 in the second cell region CA2. The third insulating material layer 478 can be filled between the storage cells 430 in the first direction, and simultaneously between the second lines 450 in the first cell region CA1. The k-value of the third insulating material layer 478 can be lower than the k-value of the first insulating material layer 472 and the second insulating material layer 476.

[0107] It can be done in the above Figures 4A to 11B The manufacturing method of the embodiment is omitted Figures 6A to 7B The first insulating material layer to the third insulating material layers 472, 476, and 478 are formed using a specific process. Alternatively, they can be formed by... Figures 12A to 17B The manufacturing method of the embodiment is omitted Figure 12A and Figure 12B The formation process of the first mask pattern M1 and Figures 13A to 14B The process is used to form the first insulating material layer to the third insulating material layer 472, 476 and 478.

[0108] according to Figure 19A and Figure 19B In one embodiment, a low-k material can be present between the second lines 450 in the first cell region CA1, and thus the capacitance caused by the low-k material can be reduced. For example, the first capacitance can be smaller than the second capacitance, the first capacitance being defined by a pair of first adjacent portions of the second line 450 in the first cell region CA1 and a portion of the third insulating material layer 478 disposed between the first adjacent portions of the second line 450, and the second capacitance being defined by a pair of second adjacent portions of the second line 450 in the second cell region CA2 and a portion of the second insulating material layer 476 disposed between the second adjacent portions of the second line 450.

[0109] Figure 20 This is an example of a configuration diagram of a microprocessor that implements a storage circuit system based on the disclosed technology.

[0110] refer to Figure 20The microprocessor 1000 can perform a series of tasks for controlling and tuning the reception of data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a storage unit 1010, a processing unit 1020, and a control unit 1030, etc. The microprocessor 1000 can be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0111] Storage unit 1010 is a data storage component in microprocessor 1000, such as processor registers or registers. Storage unit 1010 may include various registers, such as data registers, address registers, and floating-point registers. Storage unit 1010 can temporarily store data processed by arithmetic unit 1020, the result data of the processed data, and the address of the data used for the processed data.

[0112] The memory cell 1010 may include one or more of the semiconductor devices described in the embodiments. For example, the memory cell 1010 may include: a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region relatively close to the peripheral circuit region and a second cell region relatively far from the peripheral circuit region; a plurality of first lines disposed on the substrate and extending in a first direction; a plurality of second lines disposed on the first lines and extending in a second direction intersecting the first direction; a plurality of memory cells located at the intersection regions between the first and second lines in the cell region; a first insulating layer located between the plurality of first lines, between the plurality of second lines, or both in the first cell region; and a second insulating layer located between the plurality of first lines and between the plurality of second lines in the second cell region, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer. This improves the operating characteristics of the memory cell 1010. Consequently, it improves the operating characteristics of the microprocessor 1000.

[0113] The arithmetic unit 1020 can perform arithmetic or logical operations based on the result of decoding the command by the control unit 1030. The arithmetic unit 1020 may include at least one arithmetic logic unit (ALU).

[0114] The control unit 1030 can receive signals from the storage unit 1010, the arithmetic unit 1020 and the external devices of the microprocessor 1000, extract and decode commands, control the input and output of signals of the microprocessor 1000, and perform processing represented by the program.

[0115] In addition to the storage unit 1010, the microprocessor 1000 according to this embodiment may further include a cache storage unit 1040, which can temporarily store data to be input from an external device or data to be output to an external device. In this case, the cache storage unit 1040 can exchange data with the storage unit 1010, the arithmetic unit 1020 and the control unit 1030 through the bus interface 1050.

[0116] Figure 21 This is an example of a processor configuration diagram that implements a storage circuit system based on the disclosed technology.

[0117] refer to Figure 21 The processor 1100 can improve performance and achieve versatility by including various functions in addition to those of the microprocessor 1000 described above. The processor 1100 may include a core unit 1110 serving as a microprocessor, a cache unit 1120 for temporarily storing data, and a bus interface 1130 for transferring data between internal and external devices. The processor 1100 may include various system-on-a-chip (SoCs), such as multi-core processors, graphics processing units (GPUs), and application processors (APs).

[0118] The core unit 1110 of this embodiment is the part that performs arithmetic and logical operations on data input from external devices, and may include a storage unit 1111, an arithmetic unit 1112, and a control unit 1113. The storage unit 1111, the arithmetic unit 1112, and the control unit 1113 may be substantially the same as the storage unit 1010, the arithmetic unit 1020, and the control unit 1030.

[0119] The cache storage unit 1120 is a component that temporarily stores data to compensate for the difference in data processing speed between the high-speed core unit 1110 and the low-speed external devices. The cache storage unit 1120 may include a primary storage unit 1121 and a secondary storage unit 1122. Furthermore, when higher storage capacity is required, the cache storage unit 1120 may include a tertiary storage unit 1123. The cache storage unit 1120 may include an increased number of storage units as needed. That is, the number of storage units included in the cache storage unit 1120 can be varied according to the design. The primary storage unit 1121, secondary storage unit 1122, and tertiary storage unit 1123 may store and distinguish data at the same or different speeds. When the speeds of the various storage units 1121, 1122, and 1123 differ, the primary storage unit 1121 may have the highest speed. At least one of the main storage section 1121, secondary storage section 1122, and tertiary storage section 1123 of the cache memory cell 1120 may include one or more of the semiconductor devices described above according to the embodiments. For example, the cache memory cell 1120 may include: a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region relatively close to the peripheral circuit region and a second cell region relatively far from the peripheral circuit region; a plurality of first lines disposed on the substrate and extending in a first direction; a plurality of second lines disposed on the first lines and extending in a second direction intersecting the first direction; a plurality of memory cells located at the intersection regions between the first and second lines in the cell region; a first insulating layer located between the plurality of first lines, between the plurality of second lines, or both between the plurality of first lines and between the plurality of second lines in the first cell region; and a second insulating layer located between the plurality of first lines and between the plurality of second lines in the second cell region, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer. This improves the operating characteristics of the cache memory cell 1120. As a result, the operating characteristics of the processor 1100 can be improved.

[0120] Although all the primary storage units 1121, secondary storage units 1122, and tertiary storage units 1123 are shown to be configured inside the cache storage unit 1120 in this embodiment, at least one of the primary storage units 1121, secondary storage units 1122, and tertiary storage units 1123 of the cache storage unit 1120 may be configured outside the core unit 1110 and may compensate for the difference in data processing speed between the core unit 1110 and external devices.

[0121] The bus interface 1130 is the part that connects the core unit 1110, the cache storage unit 1120 and external devices and allows for efficient data transfer.

[0122] The processor 1100 according to this embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or connected via a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the core units 1110 described above. The storage unit in each core unit 1110 may be configured to share storage units outside the core unit 1110 via the bus interface 1130.

[0123] The processor 1100 according to this embodiment may further include an embedded storage unit 1140 for storing data, a communication module unit 1150 capable of sending data to and receiving data from external devices via wired or wireless means, a memory control unit 1160 for driving external storage devices, and a media processing unit 1170 that processes data processed in the processor 1100 or data input from external input devices and outputs the processed data to external interface devices, etc. Furthermore, the processor 1100 may include multiple various modules and devices. In this case, the added modules can exchange data with the core unit 1110 and the cache storage unit 1120, as well as with each other, via the bus interface 1130.

[0124] Embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (Dynamic Random Access Memory), mobile DRAM, SRAM (Static Random Access Memory), and memory with similar functions. Non-volatile memory may include ROM (Read-Only Memory), NOR flash memory, NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), spin-transfer torque random access memory (STTMRAM), magnetic random access memory (MRAM), and memory with similar functions.

[0125] Communication module unit 1150 may include modules capable of connecting to wired networks, modules capable of connecting to wireless networks, and both. Like various devices that send and receive data via transmission lines, wired network modules may include Local Area Networks (LANs), Universal Serial Bus (USB), Ethernet, Power Line Communication (PLC), etc. Like various devices that send and receive data without transmission lines, wireless network modules may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High-Speed ​​Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), Ultra Wideband (UWB), etc.

[0126] The memory control unit 1160 manages and processes data transferred between the processor 1100 and external storage devices operating according to different communication standards. The memory control unit 1160 may include various memory controllers, such as devices that can control IDE (Integrated Circuit Device), SATA (Serial Advanced Technology Accessory), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, Secure Digital High Capacity (SDHC) cards, Memory Stick cards, Smart Media (SM) cards, Multimedia Cards (MMC), Embedded MMC (eMMC), Compact Flash (CF) cards, etc.

[0127] The media processing unit 1170 can process data processed in the processor 1100 or data input from external input devices in the form of images, voice, and other formats, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), a high-definition multimedia interface (HDMI) controller, etc.

[0128] Figure 22 This is an example of a system configuration diagram for implementing a storage circuit system based on the disclosed technology.

[0129] Reference Figure 22The system 1200, as a device for processing data, can perform a series of operations on the data, including input, processing, output, communication, and storage. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240. The system 1200 in this embodiment can be various electronic systems operated by a processor, such as computers, servers, PDAs (Personal Digital Assistants), portable computers, network tablets, cordless phones, mobile phones, smartphones, digital music players, PMPs (Portable Multimedia Players), cameras, GPS devices, video cameras, recorders, telematics, audiovisual (AV) systems, and smart TVs.

[0130] Processor 1210 can decode input commands, perform operations and comparisons on data stored in system 1200, and control these operations. Processor 1210 can be substantially the same as the microprocessor 1000 or processor 1100 described above.

[0131] The primary storage device 1220 is a storage device that can temporarily store, retrieve, and run program code or data from the secondary storage device 1230 during program execution, and can retain its stored contents even when power is cut off. The secondary storage device 1230 is a storage device used to store program code or data. Although the secondary storage device 1230 is slower than the primary storage device 1220, it can store a larger amount of data. The primary storage device 1220 or the secondary storage device 1230 may include one or more of the semiconductor devices described above according to the embodiments. For example, the primary storage device 1220 or the auxiliary storage device 1230 may include: a substrate comprising a cell region and a peripheral circuit region, the cell region comprising a first cell region relatively close to the peripheral circuit region and a second cell region relatively far from the peripheral circuit region; a plurality of first lines disposed on the substrate and extending in a first direction; a plurality of second lines disposed on the first lines and extending in a second direction intersecting the first direction; a plurality of memory cells located at the intersection regions between the first lines and the second lines in the cell regions; a first insulating layer located between the plurality of first lines, between the plurality of second lines, or both in the first cell region; and a second insulating layer located between the plurality of first lines and between the plurality of second lines in the second cell region, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer. This improves the operating characteristics of the primary storage device 1220 or the auxiliary storage device 1230. Consequently, it improves the operating characteristics of the system 1200.

[0132] In addition to or excluding the aforementioned semiconductor devices, the primary storage device 1220 or the auxiliary storage device 1230 may include a storage system (see [link to storage system]). Figure 23 (See attached figure 1300).

[0133] Interface device 1240 can be used to perform command and data exchange between system 1200 and external devices in this embodiment. Interface device 1240 can be a keypad, keyboard, mouse, speaker, microphone, display, various human-computer interaction devices (HID), communication devices, etc. The communication device can be basically the same as the communication module unit 1150 described above.

[0134] Figure 23 This is an example of a configuration diagram of a storage system based on the disclosed technology that implements the storage circuit system.

[0135] Reference Figure 23 The storage system 1300 may include: a memory 1310 with non-volatile characteristics, serving as a component for storing data; a controller 1320, which controls the memory 1310; an interface 1330, used for connecting to external devices; and a buffer memory 1340, used for temporarily storing data to efficiently transfer data between the interface 1330 and the memory 1310. The storage system 1300 can simply refer to a memory for storing data, or it can refer to a data storage device for long-term storage of stored data. The storage system 1300 can be a disk type such as a solid-state drive (SSD), or a card type such as a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a mini Secure Digital (mSD) card, a Micro Secure Digital (microSD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a Multimedia Card (MMC), an Embedded MMC (eMMC), a Compact Flash (CF) card, etc.

[0136] Memory 1310 or buffer memory 1340 may include one or more of the semiconductor devices described above according to the embodiments. For example, memory 1310 or buffer memory 1340 may include: a substrate including cell regions and peripheral circuit regions, the cell regions including a first cell region relatively close to the peripheral circuit regions and a second cell region relatively far from the peripheral circuit regions; a plurality of first lines disposed on the substrate and extending in a first direction; a plurality of second lines disposed on the first lines and extending in a second direction intersecting the first direction; a plurality of memory cells located at the intersection regions between the first lines and the second lines in the cell regions; a first insulating layer located between the plurality of first lines, between the plurality of second lines, or both between the plurality of first lines and between the plurality of second lines in the first cell regions; and a second insulating layer located between the plurality of first lines and between the plurality of second lines in the second cell regions, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer. This improves the operating characteristics of memory 1310 or buffer memory 1340. Consequently, it improves the operating characteristics of storage system 1300.

[0137] In addition to or excluding the semiconductor devices described above, memory 1310 or buffer memory 1340 may include various types of memory, such as non-volatile memory or volatile memory.

[0138] The controller 1320 can control the data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321, which is used to perform operations such as processing commands input from outside the storage system 1300 through the interface 1330.

[0139] Interface 1330 is used to perform command and data exchange between storage system 1300 and external devices. When storage system 1300 is a card type or disk type, interface 1330 may be compatible with interfaces used in devices of card type or disk type, or with interfaces similar to those mentioned above. Interface 1330 may be compatible with one or more interfaces of different types.

[0140] Based on the storage devices disclosed herein Figures 20 to 23 The features described in the examples of electronic devices or systems above can be implemented in a variety of devices, systems, or applications. Some examples include mobile phones or other portable communication devices, tablets, laptops or notebook computers, game consoles, smart TVs, set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0141] While this patent document contains numerous details, these details should not be construed as limiting the scope of any invention or the scope of protection claimed. Rather, they should be interpreted as descriptions of features that may be implemented for specific embodiments of a particular invention. Specific features described in the context of individual embodiments in this patent document may also be implemented in combination with a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in any suitable sub-combination. Furthermore, while features may be described above as functioning in a particular combination, and even initially claimed in this manner, in some cases one or more features from the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0142] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or as requiring all of the shown operations to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0143] Only a few implementation methods and examples have been described. Other implementation methods, improvements, and variations can be made based on the descriptions and illustrations in this patent document.

[0144] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the teachings as defined in the appended claims.

Claims

1. An electronic device including a semiconductor memory, the semiconductor memory comprising: A substrate, the substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being configured to be closer to the peripheral circuit region than the second cell region; A plurality of first lines are disposed on the substrate and each extends in a first direction; A plurality of second lines are disposed on the first line and each extends in a second direction intersecting the first direction; Multiple storage cells are located at the intersection area between the first line and the second line in the cell region; A first insulating layer is located between the plurality of first lines, between the plurality of second lines, or between both the plurality of first lines and the plurality of second lines in the first unit region; as well as A second insulating layer is located between the plurality of first lines and between the plurality of second lines in the second unit region. Wherein, the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer. 2.The electronic device of claim 1, wherein, The second insulating layer comprises silicon oxide, and The first insulating layer comprises an insulating material having a dielectric constant lower than that of the silicon oxide.

3. The electronic device according to claim 1, wherein, The elements constituting the first insulating layer are the same as those constituting the second insulating layer.

4. The electronic device according to claim 1, wherein, The storage unit includes a first plurality of storage units in the first unit region and a second plurality of storage units in the second unit region, and the first insulating layer is also located between the first plurality of storage units in the first unit region.

5. The electronic device according to claim 1, wherein, The storage unit includes: a first plurality of storage units in the first unit region and a second plurality of storage units in the second unit region, and the second insulating layer is also located between the second plurality of storage units in the second unit region.

6. The electronic device according to claim 1, wherein, The first insulating layer is located between the plurality of first lines in the first unit region, and The second insulating layer is also located between the plurality of second lines in the first unit region.

7. The electronic device according to claim 6, wherein, The storage unit includes: a first plurality of storage units and a second plurality of storage units in the first unit region, wherein the first plurality of storage units and the second plurality of storage units are respectively arranged in the first direction and the second direction. Wherein, the first insulating layer is further located in the second direction between the second plurality of memory cells in the first cell region, and The second insulating layer is further located in the first direction between the first plurality of memory cells in the first cell region.

8. The electronic device according to claim 1, wherein, The first insulating layer is located between the plurality of second wires in the first unit region, and The second insulating layer is further located between the plurality of first lines in the first unit region.

9. The electronic device according to claim 8, wherein, The storage unit includes: a first plurality of storage units and a second plurality of storage units in the first unit region, wherein the first plurality of storage units and the second plurality of storage units are respectively arranged in the first direction and the second direction. Wherein, the first insulating layer is further located in the first direction between the first plurality of memory cells in the first cell region, and The second insulating layer is further located in the second direction between the second plurality of memory cells in the first cell region.

10. The electronic device according to claim 1, wherein, The storage unit includes: a first plurality of storage units in the first unit region and a second plurality of storage units in the second unit region, and The current supplied to the first plurality of memory cells in the first unit region is less than the current supplied to the second plurality of memory cells in the second unit region.

11. The electronic device of claim 1, further comprising a microprocessor, the microprocessor comprising: A control unit configured to receive signals including commands from outside the microprocessor, and to extract, decode, or control the input or output of signals to the microprocessor based on the commands; A computation unit configured to perform computations based on the result of the control unit decoding the command; as well as A storage unit configured to store data for performing the operation, data corresponding to the result of performing the operation, or the address of the data on which the operation is performed. The semiconductor memory is part of the storage unit in the microprocessor.

12. The electronic device of claim 1, further comprising a processor, the processor comprising: A core unit configured to perform operations corresponding to commands input from outside the processor by using data; A high-speed cache storage unit, the high-speed cache storage unit being configured to store data for performing the operation, data corresponding to the result of performing the operation, or the address of the data on which the operation is performed; as well as A bus interface, connected between the core unit and the cache memory unit, is configured to transfer data between the core unit and the cache memory unit. The semiconductor memory is part of the cache memory unit in the processor.

13. The electronic device of claim 1, further comprising a processing system, the processing system comprising: A processor configured to decode commands received by the processor and to control operations on information based on the result of decoding the commands; An auxiliary storage device configured to store a program for decoding the command and the information; A primary storage device, configured to call and store the program and information from the secondary storage device, such that the processor can use the program and information to perform the operation while running the program; as well as An interface device configured to perform communication between at least one of the processor, the auxiliary storage device, and the main storage device and an external source. The semiconductor memory is a part of the auxiliary storage device or the main storage device in the processing system.

14. The electronic device of claim 1, further comprising a storage system, the storage system comprising: A memory configured to store and retain data regardless of the power supply. A memory controller configured to control the input of data to and output of data from the memory according to commands input from an external source; A buffer memory configured to buffer data exchanged between the memory and the external environment; as well as An interface configured to perform communication between at least one of the memory, the memory controller, and the buffer memory and the external environment. The semiconductor memory is part of the memory or the buffer memory in the storage system.

15. An electronic device including a semiconductor memory, the semiconductor memory comprising: A substrate, the substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being configured to be closer to the peripheral circuit region than the second cell region; A plurality of first lines are disposed on the substrate and each extends in a first direction; A plurality of second lines are disposed on the first line and each extends in a second direction intersecting the first direction; Multiple storage cells are located at the intersection area between the first line and the second line in the cell region; A first insulating layer is located between the plurality of first lines, between the plurality of second lines, or between both the plurality of first lines and the plurality of second lines in the first unit region; as well as A second insulating layer is located between the plurality of first lines and between the plurality of second lines in the second unit region. Wherein, when the first insulating layer is located between the plurality of first lines, the first capacitance is smaller than the second capacitance. The first capacitance is generated by a first adjacent portion of the plurality of first lines in the first unit region and a first portion of the first insulating layer. The second capacitance is generated by a second adjacent portion of the plurality of first lines in the second unit region and a first portion of the second insulating layer. Wherein, when the first insulating layer is located between the plurality of second lines, the third capacitance is smaller than the fourth capacitance. The third capacitance is generated by the first adjacent portion of the plurality of second lines in the first unit region and the second portion of the first insulating layer. The fourth capacitance is generated by the second adjacent portion of the plurality of second lines in the second unit region and the second portion of the second insulating layer.

16. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: A substrate is provided that includes a peripheral circuit region and a cell region, wherein the cell region includes a first cell region and a second cell region, and the first cell region is configured to be closer to the peripheral circuit region than the second cell region; Multiple stacked structures are formed on the substrate, each of the multiple stacked structures extending in a first direction, and each stacked structure includes a first line and an initial memory cell disposed on the first line. A first insulating material layer is formed to fill the spaces between the stacked structures; One or more portions of the first insulating material layer in the first unit region are replaced with a second insulating material layer having a lower dielectric constant than the first insulating material layer. A plurality of second lines are formed on the stacked structure, the first insulating material layer, and the second insulating layer, each of the plurality of second lines extending in a second direction; and Multiple memory cells are formed by etching the initial memory cell exposed by the second line.

17. The method according to claim 16, wherein, The portion in which the second insulating material layer replaces the first insulating layer includes: Forming a mask pattern that opens into the first unit region and covers the second unit region; and The first insulating material layer exposed by the mask pattern is subjected to heat treatment.

18. The method according to claim 17, wherein, The heat treatment includes ultraviolet annealing.

19. The method of claim 17, wherein, The elements constituting the first insulating material layer are the same as the elements constituting the second insulating material layer.

20. The method of claim 16, wherein, The portion in which the second insulating material layer replaces the first insulating layer includes: A mask pattern is formed that opens into the first unit region and covers the second unit region; A space is formed by removing the first insulating material layer exposed by the mask pattern; and The space is filled with the second insulating material layer.

21. The method of claim 16, further comprising, after forming the plurality of storage cells: A third insulating material layer is formed, which fills the spaces between the second lines in the first direction and between the memory cells; as well as One or more portions of the third insulating material layer in the first unit region are replaced with a fourth insulating material layer having a lower dielectric constant than the third insulating material layer.

22. The method according to claim 21, wherein, The portion in which the third insulating layer is replaced by the fourth insulating layer includes: Forming a mask pattern that opens into the first unit region and covers the second unit region; and The third insulating material layer exposed by the mask pattern is subjected to heat treatment.

23. The method according to claim 22, wherein, The heat treatment includes ultraviolet annealing.

24. The method according to claim 22, wherein, The elements constituting the third insulating material layer are the same as those constituting the fourth insulating material layer.

25. The method according to claim 21, wherein, The portion in which the third insulating layer is replaced by the fourth insulating layer includes: A mask pattern is formed that opens into the first unit region and covers the second unit region; A space is formed by removing the third insulating material layer exposed by the mask pattern; and The space is filled with the fourth insulating material layer.

26. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: A substrate is provided that includes a peripheral circuit region and a cell region, wherein the cell region includes a first cell region and a second cell region, and the first cell region is configured to be closer to the peripheral circuit region than the second cell region; Multiple stacked structures are formed on the substrate, each of the multiple stacked structures extending in a first direction, and each stacked structure includes a first line and an initial memory cell disposed on the first line. A first insulating material layer is formed to fill the spaces between the stacked structures; A plurality of second lines are formed on the stacked structure and the first insulating material layer, each of the plurality of second lines extending in a second direction; Multiple memory cells are formed by etching the initial memory cells exposed by the second line; A third insulating material layer is formed, the third insulating material layer filling the spaces between the second lines in the first direction and between the memory cells; and One or more portions of the third insulating material layer in the first unit region are replaced with a fourth insulating material layer having a lower dielectric constant than the third insulating material layer.

27. The method according to claim 26, wherein, The portion in which the third insulating layer is replaced by the fourth insulating layer includes: Forming a mask pattern that opens into the first unit region and covers the second unit region; and The third insulating material layer exposed by the mask pattern is subjected to heat treatment.

28. The method according to claim 27, wherein, The heat treatment includes ultraviolet annealing.

29. The method according to claim 27, wherein, The elements constituting the third insulating material layer are the same as those constituting the fourth insulating material layer.

30. The method according to claim 26, wherein, The portion in which the third insulating layer is replaced by the fourth insulating layer includes: A mask pattern is formed that opens into the first unit region and covers the second unit region; A space is formed by removing the third insulating material layer exposed by the mask pattern; and The space is filled with the fourth insulating material layer.

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