A vertical structure parallel array LED chip and a preparation method thereof

Abstract

The application relates to the technical field of LED, and discloses a vertical structure parallel array LED chip and a preparation method thereof. The vertical structure parallel array LED chip comprises, from bottom to top, a conductive substrate, a bonding metal layer, a p-contact mirror metal and a protective layer, a p-type GaN layer, an InGaN / GaN multi-quantum well layer, an n-type GaN layer and an N electrode. The n-type GaN layer, the InGaN / GaN multi-quantum well layer and the p-type GaN layer are divided into a plurality of independent units through etching, and an insulating material is deposited in etching channels between the independent units to form isolation; the N electrode is connected with the independent units to form a parallel array. The LED chip has the advantages of a vertical structure LED chip, and the parallel array method is adopted to reduce the junction capacitance of the chip, thereby reducing the RC time constant, and the performance is significantly improved compared with the prior art, and the LED chip can be used for preparing a high-bandwidth LED chip suitable for visible light communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED, more particularly, to a vertical structure parallel array LED chip and a preparation method thereof. BACKGROUND

[0002] With the continuous expansion of the market share of LED lighting, the application scenarios of LED are also more and more broad, and with the gradual development of visible light communication technology, LED is considered as the most ideal light source of visible light communication technology because of excellent photoelectric performance, low cost, long service life and fast modulation rate.

[0003] According to the arrangement and stacking mode of different component structures of LED, LED can be mainly classified into the following categories: forward (also known as horizontal) structure, flip-chip structure and vertical structure. The various layer structures of the vertical structure LED are on the same vertical plane, and the current can be directly conducted vertically, effectively solving the current congestion problem existing in the forward (also known as horizontal) structure and flip-chip structure, and without the need to additionally etch the n region, the light emitting area is ensured, and since the metal substrate or silicon substrate with good heat conduction and electrical conductivity is selected under the p-GaN, the heat generated in the device can be effectively conducted out. Therefore, the vertical structure LED has great advantages in both light emitting performance and service life.

[0004] The prior art discloses a parallel array LED chip suitable for visible light communication, which comprises, from bottom to top, a conductive substrate, a bonding metal layer, a first insulating layer, a p-contact mirror metal, a protective layer and a light-emitting active region, the light-emitting active region comprises a P electrode and a plurality of array distributed light-emitting active units, and an etching channel is arranged between adjacent light-emitting active units, each light-emitting active unit comprises a functional layer and at least one columnar N electrode, the functional layer comprises a p-type GaN layer, an InGaN / GaN multi-quantum well layer and an n-type GaN layer, the columnar N electrode is located in the interior of the functional layer, the top of the columnar N electrode is in ohmic contact with the n-type GaN layer, and the bottom of the columnar N electrode is in electrical connection with the bonding metal layer.

[0005] The prior art discloses a GaN vertical structure optoelectronic device for visible light communication, which uses a multi-quantum well (MQW) as an active region and adopts a vertical structure to design and prepare a blue light communication device on a 4-inch wafer. In the preparation process, photolithography process, maskless etching technology, electrode evaporation and annealing process are used. In order to improve the light emitting performance of the device, the thickness of the epitaxial layer is thinned to 1.1 microns, which effectively reduces the light waveguide mode in the device, and the optimization of the size structure of the device reduces the RC constant of the device and improves the response rate of the device. In addition, Ni / Ag is integrated as a mirror under the p-GaN, and a rough light emitting surface is further improved to improve the light emitting efficiency.

[0006] In summary, the prior art vertical structure LED disclosed above reduces the RC constant of the device and improves the light output power to some extent, but the modulation bandwidth and light output power are still insufficient. SUMMARY

[0007] The present application provides a vertical structure parallel array LED chip to overcome the insufficient modulation bandwidth and light output power of the prior art vertical structure LED device.

[0008] Meanwhile, a preparation method of the vertical structure parallel array LED chip is provided.

[0009] To solve the above technical problems, the technical solutions of the present application are as follows:

[0010] A vertical structure parallel array LED chip comprises, from bottom to top, a conductive substrate, a bonding metal layer, a p-contact mirror metal and a protective layer, a p-type GaN layer, an InGaN / GaN multi-quantum well layer, an n-type GaN layer, and an N electrode.

[0011] The n-type GaN layer, the InGaN / GaN multi-quantum well layer, and the p-type GaN layer are divided into several independent units by etching, and an insulating material is deposited in the etching channels between the independent units to form isolation.

[0012] The N electrode is connected to each independent unit to form a parallel array.

[0013] The RC constant of the LED device is closely related to the modulation bandwidth of the communication performance, and the capacitance C and the resistance R of the parallel LED can be represented by the following formula:

[0014] C = NC1 + C0

[0015]

[0016] wherein N is the number of array units, C1 is the junction capacitance of a single unit, C0 is a parasitic capacitance constant term, R1 is the resistance of a single unit, and R0 is a series resistance term. In the parallel array LED, the increase in capacitance caused by the increase in the number of array units is not obvious according to the formula. However, the resistance of the LED decreases significantly with the increase in the number of array units, so the parallel array can effectively reduce the RC time constant, thereby increasing the modulation bandwidth and improving the communication performance of the device.

[0017] Preferably, the N electrode forms an ohmic contact with the upper surface of the n-type GaN layer of each independent unit.

[0018] Preferably, the N electrode is one of Ti, Cr, Ag, Au, and Pt, or an alloy of two or more of them, and has a thickness of 500-1000 nm.

[0019] Preferably, the conductive substrate is a conductive silicon substrate with a thickness of 200-500 μm; and the insulating material is SiO2.

[0020] Preferably, the p-contact mirror metal and protective layer comprise a p-contact mirror metal and a protective layer; the p-contact mirror metal is one or both of Ag and Ni, with a thickness of 600-1000 nm; and the protective layer is a TiW layer, with a thickness of 200-300 nm.

[0021] Preferably, the bonding metal layer is an alloy of one or more of Ni, Au, Sn, and Ti, with a thickness of 700-1000 nm.

[0022] A method for preparing the vertical-structure parallel-array LED chip, comprising the following steps:

[0023] (1) Taking a Si substrate, and using a MOCVD device to grow successively a 5-μm-thick AlGaN buffer layer, an n-type GaN layer, an InGaN / GaN multi-quantum-well layer, and a p-type GaN layer (105) on the Si substrate, to obtain an LED epitaxial wafer; wherein the n-type GaN is doped by introducing silane gas to dope the n-type GaN with Si during growth, and the p-type GaN is doped by introducing dimethyl magnesium gas to dope the p-type GaN with Mg during growth;

[0024] Continuing to use an electron beam evaporation device to deposit a p-contact mirror metal and a protective layer on the p-type GaN layer, with a metal evaporation rate of 15 angstroms per second;

[0025] (2) Depositing a bonding metal layer on the LED chip obtained in step (1), to obtain a first wafer;

[0026] (3) Preparing a bonding metal layer on another conductive silicon substrate by a deposition process, to obtain a second wafer;

[0027] (4) Activating the bonding metal layers of the first wafer and the second wafer, aligning the treated bonding metal layers, and then feeding them into a bonder for pre-bonding, to form firm bonds between the wafers, and to obtain an LED chip semi-product;

[0028] (5) Mechanically grinding the Si substrate of the LED chip semi-product, and then immersing it in a mixed solution of hydrofluoric acid, glacial acetic acid, and nitric acid, to etch until the Si substrate disappears, and then using ICP etching to remove the AlGaN buffer layer, to expose the n-type GaN layer;

[0029] (6) Then, the n-type GaN layer, the InGaN / GaN multi-quantum well layer and the p-type GaN layer are divided into several independent units by ICP etching, the whole epitaxial structure is divided into small blocks which are not connected with each other, each small block corresponds to an LED chip, then a P electrode pad metal is deposited to be connected with the contact layer metal, thus the P electrode is led out to the surface from the inside of the chip; then SiO2 is deposited by PECVD to isolate different independent units; the thickness of the SiO2 layer is 2 μm;

[0030] (7) Finally, the N electrode step is etched by lithography, and the N electrode is deposited to obtain a vertical structure parallel array LED chip.

[0031] Preferably, the molar concentration ratio of hydrofluoric acid: glacial acetic acid: nitric acid in step (5) is 5:1:5.

[0032] Compared with the prior art, the beneficial effects of the technical scheme of the present application are:

[0033] The vertical structure parallel array LED chip provided by the present application has the advantages of the vertical structure LED chip, and the parallel array method is adopted to reduce the junction capacitance of the chip, thereby reducing the RC time constant, and the performance is significantly improved compared with the prior art, and the vertical structure parallel array LED chip can be used to prepare a high-bandwidth LED chip suitable for visible light communication.

[0034] The vertical structure parallel array LED chip provided by the present application can further improve the light output power of the LED by increasing the number of parallel chips, and is suitable for more application scenarios.

[0035] The array LED chip provided by the present application has a simple process, high yield, is suitable for industrial production, and has good application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a front view of the vertical structure parallel array LED chip structure.

[0037] Figure 2 It is a top view of the vertical structure parallel array LED chip structure. DETAILED DESCRIPTION

[0038] The present application will be further described below in combination with the drawings and specific embodiments, but the embodiments do not limit the present application in any form. Unless otherwise specified, the reagents, methods and devices used in the present application are conventional reagents, methods and devices in the technical field.

[0039] Unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0040] Example 1

[0041] AsFigures 1-2 As shown in the figure, a vertical structure parallel array LED chip comprises, from bottom to top, a conductive substrate 101, a bonding metal layer 102, a p-contact mirror metal and protective layer 103, a p-type GaN layer 105, an InGaN / GaN multi-quantum well layer 106, an n-type GaN layer 107, and an N electrode 108 arranged in sequence;

[0042] The n-type GaN layer 107, the InGaN / GaN multi-quantum well layer 106, and the p-type GaN layer 105 are divided into several independent units by etching, and an insulating material is deposited in the etching channels between the independent units to form isolation;

[0043] The N electrode 018 is connected to each independent unit to form a parallel array.

[0044] The N electrode 108 forms an ohmic contact with the upper surface of the n-type GaN layer of each independent unit.

[0045] The N electrode 108 is Ti-Cr alloy with a thickness of 500 nm.

[0046] The conductive substrate is a conductive silicon substrate with a thickness of 500 μm; and the insulating material is SiO2.

[0047] The p-contact mirror metal and protective layer comprises a p-contact mirror metal and a protective layer; the p-contact mirror metal is Ag with a thickness of 800 nm; and the protective layer is a TiW layer with a thickness of 300 nm.

[0048] The bonding metal layer is an alloy of Ni and Au with a thickness of 1000 nm.

[0049] A preparation method of a vertical structure parallel array LED chip comprises the following steps:

[0050] (1) Take a Si substrate, and use an MOCVD device to grow, on the Si substrate, an AlGaN buffer layer with a thickness of 5 um, an n-type GaN layer 107, an InGaN / GaN multi-quantum well layer 106, and a p-type GaN layer 105 in sequence to obtain an LED epitaxial wafer; wherein the doping of the n-type GaN is realized by introducing silane gas to dope Si elements during growth, and the doping of the p-type GaN is realized by introducing dimethyl magnesium gas to dope Mg during growth;

[0051] Continue to use an electron beam evaporation device to deposit the p-contact mirror metal and protective layer 103 on the p-type GaN layer 105, and the metal evaporation rate is 15 angstroms per second;

[0052] (2) Deposit a bonding metal layer 102 on the LED chip obtained in step (1) to obtain a first wafer;

[0053] (3) on another conductive silicon substrate 101, a bonding metal layer 102 is prepared by deposition process, thus obtaining a second wafer;

[0054] (4) the bonding metal layer of the prepared first wafer and the second wafer is surface activated, and the treated bonding metal layer is aligned and then sent into a bonder for pre-bonding, thus forming a firm bond between the pre-bonded wafers, obtaining an LED chip semi-finished product;

[0055] (5) the Si substrate of the LED chip semi-finished product is mechanically polished and then immersed in a mixed solution of hydrofluoric acid, glacial acetic acid and nitric acid, and etched until the Si substrate disappears, and then ICP etching is used to remove the AlGaN buffer layer to expose the n-type GaN layer 107;

[0056] In step (5), the molar concentration ratio of hydrofluoric acid, glacial acetic acid and nitric acid is 5:1:5.

[0057] (6) Then, the n-type GaN layer 107, the InGaN / GaN multi-quantum well layer 106 and the p-type GaN layer 105 are divided into several independent units by ICP etching, and the whole epitaxial structure is divided into small blocks that are not connected to each other, each small block corresponding to an LED chip, and then the P electrode pad metal is connected with the contact layer metal, and the P electrode is led out to the surface from the inside of the chip; then PECVD is used to deposit SiO2 to isolate different independent units; the thickness of the SiO2 layer is 2 μm;

[0058] (7) Finally, the N electrode step is etched by lithography, and the N electrode 108 is deposited to obtain a vertical structure parallel array LED chip.

[0059] Example 2

[0060] As shown in Figures 1-2 A vertical structure parallel array LED chip, comprising, from bottom to top, a conductive substrate 101, a bonding metal layer 102, a p-contact mirror metal and a protective layer 103, a p-type GaN layer 105, an InGaN / GaN multi-quantum well layer 106, an n-type GaN layer 107, and an N electrode 108;

[0061] The n-type GaN layer 107, the InGaN / GaN multi-quantum well layer 106 and the p-type GaN layer 105 are divided into several independent units by etching, and the etching channels between the independent units are deposited with insulating material to form isolation;

[0062] The N electrode 018 is connected with each independent unit to form a parallel array.

[0063] The N electrode 108 forms an ohmic contact with the upper surface of the n-type GaN layer of each independent unit.

[0064] The N electrode 108 is Cr, and the thickness is 500 nm.

[0065] The conductive substrate is a conductive silicon substrate, and the thickness is 200 μm; the insulating material is SiO2.

[0066] The p-contact mirror metal and the protective layer include a p-contact mirror metal and a protective layer; the p-contact mirror metal is Ni, and the thickness is 600 nm; the protective layer is a TiW layer, and the thickness of the protective layer is 200 nm.

[0067] The bonding metal layer is Sn, and the thickness is 700 nm.

[0068] A preparation method of a vertical structure parallel array LED chip includes the following steps:

[0069] (1) Taking a Si substrate, using a MOCVD device to grow a 5 um thick AlGaN buffer layer, an n-type GaN layer 107, an InGaN / GaN multi-quantum well layer 106 and a p-type GaN layer 105 on the Si substrate in sequence to obtain an LED epitaxial wafer; wherein the n-type GaN is doped by introducing silane gas to realize Si element doping during growth, and the p-type GaN is doped by introducing dimethyl magnesium gas to realize Mg doping during growth;

[0070] Continuing to use an electron beam evaporation device to deposit a p-contact mirror metal and a protective layer 103 on the p-type GaN layer 105, and the metal evaporation rate is 15 angstroms / second;

[0071] (2) Depositing a bonding metal layer 102 on the LED chip obtained in step (1) to obtain a first wafer;

[0072] (3) Preparing a bonding metal layer 102 on another conductive silicon substrate 101 by a deposition process to obtain a second wafer;

[0073] (4) Surface activating the bonding metal layer of the first wafer and the second wafer, aligning the treated bonding metal layer, and then sending them into a bonder for pre-bonding, so that a firm bond is formed between the wafers, and an LED chip semi-finished product is obtained;

[0074] (5) After mechanical grinding, the Si substrate of the LED chip semi-finished product is immersed in a mixed solution of hydrofluoric acid, glacial acetic acid and nitric acid, and etched until the Si substrate disappears, and then ICP etching is used to remove the AlGaN buffer layer to expose the n-type GaN layer 107;

[0075] In step (5), the molar concentration ratio of hydrofluoric acid, glacial acetic acid and nitric acid is 5:1:5.

[0076] (6) Then, the n-type GaN layer 107, the InGaN / GaN multi-quantum well layer 106 and the p-type GaN layer 105 are divided into several independent units by ICP etching, and the whole epitaxial structure is divided into several small blocks which are not connected with each other, each of which corresponds to an LED chip. Then, the P electrode pad metal is connected with the contact layer metal, and the P electrode is led out to the surface from the inside of the chip. Then, SiO2 is deposited by PECVD to isolate different independent units. The thickness of the SiO2 layer is 2 μm;

[0077] (7) Finally, the N electrode step is etched by lithography, and the N electrode 108 is deposited to obtain a vertical structure parallel array LED chip.

[0078] Embodiments 3-5

[0079] The technical solutions of embodiments 3-5 are similar to those of embodiment 1, and the difference is shown in Table 1.

[0080] Table 1 Technical solutions of embodiments 3-5

[0081]

[0082] Performance test

[0083] The LED chips of embodiments 1-5 are tested for performance, and the performance test process is as follows:

[0084] Photoelectric performance test: The integrating sphere used for testing is a 0.5 m diameter integrating sphere of a far photoelectric type with a model number of HAAS-2000. The corresponding clamp is used for sample preparation by Al substrate to measure the parameters such as IV, LOP and luminescence spectrum of the LED sample.

[0085] The integrating sphere is made of metal material, and the inner wall of the sphere shell is coated with a white high-diffuse reflection layer (usually magnesium oxide or barium sulfate) or other high-reflectivity polymer material, and each point in the inner wall of the sphere shell can form uniform diffuse reflection. When testing, the light emitted by the sample enters the inside of the integrating sphere and is reflected repeatedly by the inner wall, and finally is accepted by the detection system for data analysis and processing. The integrating sphere is commonly used to test the luminous flux, color temperature, light efficiency and other parameters of LED light sources, and can also be used to measure the reflectivity and transmittance of objects.

[0086] Communication performance: 3dB bandwidth is a very important communication performance of LED, and the size of bandwidth significantly affects the channel capacity and communication speed of LED in communication system. 3dB bandwidth can be tested by oscilloscope or network analyzer. The test platform based on network analyzer is adopted in this patent, which mainly contains a bias device, model ZFBT-6GW+, for coupling the bias voltage and AC signal of LED; a programmed linear power supply, model SS-L303SPD, which can provide bias voltage for LED device; a high bandwidth APD detector, model APD210, which can test LED devices with a maximum bandwidth of 1.6GHz, for detecting the intensity change of LED light output power; and a blue filter, model FB450-40, for filtering the slow response yellow phosphor part in white LED light.

[0087] Table 2 test results

[0088] Light output power @ 100 mA Bandwidth @ 100 mA Example 1 8.5 mW 195 MHz Example 2 9.5 mW 182 MHz Example 3 9.8 mW 179 MHz Example 4 9.7 mW 186 MHz Example 5 9.6 mW 191 MHz

[0089] From table 2, the light output performance of LED chips in 5 embodiments is in the order of milliwatt, which is sufficient to meet the needs of visible light communication, and the bandwidth is as high as several hundred megahertz, which has excellent communication performance.

[0090] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not intended to limit the embodiments of the present application. For those skilled in the art, other different forms of changes or variations can be made on the basis of the above description. Here, all the embodiments are not required to be exhausted. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.

Claims

1. A vertical structure parallel array LED chip, characterized in that, The vertical structure parallel array LED chip comprises, from bottom to top, a conductive substrate, a bonding metal layer, a p-contact mirror metal and a protective layer, a p-type GaN layer, an InGaN / GaN multi-quantum well layer, an n-type GaN layer and an N electrode. The n-type GaN layer, the InGaN / GaN multi-quantum well layer and the p-type GaN layer are divided into several independent units by etching, and an insulating material is deposited in the etching channels between the independent units to form isolation. The N electrode is connected with each independent unit to form a parallel array. The N electrode forms an ohmic contact with the upper surface of the n-type GaN layer of each independent unit. The N electrode is one of Ti, Cr, Ag, Au and Pt, or an alloy of two or more of them, and has a thickness of 500-1000 nm. The preparation method of the vertical structure parallel array LED chip comprises the following steps: (1) A Si substrate is taken, and a 5-um-thick AlGaN buffer layer, an n-type GaN layer (107), an InGaN / GaN multi-quantum well layer (106) and a p-type GaN layer (105) are sequentially grown on the Si substrate by using a MOCVD device to obtain an LED epitaxial wafer; a p-contact mirror metal and a protective layer (103) are deposited on the p-type GaN layer (105) by using an electron beam evaporation device, and the metal evaporation rate is 15 angstroms per second; (2) A bonding metal layer (102) is deposited on the LED chip in step (1) to obtain a first wafer; (3) A bonding metal layer (102) is prepared on another conductive Si substrate (101) by a deposition process to obtain a second wafer; (4) The bonding metal layers of the prepared first wafer and second wafer are surface-activated, the treated bonding metal layers are aligned, and then they are sent into a bonder together for pre-bonding, a firm bond is formed between the wafers after pre-bonding, and an LED chip semi-finished product is obtained; (5) The Si substrate of the LED chip semi-finished product is mechanically ground and then immersed in a mixed solution of hydrofluoric acid, glacial acetic acid and nitric acid until the Si substrate disappears, and then the AlGaN buffer layer is removed by ICP etching to expose the n-type GaN layer (107); (6) Then, the n-type GaN layer (107), the InGaN / GaN multi-quantum well layer (106) and the p-type GaN layer (105) are divided into several independent units by ICP etching, the whole epitaxial structure is divided into small blocks that are not connected with each other, each small block corresponds to an LED chip, then a P electrode pad metal is deposited to be connected with a contact layer metal, and thus the P electrode is led out to the surface from the inside of the chip; then SiO2 is deposited by PECVD to isolate different independent units; (7) Finally, a step for an N electrode is etched by lithography, and the N electrode (108) is deposited to obtain a vertical structure parallel array LED chip.

2. The vertical structure parallel array LED chip of claim 1, wherein, The conductive substrate is a conductive Si substrate, and has a thickness of 200-500 μm; and the insulating material is SiO2.

3. The vertical structure parallel array LED chip of claim 1, wherein, The p-contact mirror metal and the protective layer comprise a p-contact mirror metal and a protective layer.

4. The vertical structure parallel array LED chip of claim 3, wherein, The p-contact mirror metal is one or both of Ag and Ni, and the thickness is 600-1000 nm; the protective layer is a TiW layer, and the thickness of the protective layer is 200-300 nm.

5. The vertical-structure parallel-array LED chip of claim 1, wherein, The bonding metal layer is an alloy composed of one or more of Ni, Au, Sn, and Ti, and the thickness is 700-1000 nm.

6. The vertical-structure parallel-array LED chip of claim 1, wherein, The molar concentration ratio of hydrogen fluoride, glacial acetic acid, and nitric acid in step (5) is 5:1:

5.

7. The vertical-structure parallel-array LED chip of claim 1, wherein, The doping of n-type GaN in step (1) is achieved by introducing silane gas during growth to dope with Si element, and the doping of p-type GaN is achieved by introducing dimethyl magnesium gas during growth to dope with Mg.

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