Frequency multiplication circuit and frequency multiplication device

Abstract

The application relates to a frequency multiplication circuit and a frequency multiplication device. The frequency multiplication circuit comprises a first high-voltage switch circuit, a second high-voltage switch circuit and a delay circuit. The application replaces the operational amplifier in the traditional frequency multiplication circuit with the first high-voltage switch circuit, the second high-voltage switch circuit and the delay circuit, can generate a frequency multiplication signal based on a reference pulse signal and an input voltage, and can adapt to a high-voltage environment. Meanwhile, since the frequency multiplication signal is obtained by synthesizing the pulse signals output by the first high-voltage switch circuit and each second high-voltage switch circuit, a single first high-voltage switch circuit or second high-voltage switch circuit only needs to output a pulse in the period of a reference pulse signal, thereby avoiding the problem that a single high-voltage switch circuit cannot directly output a high-frequency signal due to a low switching rate of the single high-voltage switch circuit.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a frequency multiplier circuit and a frequency multiplier device. Background Technology

[0002] Currently, traditional frequency multiplier circuits typically consist of operational amplifiers, mainly because the operating frequency of the operational amplifiers is high enough to generate multi-frequency signals based on a reference signal. However, the current problem is that existing frequency multiplier circuits can generally only be applied to low-voltage signals. The operational amplifiers and other components in existing frequency multiplier circuits cannot withstand excessively high voltages, and the cost is relatively high. Summary of the Invention

[0003] The purpose of this application is to provide a frequency multiplier circuit and a frequency multiplier device, which aims to solve the problem that traditional frequency multiplier circuits cannot be applied to high-voltage circuits.

[0004] A first aspect of this application provides a frequency multiplier circuit, comprising: a first high-voltage switching circuit connected to a signal input terminal and a high-voltage power supply terminal, the first high-voltage switching circuit being configured to generate and output a first pulse signal based on a periodically changing reference pulse signal provided by the signal input terminal by controlling the switching between the high-voltage power supply terminal and ground; a delay circuit and X-1 second high-voltage switching circuits, wherein X is the frequency amplification factor of the frequency multiplier circuit, X equals 2 to the power of N, and N is a natural number greater than or equal to 1; the delay circuit includes X-1 first delay units connected in series, each of the second high-voltage switching circuits corresponding one-to-one with the first delay unit, wherein the input terminal of the delay circuit is connected to the signal input terminal, and the output terminal of each first delay unit is connected to the corresponding second high-voltage switching circuit, the first delay unit being used to delay the received signal and output it to the next adjacent first delay unit. The first high-voltage switch circuit is configured to generate and output X-1 second pulse signals based on the delayed reference pulse signal output by the corresponding first delay unit, by controlling the switching between the high-voltage power supply terminal and the ground terminal; the output terminal of the first high-voltage switch circuit is connected to the output terminal of each of the second high-voltage switch circuits and connected to the ground terminal through a pull-down resistor; the first pulse signal and each of the second pulse signals are used to synthesize a frequency multiplication signal; the duty cycle of the first pulse signal and each of the second pulse signals is 1 / X of the duty cycle of the reference pulse signal, and the frequency of the first pulse signal and each of the second pulse signals is the same as the frequency of the reference pulse signal; the delay duration of each of the first delay units is 1 / X of the period of the reference pulse signal.

[0005] In one embodiment, the first high-voltage switching circuit includes a second delay unit, a first switching transistor, and a second switching transistor. The first conducting terminal of the first switching transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the first switching transistor is connected to the first conducting terminal of the second switching transistor, the control terminal of the first switching transistor is connected to the signal input terminal, the first terminal of the second delay unit is connected to the control terminal of the first switching transistor, the second terminal of the second delay unit is connected to the control terminal of the second switching transistor, and the second conducting terminal of the second switching transistor is the output terminal of the first high-voltage switching circuit. The duty cycle of the reference pulse signal is Y, and the delay duration of the second delay unit is Y(X-1) / X, which is the period of the reference pulse signal.

[0006] In one embodiment, each of the second high-voltage switching circuits includes a second delay unit, a third switching transistor, and a fourth switching transistor. The first conducting terminal of the third switching transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the third switching transistor is connected to the first conducting terminal of the fourth switching transistor, the control terminal of the third switching transistor is connected to the delay circuit, the first terminal of the second delay unit is connected to the control terminal of the third switching transistor, the second terminal of the second delay unit is connected to the control terminal of the fourth switching transistor, and the second conducting terminal of the fourth switching transistor is the output terminal of the second high-voltage switching circuit.

[0007] In one embodiment, the first switch, the second switch, the third switch, and the fourth switch are all MOSFETs.

[0008] In one embodiment, the first switch, the second switch, the third switch, and the fourth switch are all IGBTs.

[0009] In one embodiment, each of the first delay unit and the second delay unit includes a capacitor.

[0010] In one embodiment, N equals 1, X equals 2, and the frequency multiplication signal is a second frequency multiplication signal.

[0011] In one embodiment, N equals 2, X equals 4, and the frequency multiplication signal is a fourth frequency multiplication signal.

[0012] In one embodiment, N equals 3, X equals 8, and the frequency multiplication signal is an eighth frequency multiplication signal.

[0013] A second aspect of this application provides a frequency multiplier device, including a plurality of frequency multiplier circuits as described above, wherein each frequency multiplier circuit is connected in series, and between two adjacent frequency multiplier circuits, the frequency multiplier signal output by the preceding frequency multiplier circuit is used as the reference pulse signal of the following frequency multiplier circuit.

[0014] The beneficial effects of this application embodiment compared with the prior art are as follows: This application replaces the operational amplifier in the traditional frequency multiplier circuit with a first high-voltage switching circuit, a second high-voltage switching circuit, and a delay circuit, which can generate a frequency multiplier signal based on a reference pulse signal and an input voltage. This application can adapt to high-voltage environments. Simultaneously, since the frequency multiplier signal is synthesized from the pulse signals output by the first high-voltage switching circuit and each of the second high-voltage switching circuits, a single first high-voltage switching circuit or second high-voltage switching circuit only needs to output one pulse within one period of a reference pulse signal. The switching frequency of a single first high-voltage switching circuit or second high-voltage switching circuit is low, thereby avoiding the problem that a single high-voltage switching circuit cannot directly and continuously output a high-frequency signal due to its low switching rate. Attached Figure Description

[0015] Figure 1 A schematic diagram of the frequency multiplier circuit provided in one embodiment of this application;

[0016] Figure 2 A schematic diagram of the first high-voltage switching circuit provided in an embodiment of this application;

[0017] Figure 3 A schematic diagram of the second high-voltage switching circuit provided in an embodiment of this application;

[0018] Figure 4 A schematic diagram of a delay circuit provided in an embodiment of this application;

[0019] Figure 5 A detailed circuit diagram of a frequency multiplier circuit provided in an embodiment of this application;

[0020] Figure 6 The signal waveform diagram is shown for a frequency multiplier circuit provided in an embodiment of this application.

[0021] Figure 7 A schematic diagram of a frequency multiplier device provided in an embodiment of this application.

[0022] The above figures illustrate: 10, frequency multiplier circuit; 100, first high-voltage switch circuit; 200, second high-voltage switch circuit; 300, delay circuit; 310, first delay unit; 400, second delay unit. Detailed Implementation

[0023] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0024] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0025] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0027] Figure 1 A schematic diagram of a frequency multiplier circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0028] A frequency multiplier circuit 10 includes: a first high-voltage switching circuit 100, a delay circuit 300, and X-1 second high-voltage switching circuits 200, wherein X is the frequency amplification factor of the frequency multiplier circuit 10, X equals 2 to the power of N, and N is a natural number greater than or equal to 1. The first high-voltage switching circuit 100 is connected to a signal input terminal and a high-voltage power supply terminal respectively, and is configured to generate and output a first pulse signal based on a periodically changing reference pulse signal VIN provided by the signal input terminal by controlling the switching between the high-voltage power supply terminal and the ground terminal. The high-voltage power supply terminal is used to provide an input voltage VDD, which can reach 5V to 700V, specifically 600V.

[0029] The delay circuit 300 includes X-1 first delay units 310 connected in series. Each second high-voltage switching circuit 200 corresponds one-to-one with a first delay unit 310. The input terminal of the first delay unit 310 is also the input terminal of the delay circuit 300, which is connected to the signal input terminal to receive the reference pulse signal VIN. The input terminal of each first delay unit 310 is connected to the output terminal of the adjacent first delay unit 310, and the output terminal of each first delay unit 310 is also connected to the corresponding second high-voltage switching circuit 200. The first delay unit 310 is used to delay the signal received at its input terminal and then output it through its output terminal to the adjacent next first delay unit 310 or the corresponding second high-voltage switching circuit 200.

[0030] Each of the second high-voltage switching circuits 200 is also connected to the high-voltage power supply terminal. Each second high-voltage switching circuit 200 is configured to generate and output X-1 second pulse signals based on the delayed reference pulse signal VIN output by the corresponding first delay unit 310, by controlling the on / off state between the high-voltage power supply terminal and the ground terminal. The output terminal of the first high-voltage switching circuit 100 is connected to the output terminal of each of the second high-voltage switching circuits 200. The output terminal of the first high-voltage switching circuit 100 is connected to the ground terminal through a pull-down resistor R1. The first pulse signal and each of the second pulse signals are used to synthesize a frequency multiplication signal. The first high-voltage switching circuit 100 controls the conduction between the high-voltage power supply terminal and the ground terminal, that is, controls the conduction between the high-voltage power supply terminal and the output terminal of the first high-voltage switching circuit 100. The first high-voltage switching circuit 100 controls the disconnection between the high-voltage power supply terminal and the ground terminal, that is, controls the disconnection between the high-voltage power supply terminal and the output terminal of the first high-voltage switching circuit 100. The duty cycle of the first pulse signal and each of the second pulse signals is 1 / X of the duty cycle of the reference pulse signal VIN. The pulse width of the first pulse signal and each of the second pulse signals is 1 / X of the pulse width of the reference pulse signal VIN. The frequencies of the first pulse signal and each of the second pulse signals are the same as the frequency of the reference pulse signal VIN. The delay duration of each of the first delay units 310 is 1 / X of the period of the reference pulse signal VIN. The first pulse signal and each of the second pulse signals are used to synthesize the frequency multiplier signal VOUT. Let the period of the reference pulse signal VIN be T, then the delay duration of each first delay unit 310 is T / X. Since the first delay units 310 are connected in series, the signal received by the next first delay unit 310 is already the reference pulse signal VIN after being delayed by the previous first delay unit 310. Therefore, taking the reference pulse signal VIN provided by the signal input terminal as a reference, let the cumulative delay duration between the signal output by each first delay unit 310 and the reference pulse signal VIN provided by the signal input terminal be T1, T2, ..., T in ascending order. X-1Then we can obtain T1 = T / X, T2 = T1 + T / X, T3 = T2 + T / X, ..., T X-1 =T X-2 +T / X.

[0031] It should be noted that in this embodiment, the second high-voltage switching circuit 200 has the same circuit structure as the first high-voltage switching circuit 100. However, the reference pulse signal VIN received by the second high-voltage switching circuit 200 is delayed by the delay circuit 300, and the cumulative delay duration corresponding to each first delay unit 310 has an increasing relationship, resulting in an increasing phase difference between each second pulse signal output by each second high-voltage switching circuit 200 and the first pulse signal. Finally, by synthesizing the first pulse signal and each second pulse signal, the corresponding frequency multiplier signal VOUT can be obtained. The delay duration of the first delay unit 310 corresponds to the phase difference between adjacent pulses of the frequency multiplier signal VOUT.

[0032] In this embodiment, the operational amplifier in a traditional frequency multiplier circuit is replaced by a first high-voltage switching circuit 100, a second high-voltage switching circuit 200, and a delay circuit 300. This allows the generation of a frequency multiplier signal VOUT based on a reference pulse signal VIN and an input voltage VDD. Furthermore, since the frequency multiplier signal VOUT is synthesized from the pulse signals output by the first high-voltage switching circuit 100 and each of the second high-voltage switching circuits 200, the switching frequency of a single first high-voltage switching circuit 100 or second high-voltage switching circuit 200 is relatively low. This avoids the problem that a single high-voltage switching circuit cannot directly output a high-frequency signal due to its low switching rate. Additionally, the delay duration of each first delay unit 310 can be configured according to the period of the reference pulse signal VIN and the frequency amplification factor of the target frequency multiplier signal VOUT. In other words, by adjusting the phase difference between the pulse signals, the corresponding frequency multiplier signal VOUT can be synthesized.

[0033] Meanwhile, traditional frequency multiplier circuits using operational amplifiers typically require multiple cycles of the reference pulse signal VIN before outputting the target multiplied signal VOUT. However, this embodiment can output the corresponding multiplied signal VOUT immediately upon receiving the reference pulse signal VIN. Traditional frequency multiplier circuits require modifications to their overall architecture when parameters such as the period of the reference pulse signal VIN change. This embodiment, however, only needs to change the parameters of each of the first delay units 310 to adapt to these changes.

[0034] like Figure 2As shown, in this embodiment, the first high-voltage switching circuit 100 includes a second delay unit 400, a first switching transistor Q1, and a second switching transistor Q2. The first conducting terminal of the first switching transistor Q1 is connected to the high-voltage power supply terminal, and the second conducting terminal of the first switching transistor Q1 is connected to the first conducting terminal of the second switching transistor Q2. The control terminal of the first switching transistor Q1 is connected to the signal input terminal. The first terminal of the second delay unit 400 is connected to the control terminal of the first switching transistor Q1, and the second terminal of the second delay unit 400 is connected to the control terminal of the second switching transistor Q2. The second conducting terminal of the second switching transistor Q2 is the output terminal of the first high-voltage switching circuit 100. Specifically, the second conducting terminal of the second switching transistor Q2 is connected to the first terminal of the pull-down resistor, and the second terminal of the pull-down resistor is connected to the ground terminal. Let the duty cycle of the reference pulse signal VIN be Y, and the delay duration of the second delay unit 400 be Y(X-1) / X of the period of the reference pulse signal VIN. Specifically, let the delay duration of the second delay unit 400 be Ti, then Ti = Y(X-1)T / X, where Y is greater than 0 and less than 1, and Y is usually set to 0.5.

[0035] It should be noted that when both the first switch Q1 and the second switch Q2 are turned on, the second conducting terminal of the second switch Q2 is connected to the high-voltage power supply terminal, and the voltage at the first conducting terminal of the first switch Q1 is high. That is, the first pulse signal output by the first high-voltage switching circuit 100 is high. When either the first switch Q1 or the second switch Q2 is turned off, the second conducting terminal of the second switch Q2 is disconnected from the high-voltage power supply terminal and grounded. That is, the pulse signal output by the high-voltage switching circuit is low. Therefore, by delaying the reference pulse signal VIN transmitted to the second switch Q2 through the second delay unit 400, a phase difference exists between the signals received by the first switch Q1 and the second switch Q2, so that the time for the first switch Q1 and the second switch Q2 to conduct simultaneously is only YT-Ti, that is, the time for the first switch Q1 and the second switch Q2 to conduct simultaneously is equal to YT / X. The pulse width of the first pulse signal output by the first high voltage switching circuit 100 is 1 / X of the pulse width of the reference pulse signal VIN, which corresponds to the single pulse width of the target frequency multiplier signal VOUT. At this time, the duty cycle of the first pulse signal output by the first high voltage switching circuit 100 is also only 1 / X of the duty cycle of the reference pulse signal VIN.

[0036] like Figure 3As shown, in this embodiment, the second high-voltage switching circuit 200 includes a second delay unit 400, a third switch Q3, and a fourth switch Q4. The first conducting terminal of the third switch Q3 is connected to the high-voltage power supply terminal, the second conducting terminal of the third switch Q3 is connected to the first conducting terminal of the fourth switch Q4, the control terminal of the third switch Q3 is connected to the output terminal of the corresponding first delay unit 310 in the delay circuit 300, the first terminal of the second delay unit 400 is connected to the control terminal of the third switch Q3, the second terminal of the second delay unit 400 is connected to the control terminal of the fourth switch Q4, and the second conducting terminal of the fourth switch Q4 is the output terminal of the first high-voltage switching circuit 100. Specifically, the second conducting terminal of the fourth switch Q4 is connected to the first terminal of the pull-down resistor. The principle of the second high-voltage switch circuit 200 outputting the second pulse signal is similar to that of the first high-voltage switch circuit 100 outputting the first pulse signal. The difference is that the signal received by the second high-voltage switch circuit 200 is a reference pulse signal delayed by the delay circuit 300. The different received signals cause a phase difference between the second pulse signal output by the second high-voltage switch circuit 200 and the first pulse signal.

[0037] In this embodiment, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are all Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Specifically, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are all NMOS transistors. The drain of the NMOS transistor corresponds to the first on-terminal of the switch, the source of the NMOS transistor corresponds to the second on-terminal of the switch, and the gate of the NMOS transistor corresponds to the control terminal of the switch. In one example, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are all N-type LDMOS (laterally-diffused metal-oxide semiconductor) transistors.

[0038] In another embodiment, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are all insulated gate bipolar transistors (IGBTs).

[0039] Both MOSFETs and IGBTs can withstand higher voltages, and compared to operational amplifiers, MOSFETs and IGBTs are less expensive.

[0040] In another embodiment, the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are all switching devices / chips made of compound semiconductor materials, such as GaN / SiC / GaAs switching devices / chips.

[0041] In this embodiment, each of the first delay unit 310 and the second delay unit 400 includes a capacitor, and both are capacitor delay units. In one example, such as Figure 2 As shown, the second delay unit 400 of the first high-voltage switching circuit 100 includes a capacitor C1. The first end of the capacitor C1 is connected to the control terminal of the corresponding first switching transistor Q1, and the second end of the capacitor C1 is connected to the control terminal of the corresponding second switching transistor Q2. The first end of the capacitor C1 is the input terminal of the second delay unit 400, and the second end of the capacitor C1 is the output terminal of the second delay unit 400. In one example, as... Figure 4 As shown, the first delay unit 310 includes capacitor C2, and the (X-1)th first delay unit 310 includes capacitor C3. The first end of capacitor C2 is both the input terminal of the delay circuit 300 and the corresponding first delay unit 310, used to connect to the signal input terminal. The second end of capacitor C2 is the output terminal of the first delay unit 310, used to connect to the corresponding second high-voltage switching circuit 200 and the input terminal of the adjacent next first delay unit 310. The first end of capacitor C3 is the input terminal of the corresponding first delay unit 310, used to connect to the output terminal of the adjacent previous first delay unit 310. The second end of capacitor C3 is the output terminal of the corresponding first delay unit 310, used to connect to the corresponding second high-voltage switching circuit 200. The value of capacitor C1 corresponds to the delay duration of the second delay unit 400 and is used to configure the pulse width of the target frequency multiplication signal VOUT. The values ​​of capacitors C2 and C3 are equal and correspond to the delay duration of the first delay unit 310, used to configure the phase difference between each pulse of the target frequency multiplication signal VOUT.

[0042] In one embodiment, N equals 1, X equals 2, and the frequency multiplier circuit 10 is specifically a frequency doubling circuit, such as... Figure 5 As shown, Figure 5 This is a specific circuit diagram of this embodiment, where the frequency multiplication signal VOUT is a second frequency multiplication signal.

[0043] Accordingly, this embodiment has one first delay unit 310 and two second delay units 400. The delay duration of the first delay unit 310 is T / 2, and the delay duration of the second delay unit 400 is YT / 2. When Y is 0.5, the delay duration of the second delay unit 400 is T / 4. In this embodiment, the waveforms of the reference pulse signal, the first pulse signal V1, the second pulse signal V2, and the frequency multiplication signal VOUT are as follows: Figure 6 As shown.

[0044] In another embodiment, N equals 2, X equals 4, the frequency multiplier circuit 10 is a quadruple frequency multiplier circuit, and the frequency multiplier signal VOUT is a quadruple frequency multiplier signal. Accordingly, this embodiment has three first delay units 310 and four second delay units 400. The delay duration of each first delay unit 310 is T / 4, and the cumulative delay durations corresponding to the signals output by each first delay unit 310, from smallest to largest, are T / 4, T / 2, and 3T / 4, respectively. The delay duration of the second delay unit 400 is 3YT / 4. Wherein, when Y is 0.5, the delay duration of the second delay unit 400 is 3T / 8.

[0045] In another embodiment, N equals 3, X equals 8, the frequency multiplier circuit 10 is an eighth-multiplier circuit, and the frequency multiplier signal VOUT is an eighth-multiplier signal. Accordingly, this embodiment has seven first delay units 310 and eight second delay units 400. The delay duration of each first delay unit 310 is T / 8, and the cumulative delay durations corresponding to the signals output by each first delay unit 310, from smallest to largest, are T / 8, T / 4, 3T / 8, T / 2, 5T / 8, 3T / 4, and 7T / 8, respectively. The delay duration of the second delay unit 400 is 7T / 8. Wherein, when Y is 0.5, the delay duration of the second delay unit 400 is 7T / 16.

[0046] Figure 7 A schematic diagram of a frequency multiplier device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0047] A frequency multiplier includes a plurality of frequency multiplier circuits 10 according to any of the above embodiments. The frequency multiplier circuits 10 are connected in series. Between two adjacent frequency multiplier circuits 10, the multiplied signal output by the preceding frequency multiplier circuit 10 is used as a reference pulse signal for the following frequency multiplier circuit 10. Multiple frequency multiplier circuits 10 can achieve multi-stage amplification of the signal frequency. The number of frequency multiplier circuits 10 and the frequency amplification factor of each frequency multiplier circuit 10 can be set according to actual conditions. The frequency amplification factor of the frequency multiplier is the product of the frequency amplification factors of each frequency multiplier circuit 10. For example, it may include two frequency multiplier circuits 10, and both frequency multiplier circuits 10 are double frequency multipliers; in this case, the frequency amplification factor of the frequency multiplier is 4.

[0048] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0049] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0050] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A frequency multiplier circuit, characterized in that, include: A first high-voltage switching circuit is connected to a signal input terminal and a high-voltage power supply terminal respectively. The first high-voltage switching circuit is configured to generate and output a first pulse signal based on a periodically changing reference pulse signal provided by the signal input terminal by controlling the switching between the high-voltage power supply terminal and the ground terminal. The circuit includes a delay circuit and X-1 second high-voltage switching circuits, where X is the frequency amplification factor of the frequency multiplier circuit, X equals 2 to the power of N, and N is a natural number greater than or equal to 1. The delay circuit includes X-1 first delay units connected in series, and each second high-voltage switching circuit corresponds to one of the first delay units. The input terminal of the delay circuit is connected to the signal input terminal, and the output terminal of each first delay unit is connected to the corresponding second high-voltage switching circuit. The first delay unit is used to delay the received signal and output it to the next adjacent first delay unit or the corresponding second high-voltage switching circuit. Each of the second high-voltage switching circuits is also connected to the high-voltage power supply terminal. Each of the second high-voltage switching circuits is configured to generate and output X-1 second pulse signals based on the delayed reference pulse signal output by the corresponding first delay unit by controlling the switching between the high-voltage power supply terminal and the ground terminal. The output terminal of the first high-voltage switching circuit is connected to the output terminal of each of the second high-voltage switching circuits and is connected to the ground terminal through a pull-down resistor. The first pulse signal and each of the second pulse signals are used to synthesize a frequency multiplication signal. The duty cycle of the first pulse signal and each of the second pulse signals is 1 / X of the duty cycle of the reference pulse signal, and the frequency of the first pulse signal and each of the second pulse signals is the same as the frequency of the reference pulse signal. The delay duration of each of the first delay units is 1 / X of the period of the reference pulse signal. The first high-voltage switching circuit includes a second delay unit, a first switching transistor, and a second switching transistor. The first conducting terminal of the first switching transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the first switching transistor is connected to the first conducting terminal of the second switching transistor, the control terminal of the first switching transistor is connected to the signal input terminal, the first terminal of the second delay unit is connected to the control terminal of the first switching transistor, the second terminal of the second delay unit is connected to the control terminal of the second switching transistor, and the second conducting terminal of the second switching transistor is the output terminal of the first high-voltage switching circuit. The duty cycle of the reference pulse signal is Y, and the delay duration of the second delay unit is Y(X-1) / X, which is the period of the reference pulse signal.

2. The frequency multiplier circuit as described in claim 1, characterized in that, Each of the second high-voltage switching circuits includes a second delay unit, a third switching transistor, and a fourth switching transistor. The first conducting terminal of the third switching transistor is connected to the high-voltage power supply terminal, the second conducting terminal of the third switching transistor is connected to the first conducting terminal of the fourth switching transistor, the control terminal of the third switching transistor is connected to the delay circuit, the first terminal of the second delay unit is connected to the control terminal of the third switching transistor, the second terminal of the second delay unit is connected to the control terminal of the fourth switching transistor, and the second conducting terminal of the fourth switching transistor is the output terminal of the second high-voltage switching circuit.

3. The frequency multiplier circuit as described in claim 2, characterized in that, The first switch, the second switch, the third switch, and the fourth switch are all MOSFETs.

4. The frequency multiplier circuit as described in claim 2, characterized in that, The first switch, the second switch, the third switch, and the fourth switch are all IGBTs.

5. The frequency multiplier circuit as described in claim 2, characterized in that, Each of the first delay unit and the second delay unit includes a capacitor.

6. The frequency multiplier circuit according to any one of claims 1 to 5, characterized in that, N equals 1, X equals 2, and the frequency multiplication signal is a second frequency multiplication signal.

7. The frequency multiplier circuit according to any one of claims 1 to 5, characterized in that, N equals 2, X equals 4, and the frequency multiplication signal is a quadruple frequency multiplication signal.

8. The frequency multiplier circuit according to any one of claims 1 to 5, characterized in that, N equals 3, X equals 8, and the frequency multiplication signal is an eighth frequency multiplication signal.

9. A frequency multiplier, characterized in that, It includes multiple frequency multiplier circuits as described in any one of claims 1 to 8, wherein each frequency multiplier circuit is connected in series, and between two adjacent frequency multiplier circuits, the frequency multiplier signal output by the preceding frequency multiplier circuit is used as the reference pulse signal of the following frequency multiplier circuit.

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