A voltage-pulse width conversion circuit for temperature sensor and temperature sensor

Abstract

The present invention discloses a voltage-to-pulse-width conversion circuit and a temperature sensor for a temperature sensor. The present invention proposes a new conversion scheme, namely a voltage-to-pulse-width conversion scheme, in the temperature sensor to change the voltage readout architecture. The front end of the temperature sensor can generate a voltage V proportional to the absolute temperature. PTAT and the voltage V which is inversely proportional to the absolute temperature CTAT , through the comparison output of the comparator and the logic processing of the digital circuit, the high level of the pulse width modulation output will PTAT and V CTAT This is converted into pulse width, completing capacitor reset at a low level, separating the capacitor reset time from the voltage-to-pulse-width conversion time. This novel voltage-to-pulse-width conversion architecture avoids the error caused by adding the capacitor reset time directly to the duty cycle output, as is the case with existing technologies. Furthermore, the capacitor reset time is generated internally by the circuit, eliminating the need for an additional clock and reducing system complexity.

Description

Technical Field

[0001] The present invention belongs to the field of sensors, and in particular relates to a voltage-pulse width conversion circuit for a temperature sensor and a temperature sensor. Background Art

[0002] Temperature monitoring is fundamental to many industries and crucial in production and daily life. CMOS temperature sensors are widely used in various fields, such as on-chip thermal management, the Internet of Things (IoT), and real-time clock (RTC) calibration. Typically, a CMOS temperature sensor consists of a temperature sensing device and a readout interface. Common temperature sensing devices include bipolar junction transistors (BJTs), MOSFETs, and resistors. Currently, the most commonly used readout interface in academia and industry is the analog-to-digital converter (ADC). Other time-domain readout solutions convert temperature information into pulses or frequencies, which are then further digitized using a time-to-digital converter (TDC) or a frequency-to-digital converter (FDC). Alternatively, a duty cycle modulator (DCM) can be used to convert temperature information into a duty cycle output. This solution offers a simple interface and can be easily and reliably connected to digital systems, such as microcontrollers, as well as analog systems, such as thermostats.

[0003] However, a drawback of existing technologies is that the time required to reset the capacitor is directly added to the duty cycle output, increasing errors. The existing solution to this error is to introduce an external clock to accurately generate the reset time, allowing digital calibration on the back end to eliminate the error. However, this requires an additional clock and increases system complexity. Therefore, how to eliminate this error in existing technologies without increasing system complexity is a pressing technical problem in the field of temperature sensors. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems existing in the above-mentioned prior art and to provide a voltage-to-pulse width conversion circuit for a temperature sensor and a temperature sensor.

[0005] The specific technical solutions adopted in the present invention are as follows:

[0006] In a first aspect, the present invention provides a voltage-to-pulse width conversion circuit for a temperature sensor, comprising a first capacitor, a current source, a comparator, and a digital module;

[0007] The first input of the voltage-pulse width conversion circuit is the first voltage V output by the external first voltage source which is positively correlated with the temperature. PTAT The second input is the second voltage V output by the external second voltage source which is negatively correlated with the temperature. CTAT ;

[0008] A third switch is connected in parallel across the first capacitor, and the first capacitor is discharged by turning off the third switch;

[0009] The output end of the current source is connected to the first capacitor, for charging the first capacitor;

[0010] The positive input terminal of the comparator is connected to an external first voltage source through a first switch and is connected to an external second voltage source through a second switch, the negative input terminal of the comparator is connected to the output terminal of the current source and the first capacitor, and the output terminal of the comparator is connected to the digital module; the comparator is used to compare the voltages input to the positive and negative input terminals and output the voltage comparison result;

[0011] The input end of the digital module is connected to the output end of the comparator, and outputs the control signal Φ1 of the first switch, the control signal Φ2 of the second switch, the control signal RST of the third switch at both ends of the first capacitor, and finally the pulse width modulation output signal for reflecting the temperature.

[0012] In a second aspect, the present invention provides a temperature sensor based on pulse width modulation output, which includes a voltage-pulse width conversion circuit and a PTAT bias current generating circuit as described in any solution of the first aspect above;

[0013] The PTAT bias current generating circuit is used to generate two inputs of the voltage-to-pulse width conversion circuit, and includes a first bipolar junction transistor, a second bipolar junction transistor, a third bipolar junction transistor, an operational amplifier, a second capacitor, a resistor, a bias resistor, and a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; the first bipolar junction transistor and the second bipolar junction transistor are both PNP bipolar junction transistors, and the third bipolar junction transistor is an NPN bipolar junction transistor;

[0014] The positive input terminal of the operational amplifier is connected to the emitter of the second bipolar junction transistor, the negative input terminal of the operational amplifier is connected to one end of the resistor, the other end of the resistor is connected to the emitter of the first bipolar junction transistor, the base and collector of the first bipolar junction transistor and the second bipolar junction transistor are both grounded, the output terminal of the operational amplifier is connected to the gate of the ninth MOS transistor, and the two ends of the second capacitor are respectively connected to the gate and source of the ninth MOS transistor, and the drain of the ninth MOS transistor is connected to the gate of the second MOS transistor and the drain of the fifth MOS transistor;

[0015] The first MOS tube and the fifth MOS tube are cascaded, the second MOS tube and the sixth MOS tube are cascaded, the third MOS tube and the seventh MOS tube are cascaded, and the fourth MOS tube and the eighth MOS tube are cascaded, and the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are commonly gated, and the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are commonly gated, thereby forming a current mirror; the first branch formed by the cascade connection of the second MOS tube and the sixth MOS tube provides a bias current for the negative input terminal of the operational amplifier, and the second branch formed by the cascade connection of the third MOS tube and the seventh MOS tube provides a bias current for the positive input terminal of the operational amplifier; the third branch formed by the cascade connection of the fourth MOS tube and the eighth MOS tube is connected to the grounded bias resistor through the fourth switch, thereby generating a first voltage V that is positively correlated with temperature PTAT At the same time, the third branch is connected to the base and collector of the third bipolar junction transistor through the fifth switch, thereby generating a second voltage V CTAT , the emitter of the third bipolar junction transistor is grounded.

[0016] As a preferred embodiment of the second aspect, the first branch, the second branch and the third branch use dynamic element matching (DEM) technology to improve matching.

[0017] As a preferred embodiment of the second aspect, the resistor, the first bipolar junction transistor and the second bipolar junction transistor use Kelvin Connection Dynamic Element Matching (KC-DEM) technology to reduce mismatch of the bipolar junction transistors.

[0018] As a preferred embodiment of the second aspect, the operational amplifier uses chopping technology to reduce offset voltage 1 / f noise.

[0019] As a preferred embodiment of the second aspect, the comparator adopts a chopping technology to reduce the offset voltage.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention proposes a new conversion scheme, namely voltage-pulse width conversion scheme, in the temperature sensor to change the voltage readout architecture. The temperature sensor front end can generate a voltage V proportional to the absolute temperature. PTAT and the voltage V which is inversely proportional to the absolute temperature CTAT , through the comparison output of the comparator and the logic processing of the digital circuit, the high level of the pulse width modulation output will PTAT and V CTAT This is converted into pulse width, completing capacitor reset at a low level, separating the capacitor reset time from the voltage-to-pulse-width conversion time. This novel voltage-to-pulse-width conversion architecture avoids errors caused by the prior art where the capacitor reset time is directly added to the duty cycle output. Furthermore, the capacitor reset time is generated internally by the circuit, eliminating the need for an additional clock and reducing system complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the schematic diagram of the voltage-pulse width conversion circuit;

[0023] Figure 2 It is the timing diagram of digital module;

[0024] Figure 3 This is the pulse width modulation output temperature sensor circuit diagram;

[0025] Figure 4 This is the timing diagram for the DEM and chopping control clock. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in the various embodiments of the present invention can be combined accordingly without conflicting with each other.

[0027] In the description of the present invention, it should be understood that the terms "first" and "second" are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly specifying the number of technical features being described. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one of such features.

[0028] In a preferred embodiment of the present invention, a voltage-pulse width conversion circuit for a temperature sensor is provided, which converts the capacitor reset time to V PTAT 、V CTATThe time of voltage-pulse width conversion is separated, which has smaller error and higher accuracy than traditional conversion circuit. Figure 1 As shown, the voltage-pulse width conversion circuit includes a first capacitor C1, a current source D, a comparator E and a digital module F. The first input of the voltage-pulse width conversion circuit is a first voltage V output by an external first voltage source A that is positively correlated with temperature. PTAT The second input is the second voltage V output by the external second voltage source B, which is negatively correlated with the temperature. CTAT . A third switch SW3 is connected in parallel at both ends of the first capacitor C1, and the first capacitor C1 is discharged by turning off the third switch SW3. The output end of the current source D is connected to the first capacitor C1 and is used to charge the first capacitor C1. The positive input end of the comparator E is connected to the external first voltage source A through the first switch SW1 and is connected to the external second voltage source B through the second switch SW2. The negative input end of the comparator E is connected to the output end of the current source D and the first capacitor C1, and the output end of the comparator E is connected to the digital module F. The comparator E is used to compare the voltages input at the positive and negative input ends and output the voltage comparison result. The input end of the digital module F is connected to the output end of the comparator E, and outputs the control signal Φ1 of the first switch SW1, the control signal Φ2 of the second switch SW2, the control signal RST of the third switch SW3 at both ends of the first capacitor C1, and finally the pulse width modulation output signal used to reflect the temperature.

[0029] It should be noted that the two inputs of the above-mentioned voltage-to-pulse-width conversion circuit can be obtained by an external induction device and then input into the voltage-to-pulse-width conversion circuit.

[0030] exist Figure 1 In the voltage-to-pulse width conversion architecture shown, the circuit operates in two alternating phases. The first capacitor C is connected to the negative input of the comparator E. The voltage V C After the initial reset to 0 (followed by the charging current I C At the beginning of phase 1 (i.e. Φ1), the first switch SW1 is turned on, the second switch SW2 is turned off, and V PTAT and V C Connected to the positive input and negative input of comparator E respectively. C Less than V PTAT The output of comparator E remains at logic high level. Once V C Greater than V PTAT The output of the comparator E changes to a logic low level, generating a falling edge. When the falling edge is generated, the third switch SW3 is controlled to close and discharge through the control signal RST, so that the voltage V CReset to 0, the comparator E output returns to logic high level. After the reset is completed, the circuit enters phase 2 (ie Φ2), at this time, the first switch SW1 is closed, the second switch SW2 is opened, V CTAT is connected to the positive input of comparator E, and the first capacitor C is still connected to the negative input of comparator E. C Greater than V CTAT When the comparator E output changes to logic low again, the voltage V on the first capacitor C C Reset to 0, the circuit enters a new cycle. After converting to the time domain, V CTAT and V PTAT It can represent:

[0031]

[0032]

[0033] Among them I C is the charging current, C is the capacitance of the first capacitor, t h1_start and t h1_end are the start and end time of the logic high level of phase 1 (Φ1), t h2_start and t h2_end These are the start and end times of the logic high level of phase 2 (Φ1), respectively.

[0034] The output of digital module F includes phase conversion signal (Φ1, Φ2), capacitor reset signal (RST) and pulse width modulation output signal. The specific conversion logic of digital module F is as follows Figure 2 , the process is as follows:

[0035] During the comparison by comparator E, the output of comparator E is connected to the CLK terminal of a D flip-flop after being connected to an inverter. The QN output of the D flip-flop is connected to the D terminal, and a new signal DOUT is generated at the Q output. The new signal DOUT undergoes a level jump when a falling edge occurs at the output of comparator E, and non-overlapping clock signals Φ1 and Φ2 are generated through a logic circuit to control the first switch SW1 and the second switch SW2. The new signal DOUT is then delayed by an RC delay to generate a signal DOUTD. The signals DOUT and DOUTD are connected to the inputs of an exclusive-OR gate, and the output of the exclusive-OR gate generates a control signal RST. The control signal RST is connected to the third switch SW3 to reset the first capacitor C1. Simultaneously, the output of comparator E and the control signal RST are connected to the two terminals of a latch module as inputs, and the latch module outputs a pulse-width modulated output signal, so that the final pulse-width modulated output signal remains at a low level when the control signal RST is high, and normally outputs a high level when the control signal RST is low.

[0036] above Figure 1The novel voltage-to-pulse-width conversion architecture shown can be used in scenarios where voltage reading is required. The following describes its specific implementation using a temperature sensor as an example.

[0037] like Figure 3 As shown, in a preferred embodiment of the present invention, a temperature sensor based on pulse width modulation output is provided, which includes the above-mentioned Figure 1 The voltage-pulse width conversion circuit and PTAT bias current generating circuit for temperature sensor are shown. Figure 1 Consistent, PTAT bias current generation circuit is used to generate Figure 1 The two inputs of the voltage-pulse width conversion circuit shown in the figure generate V PTAT and V CTAT The PTAT bias current generating circuit includes a first bipolar junction transistor Q1, a second bipolar junction transistor Q2, a third bipolar junction transistor Q3, an operational amplifier G, a second capacitor C2, a resistor R1, a bias resistor R2 and a first MOS transistor M P1 , the second MOS tube M P2 , the third MOS tube M P3 , the fourth MOS tube M P4 , the fifth MOS tube M P5 , the sixth MOS tube M P6 , the seventh MOS tube M P7 , the eighth MOS tube M P8 、Ninth MOS tube M N1 .

[0038] The first bipolar junction transistor Q1 and the second bipolar junction transistor Q2 are both PNP bipolar junction transistors, and the third bipolar junction transistor Q3 is an NPN bipolar junction transistor.

[0039] The positive input terminal of the operational amplifier G is connected to the emitter of the second bipolar junction transistor Q2, the negative input terminal of the operational amplifier G is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the first bipolar junction transistor Q1, the base and collector of the first bipolar junction transistor Q1 and the second bipolar junction transistor Q2 are grounded, and the output terminal of the operational amplifier G is connected to the ninth MOS transistor M N1 The gate of the second capacitor C2 is connected to the ninth MOS tube M N1 The gate and source of the ninth MOS tube M N1 The drain is connected to the second MOS tube M P2 The gate and the fifth MOS tube M P5 of the drain.

[0040] The first MOS tube M P1And the fifth MOS tube M P5 Cascade, the second MOS tube M P2 And the sixth MOS tube M P6 Cascade, the third MOS tube M P3 And the seventh MOS tube M P7 Cascade, the fourth MOS tube M P4 And the eighth MOS tube M P8 Cascade, and the first MOS tube M P1 , the second MOS tube M P2 , the third MOS tube M P3 And the fourth MOS tube M P4 Common gate, fifth MOS tube M P5 , the sixth MOS tube M P6 , the seventh MOS tube M P7 And the eighth MOS tube M P8 Common gate, first MOS tube M P1 , the second MOS tube M P2 , the third MOS tube M P3 , the fourth MOS tube M P4 , the fifth MOS tube M P5 , the sixth MOS tube M P6 , the seventh MOS tube M P7 And the eighth MOS tube M P8 Together they form a current mirror. The second MOS tube M P2 And the sixth MOS tube M P6 The first branch formed by the cascade provides bias current for the negative input terminal of the operational amplifier G. The third MOS tube M P3 And the seventh MOS tube M P7 The second branch formed by the cascade provides a bias current for the positive input terminal of the operational amplifier G; the fourth MOS tube M P4 And the eighth MOS tube M P8 The third branch formed by the cascade is connected to the bias resistor R2 connected to the ground via the fourth switch SW4, thereby generating a first voltage V that is positively correlated with the temperature. PTAT At the same time, the third branch is also connected to the base and collector of the third bipolar junction transistor Q3 through the fifth switch SW5, thereby generating a second voltage V CTAT , the emitter of the third bipolar junction transistor Q3 is grounded.

[0041] Therefore, the above Figure 3The pulse width modulation output temperature sensor in the circuit is mainly divided into two parts: the PTAT bias current generation circuit and the voltage-to-pulse width conversion circuit. The design sets the PNP type BJT area ratio, that is, the area ratio of the first bipolar junction transistor Q1 and the second bipolar junction transistor Q2 is 3:1, and the bias current ratio of Q1 and Q2 is 1:5, thereby generating the base-emitter voltage difference between the bipolar junction transistors Q1 and Q2, ΔV BE , and converted into PTAT bias current I=ΔV BE / R1. At the same time, the bias current I is set so that the proportionality factor β between the base current and the collector current of transistors Q1 and Q2 is close. The bias resistor R2 is used to generate V PTAT =2·R2·ΔV BE / R1=n·ΔV BE , where n is the magnification factor, which is determined by the ratio of resistor R2 to resistor R1 and the current mirror replication ratio 2. An NPN type BJT is used to generate V BE , which can provide higher β, V CTAT =V BE Let X = V BE / (n·ΔV BE ), we can get:

[0042]

[0043] Where μ is the linear formula for temperature and k is the curvature compensation coefficient in the digital domain. The temperature can be calculated as:

[0044] T=A·μ+B (4)

[0045] Where A and B are temperature calculation coefficients, and T is the Celsius temperature. Let t1 = t h1_end -t h1_start , t2=t h2_end -t h2_start , combining formulas (1)-(3), μ can be written as

[0046]

[0047] Finally, by measuring the values ​​of t1 and t2 of the PWM output, the temperature can be easily calculated.

[0048] The operational transconductance amplifier (OTA) used in the above PTAT bias current generation circuit is a PMOS input sleeve structure. At the same time, the proposed design connects the output of the OTA to a common source amplifier that uses a diode-connected load and makes Figure 3 Medium M P2The gate becomes a low impedance node. A continuous time dynamic comparator is used to convert the voltage into a pulse width output, which is a low power comparator design. The comparator output is connected to the digital module for digital processing. The digital module outputs a phase conversion signal, a capacitor reset signal, and a pulse width modulation signal. The specific digital module conversion logic is as follows: Figure 2 As shown, the specific process is as described above and will not be repeated here.

[0049] In order to achieve better layout matching, in the present invention, resistors R1 and R2 use the same type of resistor HRPOLYU, which can achieve a matching accuracy of less than 0.2%. The current mirror also has mismatch, which depends on the matching of the PMOS tube. It is difficult to achieve a matching degree of less than 1% by relying solely on layout matching. Therefore, Dynamic Element Matching (DEM) is used to match the current mirror. Figure 3 The DEM1 frame has 8 branches of current (including the first branch, the second branch and the third branch, the unit current branch ratio of the three branches is 1:5:2) and uses DEM technology to further improve the matching degree. Figure 3 The part framed by DEM2 (i.e., R1, Q1, and Q2) applies Kelvin Connection Dynamic Element Matching (KC-DEM) to reduce the mismatch of BJT.

[0050] The offset voltage of the op amp in the PTAT bias current generation circuit will be directly superimposed on ΔV BE When the resistor ratio is used to amplify the voltage, it is amplified proportionally. Therefore, the op amp needs to use chopping technology to reduce the impact of the offset voltage and low-frequency 1 / f noise. In addition, there is also an offset voltage in the comparator, which will be directly superimposed on V PTAT and V CTAT This results in a non-negligible voltage-time conversion error. To eliminate this error, we also need to use chopping technology for the comparator. Unlike the traditional solution that uses an external clock to generate the control signal, the control clocks for DEM and chopping are both generated by the duty cycle modulated output and are generated when the capacitor is reset. Therefore, the circuit has enough time to stabilize before the next flip. The frequencies of chopping, DEM1, and DEM2 are f DCM / 2, f DCM / 8,f DCM / 4, where f DCM is the duty cycle modulated output frequency. Figure 4 It is the timing diagram of duty cycle modulation output, DEM and chopping control clock.

[0051] When using DEM and chopping, the switching ripple will cause errors in the PTAT bias current. Therefore, to avoid the capacitor voltage V C The voltage error on the charging current I C Generated by an independent bias current circuit instead of using a PTAT bias circuit.

[0052] The embodiment described above is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Persons skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent substitution or equivalent transformation falls within the scope of protection of the present invention.

Claims

1. A voltage-to-pulse width conversion circuit for a temperature sensor, characterized in that: It includes a first capacitor (C1), a current source (D), a comparator (E) and a digital module (F); The first input of the voltage-pulse width conversion circuit is the first voltage V output by the external first voltage source (A) which is positively correlated with the temperature. PTAT The second input is the second voltage V output by the external second voltage source (B) which is negatively correlated with the temperature. CTAT ; A third switch (SW3) is connected in parallel to both ends of the first capacitor (C1), and the first capacitor (C1) is discharged by turning off the third switch (SW3); The output end of the current source (D) is connected to the first capacitor (C1) for charging the first capacitor (C1); The positive input terminal of the comparator (E) is connected to an external first voltage source (A) through a first switch (SW1) and is connected to an external second voltage source (B) through a second switch (SW2); the negative input terminal of the comparator (E) is connected to the output terminal of the current source (D) and the first capacitor (C1); and the output terminal of the comparator (E) is connected to a digital module (F); the comparator (E) is used to compare the voltages inputted at the positive and negative input terminals and output a voltage comparison result; The input end of the digital module (F) is connected to the output end of the comparator (E), and outputs a control signal Φ1 of the first switch (SW1), a control signal Φ2 of the second switch (SW2), a control signal RST of the third switch (SW3) at both ends of the first capacitor (C1), and ultimately a pulse width modulation output signal for reflecting temperature.

2. A temperature sensor based on pulse width modulation output, characterized in that: comprising the voltage-pulse width conversion circuit and the PTAT bias current generating circuit as claimed in claim 1; The PTAT bias current generating circuit is used to generate two inputs of the voltage-pulse width conversion circuit, and includes a first bipolar junction transistor (Q1), a second bipolar junction transistor (Q2), a third bipolar junction transistor (Q3), an operational amplifier (G), a second capacitor (C2), a resistor (R1), a bias resistor (R2), and a first MOS transistor (M P1 ), the second MOS tube (M P2 ), the third MOS tube (M P3 ), the fourth MOS tube (M P4 ), the fifth MOS tube (M P5 ), the sixth MOS tube (M P6 ), the seventh MOS tube (M P7 ), the eighth MOS tube (M P8 ), the ninth MOS tube (M N1 ); the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2) are both PNP bipolar junction transistors, and the third bipolar junction transistor (Q3) is an NPN bipolar junction transistor; The positive input terminal of the operational amplifier (G) is connected to the emitter of the second bipolar junction transistor (Q2), the negative input terminal of the operational amplifier (G) is connected to one end of the resistor (R1), the other end of the resistor (R1) is connected to the emitter of the first bipolar junction transistor (Q1), the base and collector of the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2) are grounded, and the output terminal of the operational amplifier (G) is connected to the ninth MOS transistor (M N1 ) gate, and at the same time, both ends of the second capacitor (C2) are connected to the ninth MOS tube (M N1 ) gate and source, the ninth MOS tube (M N1 ) is connected to the drain of the second MOS tube (M P2 ) and the gate of the fifth MOS tube (M P5 ) of the drain; The first MOS tube (M P1 ) and the fifth MOS tube (M P5 ) cascade, the second MOS tube (M P2 ) and the sixth MOS tube (M P6 ) cascade, the third MOS tube (M P3 ) and the seventh MOS tube (M P7 ) cascade, the fourth MOS tube (M P4 ) and the eighth MOS tube (M P8 ) cascade, and the first MOS tube (M P1 ), the second MOS tube (M P2 ), the third MOS tube (M P3 ) and the fourth MOS tube (M P4 ) common gate, the fifth MOS tube (M P5 ), the sixth MOS tube (M P6 ), the seventh MOS tube (M P7 ) and the eighth MOS tube (M P8 ) together to form a current mirror; the second MOS tube (M P2 ) and the sixth MOS tube (M P6 ) cascaded to form the first branch to provide bias current for the negative input terminal of the operational amplifier (G), and the third MOS tube (M P3 ) and the seventh MOS tube (M P7 ) cascaded to form a second branch that provides bias current for the positive input of the operational amplifier (G); the fourth MOS tube (M P4 ) and the eighth MOS tube (M P8 ) is connected to the bias resistor (R2) connected to the ground via the fourth switch (SW4), thereby generating a first voltage V that is positively correlated with temperature. PTAT At the same time, the third branch is connected to the base and collector of the third bipolar junction transistor (Q3) through the fifth switch (SW5), thereby generating a second voltage V CTAT , the emitter of the third bipolar junction transistor (Q3) is grounded.

3. The temperature sensor based on pulse width modulation output according to claim 2, characterized in that: The first branch, the second branch and the third branch use dynamic element matching (DEM) technology to improve matching.

4. The temperature sensor based on pulse width modulation output according to claim 2, characterized in that: The resistor (R1), the first bipolar junction transistor (Q1) and the second bipolar junction transistor (Q2) adopt Kelvin Connection Dynamic Element Matching (KC-DEM) technology to reduce mismatch of the bipolar junction transistors.

5. The temperature sensor based on pulse width modulation output according to claim 2, characterized in that: The operational amplifier (G) uses chopping technology to reduce offset voltage and 1 / f noise.

6. The temperature sensor based on pulse width modulation output according to claim 2, characterized in that: The comparator (E) uses chopping technology to reduce the offset voltage.

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