Display substrate and manufacturing method thereof, and display device
By using a septum column composed of polymer elastomer and nanoparticles in an OLED display device and performing ultraviolet light irradiation repair treatment, the packaging failure problem caused by surface damage of the septum column is solved, and higher packaging effect and light output efficiency are achieved.
Patent Information
- Application Number
- CN202180000537.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-03-19
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2041-03-19
AI Technical Summary
The existing OLED display devices have problems of sub-pixel packaging failure during the packaging process, mainly because the packaging layer is punctured due to damage to the surface of the septum column, which in turn causes water and oxygen to penetrate into the organic light emitting layer.
A septum column including polymer elastomer and nanoparticles was used, and after the organic light emitting layer was evaporated, the septum column was subjected to ultraviolet irradiation repair treatment, so that the protrusions on the surface of the septum column changed from sharp to gentle, with a height less than 0.2 μm.
The damage to the surface of the diaphragm column is effectively repaired, the protruding puncture of the packaging layer is avoided, the packaging effect is improved, the service life of the display substrate is enhanced, and the light output efficiency is improved.
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Figure CN115380386B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art
[0002] Organic Light Emitting Diode (OLED) is a new type of flat panel display that has gradually attracted more attention. OLED is an active light-emitting element with the advantages of high brightness, color saturation, ultra-thinness, wide viewing angle, low power consumption, extremely high response speed and flexibility, which can better meet the personalized needs of users. With the continuous development of display technology, display devices with OLED as the light-emitting element and thin film transistor (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention
[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0004] A display substrate comprises a pixel definition layer and a spacer column arranged on a driving structure layer, wherein the spacer column is arranged on a surface of the pixel definition layer away from the driving structure layer, and the orthographic projection of the spacer column on a substrate is located within the range of the orthographic projection of the pixel definition layer on the substrate; the surface of the spacer column away from the driving structure layer has a protrusion, and the height of the protrusion is less than 0.2 μm.
[0005] In an exemplary embodiment, the material of the spacer column includes a polymer elastomer and nanoparticles, and the nanoparticles account for 0.5 wt % to 5 wt % of the spacer column.
[0006] In an exemplary embodiment, the nanoparticles have a diameter of 20 nm to 100 nm.
[0007] In an exemplary embodiment, the nanoparticles include methyl-modified inorganic nanoparticles.
[0008] In an exemplary embodiment, the methyl-modified inorganic nanoparticles include at least one of methyl-modified inorganic silicon oxide nanoparticles, methyl-modified inorganic zinc oxide nanoparticles, and methyl-modified inorganic zirconium oxide nanoparticles.
[0009] In an exemplary embodiment, the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology of the polymer elastomer is a cross-linked network formed by chemical connection, and the mesh diameter of the cross-linked network is 0.5 μm to 2.0 μm.
[0010] In an exemplary embodiment, the spacer pillar has a height of 1 μm to 1.5 μm.
[0011] In an exemplary embodiment, the light emitting structure layer further includes a pixel definition layer, the spacer column is disposed on a side of the pixel definition layer away from the substrate, and the pixel definition layer and the spacer column are made of the same material.
[0012] In an exemplary embodiment, the spacer pillars and the pixel definition layer are an integral structure.
[0013] A display device comprises the above-mentioned display substrate.
[0014] A method for preparing a display substrate, comprising:
[0015] A pixel definition layer and a spacer column are formed on the driving structure layer, wherein the spacer column is arranged on a surface of the pixel definition layer away from the driving structure layer, and an orthographic projection of the spacer column on the substrate is within a range of an orthographic projection of the pixel definition layer on the substrate;
[0016] Use fine metal mask to evaporate the organic light-emitting layer;
[0017] The spacer column is repaired, and a surface of the spacer column on a side away from the driving structure layer has a protrusion, and the height of the protrusion is less than 0.2 μm.
[0018] In an exemplary embodiment, the material of the spacer column includes a polymer elastomer and nanoparticles, the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology is a cross-linked network formed by chemical connection, and the mesh diameter of the cross-linked network is 0.5 μm to 2.0 μm; the spacer column is repaired, comprising:
[0019] The spacer column is irradiated with ultraviolet light, and the cross-linked network of the polymer elastomer expands and contracts under the ultraviolet light, so that the protrusions on the surface of the spacer column change from sharp to gentle, and the height of the protrusions is less than 0.2 μm.
[0020] In an exemplary embodiment, the irradiation intensity of the ultraviolet light is 5 mW / cm 2 Up to 20mW / cm 2 The irradiation time of the ultraviolet light is 100 seconds to 300 seconds.
[0021] In an exemplary embodiment,
[0022] Forming a pixel definition layer and a spacer column on the driving structure layer, comprising: forming a pixel definition layer on the driving structure layer; using a spacer column mask to form a spacer column on the pixel definition layer;
[0023] The spacer column is irradiated with ultraviolet light, comprising: placing the spacer column mask on the display substrate, and irradiating with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the spacer column mask and irradiates the spacer column.
[0024] In an exemplary embodiment,
[0025] Forming a pixel definition layer and a spacer column on the driving structure layer, comprising: using a gray tone mask to form the pixel definition layer and the spacer column on the driving structure layer through a same patterning process;
[0026] The spacer column is irradiated with ultraviolet light, comprising: placing the gray tone mask on the display substrate, and irradiating with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the gray tone mask and irradiates the spacer column.
[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.
[0029] Figure 1 is a structural schematic diagram of an OLED display device;
[0030] Figure 2 It is a schematic diagram of a planar structure of a display substrate;
[0031] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;
[0032] Figure 4 is a working timing diagram of a pixel driving circuit;
[0033] Figure 5 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;
[0034] Figure 6 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a driving structure layer pattern;
[0035] Figure 7 A schematic diagram of an exemplary embodiment of the present disclosure after an anode pattern is formed;
[0036] Figure 8 A schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;
[0037] Fig. 9 A schematic diagram of an exemplary embodiment of the present disclosure after forming a spacer column pattern;
[0038] Fig.10 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern;
[0039] Fig.11 Schematic diagram of generating sharp protrusions on the surface of the septum column;
[0040] Fig.12 It is a schematic diagram of the spacer column after the surface damage is repaired according to the exemplary embodiment of the present disclosure;
[0041] Fig.13 A schematic diagram of an exemplary embodiment of the present disclosure after a cathode pattern is formed;
[0042] Fig.14 It is a schematic diagram after forming a packaging structure layer pattern according to an exemplary embodiment of the present disclosure;
[0043] Fig.15 It is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure.
[0044] Description of reference numerals:
[0045] 1—glass carrier; 10—substrate; 21—anode;
[0046] 22—pixel definition layer; 23—organic light emitting layer; 24—cathode;
[0047] 25—spacer column; 26—protrusion; 31—first packaging layer;
[0048] 32—second packaging layer; 33—third packaging layer; 101—transistor;
[0049] 102—storage capacitor; 103—driving structure layer; 104—light emitting structure layer;
[0050] 105—packaging structure layer. DETAILED DESCRIPTION
[0051] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
[0052] In the drawings, the size of the constituent elements, the thickness of the layer, or the area may be exaggerated for the sake of clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values shown in the drawings.
[0053] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion among constituent elements rather than to limit the quantity.
[0054] In this document, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.
[0055] In this document, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.
[0056] In this article, a transistor refers to a component including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or drain electrode terminal, drain region, or drain electrode) and a source electrode (or source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the channel region refers to the region where the current mainly flows.
[0057] In this article, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may sometimes be interchanged. Therefore, in this article, the "source electrode" and the "drain electrode" may be interchanged.
[0058] In this article, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.
[0059] In this article, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the state where the angle is greater than 85° and less than 95°.
[0060] In this document, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".
[0061] The term "about" as used herein refers to values that are not strictly limited and allow for process and measurement errors.
[0062] Figure 1 Schematic diagram of the structure of an OLED display device. Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal to generate a luminous signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each subpixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. Subpixel Pxij may refer to a subpixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.
[0063] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a frame area located outside the display area. Figure 2As shown, the display area of the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.
[0064] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in horizontal parallel, vertical parallel, or in a herringbone manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in horizontal parallel, vertical parallel, or in a square manner, which is not limited in the present disclosure.
[0065] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C1 and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).
[0066] In an exemplary embodiment, a first end of the storage capacitor C1 is connected to the first power line VDD, and a second end of the storage capacitor C1 is connected to the second node N2 , ie, the second end of the storage capacitor C1 is connected to the control electrode of the third transistor T3 .
[0067] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.
[0068] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
[0069] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C1, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.
[0070] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
[0071] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.
[0072] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.
[0073] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
[0074] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
[0075] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.
[0076] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.
[0077] Figure 4 This is a working timing diagram of a pixel driving circuit. Figure 3 The operation process of the pixel driving circuit of the example is described in detail. Figure 3The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C1 and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.
[0078] In an exemplary embodiment, the operation process of the pixel driving circuit may include:
[0079] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.
[0080] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C1 is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1. The voltage of the second end (the second node N2) of the storage capacitor C1 is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
[0081] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
[0082] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:
[0083] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2
[0084] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.
[0085] Figure 5 FIG. 1 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a sub-pixel in an OLED display substrate. Figure 5As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 103 disposed on a substrate 10, a light emitting structure layer 104 disposed on a side of the driving circuit layer 103 away from the substrate 10, and an encapsulation structure layer 105 disposed on a side of the light emitting structure layer 104 away from the substrate 10. In an exemplary embodiment, the driving circuit layer 103 may include a transistor 101 and a storage capacitor 102. In an exemplary embodiment, the light emitting structure layer 104 is a light emitting device that makes an organic material emit light, and the light emitting structure layer 104 may include an anode 21, a pixel definition layer 22, an organic light emitting layer 23, a cathode 24, and a spacer column 25, the pixel definition layer 22 is provided with a pixel opening exposing the anode 21, the organic light emitting layer 23 is disposed between the anode 21 and the cathode 24, the spacer column 25 is disposed on the surface of the pixel definition layer 22 away from the substrate 10, and the orthographic projection of the spacer column 25 on the substrate is located within the range of the orthographic projection of the pixel definition layer 22 on the substrate. In an exemplary embodiment, the spacer column (PS) 25 is configured to support a fine metal mask or an open mask used for evaporating an organic light-emitting material. The encapsulation structure layer 105 may include a first encapsulation layer disposed on a side of the light-emitting structure layer 104 away from the substrate, a second encapsulation layer disposed on a side of the first encapsulation layer away from the substrate, and a third encapsulation layer disposed on a side of the second encapsulation layer away from the substrate, and the second encapsulation layer of organic material is disposed between the first encapsulation layer and the third encapsulation layer of inorganic material to form a laminated structure of inorganic material / organic material / inorganic material.
[0086] In an exemplary embodiment, the material of the spacer column 25 may include a polymer elastomer and nanoparticles. The material of the polymer elastomer may include polyurethane, polysiloxane or liquid crystal block polymer, etc., the nanoparticles may be inorganic nanoparticles, the inorganic nanoparticles may be methyl-modified inorganic nanoparticles, and the methyl-modified inorganic nanoparticles may include methyl-modified inorganic silicon oxide nanoparticles, methyl-modified inorganic zinc oxide nanoparticles or methyl-modified inorganic zirconium oxide nanoparticles, etc.
[0087] In an exemplary embodiment, the methyl-modified inorganic nanoparticles may be prepared by introducing methyl groups onto the surface of the inorganic nanoparticles through treatment with a surfactant.
[0088] In an exemplary embodiment, the polymer elastomer has a morphology of a cross-linked network, and the inorganic nanoparticles are dispersed in the meshes of the cross-linked network composed of the polymer elastomer to support the cross-linked network, wherein the cross-linked network is formed by chemical connection of the polymer elastomer.
[0089] In exemplary embodiments, the inorganic nanoparticles may have a particle size of about 20 nm to about 100 nm.
[0090] In an exemplary embodiment, the inorganic nanoparticles may account for about 0.5 wt % to about 5 wt % in the spacer column.
[0091] In an exemplary embodiment, the thickness of the spacer column 25 may be about 1.0 μm to 1.5 μm.
[0092] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
[0093] In an exemplary embodiment, the preparation process of the display substrate includes the following operations.
[0094] (1) Forming a substrate on a glass carrier. In an exemplary embodiment, forming a substrate on a glass carrier may include: coating a first flexible material film on a glass carrier 1, and forming a first flexible layer after curing; coating a second flexible material film on a surface of the first flexible layer away from the glass carrier, and forming a second flexible layer after curing; coating a third flexible material film on a surface of the second flexible layer away from the glass carrier, and forming a third flexible layer after curing, forming a flexible substrate on the glass carrier, the substrate including a first flexible layer, a second flexible layer, and a third flexible layer stacked. In an exemplary embodiment, the first flexible layer, the second flexible layer, and the third flexible layer may be made of the same material, or may be made of different materials. In some possible implementations, the materials of the first flexible layer, the second flexible layer, and the third flexible layer may include polyimide (PI).
[0095] In another exemplary embodiment, forming a substrate on a glass carrier 1 may include: first coating a first flexible material film on the glass carrier, and forming a first flexible layer after curing; then depositing a first inorganic material film on the first flexible layer to form a first inorganic layer covering the first flexible layer; then coating a second flexible material film on the first inorganic layer, and forming a second flexible layer after curing; then depositing a second inorganic material film on the second flexible layer to form a second inorganic layer covering the second flexible layer, and forming a flexible substrate on the glass carrier, the substrate including a first flexible layer, a first inorganic layer, a second flexible layer, and a second inorganic layer stacked. In an exemplary embodiment, the materials of the first flexible material film and the second flexible material film may be polyimide (PI), polyethylene terephthalate (PET), pressure sensitive adhesive (PSA), or a surface-treated polymer soft film, and the materials of the first and second inorganic material films may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the first inorganic layer and the second inorganic layer may be referred to as a first barrier layer and a second barrier layer.
[0096] In another exemplary embodiment, forming a substrate on a glass carrier 1 may include: first coating a first flexible material film on the glass carrier, and curing the film to form a first flexible layer; then depositing a first inorganic material film on the first flexible layer to form a first inorganic layer covering the first flexible layer; then depositing an amorphous silicon film on the first inorganic layer to form an amorphous silicon layer covering the first inorganic layer; then coating a second flexible material film on the amorphous silicon layer, and curing the film to form a second flexible layer; then depositing a second inorganic material film on the second flexible layer to form a second inorganic layer covering the second flexible layer, and forming a flexible substrate on the glass carrier, the substrate including the stacked first flexible layer, the first inorganic layer, the semiconductor layer, the second flexible layer, and the second inorganic layer. In an exemplary embodiment, the material of the semiconductor layer may be amorphous silicon (a-si).
[0097] In an exemplary embodiment, the substrate may be a rigid substrate.
[0098] (2) forming a driving structure layer pattern on the substrate, such as Figure 6 In an exemplary embodiment, the driving structure layer may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 6 , three sub-pixels are illustrated, and the driving structure layer of each sub-pixel is illustrated by taking a transistor 101 and a storage capacitor 102 as an example. In an exemplary embodiment, the preparation process of the driving structure layer may include:
[0099] A first insulating film and a semiconductor layer film are sequentially deposited on a substrate 10, and the semiconductor layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10, and a semiconductor layer pattern arranged on the first insulating layer 11, wherein the semiconductor layer pattern includes at least an active layer arranged in each sub-pixel.
[0100] Subsequently, a second insulating film and a first metal film are deposited in sequence, and the first metal film is patterned through a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a first metal layer pattern arranged on the second insulating layer 12, wherein the first metal layer pattern includes at least a gate electrode and a first capacitor electrode arranged in each sub-pixel.
[0101] Subsequently, a third insulating film and a second metal film are deposited in sequence, and the second metal film is patterned through a patterning process to form a third insulating layer 13 covering the first metal layer, and a second metal layer pattern arranged on the third insulating layer 13, wherein the second metal layer pattern includes at least a second capacitor electrode arranged in each sub-pixel, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.
[0102] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer 14 pattern covering the second metal layer. A plurality of via patterns are provided on the fourth insulating layer 14. The plurality of via patterns include at least two first vias provided in each sub-pixel. The positions of the two first vias correspond to the two ends of the active layer respectively. The fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the two first vias are etched away to expose the surface of the active layer.
[0103] Subsequently, a third metal film is deposited and patterned by a patterning process to form a third metal layer pattern on the fourth insulating layer 14. The third metal layer pattern includes at least a source electrode and a drain electrode arranged in each sub-pixel. The source electrode and the drain electrode are respectively connected to the active layer of the sub-pixel through a first via hole to form a conductive channel between the source electrode and the drain electrode.
[0104] Subsequently, a flat film is coated to form a flat (PLN) layer 15 covering the entire substrate 10, and a via pattern is formed on the flat layer 15 through a patterning process, the via pattern at least including a second via hole set in each sub-pixel, and the flat layer 15 in the second via hole is removed to expose the surface of the drain electrode. In an exemplary embodiment, the surface of the flat layer 15 away from the substrate 10 is a flat surface, and the flattening layer can be made of a material such as resin.
[0105] At this point, the structure formed includes: a substrate 10 disposed on the glass carrier 1, and a driving structure layer 103 disposed on the substrate 10, such as Figure 6 As shown. The active layer, gate electrode, source electrode and drain electrode in each sub-pixel constitute a transistor 101, and the first capacitor electrode and the second capacitor electrode constitute a storage capacitor 102. In an exemplary embodiment, the transistor may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor.
[0106] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer and the third insulating layer are called gate insulation (GI) layers, and the fourth insulating layer is called an interlayer insulation (ILD) layer. The flat layer class uses organic materials such as resins. The first metal film, the second metal film and the third metal film may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The active layer film can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
[0107] (3) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a conductive film on the substrate formed with the aforementioned pattern, patterning the conductive film through a patterning process to form a conductive layer pattern, wherein the conductive layer pattern includes at least an anode 21 disposed in each sub-pixel, and the anode 21 is connected to the drain electrode of the first transistor 101 through a second via hole, such as Figure 7 shown.
[0108] In an exemplary embodiment, the conductive film may be a single layer of transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or the conductive film may be a composite layer of metal material and transparent conductive material, such as Ag / ITO, Ag / IZO or ITO / Ag / ITO, etc. The thickness of the metal material in the composite layer may be about 80nm to 100nm, and the thickness of the transparent conductive material in the composite layer may be about 5nm to 20nm, so that the average reflectivity of the anode in the visible light region is about 85% to 95%.
[0109] (4) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate formed with the aforementioned pattern, performing mask exposure and development on the pixel definition film through a patterning process to form a pixel definition (PDL) layer 22, and in each sub-pixel, a pixel opening is opened on the pixel definition layer 22, and the pixel definition film in the pixel opening is developed away to expose the surface of the anode 21, such as Figure 8 shown.
[0110] In an exemplary embodiment, the thickness of the pixel definition layer may be about 1 μm to 1.5 μm.
[0111] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the pixel opening can be square, rectangular, circular, elliptical or hexagonal, etc., and can be set according to actual needs, and the present disclosure is not limited here. In an exemplary embodiment, the pixel definition film can be made of materials such as polyimide, acrylic or polyethylene terephthalate.
[0112] (6) Forming a spacer column pattern. In an exemplary embodiment, forming the spacer column pattern may include: coating a spacer film on the substrate formed with the aforementioned pattern, patterning the spacer film through a patterning process to form a spacer column 25 pattern, wherein the spacer column 25 is disposed on the surface of the pixel definition layer 22 away from the substrate, and the orthographic projection of the spacer column 25 on the substrate is within the range of the orthographic projection of the pixel definition layer 22 on the substrate, such as Fig. 9 shown.
[0113] In an exemplary embodiment, for a plurality of pixel units on a display substrate, at least one spacer column may be disposed in at least one pixel unit including an R sub-pixel, a G sub-pixel, and a B sub-pixel. In the display area, the plurality of spacer columns may be evenly distributed, and in the frame area, the plurality of spacer columns may be disposed in an area within the boundary of the encapsulation layer, and no spacer column is disposed in an area outside the boundary of the encapsulation layer.
[0114] In an exemplary embodiment, the material of the spacer column may include a polymer elastomer and inorganic nanoparticles. The material of the polymer elastomer may include polyurethane, polysiloxane or liquid crystal block polymer, etc., and the inorganic nanoparticles may be methyl-modified inorganic nanoparticles, and the methyl-modified inorganic nanoparticles may include methyl-modified inorganic silicon oxide nanoparticles, methyl-modified inorganic zinc oxide nanoparticles or methyl-modified inorganic zirconium oxide nanoparticles, etc. The morphology of the polymer elastomer is a cross-linked network formed by chemical connection, and the inorganic nanoparticles are dispersed in the mesh of the cross-linked network composed of the polymer elastomer to support the cross-linked network.
[0115] In an exemplary embodiment, the molecular weight of the polymer elastomer may be about one million to ten million, the refractive index of the polymer elastomer may be about 1.5 to 1.7, and the mesh diameter of the cross-linked network may be about 0.5 μm to 2.0 μm.
[0116] In an exemplary embodiment, the methyl-modified inorganic nanoparticles may be prepared by introducing methyl groups onto the surface of the inorganic nanoparticles through treatment with a surfactant.
[0117] In exemplary embodiments, the inorganic nanoparticles may have a diameter of about 20 nm to about 100 nm.
[0118] In an exemplary embodiment, the inorganic nanoparticles may account for about 0.5 wt % to 5 wt % of the spacer column, and the inorganic nanoparticles may be uniformly distributed in the polymer elastomer.
[0119] In a plane parallel to the substrate, the spacer column may be in a square, rectangular, circular, elliptical or hexagonal shape, etc. For a rectangular spacer column, the width of the spacer column may be about 5 μm to 10 μm.
[0120] In an exemplary embodiment, the height of the spacer pillar may be about 1 μm to 1.5 μm.
[0121] In a plane perpendicular to the substrate, the cross-sectional shape of the spacer column may be a trapezoid, and a base angle of the trapezoid may be approximately 40° to 60°.
[0122] In an exemplary embodiment, the spacer film coating and patterning process may be performed in the following manner: first, a polymer elastomer, inorganic nanoparticles and a photosensitive agent are mixed to form a sol, and then the sol is uniformly coated on the substrate formed with the aforementioned pattern to form a spacer film, and then the spacer film is exposed and developed using a spacer column mask, and then a spacer column pattern is formed through a local ultraviolet curing process.
[0123] In an exemplary embodiment, the spacer column mask includes a light-transmitting area and a light-opaque area, and the photosensitive agent is a negative photosensitive agent. After the spacer film is exposed, the spacer film corresponding to the light-transmitting area position of the spacer column mask forms a fully exposed area, and the spacer film corresponding to the light-opaque area position of the spacer column mask forms an unexposed area. After development, the spacer film in the fully exposed area is retained to form a spacer column pattern, and the spacer film in the unexposed area is completely removed.
[0124] (7) Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming an organic light-emitting layer pattern may include: arranging an evaporation mask on the substrate on which the aforementioned pattern is formed, forming an organic light-emitting layer 13 pattern by an evaporation process, and the organic light-emitting layer 23 is connected to the anode 21 in the pixel opening, such as Fig.10 shown.
[0125] In an exemplary embodiment, the organic light-emitting layer may include an emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the light-emitting layers of different sub-pixels are different. For example, a red sub-pixel includes a red light-emitting layer, a green sub-pixel includes a green light-emitting layer, and a blue sub-pixel includes a blue light-emitting layer.
[0126] In an exemplary embodiment, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, Fine Metal Mask) and an open mask (Open Mask), or by inkjet printing. Although the organic light-emitting layers of the multiple sub-pixels illustrated in the accompanying drawings are isolated structures, in an exemplary embodiment, in order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer can use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer can use a common layer. In an exemplary embodiment, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), but isolation is achieved by means of a surface step difference of the film layer formed or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
[0127] In an exemplary embodiment, the organic light-emitting layer may be prepared by the following preparation method. After the isolation column is prepared, an open mask is first used to sequentially evaporate the hole injection layer and the hole transport layer to form a common layer of the hole injection layer and the hole transport layer on the display substrate, that is, the hole injection layers of all sub-pixels are connected, and the hole transport layers of all sub-pixels are connected. The areas of the hole injection layer and the hole transport layer are roughly the same, but the thicknesses are different. Subsequently, a fine metal mask is used to evaporate the electron blocking layer and the red light-emitting layer, the electron blocking layer and the green light-emitting layer, and the electron blocking layer and the blue light-emitting layer in different sub-pixels. The electron blocking layer and the light-emitting layer of adjacent sub-pixels may have a small amount of overlap (for example, the overlapping portion occupies less than 10% of the area of the respective light-emitting layer patterns), or may be isolated. Subsequently, an open mask is used to sequentially evaporate a hole blocking layer, an electron transport layer and an electron injection layer to form a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate, that is, the hole blocking layers of all sub-pixels are connected, the electron transport layers of all sub-pixels are connected, and the electron injection layers of all sub-pixels are connected.
[0128] In an exemplary embodiment, the positive projection of one or more layers of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the cathode on the substrate is continuous. In some examples, at least one layer of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the cathode of at least one row or column of sub-pixels is connected. In some examples, at least one layer of the hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, the electron injection layer, and the cathode of multiple sub-pixels is connected.
[0129] In an exemplary embodiment, since the hole blocking layer is a common layer and the light-emitting layers of different sub-pixels are isolated, the orthographic projection of the light-emitting layer on the substrate is within the range of the orthographic projection of the hole blocking layer on the substrate, and the area of the hole blocking layer is larger than the area of the light-emitting layer. Since the hole blocking layer is a common layer, the orthographic projection of the hole blocking layer on the substrate at least includes the orthographic projections of the light-emitting regions of two sub-pixels on the substrate. In an exemplary embodiment, the orthographic projections of the light-emitting layers of at least some sub-pixels on the substrate overlap with the orthographic projections driven by the pixel driving circuit on the substrate.
[0130] In an exemplary embodiment, the electron blocking layer can serve as a microcavity adjustment layer between the hole transport layer and the light-emitting layer, so that the thickness of the organic light-emitting layer between the cathode and the anode can be designed to meet the optical path requirements of the optical microresonant cavity to obtain the optimal light output intensity and color.
[0131] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, and the doping ratio of the guest material in the light-emitting layer is 1% to 20%. Within the doping ratio range, on the one hand, the host material of the light-emitting layer can effectively transfer the exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer "dilutes" the guest material of the light-emitting layer, effectively improving the mutual collision between the molecules of the guest material of the light-emitting layer, and the fluorescence quenching caused by the mutual collision between the energy, thereby improving the luminous efficiency and the life of the device. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage. In an exemplary embodiment, the host material and the guest material can be co-evaporated by a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the doping ratio can be regulated by controlling the evaporation rate of the guest material during the evaporation process, or by controlling the evaporation rate ratio of the host material and the guest material.
[0132] In an exemplary embodiment, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or may be made of a p-type dopant of a strong electron-withdrawing system and a dopant of a hole transport material. In an exemplary embodiment, the hole injection layer may have a thickness of about 5 nm to 20 nm.
[0133] In an exemplary embodiment, the hole transport layer may be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan, etc. In an exemplary embodiment, the hole transport layer may have a thickness of about 60 nm to 150 nm.
[0134] In an exemplary embodiment, the electron blocking layer may be an aromatic amine compound having hole transport properties, and its substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan, etc. In an exemplary embodiment, the thickness of the electron blocking layer may be about 5 nm to 20 nm.
[0135] In an exemplary embodiment, the light-emitting layer may include a light-emitting host material and a light-emitting guest material. The light-emitting host material may be a bipolar single host, or may be a double host formed by blending a hole-type host and an electron-type host. The light-emitting guest material may be a phosphorescent material, a fluorescent material, a delayed fluorescent material, etc. In an exemplary embodiment, the thickness of the light-emitting layer may be about 10 nm to 25 nm.
[0136] In an exemplary embodiment, the hole blocking layer and the electron transport layer may be made of aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolephenanthridine derivatives; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; compounds containing nitrogen-containing six-membered ring structures such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives (including compounds having phosphine oxide-based substituents on heterocyclic rings), etc. In an exemplary embodiment, the thickness of the hole blocking layer may be about 5nm to 15nm, and the thickness of the electron transport layer may be about 20nm to 50nm.
[0137] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg) or calcium (Ca), or a compound of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5 nm to 2 nm.
[0138] (8) Repairing the damage on the surface of the spacer column. In an exemplary embodiment, repairing the damage on the surface of the spacer column may include: irradiating the spacer column with ultraviolet light on the substrate on which the aforementioned pattern is formed to eliminate the surface damage of the spacer column.
[0139] Since organic materials are easy to react with water and oxygen, OLED display devices have very high requirements for packaging. After years of development, the existing thin film packaging method can basically meet the requirements of flexible OLED for water vapor and oxygen permeability, and has the characteristics of lightness, thinness, and easy bending. However, in actual production, there is still the problem of sub-pixel packaging failure, which reduces the yield rate. Studies have found that the sub-pixel packaging failure in actual production is caused by surface damage to the spacer column. Since the organic light-emitting layer needs to be evaporated onto the display substrate through a fine metal mask, a spacer column is made on the display substrate to support the fine metal mask. Generally, the process of evaporating the organic light-emitting layer using a fine metal mask includes: first aligning the fine metal mask with the first sub-pixel and leaning against the surface of the spacer column, evaporating the first color light-emitting layer in the first sub-pixel, and leaving the fine metal mask after the evaporation is completed. Then aligning the fine metal mask with the second sub-pixel and leaning against the surface of the spacer column, evaporating the second color light-emitting layer in the second sub-pixel, and leaving the fine metal mask after the evaporation is completed.
[0140] Then the fine metal mask is aligned with the third sub-pixel and placed against the surface of the spacer column, and the third color luminous layer is evaporated in the third sub-pixel. After the evaporation is completed, the fine metal mask is separated from the spacer column.
[0141] Fig.11 The figure shows the sharp protrusions on the surface of the septum column. Fig.11As shown, due to multiple frictions between the fine metal mask and the spacer column during the alignment process before evaporation and the separation process after evaporation, the surface of the spacer column is damaged, so that some sharp protrusions 26 are generated on the surface of the spacer column 25. Actual measurements show that the height of the sharp protrusions can reach 0.5μm to 1μm. Since these sharp protrusions are located at the top of the spacer column, that is, on the side of the spacer column facing the encapsulation layer to be formed subsequently, these sharp protrusions can easily pierce the encapsulation layer, allowing water and oxygen to penetrate into the organic light-emitting layer through the rupture, resulting in encapsulation failure.
[0142] Fig.12 It is a schematic diagram of the spacer column after the surface damage is repaired in the exemplary embodiment of the present disclosure. In the exemplary embodiment, the damage repair process for the surface of the spacer column can be carried out in the following manner. First, the spacer column mask of the previously patterned spacer column is set on the display substrate, and the alignment method of the spacer column mask is the same as the alignment method of the patterned spacer column, that is, the position of the light-transmitting area in the spacer column mask corresponds to the position of the spacer column in the display substrate. Subsequently, ultraviolet light equipment is used for irradiation, and the ultraviolet light is irradiated to the spacer column through the light-transmitting area of the spacer column mask. Since the polymer elastomer will undergo expansion and contraction of the cross-linked network under ultraviolet light irradiation, the raised portion is in an expanded state and the flat portion is in a contracted state, so that the protrusions on the surface of the spacer column change from sharp to gentle, and the height is reduced. The height h of the gentle protrusion can be reduced to less than 0.2μm, thereby realizing the surface damage repair of the spacer column. Fig.12 shown.
[0143] In an exemplary embodiment, the irradiation intensity of the ultraviolet light may be about 5 mW / cm 2 Up to 20mW / cm 2 The irradiation time of ultraviolet light can be about 100 seconds to 300 seconds.
[0144] (9) Forming a cathode pattern. In an exemplary embodiment, forming a cathode pattern may include: forming a cathode 24 pattern on a substrate having the aforementioned pattern formed thereon by an evaporation process, wherein the cathode 24 is connected to the organic light emitting layer 23, such as Fig.13 shown.
[0145] In an exemplary embodiment, the cathodes 24 of the plurality of sub-pixels are a planar integrated structure, and the cathodes 24 wrap around the surfaces of the spacer pillars 25 .
[0146] In an exemplary embodiment, the cathode can be made of a metal material, which can be magnesium (Mg), silver (Ag) or aluminum (Al), or an alloy material, such as an alloy of Mg:Ag, with a Mg:Ag ratio of approximately 9:1 to 1:9, and the thickness of the cathode can be approximately 10nm to 20nm.
[0147] At this point, the pattern of the light emitting structure layer 104 is completed on the driving structure layer 103, such as Fig.13 As shown. In an exemplary embodiment, the anode 21, the organic light-emitting layer 23 and the cathode 24 in the light-emitting structure layer 104 constitute an OLED light-emitting element, the organic light-emitting layer 23 is arranged between the anode 21 and the cathode 24, holes and electrons are respectively injected into the organic light-emitting layer 23 by the anode 21 and the cathode 24, when the electrons and holes meet in the organic light-emitting layer 23, the electrons and holes recombine to generate excitons, and these excitons emit light while changing from an excited state to a ground state, and the organic light-emitting layer 23 emits light of a corresponding grayscale.
[0148] (9) Forming a packaging structure layer. In an exemplary embodiment, forming a packaging structure layer may include: depositing a first inorganic thin film using an open mask to form a first packaging layer 31. Subsequently, inkjet printing an organic material on the first packaging layer using an inkjet printing process, and forming a second packaging layer 32 after curing. Subsequently, depositing a second inorganic thin film using an open mask to form a third packaging layer 33, such as Fig.14 In an exemplary embodiment, the first encapsulation layer and the third encapsulation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer, and the second encapsulation layer may be made of a resin material.
[0149] At this point, the pattern of the encapsulation structure layer 105 is completed on the light emitting structure layer 104, such as Fig.14 As shown. The encapsulation structure layer 105 may include a first encapsulation layer 31, a second encapsulation layer 32, and a third encapsulation layer 33 stacked to form an inorganic material / organic material / inorganic material stacked structure, and the organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer. In an exemplary embodiment, the thickness of the first encapsulation layer may be approximately 800nm to 1200nm, the thickness of the second encapsulation layer may be approximately 6000nm to 10000nm, and the thickness of the third encapsulation layer may be approximately 600nm to 800nm.
[0150] In an exemplary embodiment, after the encapsulation structure layer is prepared, a touch structure layer (TSP) may be formed on the encapsulation structure layer, and the touch structure layer may include a touch electrode layer, or a touch electrode layer and a touch insulating layer. In an exemplary embodiment, when preparing a flexible display substrate, the preparation process of the display substrate may also include processes such as peeling off the glass carrier 1, attaching a back film, and cutting, which are not limited in this disclosure.
[0151] It can be seen from the structure shown in the exemplary embodiment of the present invention and its preparation process that the present invention adopts a spacer column including a polymer elastomer and inorganic nanoparticles, and repairs the spacer column after evaporating the light-emitting layer, thereby effectively repairing the surface damage of the spacer column caused by the fine metal mask, so that the protrusions on the surface of the spacer column change from sharp to flat, and the height of the protrusions is greatly reduced, thereby avoiding the protrusions piercing the packaging layer, thereby avoiding packaging failure, effectively ensuring the packaging effect, eliminating the problem of sub-pixel packaging failure, and improving the yield rate.
[0152] In an exemplary embodiment, part of the light emitted by the organic light-emitting layer will pass through the spacer column and be incident on the encapsulation layer before being emitted. In a display substrate, the spacer column is usually made of an organic material with a relatively high refractive index. According to optical principles, when light is incident from a light-dense medium with a relatively large refractive index to a light-sparse medium with a relatively small refractive index, if the incident angle is greater than the total reflection angle of the interface between the light-dense medium and the light-sparse medium, total emission will occur. In this way, part of the light inside the spacer column will be totally reflected at the interface of the spacer column, so that the light is confined within the spacer column, causing light loss, and reducing the light output efficiency and luminous brightness. The present disclosure adopts a spacer column including inorganic nanoparticles. Through the refraction and / or reflection of the light by the inorganic nanoparticles, the transmission direction of the light in the spacer column can be changed, and the total reflection of the light at the interface of the spacer column is eliminated, thereby effectively improving the light output efficiency and effectively increasing the luminous brightness.
[0153] In an exemplary embodiment, external water and oxygen may penetrate into the organic light-emitting layer through the spacer column. In a display substrate, the spacer column is usually made of organic material, which has a high water and oxygen permeability and thus has a weak ability to block water and oxygen. The present disclosure uses a spacer column including inorganic nanoparticles. Since the inorganic nanoparticles have a strong ability to block water and oxygen, the ability of the spacer column to block water and oxygen is effectively improved, and the probability of external water and oxygen penetrating into the organic light-emitting layer through the spacer column is reduced, thereby effectively increasing the service life of the display substrate.
[0154] The structure and preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the transistor in the driving structure layer can be a top gate structure, or a bottom gate structure, a single gate structure, or a double gate structure. For another example, other film layer structures, electrode structures, or lead structures can also be provided in the driving structure layer and the light-emitting structure layer. For another example, the substrate can be a glass substrate, which is not limited in the present disclosure.
[0155] Fig.15This is a schematic diagram of the cross-sectional structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the structure of a sub-pixel in an OLED display substrate. On a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 103 disposed on a substrate 10, a light-emitting structure layer 104 disposed on a side of the driving circuit layer 103 away from the substrate 10, and a packaging structure layer 105 disposed on a side of the light-emitting structure layer 104 away from the substrate 10. In an exemplary embodiment, the structures of the driving circuit layer 103 and the packaging structure layer 105 in the display substrate of this exemplary embodiment are the same as those of the aforementioned embodiment, except that the pixel definition layer 22 and the spacer column 25 in the light-emitting structure layer 104 of this exemplary embodiment are made of the same material and can be formed simultaneously through the same patterning process. Fig.15 As shown, the light-emitting structure layer 104 may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, a cathode 24 and a spacer column 25. The pixel definition layer 22 is provided with a pixel opening exposing the anode 21. The organic light-emitting layer 23 is arranged between the anode 21 and the cathode 24. The spacer column 25 is arranged on the pixel definition layer 22. The materials of the pixel definition layer 22 and the spacer column 25 may include polymer elastomers and inorganic nanoparticles, that is, the materials of the pixel definition layer 22 and the spacer column 25 are the same.
[0156] In an exemplary embodiment, the materials and parameters of the polymer elastomer and the inorganic nanoparticles may be the same as those in the aforementioned embodiment, and will not be described in detail herein.
[0157] In the preparation process of the display substrate of this exemplary embodiment, the processes of forming a base, forming a driving structure layer, forming an anode, forming an organic light-emitting layer, repairing damage to the spacer column, forming a cathode and forming a packaging structure layer can be the same as those of the aforementioned embodiments, with the difference that the pixel definition layer and the spacer column can be formed simultaneously by a single patterning process in this exemplary embodiment.
[0158] In an exemplary embodiment, the following process can be used to simultaneously form a pixel definition layer and a spacer column using a single patterning process. First, a polymer elastomer, inorganic nanoparticles and a photosensitive agent are mixed to form a sol, and then the sol is evenly coated on the substrate forming the aforementioned pattern to form a pixel definition film. Subsequently, the pixel definition film is exposed using a gray tone mask, and after development, a fully exposed area, a partially exposed area and an unexposed area are formed, the pixel definition film in the fully exposed area is retained to form a spacer column pattern, the pixel definition film in the partially exposed area is partially removed to form a pixel definition layer pattern, and the pixel definition film in the unexposed area is completely removed to form a pixel opening pattern.
[0159] In an exemplary embodiment, when repairing damage to the spacer column, the gray tone mask is first set on the display substrate, the position of the light-transmitting area (fully exposed area) of the gray tone mask corresponds to the position of the spacer column, and then ultraviolet light equipment is used for irradiation. The ultraviolet light passes through the light-transmitting area of the gray tone mask and irradiates the spacer column, thereby repairing the surface damage of the spacer column.
[0160] The exemplary embodiment of the present disclosure adopts a spacer column including a polymer elastomer and inorganic nanoparticles, and repairs the spacer column after evaporating the light-emitting layer, thereby effectively repairing the surface damage of the spacer column caused by the fine metal mask, so that the protrusions on the surface of the spacer column change from sharp to gentle, and the height of the protrusions is greatly reduced, thereby avoiding the protrusions from piercing the packaging layer, thereby avoiding packaging failure, effectively ensuring the packaging effect, eliminating the problem of sub-pixel packaging failure, and improving the yield rate.
[0161] In an exemplary embodiment, part of the light emitted by the organic light-emitting layer will pass through the pixel definition layer and be incident on the encapsulation layer before being emitted. In a display substrate, the pixel definition layer is usually made of an organic material with a relatively high refractive index. According to optical principles, when light is incident from a light-dense medium with a relatively large refractive index to a light-sparse medium with a relatively small refractive index, if the incident angle is greater than the total reflection angle of the interface between the light-dense medium and the light-sparse medium, total emission will occur. In this way, part of the light inside the pixel definition layer will be totally reflected at the interface of the pixel definition layer, so that the light is confined within the pixel definition layer, causing light loss, and reducing light output efficiency and luminous brightness. The present disclosure adopts a pixel definition layer and spacer columns including inorganic nanoparticles. Through the refraction and / or reflection of light by inorganic nanoparticles, the transmission direction of light in the pixel definition layer can be changed, and the total reflection of light at the interface of the pixel definition layer is eliminated, thereby effectively improving the light output efficiency and effectively increasing the luminous brightness.
[0162] In an exemplary embodiment, external water and oxygen may penetrate into the organic light-emitting layer through the pixel definition layer. In a display substrate, the pixel definition layer is usually made of organic materials, which have a high water and oxygen permeability and thus have a weak ability to block water and oxygen. The present disclosure uses a pixel definition layer and a spacer column including inorganic nanoparticles. Since the inorganic nanoparticles have a strong ability to block water and oxygen, the ability of the pixel definition layer and the spacer column to block water and oxygen is effectively improved, and the probability of external water and oxygen penetrating into the organic light-emitting layer through the pixel definition layer and the spacer column is reduced, thereby effectively increasing the service life of the display substrate.
[0163] The present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the method for preparing a display substrate may include:
[0164] S1. forming a pixel definition layer and a spacer column on the driving structure layer, wherein the spacer column is arranged on a surface of the pixel definition layer away from the driving structure layer, and an orthographic projection of the spacer column on the substrate is within a range of an orthographic projection of the pixel definition layer on the substrate;
[0165] S2, using a fine metal mask to evaporate the organic light-emitting layer;
[0166] S3. Repairing the spacer column, wherein the surface of the spacer column away from the driving structure layer has a protrusion, and the height of the protrusion is less than 0.2 μm.
[0167] In an exemplary embodiment, the material of the spacer column includes a polymer elastomer and nanoparticles, the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology is a cross-linked network formed by chemical connection, and the mesh diameter of the cross-linked network is 0.5 μm to 2.0 μm; repairing the spacer column may include:
[0168] The spacer column is irradiated with ultraviolet light, and the cross-linked network of the polymer elastomer expands and contracts under the ultraviolet light, so that the protrusions on the surface of the spacer column change from sharp to gentle, and the height of the protrusions is less than 0.2 μm.
[0169] In an exemplary embodiment, the irradiation intensity of the ultraviolet light may be about 5 mW / cm 2 Up to 20mW / cm 2 The irradiation time of the ultraviolet light can be about 100 seconds to 300 seconds.
[0170] In an exemplary embodiment, forming a pixel definition layer and a spacer column on the driving structure layer may include: forming a pixel definition layer on the driving structure layer; forming a spacer column on the pixel definition layer using a spacer column mask;
[0171] The step of irradiating the spacer column with ultraviolet light may include: placing the spacer column mask on the display substrate and irradiating the spacer column with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the spacer column mask and irradiates the spacer column.
[0172] In an exemplary embodiment, forming a pixel definition layer and a spacer column on the driving structure layer may include: using a gray tone mask to form the pixel definition layer and the spacer column on the driving structure layer through a same patterning process;
[0173] The spacer column is irradiated with ultraviolet light, comprising: placing the gray tone mask on the display substrate, and irradiating with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the gray tone mask and irradiates the spacer column.
[0174] The preparation method of the display substrate disclosed herein adopts a spacer column including a polymer elastomer and inorganic nanoparticles, and repairs the spacer column after evaporating the light-emitting layer, thereby effectively ensuring the packaging effect, effectively improving the light output efficiency, and effectively increasing the service life of the display substrate. The preparation method disclosed herein has a small process improvement, high compatibility, simple process realization, easy implementation, high production efficiency, low production cost, and high yield rate.
[0175] The present disclosure also provides a display device, including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a car display, a smart watch, a smart bracelet, etc.
[0176] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the relevant field can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be based on the scope defined by the attached claims.
Claims
1. A display substrate, comprising a pixel definition layer and a spacer column arranged on a driving structure layer, wherein the spacer column is arranged on a surface of the pixel definition layer away from the driving structure layer, and the orthographic projection of the spacer column on the substrate is located within the range of the orthographic projection of the pixel definition layer on the substrate; the surface of the spacer column away from the driving structure layer has a protrusion obtained by ultraviolet light irradiation, and the height of the protrusion is less than 0.2μm.
2. The display substrate according to claim 1, wherein: The material of the spacer column includes a polymer elastomer and nanoparticles, and the nanoparticles account for 0.5wt% to 5wt% in the spacer column.
3. The display substrate according to claim 2, wherein: The diameter of the nanoparticles is 20 nm to 100 nm.
4. The display substrate according to claim 2, wherein: The nanoparticles include methyl-modified inorganic nanoparticles.
5. The display substrate according to claim 4, wherein: The methyl-modified inorganic nanoparticles include at least one of methyl-modified inorganic silicon oxide nanoparticles, methyl-modified inorganic zinc oxide nanoparticles and methyl-modified inorganic zirconium oxide nanoparticles.
6. The display substrate according to any one of claims 2 to 5, wherein: The polymer elastomer comprises at least one of polyurethane, polysiloxane and liquid crystal block polymer. The morphology of the polymer elastomer is a cross-linked network formed by chemical connection. The mesh diameter of the cross-linked network is 0.5 μm to 2.0 μm.
7. The display substrate according to any one of claims 1 to 5, wherein: The spacer column has a height of 1 μm to 1.5 μm.
8. The display substrate according to any one of claims 1 to 5, wherein: The pixel definition layer and the spacer pillars are made of the same material.
9. The display substrate according to any one of claims 1 to 5, wherein: The spacer column and the pixel definition layer are an integrated structure.
10. A display device comprising the display substrate according to any one of claims 1 to 9.
11. A method for preparing a display substrate, comprising: A pixel definition layer and a spacer column are formed on the driving structure layer, wherein the spacer column is arranged on a surface of the pixel definition layer away from the driving structure layer, and an orthographic projection of the spacer column on the substrate is within a range of an orthographic projection of the pixel definition layer on the substrate; Use fine metal mask to evaporate the organic light-emitting layer; The spacer column is repaired, and the surface of the spacer column on the side away from the driving structure layer has a protrusion obtained by ultraviolet light irradiation, and the height of the protrusion is less than 0.2 μm.
12. The preparation method according to claim 11, wherein The material of the spacer column includes a polymer elastomer and nanoparticles, the polymer elastomer includes at least one of polyurethane, polysiloxane and liquid crystal block polymer, and the morphology is a cross-linked network formed by chemical connection, and the mesh diameter of the cross-linked network is 0.5 μm to 2.0 μm; The septum column is repaired, comprising: The spacer column is irradiated with ultraviolet light, and the cross-linked network of the polymer elastomer expands and contracts under the ultraviolet light, so that the protrusions on the surface of the spacer column change from sharp to gentle, and the height of the protrusions is less than 0.2 μm.
13. The preparation method according to claim 12, wherein: The irradiation intensity of the ultraviolet light is 5mW / cm 2 Up to 20mW / cm 2 The irradiation time of the ultraviolet light is 100 seconds to 300 seconds.
14. The preparation method according to claim 12, wherein: Forming a pixel definition layer and a spacer column on the driving structure layer, comprising: forming a pixel definition layer on the driving structure layer; using a spacer column mask to form a spacer column on the pixel definition layer; The spacer column is irradiated with ultraviolet light, comprising: placing the spacer column mask on the display substrate, and irradiating with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the spacer column mask and irradiates the spacer column.
15. The preparation method according to claim 12, wherein: Forming a pixel definition layer and a spacer column on the driving structure layer, comprising: using a gray tone mask to form the pixel definition layer and the spacer column on the driving structure layer through a same patterning process; The spacer column is irradiated with ultraviolet light, comprising: placing the gray tone mask on the display substrate, and irradiating with ultraviolet light equipment, so that the ultraviolet light passes through the light-transmitting area of the gray tone mask and irradiates the spacer column.
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