A negative pressure detection circuit

Abstract

The present invention is a negative pressure detection circuit, which adopts a bandgap reference voltage comparator structure and is applied to a GaN half-bridge drive circuit. In order to solve the influence of negative pressure on the drive circuit, the anti-negative pressure circuit adopts a buck voltage shift circuit to monitor the floating state of the high-side voltage in real time and feedback it to the bootstrap charging circuit, so that the charging time avoids the negative pressure time. The high-side negative pressure detection circuit adopts a bandgap reference comparator, which combines the bandgap reference and the voltage comparator. It is less affected by temperature. Due to the use of current comparison, it has a fast speed and can effectively avoid the influence of the high-side floating power supply rail.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a negative voltage detection circuit. Background Art

[0002] As the third-generation semiconductor device, GaN power devices are gradually replacing silicon devices and are widely used in traditional and new energy fields, greatly improving the power conversion efficiency. The half-bridge drive of GaN power devices is an important part of the current GaN power device application system, and the half-bridge drive level shift circuit is the key research technology of this drive. Designing a high-performance level shift circuit to achieve low-delay transient noise suppression and GaN negative voltage protection to meet the requirements of high reliability and low power consumption design is the research focus. In the GaN half-bridge gate drive circuit, due to the freewheeling effect of the inductive load, continuous charging of the bootstrap capacitor will cause the high-side power supply to enter a negative voltage, resulting in too high a gate-source voltage of the high-side GaN device, thus breaking down the GaN device. In order to ensure that the high-side voltage is clamped under the effective gate voltage of GaN, it is necessary to design a high-side clamping anti-negative voltage circuit to protect the GaN device. A buck level shift circuit is used to monitor the floating state of the high-side voltage in real time and feedback it to the bootstrap charging circuit, so that the charging time avoids the negative voltage time. The conventional design of voltage detection is that the reference voltage and the detection circuit are independent, and then comparison is carried out. Due to the instability of the high-side floating power supply rail and the uncertainty of the reference voltage and the detection comparison circuit, detection errors are caused.

[0003] To solve the above problems, the present invention provides a negative voltage detection circuit. In the high-side negative voltage detection circuit, a bandgap reference comparator is used, which combines the bandgap reference and the voltage comparator, is less affected by temperature, and has a fast speed due to the use of current comparison, and can effectively avoid the influence of the high-side floating power supply rail. Summary of the Invention

[0004] The purpose of the present invention is to overcome the problems existing in the prior art, and provide a negative voltage detection circuit. The bandgap reference voltage comparator structure is adopted and applied to the GaN half-bridge drive circuit. To solve the influence of negative voltage in the drive circuit, the anti-negative voltage circuit uses a buck level shift circuit to monitor the floating state of the high-side voltage in real time and feedback it to the bootstrap charging circuit, so that the charging time avoids the negative voltage time. The high-side negative voltage detection circuit uses a bandgap reference comparator, which combines the bandgap reference and the voltage comparator, is less affected by temperature, and has a fast speed due to the use of current comparison, and can effectively avoid the influence of the high-side floating power supply rail.

[0005] To achieve the above technical objectives and reach the above technical effects, the present invention is realized through the following technical solutions:

[0006] A negative pressure detection circuit, which includes a first BJT transistor Q1, a second BJT transistor Q2, an NMOS transistor M1, an NMOS transistor M2, a resistor R1 and a resistor R2. The emitter of the second BJT transistor Q2 is connected to one end of the resistor R1, and the other end of the resistor R1 is simultaneously connected to the emitter of the first BJT transistor Q1 and one end of the resistor R2. The other end of the resistor R2 is connected to the high-side voltage HB. The collector of the first BJT transistor Q1 is connected to the drain of the NMOS transistor M1. The drain of the NMOS transistor M1 is connected to the gate, forming an active resistor. The source of the NMOS transistor M1 is connected to the high-side voltage HS. The collector of the second BJT transistor Q2 is connected to the drain of the NMOS transistor M2. The drain of the second transistor M2 is connected to the gate, forming an active resistor. The source of the second transistor M2 is connected to the high-side voltage HS. The base of the first BJT transistor Q1 is connected to the base of the second BJT transistor Q2, so that the collector branch currents of the first BJT transistor Q1 and the second BJT transistor Q2 are kept consistent, and this base voltage is the reference voltage V REF ;

[0007] The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M4 is connected to the high-side voltage HS, forming a current mirror circuit. The gate of the NMOS transistor M2 is connected to the gate of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the high-side voltage HS, forming a current mirror circuit;

[0008] The drain of the NMOS transistor M3 is connected to the drain of the PMOS transistor M5. The drain of the PMOS transistor M5 is connected to the gate, forming an active resistor. The source of the PMOS transistor M5 is connected to the high-side voltage HB. The gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M6, and the source of the PMOS transistor M6 is connected to the high-side voltage HB, forming a current mirror circuit. The drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M4, serving as the output terminal V OUT 。

[0009] Further, the output terminal V OUT is connected to the gates of the PMOS transistor M7 and the NMOS transistor M8. The source of the PMOS transistor M7 is connected to the high-side voltage HB, and the source of the NMOS transistor M8 is connected to the high-side voltage HS. The drains of the PMOS transistor M7 and the NMOS transistor M8 are connected, serving as the output terminal V CTL of the inverter, and the drain of the PMOS transistor M7 is connected to the gate of the PMOS transistor M9, with the output terminal V CTLControl the conduction of PMOS transistor M9. The source of PMOS transistor M9 is connected to the high-side voltage HB and one end of resistor R3. The other end of resistor R3 is connected to the drain of PMOS transistor M9 and one end of resistor R4. The other end of resistor R4 is connected to the high-side voltage HS through resistor R5, so that resistors R3, R4, and R5 form a series voltage divider.

[0010] Further, the common end where resistor R4 is connected to resistor R5 serves as the feedback voltage terminal V F Connect the bases of the first BJT transistor Q1 and the second BJT transistor Q2, so that the voltage value of the feedback voltage terminal V F changes to achieve the bandgap reference comparison output.

[0011] Further, the reference voltage V REF employs a temperature-independent bandgap reference, which is formed by superimposing a positive temperature coefficient voltage and a negative temperature coefficient voltage.

[0012] Further, the BE junction voltage of the first BJT transistor Q1 exhibits a negative temperature coefficient voltage, and the difference between the BE junction voltages of the first BJT transistor Q1 and the second BJT transistor Q2 exhibits a positive temperature coefficient voltage.

[0013] The beneficial effects of the present invention are:

[0014] The present invention uses a buck level shift circuit to monitor the floating state of the high-side voltage in real time and feedback it to the bootstrap charging circuit, so that the charging time avoids the negative voltage time. The high-side negative voltage detection circuit uses a bandgap reference comparator, which combines the bandgap reference and the voltage comparator, and is less affected by temperature. Due to the use of current comparison, the speed is fast, and the influence of the high-side floating power supply rail can be effectively avoided. Brief Description of the Drawings

[0015] Figure 1 is a schematic diagram of the circuit structure of the present invention;

[0016] Figure 2 is a timing waveform diagram of the key nodes of the circuit of the present invention;

[0017] Figure 3 is a schematic diagram of the negative voltage detection circuit applied to a GaN half-bridge drive integrated circuit of the present invention. Detailed Embodiments

[0018] Next, the present invention will be described in detail with reference to the drawings and in combination with embodiments.

[0019] As Figure 1As shown in the figure, a negative pressure detection circuit includes a first BJT transistor Q1, a second BJT transistor Q2, an NMOS transistor M1, an NMOS transistor M2, a resistor R1 and a resistor R2. The emitter of the second BJT transistor Q2 is connected to one end of the resistor R1, and the other end of the resistor R1 is simultaneously connected to the emitter of the first BJT transistor Q1 and one end of the resistor R2. The other end of the resistor R2 is connected to the high-side voltage HB. The collector of the first BJT transistor Q1 is connected to the drain of the NMOS transistor M1. The drain of the NMOS transistor M1 is connected to the gate, forming an active resistor. The source of the NMOS transistor M1 is connected to the high-side voltage HS. The collector of the second BJT transistor Q2 is connected to the drain of the NMOS transistor M2. The drain of the second transistor M2 is connected to the gate, forming an active resistor. The source of the second transistor M2 is connected to the high-side voltage HS. The base of the first BJT transistor Q1 is connected to the base of the second BJT transistor Q2, so that the collector branch currents of the first BJT transistor Q1 and the second BJT transistor Q2 are kept consistent, and this base voltage is the reference voltage V REF ;

[0020] The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M4 is connected to the high-side voltage HS, forming a current mirror circuit. The gate of the NMOS transistor M2 is connected to the gate of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the high-side voltage HS, forming a current mirror circuit;

[0021] The drain of the NMOS transistor M3 is connected to the drain of the PMOS transistor M5. The drain of the PMOS transistor M5 is connected to the gate, forming an active resistor. The source of the PMOS transistor M5 is connected to the high-side voltage HB. The gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M6. The source of the PMOS transistor M6 is connected to the high-side voltage HB, forming a current mirror circuit. The drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M4, serving as the output terminal V OUT 。

[0022] The output terminal V OUT is connected to the gates of the PMOS transistor M7 and the NMOS transistor M8. The source of the PMOS transistor M7 is connected to the high-side voltage HB, and the source of the NMOS transistor M8 is connected to the high-side voltage HS. The drains of the PMOS transistor M7 and the NMOS transistor M8 are connected, serving as the output terminal V CTL of the inverter, and the drain of the PMOS transistor M7 is connected to the gate of the PMOS transistor M9. The inverter composed of the PMOS transistor M7 and the NMOS transistor M8 uses the output terminal V CTLTurn on the PMOS transistor M9. The source of the PMOS transistor M9 is connected to the high-side voltage HB and one end of the resistor R3. The other end of the resistor R3 is connected to the drain of the PMOS transistor M9 and one end of the resistor R4. The other end of the resistor R4 is connected to the high-side voltage HS through the resistor R5, so that the resistors R3, R4, and R5 form a series voltage division.

[0023] The common end where the resistor R4 is connected to the resistor R5 serves as the feedback voltage terminal V F Connect the bases of the first BJT transistor Q1 and the second BJT transistor Q2 to the feedback voltage terminal V F to change the voltage value and achieve the bandgap reference comparison output.

[0024] The reference voltage V REF Adopts a temperature-independent bandgap reference, which is formed by superimposing a positive temperature coefficient voltage and a negative temperature coefficient voltage.

[0025] The BE junction voltage of the first BJT transistor Q1 exhibits a negative temperature coefficient voltage, and the difference between the BE junction voltages of the first BJT transistor Q1 and the second BJT transistor Q2 exhibits a positive temperature coefficient voltage.

[0026] The principle and detection process of the present invention

[0027] The negative voltage detection circuit uses a bandgap reference comparator and directly realizes negative voltage detection and voltage comparison with the bandgap reference voltage threshold. The bandgap reference works as follows: Since the NMOS transistors M1 and M2 have the same size and their gates and drains are short-circuited, they are equivalent to active resistors with the same resistance value. Also, the bases of the BJT transistors Q1 and Q2 are connected. Then, the collector currents of the two branches of the BJT transistors Q1 and Q2 are the same. From I EC1 =I EC2 =I R1 , and from I R2 =I R1 +I EC1 , then I R2 =2I R1 , where I R1 =(V EB1 -V EB2 ) / R1, then I R2 =2(V EB1 -V EB2 ) / R1, and the reference voltage V REF =V EB1 +I R2 *R2. Therefore, V REF =V EB1 +2 R2 *(V EB1 -V EB2 ) / R1, where V EB2is inversely proportional to the temperature, V EB1 -V EB2 is proportional to the temperature. Therefore, the bandgap reference voltage V REF is approximately 1.25 V and is independent of temperature.

[0028] As Figure 2 shown, during normal operation, the output terminal V OUT tends to be at a low level. When a negative voltage occurs, the voltage between the high-side power floating rails HB-HS decreases. When the voltage of the feedback voltage terminal V F [(R5) / (R3+R4+R5)]*(HB-HS) is lower than the bandgap reference voltage V REF , the change in the base voltages of the BJT transistors Q1 and Q2 (V REF -V F ) causes the output terminal V OUT to tend to be at a high level. After passing through the inverter composed of the PMOS transistor M7 and the NMOS transistor M8, it becomes a low level. This low level turns on the PMOS transistor M9, and the resistor R3 is short-circuited. At this time, the voltage of the feedback voltage terminal V F is [(R5) / ( R4+R5)]*(HB-HS). When the negative voltage disappears and returns to normal operation, the voltage of the feedback voltage terminal V F increases and tends to the bandgap reference voltage V REF . At this time, the output terminal V OUT tends to be at a low level. This low level causes the PMOS transistor M9, which is used as a switching transistor, to turn off through the inverter, and the voltage returns to normal.

[0029] As Figure 3 shown, it is the circuit block diagram of the GaN power device half-bridge gate driver chip and the application system. The half-bridge drive circuit is divided into two channels: the high side and the low side. The high-side drive circuit uses a bootstrap boost method to achieve signal transmission. The two inputs HI and LI enter the high-side and low-side channels respectively; the high-side negative voltage detection circuit outputs a pulse signal to directly control the buck level shift circuit. After passing through the logic processing protection circuit and then through the buffer, a pulse control signal is generated to directly control the switching transistor. The control signal is at a high level during the negative voltage period, and the switching transistor is not turned on, cutting off the charging circuit of the bootstrap capacitor; when operating normally, the control signal is at a low level, the switching transistor is turned on, and the bootstrap capacitor starts to be charged, achieving the purpose of protecting the high-side GaN device.

[0030] In addition, it should be noted that unless otherwise specified or indicated, the terms "first", "second", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0031] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A negative pressure detection circuit, characterized in that, The circuit includes a first BJT transistor Q1, a second BJT transistor Q2, an NMOS transistor M1, an NMOS transistor M2, a resistor R1 and a resistor R2. The emitter of the second BJT transistor Q2 is connected to one end of the resistor R1, and the other end of the resistor R1 is simultaneously connected to the emitter of the first BJT transistor Q1 and one end of the resistor R2. The other end of the resistor R2 is connected to the high-side voltage HB. The collector of the first BJT transistor Q1 is connected to the drain of the NMOS transistor M1. The drain of the NMOS transistor M1 is connected to the gate, forming an active resistor. The source of the NMOS transistor M1 is connected to the high-side voltage HS. The collector of the second BJT transistor Q2 is connected to the drain of the NMOS transistor M2. The drain of the second transistor M2 is connected to the gate, forming an active resistor. The source of the second transistor M2 is connected to the high-side voltage HS. The base of the first BJT transistor Q1 is connected to the base of the second BJT transistor Q2, so that the collector branch currents of the first BJT transistor Q1 and the second BJT transistor Q2 are kept consistent, and this base voltage is the reference voltage V REF ; The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M4, and the source of the NMOS transistor M4 is connected to the high-side voltage HS, forming a current mirror circuit. The gate of the NMOS transistor M2 is connected to the gate of the NMOS transistor M3, and the source of the NMOS transistor M3 is connected to the high-side voltage HS, forming a current mirror circuit; The drain of the NMOS transistor M3 is connected to the drain of the PMOS transistor M5. The drain of the PMOS transistor M5 is connected to its gate to form an active resistor. The source of the PMOS transistor M5 is connected to the high-side voltage HB. The gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M6. The source of the PMOS transistor M6 is connected to the high-side voltage HB to form a current mirror circuit. The drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M4 to serve as the output terminal V OUT .

2. The negative pressure detection circuit according to claim 1, wherein The output terminal V OUT is connected to the gates of PMOS transistor M7 and NMOS transistor M8. The source of PMOS transistor M7 is connected to the high-side voltage HB, the source of NMOS transistor M8 is connected to the high-side voltage HS, and the drains of PMOS transistor M7 and NMOS transistor M8 are connected together to serve as the output terminal V of the inverter CTL , and the drain of PMOS transistor M7 is connected to the gate of PMOS transistor M9 to control the conduction of PMOS transistor M9 with the output terminal V CTL . The source of PMOS transistor M9 is connected to the high-side voltage HB and one end of resistor R3. The other end of resistor R3 is connected to the drain of PMOS transistor M9 and one end of resistor R4. The other end of resistor R4 is connected to the high-side voltage HS through resistor R5, such that resistors R3, R4, and R5 form a series voltage divider 3. The negative pressure detection circuit according to claim 2, wherein, The common terminal where the resistor R4 is connected to the resistor R5 serves as the feedback voltage terminal V F Connect the bases of the first BJT transistor Q1 and the second BJT transistor Q2 to the feedback voltage terminal V F so that the voltage value changes to achieve the bandgap reference comparison output.

4. The negative pressure detection circuit according to claim 3, wherein, The reference voltage V REF employs a temperature-independent bandgap reference, which is formed by superimposing a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient.

5. The negative pressure detection circuit according to claim 4, wherein The BE junction voltage of the first BJT transistor Q1 exhibits a negative temperature coefficient voltage, and the BE junction voltage difference between the first BJT transistor Q1 and the second BJT transistor Q2 exhibits a positive temperature coefficient voltage.

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