Display panel and display device

Abstract

The present application discloses a display panel and a display device, which relate to the field of display technology. The display panel includes a plurality of pixel electrodes, a common electrode, a common signal line, a detection line and a processor. The plurality of pixel electrodes are coupled with the common electrode to form a capacitor. The common signal line is connected between the output end of the processor and the common electrode. The detection line is connected between the detection end of the processor and the common signal line. The processor is used to output a preset electrical signal through the output end during a first time period, and to detect the voltage of the common signal line through the detection end; the processor is also used to output a compensation electrical signal through the output end according to the voltage of the common signal line during a second time period. In this way, the voltage changes of the common electrodes of the array substrate and the common electrodes of the color film substrate can be detected and compensated, thereby solving the horizontal crosstalk problem of the display panel and improving the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes multiple data lines, multiple pixel electrodes, multiple array substrate common electrodes, and multiple color filter substrate common electrodes. Each pixel electrode is coupled with the color filter substrate common electrode to form a capacitor, and each pixel electrode is also coupled with an array substrate common electrode to form a capacitor. When the display panel is operating, the multiple data lines are used to input voltages to the multiple pixel electrodes. The voltages of the multiple array substrate common electrodes and the color filter substrate common electrodes should remain constant.

[0003] However, in display panels, parasitic capacitance exists between the data lines and the common electrodes on the array substrate, as well as between the data lines and the common electrodes on the color filter substrate. In this case, when the voltage output from the data lines to the pixel electrodes changes, it affects the common electrodes on the array substrate and the color filter substrate through the parasitic capacitance, causing the voltages on these electrodes to also change. Existing technologies are unable to detect and compensate for these voltage changes on the common electrodes on the array substrate and the color filter substrate. Summary of the Invention

[0004] This application provides a display panel and display device that can solve the problem in related technologies of being unable to detect and compensate for voltage changes on common electrodes of array substrates and color filter substrates. The technical solution is as follows:

[0005] In a first aspect, a display panel is provided, comprising: a plurality of pixel electrodes, a common electrode, a common signal line, and a processor;

[0006] The plurality of pixel electrodes are coupled with the common electrode to form a capacitor; the processor has an output terminal, and the common signal line is connected between the output terminal and the common electrode;

[0007] The display panel further includes a detection line, and the processor further includes a detection terminal, wherein a first end of the detection line is connected to the detection terminal, and a second end of the detection line is connected to the common signal line, so that the detection line and the detection terminal form a detection channel for detecting the voltage of the common signal line;

[0008] The processor is used to: output a preset electrical signal through the output end during a first time period, and detect the voltage of the common signal line through the detection end; and output a compensation electrical signal through the output end during a second time period based on the voltage of the common signal line, so that the output end and the common signal line form a compensation channel for compensating for the voltage of the common signal line; wherein, when the voltage of the common signal line is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal, and the second time period is after the first time period.

[0009] In the present application, a display panel includes multiple pixel electrodes, common electrodes (including array substrate common electrodes and color filter substrate common electrodes), common signal lines, detection lines, and a processor. Multiple pixel electrodes are coupled with the common electrodes to form a capacitor. The common signal lines are connected between the output terminal of the processor and the common electrodes. The detection lines are connected between the detection terminal of the processor and the common signal lines. When the display panel is operating, the processor can output a preset electrical signal to the common signal lines during a first period of time, thereby outputting the preset electrical signal to the common electrodes. At the same time, the processor can also detect the voltage of the common signal lines through the detection lines, thereby detecting voltage changes at the common electrodes. The processor can output a compensation electrical signal to the common signal lines during a second period of time, and when the voltage of the common signal lines is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal. In this way, compensation for voltage changes at the common electrodes can be achieved. This display panel can detect and compensate for voltage changes at the array substrate common electrodes and the color filter substrate common electrodes, thereby resolving the horizontal crosstalk problem of the display panel and improving the display quality of the display panel.

[0010] Optionally, the common electrode includes a plurality of first common electrodes and a second common electrode, the common signal line includes a first signal line and a second signal line, and the output end includes a first port and a second port;

[0011] One of the plurality of first common electrodes is coupled with one of the plurality of pixel electrodes to form a capacitor, and the second common electrode is coupled with each of the plurality of pixel electrodes to form a capacitor;

[0012] The first signal line is connected between the first port and the plurality of first common electrodes, and the second signal line is connected between the second port and the second common electrode;

[0013] The second end of the detection line is connected to the first signal line or the second signal line, so that the detection line and the detection end form a first detection channel for detecting the voltage of the first signal line or a second detection channel for detecting the voltage of the second signal line;

[0014] The processor is used to: output a preset electrical signal through the first port and the second port during a first time period, and detect the voltage of the first signal line or the second signal line through the detection end; and output a compensation electrical signal through the first port or / and the second port according to the voltage of the first signal line or the second signal line during a second time period, so that the first port and the first signal line form a first compensation channel for compensating for the voltage of the first signal line, or / and, the second port and the second signal line form a second compensation channel for compensating for the voltage of the second signal line.

[0015] Optionally, the display panel includes an array substrate and a color filter substrate arranged in a cell with the array substrate, and the color filter substrate includes the second common electrode;

[0016] The array substrate includes a base substrate, and the plurality of pixel electrodes, the plurality of first common electrodes, the first signal line, the second signal line and the detection line located on the base substrate;

[0017] Along the extension direction of the base substrate, the base substrate includes a first area and a second area surrounding the first area, the multiple pixel electrodes and the multiple first common electrodes are all located in the first area, and the first signal line, the second signal line, and the detection line are all located in the second area; the orthographic projections of the first signal line, the second signal line, and the detection line on the base substrate do not intersect with each other.

[0018] Optionally, the first signal line is connected to the first port, and the second end of the detection line is connected to the first signal line;

[0019] The multiple first common electrodes are arranged in multiple rows, and the first signal line is connected to each row of the multiple first common electrodes arranged in the multiple rows; on the base substrate, the first port is located on one side of the multiple first common electrodes arranged in the multiple rows, and the second end of the detection line is located on the other side of the multiple first common electrodes arranged in the multiple rows.

[0020] Optionally, the second signal line is connected to the second port, and the second signal line is connected to the second common electrode through a first metal ball; the second end of the detection line is connected to the second common electrode through a second metal ball;

[0021] The multiple first common electrodes are arranged in multiple rows, and the first signal line is connected to each row of the multiple first common electrodes arranged in multiple rows; on the base substrate, the second port is located on one side of the multiple first common electrodes arranged in multiple rows, and the second metal ball is located on the other side of the multiple first common electrodes arranged in multiple rows.

[0022] Optionally, the first port includes a first sub-port and a second sub-port, the first end of the first signal line is connected to the first sub-port, the second end of the first signal line is connected to the second sub-port, and the first signal line surrounds the first area;

[0023] The detection end is located on a side of the first sub-port away from the second sub-port, or the detection end is located on a side of the second sub-port away from the first sub-port;

[0024] The second port includes a third sub-port and a fourth sub-port, the first end of the second signal line is connected to the third sub-port, and the second end of the second signal line is connected to the fourth sub-port, the detection end, the first sub-port, and the second sub-port are all located between the third sub-port and the fourth sub-port, and the detection line and the first signal line are all located within a surrounding range of the second signal line.

[0025] Optionally, the detection end includes a first detection port and a second detection port, and the detection line includes a first detection signal line and a second detection signal line;

[0026] The first port includes a first sub-port and a second sub-port, the first end of the first signal line is connected to the first sub-port, the second end of the first signal line is connected to the second sub-port, and the first signal line surrounds the first area;

[0027] The first sub-port and the second sub-port are located between the first detection port and the second detection port, the first end of the first detection signal line is connected to the first detection port, the first end of the second detection signal line is connected to the second detection port, and the second end of the first detection signal line and the second end of the second detection signal line are used to be connected to the first signal line or the second signal line;

[0028] The second port includes a third sub-port and a fourth sub-port, the first end of the second signal line is connected to the third sub-port, the second end of the second signal line is connected to the fourth sub-port, the first detection port, the second detection port, the first sub-port and the second sub-port are all located between the third sub-port and the fourth sub-port, and the first detection signal line, the second detection signal line and the first signal line are all located within the surrounding range of the second signal line.

[0029] Optionally, the processor is configured to: detect a first voltage through the first detection port and a second voltage through the second detection port within a first time period; and use an average value of the first voltage and the second voltage as the voltage of the common signal line.

[0030] Optionally, a difference between a voltage of the compensation electrical signal and a voltage of the preset electrical signal is equal to a difference between a voltage of the preset electrical signal and a voltage of the common signal line.

[0031] In the second aspect, a display device is also provided, comprising a display panel as described in any one of the first aspects, wherein the display device further comprises a backlight source, and the display panel is located on the light-emitting side of the backlight source so that the backlight source provides light for the display panel.

[0032] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 1 is a schematic diagram of a longitudinal cross-sectional structure of a display panel provided in Example 1 of the present application;

[0035] Figure 2 This is a schematic diagram of the frame structure of a display panel provided in Example 1 of the present application;

[0036] Figure 3 This is a schematic diagram of the positions of a plurality of pixel electrodes on a first substrate provided in Example 2 of the present application;

[0037] Figure 4 This is a schematic top view of the structure of the first array substrate provided in Example 2 of the present application;

[0038] Figure 5 is a schematic diagram of the longitudinal cross-sectional structure of the first display panel provided in the second embodiment of the present application;

[0039] Figure 6 1 is a schematic top view of the structure of the second array substrate provided in Example 2 of the present application;

[0040] Figure 7 is a schematic diagram of the longitudinal cross-sectional structure of the second display panel provided in Example 2 of the present application;

[0041] Figure 8 This is a schematic top view of the structure of the third array substrate provided in Example 2 of the present application;

[0042] Figure 9 This is a schematic top view of the structure of the first array substrate provided in Example 3 of the present application;

[0043] Figure 10 1 is a schematic top view of the structure of the second array substrate provided in Example 3 of the present application;

[0044] Figure 11 1 is a schematic top view of the structure of the third array substrate provided in Example 3 of the present application;

[0045] Figure 12 This is a schematic top view of the structure of the fourth array substrate provided in Example 3 of the present application;

[0046] Figure 13 1 is a schematic top view of the structure of the fifth array substrate provided in Example 3 of the present application;

[0047] Figure 14 1 is a schematic top view of the structure of the sixth array substrate provided in Example 3 of the present application;

[0048] Figure 15 1 is a schematic top view of the structure of the seventh array substrate provided in Example 3 of the present application;

[0049] Figure 16 1 is a schematic top view of the structure of the eighth array substrate provided in Example 3 of the present application;

[0050] Figure 17 1 is a schematic top view of the structure of the ninth array substrate provided in Example 3 of the present application;

[0051] Figure 18 This is a schematic diagram of the longitudinal cross-sectional structure of a display device provided in Example 4 of the present application.

[0052] The meanings of the figures are as follows:

[0053] 10. Display panel;

[0054] 102. Common electrode;

[0055] 12. Array substrate;

[0056] 122. a first substrate;

[0057] 1222, first area;

[0058] 1224, second area;

[0059] 123, connecting line;

[0060] 124. First common electrode;

[0061] 126. Insulation layer;

[0062] 128. pixel electrode;

[0063] 130, public signal line;

[0064] 132, first signal line;

[0065] 134, second signal line;

[0066] 1342, Part III;

[0067] 1344, Part IV;

[0068] 14. Color film substrate;

[0069] 142. a second base substrate;

[0070] 144. second common electrode;

[0071] 150, detection line;

[0072] 1502, first detection signal line;

[0073] 1504, second detection signal line;

[0074] 152, Part I;

[0075] 154, Part II;

[0076] 16. Liquid crystal layer;

[0077] 160. The first metal ball;

[0078] 170, the second metal ball;

[0079] 18. Processor;

[0080] 182. Flexible circuit board;

[0081] 184. Data driver. DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0083] It should be understood that the “multiple” mentioned in this application refers to two or more. In the description of this application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of this application, words such as “first” and “second” are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit them to be different.

[0084] The display panel provided in the embodiments of the present application is explained in detail below.

[0085] Example 1:

[0086] Figure 1 1 is a schematic diagram of a longitudinal cross-sectional structure of a display panel 10 provided in the first embodiment of the present application. Figure 1 As shown, the display panel 10 includes an array substrate 12, a color filter substrate 14, and a liquid crystal layer 16. The array substrate 12 includes a first base substrate 122, a plurality of pixel electrodes 128, and a plurality of first common electrodes 124. The color filter substrate 14 includes a second base substrate 142 and a second common electrode 144.

[0087] Specifically, the first base substrate 122 is used to carry other components of the array substrate 12, such as multiple pixel electrodes 128 and multiple first common electrodes 124. The first base substrate 122 is generally a transparent glass substrate. Generally, the multiple pixel electrodes 128 and the multiple first common electrodes 124 are all located on the same surface of the first base substrate 122. For ease of description, in each embodiment of the present application, a first direction X, a second direction Y, and a third direction Z are defined. Among them, the first direction X and the second direction Y are both extension directions of the first base substrate 122. That is, the first base substrate 122 extends in the plane where the first direction X and the second direction Y are located. The third direction Z is the thickness direction of the first base substrate 122. The first direction X, the second direction Y, and the third direction Z are perpendicular to each other.

[0088] The first common electrode 124 is the array substrate common electrode. The plurality of pixel electrodes 128 and the plurality of first common electrodes 124 are both located on the first base substrate 122. Generally, the number of pixel electrodes 128 in the array substrate 12 is equal to the number of first common electrodes 124. In this case, the position of each first common electrode 124 and each pixel electrode 128 can be as follows: Figure 1 As shown, a first common electrode 124 and a pixel electrode 128 are located in corresponding positions, and an insulating layer 126 is provided between each first common electrode 124 and the corresponding pixel electrode 128, so that each first common electrode 124 and the corresponding pixel electrode 128 are coupled to form a storage capacitor. During operation of the display panel 10, each of the plurality of pixel electrodes 128 is used to input a voltage. The storage capacitor formed by the coupling between the first common electrode 124 and the corresponding pixel electrode 128 can be used to maintain a constant voltage on the pixel electrode 128.

[0089] The color filter substrate 14 is arranged in a box with the array substrate 12. The color filter substrate 14 includes a second base substrate 142 and a second common electrode 144 located on one surface of the second base substrate 142. The second common electrode 144 is the color filter substrate common electrode. After the color filter substrate 14 is arranged in a box with the array substrate 12, Figure 1 As shown, the plurality of pixel electrodes 128, the plurality of first common electrodes 124 and the second common electrode 144 are all located between the first substrate 122 and the second substrate 142. At this time, the second common electrode 144 is coupled with each of the plurality of pixel electrodes 128 to form a liquid crystal capacitor.

[0090] The liquid crystal layer 16 is located between the color filter substrate 14 and the array substrate 12, which are arranged in a cell-to-cell configuration. The liquid crystal layer 16 may include a plurality of liquid crystal cells, each of which is located between a pixel electrode 128 and a second common electrode 144. Thus, when a voltage difference exists between the pixel electrode 128 and the second common electrode 144, the liquid crystal cell located between the pixel electrode 128 and the second common electrode 144 rotates due to the action of the liquid crystal capacitor, thereby enabling the display panel 10 to achieve a display effect.

[0091] Generally, when the display panel 10 is operating, the plurality of first common electrodes 124 and the second common electrodes 144 are both used to input voltages, and the voltages input to the plurality of first common electrodes 124 and the voltages input to the second common electrodes 144 should be equal and remain constant, thereby ensuring the display effect of the display panel 10. To this end, in the embodiment of the present application, the display panel 10 further includes a processor 18, a detection line 150, and a common signal line 130.

[0092] Figure 2 1 is a schematic diagram of the frame structure of a display panel 10 provided in the first embodiment of the present application. Figure 2 As shown, the processor 18 has an output terminal a and a detection terminal b. The output terminal a of the processor 18 is used to output an electrical signal, and the detection terminal b of the processor 18 is used to detect voltage. The processor 18 can be a data driver or a chip on film (COF) that binds a flexible circuit board and a data driver together. The detection line 150 and the common signal line 130 are both metal wires. The common signal line 130 is connected between the output terminal a of the processor 18 and the common electrode 102 (including at least one of the first common electrode 124 and the second common electrode 144) so that the electrical signal output by the output terminal a of the processor 18 can be output to the common electrode 102 through the common signal line 130. The first end of the detection line 150 is connected to the detection terminal b of the processor 18, and the second end of the detection line 150 is connected to the common signal line 130 so that the processor 18 can detect the voltage of the common signal line 130 through the detection terminal b and the detection line 150. That is, the detection line 150 and the detection end b form a detection channel, and the voltage of the common signal line 130 can be detected through the detection channel.

[0093] The continuous operating duration of the processor 18 can be divided into multiple cyclic working cycles, each of which includes a first period and a second period. The second period is after the first period, and the start time of the second period can be the end time of the first period. In each working cycle, the processor 18 is configured to perform the following steps S110 and S120.

[0094] S110 , in a first period, the processor 18 outputs a preset electrical signal through the output terminal a, and detects the voltage of the common signal line 130 through the detection terminal b.

[0095] The voltage of the preset electrical signal can be the rated voltage value of the first common electrodes 124 and the second common electrodes 144 in the display panel 10. For example, if the voltage input to the first common electrodes 124 and the second common electrodes 144 during operation of the display panel 10 is 3V (volts), that is, the rated voltage value of the first common electrodes 124 and the second common electrodes 144 is 3V, then the voltage of the first voltage signal can be 3V. In this case, the output terminal a of the processor 18 outputs a 3V electrical signal, and the voltage is detected through the detection terminal b.

[0096] S120 , during the second period, the processor 18 outputs a compensation electrical signal through the output terminal a according to the voltage of the common signal line 130 .

[0097] When the processor 18 executes step S110, it can detect the voltage through the detection terminal b, and the detected voltage is the voltage of the common signal line 130. In this way, when the processor 18 executes step S120, it can output the compensation electrical signal through the output terminal a according to the voltage of the common signal line 130 detected in step S110. The principle of the processor 18 outputting the compensation electrical signal is: when the voltage of the common signal line 130 is lower than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is higher than the voltage of the preset electrical signal; when the voltage of the common signal line 130 is higher than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is lower than the voltage of the preset electrical signal. For example, if the voltage of the preset electrical signal is 3V, and the voltage of the common signal line 130 detected in step S110 is 2.8V, the voltage of the compensation electrical signal can be 3.2V or 3.5V. If the voltage of the preset electrical signal is 3V, and the voltage of the common signal line 130 detected in step S110 is 3.3V, the voltage of the compensation electrical signal can be 2.6V or 2.7V. In this way, the voltage variation of the common electrode 102 connected to the common signal line 130 can be compensated. In other words, in step S120, when the output terminal a outputs the compensation electrical signal, the output terminal and the common signal line form a compensation channel, which is used to compensate the voltage of the common signal line.

[0098] In some specific embodiments, the difference between the voltage of the compensation signal and the voltage of the preset signal is equal to the difference between the voltage of the preset signal and the voltage of the common signal line 130. That is, in this case, if the voltage of the preset signal is 3V and the voltage of the common signal line 130 detected in step S110 is 2.8V, the voltage of the compensation signal is 3.2V. If the voltage of the preset signal is 3V and the voltage of the common signal line 130 detected in step S110 is 3.3V, the voltage of the compensation signal is 2.7V.

[0099] In an embodiment of the present application, when the display panel 10 is operating, the processor 18 can output a preset electrical signal to the common signal line 130 during a first period, thereby outputting the preset electrical signal to the common electrode 102. Simultaneously, the processor 18 can also detect the voltage of the common signal line 130 via the detection line 150, thereby detecting voltage changes on the common electrode 102. The processor 18 can output a compensation electrical signal to the common signal line 130 during a second period. When the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal; when the voltage of the common signal line 130 is greater than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is less than the voltage of the preset electrical signal. In this way, voltage changes on the common electrode 102 can be compensated. This display panel 10 can detect and compensate for voltage changes on the common electrodes of the array substrate and the color filter substrate, thereby resolving the horizontal crosstalk problem of the display panel 10 and improving the display quality of the display panel 10.

[0100] Example 2:

[0101] First, the positions of the plurality of pixel electrodes 128 and the plurality of first common electrodes 124 on the first base substrate 122 are described. Figure 3 1 is a schematic diagram of the positions of a plurality of pixel electrodes 128 on the first base substrate 122 provided in the second embodiment of the present application. Figure 3 As shown, along the extension direction of the first base substrate 122, that is, along the plane direction of the first direction X and the second direction Y, the first base substrate 122 includes a first region 1222 and a second region 1224 surrounding the first region 1222 (the dotted line in the figure is the boundary between the first region 1222 and the second region 1224). When the array substrate 12 is assembled with the color filter substrate 14 to form the display panel 10, the first region 1222 of the first base substrate 122 corresponds to the display area (luminous area) of the display panel 10, and the second region 1224 of the first base substrate 122 corresponds to the non-display area of the display panel 10. The plurality of pixel electrodes 128 are all located in the first region 1222. Generally, the plurality of pixel electrodes 128 are arranged in an array of multiple rows and columns within the first region 1222. Figure 4 1 is a schematic diagram of a top view of an array substrate 12 provided in the second embodiment of the present application, wherein the plurality of pixel electrodes 128 are not shown. Figure 4 As shown, corresponding to Figure 3 As shown, multiple pixel electrodes 128 are positioned on the first base substrate 122, and multiple first common electrodes 124 are also located in the first area 1222 and arranged in an array of multiple rows and columns, so that each first common electrode 124 can be coupled with the corresponding pixel electrode 128 to form a storage capacitor.

[0102] Next, the display panel 10 provided in the second embodiment of the present application is further described:

[0103] As mentioned above, the common electrode 102 may include a plurality of first common electrodes 124 and second common electrodes 144. Based on this, the common signal line 130 may also include a first signal line 132 and a second signal line 134, and the output terminal a of the processor 18 may also include a first port a1 and a second port a2.

[0104] like Figure 4 As shown, the first port a1 and the second port a2 are both used to output electrical signals. The first signal line 132 and the second signal line 134 are both metal wires, and the first signal line 132 and the second signal line 134 are both located on the first substrate 122. The first signal line 132 is connected between the first port a1 and the plurality of first common electrodes 124, so that when the first port a1 of the processor 18 outputs an electrical signal, the electrical signal can be transmitted to the plurality of first common electrodes 124 through the first signal line 132. Generally, as Figure 4 As shown, the plurality of first common electrodes 124 can be connected to each other through metal connecting wires 123, and connected to the first signal line 132 through the connecting wires 123. The second signal line 134 is connected between the second port a2 and the second common electrode 144, so that when the second port a2 of the processor 18 outputs an electrical signal, the electrical signal can be transmitted to the second common electrode 144 through the second signal line 134. Figure 5 FIG. 1 is a schematic diagram of a longitudinal cross-sectional structure of a display panel 10 provided in the second embodiment of the present application, wherein the liquid crystal layer 16 is not shown. Figure 4 and Figure 5 As shown, the second signal line 134 extending on the first base substrate 122 can be connected to the second common electrode 144 through the first metal ball 160 to achieve electrical signal transmission between the second signal line 134 and the second common electrode 144 .

[0105] The detection line 150 is also located on the first base substrate 122, and the detection line 150, the first signal line 132 and the second signal line 134 are all located in the second area 1224 of the first base substrate 122. Figure 4As shown, the orthographic projections of the first signal line 132, the second signal line 134, and the detection line 150 on the first substrate 122 do not intersect with each other. The orthographic projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 refers to the projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 along a direction perpendicular to the extension direction of the first substrate 122, i.e., the projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 along the third direction Z. In the embodiment of the present application, the orthographic projections of the first signal line 132, the second signal line 134, and the detection line 150 on the first substrate 122 do not intersect with each other, thereby avoiding parasitic capacitance generated by any two of the first signal line 132, the second signal line 134, and the detection line 150 intersecting with each other.

[0106] In this embodiment, the first end of detection line 150 is connected to detection terminal b, and the second end of detection line 150 can be connected to either first signal line 132 or second signal line 134. When the second end of detection line 150 is connected to first signal line 132, detection line 150 and detection terminal b form a first detection channel. The first detection channel is used to detect the voltage of first signal line 132. When the second end of detection line 150 is connected to second signal line 134, detection line 150 and detection terminal b form a second detection channel. The second detection channel is used to detect the voltage of second signal line 134.

[0107] The structure of the display panel 10 is explained in detail below from two different perspectives: the detection line 150 and the detection end b form a first detection channel; and the detection line 150 and the detection end b form a second detection channel.

[0108] In the first case, the detection line 150 and the detection end b form a first detection channel.

[0109] As mentioned above, the detection line 150 and the first signal line 132 are both located in the second region 1224 of the first base substrate 122. Therefore, the detection line 150 and the first signal line 132 can be directly connected to form a Figure 4 The structure shown.

[0110] In some specific embodiments, when the first port a1 outputs an electrical signal to the plurality of first common electrodes 124 through the first signal line 132, the voltage stability of the first common electrodes 124 that are farther from the first port a1 is worse, that is, the voltage variation is greater. Figure 4As shown, a plurality of first common electrodes 124 are arranged in an array of multiple rows and columns in the first area 1222 of the first base substrate 122. The two adjacent first common electrodes 124 in each row are connected by a connecting line 123, and the first common electrodes 124 in each row are connected to the first signal line 132 through the connecting line 123. In this case, on the first base substrate 122, the first port a1 can be located on one side of the plurality of first common electrodes 124 arranged in multiple rows, and the second end of the detection line 150 is located on the other side of the plurality of first common electrodes 124 arranged in multiple rows. That is, the first port a1 and the second end of the detection line 150 are located on opposite sides of the plurality of first common electrodes 124 arranged in multiple rows. For example, in Figure 4 In the illustrated embodiment, the first port a1 is located above the plurality of first common electrodes 124 (along the paper), while the second end of the detection line 150 is located below the plurality of first common electrodes 124 (along the paper). In this manner, the detection port b of the processor 18 can detect the voltage change of the first common electrode 124, which has the largest voltage change, and compensate for the voltage change of the common electrode 102 based on the detection result, thereby improving the compensation effect for the voltage change of the common electrode 102 and enhancing the display quality of the display panel 10.

[0111] In the second case, the detection line 150 and the detection end b form a second detection channel.

[0112] Figure 6 This is a schematic top view of another array substrate 12 provided in the second embodiment of the present application, in which the plurality of pixel electrodes 128 are not shown. Figure 7 FIG. 1 is a schematic diagram of a longitudinal cross-sectional structure of another display panel 10 provided in the second embodiment of the present application, wherein the liquid crystal layer 16 is not shown. Figure 6 and Figure 7 As shown, the second signal line 134 and the detection line 150 are both located in the second region 1224 of the first substrate 122 and extend on the first substrate 122. The second signal line 134 extending on the first substrate 122 is connected to the second port a2 and can be connected to the second common electrode 144 via the first metal ball 160, so that the second port a2 can transmit an electrical signal to the second common electrode 144 via the second signal line 134 and the first metal ball 160. The detection line 150 extending on the first substrate 122 can be connected to the second common electrode 144 via the second metal ball 170, thereby enabling electrical signal transmission between the detection line 150 and the second signal line 134. In other words, in this embodiment, the detection line 150 is connected to the second signal line 134 via the second metal ball 170, the second common electrode 144, and the first metal ball 160.

[0113] In some specific embodiments, when the second port a2 transmits an electrical signal to the second common electrode 144 through the second signal line 134 and the first metal ball 160, the farther the second common electrode 144 is from the second port a2, the worse its voltage stability is, that is, the greater the voltage change is. Therefore, in this embodiment, Figure 6 As shown, a plurality of first common electrodes 124 are arranged in an array of multiple rows and columns in the first area 1222 of the first base substrate 122. The two adjacent first common electrodes 124 in each row are connected by a connecting line 123, and the first common electrodes 124 in each row are connected to the first signal line 132 through the connecting line 123. In this case, on the first base substrate 122, the second port a2 can be located on one side of the plurality of first common electrodes 124 arranged in multiple rows, and the second metal ball 170 is located on the other side of the plurality of first common electrodes 124 arranged in multiple rows. That is, the second port a2 and the second metal ball 170 are located on opposite sides of the plurality of first common electrodes 124 arranged in multiple rows. For example, in Figure 6 In the illustrated embodiment, the second port a2 is located above the plurality of first common electrodes 124 (along the paper), while the second metal ball 170 is located below the plurality of first common electrodes 124 (along the paper). Thus, the detection terminal b of the processor 18 can detect voltage variations at locations where the voltage variations of the second common electrodes 144 are greater, and compensate for the voltage variations of the common electrodes 102 based on the detection results, thereby improving the compensation effect for the voltage variations of the common electrodes 102 and enhancing the display quality of the display panel 10.

[0114] In some other embodiments, Figure 8 This is a schematic diagram of a top view of another array substrate 12 provided in the second embodiment of the present application. Figure 8 As shown, the detection line 150 extending on the first base substrate 122 may also be directly connected to the second signal line 134. No further details will be given.

[0115] The specific working process of the processor 18 is explained in detail below from two different situations: the detection line 150 and the detection end b form a first detection channel, and the detection line 150 and the detection end b form a second detection channel.

[0116] In the first case, the detection line 150 and the detection end b form a first detection channel.

[0117] Step S110 may specifically be: During a first period, the processor 18 outputs a preset electrical signal through the first port a1 and the second port a2, and detects the voltage of the first signal line 132 through the detection terminal b. Step S120 may specifically be: During a second period, the processor 18 outputs a compensation electrical signal through the first port a1 and / or the second port a2 based on the voltage of the first signal line 132.

[0118] That is, during the first time period, both the first port a1 and the second port a2 output the preset electrical signal. At this time, since the second end of the detection line 150 is connected to the first signal line 132, the detection end b can only detect the voltage of the first signal line 132. During the second time period, the processor 18 can output the compensation electrical signal to the first signal line 132 only through the first port a1 (i.e., only compensate for the voltage changes of the multiple first common electrodes 124, in which case the second port a2 still outputs the preset electrical signal during the second time period); or output the compensation electrical signal to the second signal line 134 only through the second port a2 (i.e., only compensate for the voltage changes of the second common electrode 144, in which case the first port a1 still outputs the preset electrical signal during the second time period); or simultaneously output the compensation electrical signal to the first signal line 132 through the first port a1 and output the compensation electrical signal to the second signal line 134 through the second port a2 (i.e., simultaneously compensate for the voltage changes of the multiple first common electrodes 124 and the second common electrode 144). The voltage of the compensation electrical signal outputted by the first port a1 and / or the second port a2 of the processor 18 is obtained according to the voltage of the first signal line 132 detected by the detection terminal b, and details thereof will not be repeated.

[0119] In the second case, the detection line 150 and the detection end b form a second detection channel.

[0120] Step S110 may specifically include: during a first period, the processor 18 outputs a preset electrical signal through the first port a1 and the second port a2, and detects the voltage of the second signal line 134 through the detection terminal b. Step S120 may specifically include: during a second period, the processor 18 outputs a compensation electrical signal through the first port a1 and / or the second port a2 based on the voltage of the second signal line 134.

[0121] That is, during the first time period, both the first port a1 and the second port a2 output the preset electrical signal. At this time, since the second end of the detection line 150 is connected to the second signal line 134, the detection end b can only detect the voltage of the second signal line 134. During the second time period, the processor 18 can output the compensation electrical signal to the first signal line 132 only through the first port a1 (i.e., only compensate for the voltage changes of the multiple first common electrodes 124, in which case the second port a2 still outputs the preset electrical signal during the second time period); or output the compensation electrical signal to the second signal line 134 only through the second port a2 (i.e., only compensate for the voltage changes of the second common electrode 144, in which case the first port a1 still outputs the preset electrical signal during the second time period); or simultaneously output the compensation electrical signal to the first signal line 132 through the first port a1 and output the compensation electrical signal to the second signal line 134 through the second port a2 (i.e., simultaneously compensate for the voltage changes of the multiple first common electrodes 124 and the second common electrode 144). The voltage of the compensation electrical signal outputted by the first port a1 and / or the second port a2 of the processor 18 is obtained according to the voltage of the second signal line 134 detected by the detection terminal b, and details thereof will not be repeated.

[0122] In the two different situations described above, the first port a1 outputs a compensation electrical signal, meaning that the first port a1 and the first signal line 132 form a first compensation channel. The first compensation channel is used to compensate for the voltage of the first signal line 132. The second port a2 outputs a compensation electrical signal, meaning that the second port a2 and the second signal line 134 form a second compensation channel. The second compensation channel is used to compensate for the voltage of the second signal line 134. In each embodiment of the present application, either the first compensation channel or the second compensation channel may exist, or both may exist.

[0123] Example 3:

[0124] The following describes in detail three different embodiments how “the orthographic projections of the first signal line 132 , the second signal line 134 , and the detection line 150 on the first substrate 122 do not intersect with each other”.

[0125] In the first embodiment, Figures 9 to 11 Schematic diagram of the top view of various array substrates 12 provided in the third embodiment of the present application. Figures 9 to 11As shown, the first port a1, the second port a2, and the detection port b are each a single port. In the second direction Y, the processor 18 is located above the first substrate 122. In the first direction X (the opposite direction), the processor 18 is connected to the portion of the second region 1224 located to the left of the first region 1222. In other words, the first port a1, the second port a2, and the detection port b are all located to the left and above the first region 1222 of the first substrate 122. In this case, the detection port b can be located between the first port a1 and the second port a2, with the first port a1 located on the side of the detection port b closer to the first region 1222.

[0126] In this embodiment, the first signal line 132 may extend along the second direction Y (the column direction along the paper direction). Figure 9 As shown, if the second end of the detection line 150 is connected to the first signal line 132, the detection line 150 may include a first portion 152 extending along the second direction Y and a second portion 154 that does not extend along the second direction Y. The first end of the first portion 152 of the detection line 150 is connected to the detection end b. The first and second ends of the first portion 152 of the detection line 150 are located on opposite sides of the plurality of first common electrodes 124 arranged in multiple rows. The second portion 154 of the detection line 150 is connected between the second end of the first portion 152 of the detection line 150 and the end of the first signal line 132 away from the first port a1.

[0127] like Figure 10 and Figure 11 As shown, the second signal line 134 may include a third portion 1342 and a fourth portion 1344. The third portion 1342 extends along the second direction Y, and the fourth portion 1344 extends along the first direction X. The first end of the third portion 1342 is connected to the second port a2. The first end and the second end of the third portion 1342 are located on opposite sides of a plurality of first common electrodes 124 arranged in multiple rows. An end of the fourth portion 1344 close to the third portion 1342 is connected to the second end of the third portion 1342. If the second end of the detection line 150 is connected to the second signal line 134, the detection line 150 may extend along the second direction Y, and the first end and the second end of the detection line 150 are located on opposite sides of a plurality of first common electrodes 124 arranged in multiple rows. The length of the detection line 150 is less than or equal to the length of the third portion 1342. When the length of the detection line 150 is less than the length of the third portion 1342, as Figure 9 As shown, the second end of the detection line 150 can be connected to the second common electrode 144 through the second metal ball 170. When the length of the detection line 150 is equal to the length of the third portion 1342, as shown in FIG. Figure 11 As shown, the second end of the detection line 150 can be directly connected to the fourth portion 1344 .

[0128] In the second embodiment, Figure 12 and Figure 13 1 is a schematic diagram of a top view of two different array substrates 12 provided in the third embodiment of the present application. Figure 12 and Figure 13 As shown, the first port a1 includes a first sub-port a11 and a second sub-port a12. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The detection port b is only one port.

[0129] In this embodiment, the first end of the first signal line 132 is connected to the first sub-port a11, and the second end of the first signal line 132 is connected to the second sub-port a12, that is, the first signal line 132 is connected between the first sub-port a11 and the second sub-port a12. The first signal line 132 surrounds the first area 1222. The first end of the second signal line 134 is connected to the third sub-port a21, and the second end of the second signal line 134 is connected to the fourth sub-port a22, that is, the second signal line 134 is connected between the third sub-port a21 and the fourth sub-port a22. The detection end b is located on the side of the first sub-port a11 away from the second sub-port a12 (such as Figure 12 As shown), or, the detection end b is located on the side of the second sub-port a12 away from the first sub-port a11 (as shown Figure 13 As shown); and the detection port b, the first sub-port a11, and the second sub-port a12 are all located between the third sub-port a21 and the fourth sub-port a22. That is, the first sub-port a11 and the second sub-port a12 are located between the third sub-port a21 and the fourth sub-port a22, wherein the third sub-port a21 is adjacent to the first sub-port a11. The detection port b can be located between the adjacent third sub-port a21 and the first sub-port a11 (as shown). Figure 12 ), or may be located between the second sub-port a12 and the fourth sub-port a22 (as shown Figure 13 As shown in FIG. 1 , the detection line 150 and the first signal line 132 are both located within the surrounding range of the second signal line 134, and the detection line 150 is located outside the surrounding range of the first signal line 132. As a result, the orthographic projections of the first signal line 132, the second signal line 134, and the detection line 150 on the first substrate 122 do not intersect with each other.

[0130] In the third embodiment, Figure 14 and Figure 15 1 is a schematic diagram of a top view of two different array substrates 12 provided in the third embodiment of the present application. Figure 14 and Figure 15As shown, the first port a1 includes a first sub-port a11 and a second sub-port a12. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The detection port b includes a first detection port b1 and a second detection port b2. The detection line 150 includes a first detection signal line 1502 and a second detection signal line 1504.

[0131] In this embodiment, the first end of the first signal line 132 is connected to the first sub-port a11, and the second end of the first signal line 132 is connected to the second sub-port a12, that is, the first signal line 132 is connected between the first sub-port a11 and the second sub-port a12. The first signal line 132 surrounds the first area 1222. The first end of the second signal line 134 is connected to the third sub-port a21, and the second end of the second signal line 134 is connected to the fourth sub-port a22, that is, the second signal line 134 is connected between the third sub-port a21 and the fourth sub-port a22. The first sub-port a11 and the second sub-port a12 are located between the first detection port b1 and the second detection port b2, and the first sub-port a11, the second sub-port a12, the first detection port b1 and the second detection port b2 are all located between the third sub-port a21 and the fourth sub-port a22. In this case, the third sub-port a21, the first detection port b1, the first sub-port a11, the second sub-port a12, the second detection port b2 and the fourth sub-port a22 can be arranged in sequence along the first direction X (eg Figure 14 shown).

[0132] The first end of the first detection signal line 1502 is connected to the first detection port b1, and the first end of the second detection signal line 1504 is connected to the second detection port b2. As an example, the second end of the first detection signal line 1502 and the second end of the second detection signal line 1504 are both connected to the first signal line 132. Figure 14 As another example, one of the second end of the first detection signal line 1502 and the second end of the second detection signal line 1504 is connected to the first signal line 132, and the other is connected to the second common electrode 144 through the second metal ball 170, thereby connecting to the second signal line 134. Figure 15 As another example, the second end of the first detection signal line 1502 and the second end of the second detection signal line 1504 are both connected to the second signal line 134. In this way, the first detection signal line 1502, the second detection signal line 1504, and the first signal line 132 are all located within the surrounding range of the second signal line 134, and the first detection signal line 1502 and the second detection signal line 1504 are both located outside the surrounding range of the first signal line 132. As a result, the orthographic projections of the first signal line 132, the second signal line 134, the first detection signal line 1502, and the second detection signal line 1504 on the first substrate 122 do not intersect with each other.

[0133] In the third embodiment described above, since the detection terminal b includes the first detection port b1 and the second detection port b2, the processor 18 can detect the voltage through the first detection port b1 or the second detection port b2. Therefore, the "detecting the voltage of the common signal line 130 through the detection terminal b" in step S110 performed by the processor 18 can mean that the processor 18 detects the voltage only through the first detection port b1 or only through the second detection port b2. In some specific embodiments, when the processor 18 executes the "detecting the voltage of the common signal line 130 through the detection terminal b" in step S110, it can also be:

[0134] The processor 18 detects a voltage through the first detection port b1 (hereinafter referred to as the first voltage) and detects a voltage through the second detection port b2 (hereinafter referred to as the second voltage). The processor 18 uses the average of the first and second voltages as the voltage of the common signal line 130. In other words, in this embodiment of the present application, only one of the first detection channel and the second detection channel may exist, or both may exist.

[0135] Specifically, during the first time period, the processor 18 detects the voltage of the common signal line 130 (one of the first signal line 132 and the second signal line 134) connected to the first detection signal line 1502 via the first detection port b1. For ease of description, the voltage detected by the first detection port b1 is referred to as the first voltage. During the first time period, the processor 18 also detects the voltage of the common signal line 130 (one of the first signal line 132 and the second signal line 134) connected to the second detection signal line 1504 via the second detection port b2. For ease of description, the voltage detected by the second detection port b2 is referred to as the second voltage. The processor 18 then calculates the average of the first and second voltages and uses this average as the "voltage of the common signal line 130" described in step S110.

[0136] Figure 16 and Figure 17 1 is a schematic diagram of a top view of two different array substrates 12 provided in the third embodiment of the present application. Figure 16 and Figure 17 In the embodiment shown, the processor 18 is a chip-on-film that binds the flexible circuit board 182 and the data driver 184 together. Figure 16 In the embodiment shown, the first detection signal line 1502 and the second detection signal line 1504 are both connected to the first signal line 132. Figure 17 In the illustrated embodiment, the first detection signal line 1502 and the second detection signal line 1504 are both connected to the second signal line 134 .

[0137] like Figure 16 and Figure 17 As shown, in the embodiment of the present application, the display panel 10 may include a plurality of second signal lines 134. Each of the plurality of second signal lines 134 is configured to be connected to the second common electrode 144 via a first metal ball (not shown) to transmit an electrical signal to the second common electrode 144. The orthographic projection of any second signal line 134 on the first base substrate 122 does not intersect with the orthographic projection of any other second signal line 134 on the first base substrate 122, and the orthographic projection of any second signal line 134 on the first base substrate 122 does not intersect with the orthographic projections of the first signal line 132, the first detection signal line 1502, and the second detection signal line 1504 on the base substrate.

[0138] In some specific embodiments, such as Figure 17 As shown, the display panel 10 includes a plurality of second signal lines 134. The plurality of second signal lines 134 include second signal lines 134 surrounding the first region 1222 of the first base substrate 122, and second signal lines 134 located above the first region 1222 along the third direction Y. The port connected to each second signal line 134 is a sub-port of the second port a2 (not shown in the figure), and the sub-ports connected to different second signal lines 134 can be different. For example, the ports connected to the second signal line 134 surrounding the first region 1222 of the first base substrate 122 are still the third sub-port a21 and the fourth sub-port a22 (not shown in the figure).

[0139] In this case, the second compensation channel formed by the second port a2 and the second signal line 134 may include a first sub-channel and a second sub-channel. The first sub-channel refers to the compensation channel formed by the "second signal line 134 surrounding the first region 1222 of the first substrate 122" and the connected sub-port. The second sub-channel refers to the compensation channel formed by the "second signal line 134 located above the first region 1222 along the third direction Y" and the connected sub-port. In the embodiment of the present application, only one of the first compensation channel, the first sub-channel, and the second sub-channel may exist, or multiple may exist.

[0140] Example 4:

[0141] An embodiment of the present application further provides a display device, comprising the display panel 10 and the backlight source as in any one of the above embodiments. Figure 18 : is a schematic diagram of the longitudinal cross-sectional structure of a display device provided in the fourth embodiment of the present application. Figure 18 As shown, the display panel 10 is located on the light-emitting side of the backlight source, so that the backlight source can provide light for the display panel 10 .

[0142] Specifically, the display panel 10 includes a plurality of pixel electrodes 128, a common electrode 102, a common signal line 130, and a processor 18. The plurality of pixel electrodes 128 are coupled with the common electrode 102 to form a capacitor. The processor 18 has an output terminal a, and the common signal line 130 is connected between the output terminal a and the common electrode 102. The display panel 10 also includes a detection line 150. The processor 18 also has a detection terminal b. A first end of the detection line 150 is connected to the detection terminal b, and a second end of the detection line 150 is connected to the common signal line 130. The detection line 150 and the detection terminal b form a detection channel for detecting the voltage of the common signal line 130.

[0143] The processor 18 is configured to: during a first period, output a preset electrical signal through the output terminal a, and detect the voltage of the common signal line 130 through the detection terminal b. During a second period, output a compensation electrical signal through the output terminal a based on the voltage of the common signal line 130, so that the output terminal a and the common signal line 130 form a compensation channel for compensating the voltage of the common signal line 130; when the voltage of the common signal line 130 is lower than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is higher than the voltage of the preset electrical signal, and the second period occurs after the first period.

[0144] In some embodiments, the common electrode 102 includes a plurality of first common electrodes 124 and a second common electrode 144. The common signal line 130 includes a first signal line 132 and a second signal line 134. The output terminal a includes a first port a1 and a second port a2. One of the plurality of first common electrodes 124 is coupled to one of the plurality of pixel electrodes 128 to form a capacitor, and the second common electrode 144 is coupled to each of the plurality of pixel electrodes 128 to form a capacitor. The first signal line 132 is connected between the first port a1 and the plurality of first common electrodes 124, and the second signal line 134 is connected between the second port a2 and the second common electrode 144. The second end of the detection line 150 is connected to the first signal line 132 or the second signal line 134, so that the detection line 150 and the detection terminal b form a first detection channel for detecting the voltage of the first signal line 132 or a second detection channel for detecting the voltage of the second signal line 134.

[0145] The processor 18 is configured to: during a first period, output a preset electrical signal through the first port a1 and the second port a2, and detect the voltage of the first signal line 132 or the second signal line 134 through the detection terminal b. During a second period, based on the voltage of the first signal line 132 or the second signal line 134, output a compensation electrical signal through the first port a1 and / or the second port a2, so that the first port a1 and the first signal line 132 form a first compensation channel for compensating for the voltage of the first signal line 132, and / or the second port a2 and the second signal line 134 form a second compensation channel for compensating for the voltage of the second signal line 134.

[0146] In some embodiments, the display panel 10 includes an array substrate 12 and a color filter substrate 14 aligned with the array substrate 12. The color filter substrate 14 includes a second common electrode 144. The array substrate 12 includes a first base substrate 122, and a plurality of pixel electrodes 128, a plurality of first common electrodes 124, first signal lines 132, second signal lines 134, and detection lines 150 located on the first base substrate 122. Along the extension direction of the first base substrate 122, the first base substrate 122 includes a first region 1222 and a second region 1224 surrounding the first region 1222. The plurality of pixel electrodes 128 and the plurality of first common electrodes 124 are located in the first region 1222, and the first signal lines 132, second signal lines 134, and detection lines 150 are located in the second region 1224. The orthographic projections of the first signal lines 132, second signal lines 134, and detection lines 150 on the first base substrate 122 do not intersect with each other.

[0147] When the array substrate 12 and the color filter substrate 14 are aligned to form the display panel 10, the first region 1222 of the first base substrate 122 becomes the display region of the display panel 10, and the second region 1224 of the first base substrate 122 becomes the non-display region of the display panel 10. Therefore, the backlight source should provide light to at least the first region 1222 of the first base substrate 122.

[0148] In some embodiments, the first signal line 132 is connected to the first port a1, and the second end of the detection line 150 is connected to the first signal line 132. The plurality of first common electrodes 124 are arranged in multiple rows, and the first signal line 132 is connected to each row of the plurality of first common electrodes 124 arranged in the multiple rows. On the first base substrate 122, the first port a1 is located on one side of the plurality of first common electrodes 124 arranged in the multiple rows, and the second end of the detection line 150 is located on the other side of the plurality of first common electrodes 124 arranged in the multiple rows.

[0149] In some embodiments, the second signal line 134 is connected to the second port a2, and the second signal line 134 is connected to the second common electrode 144 via the first metal ball 160. The second end of the detection line 150 is connected to the second common electrode 144 via the second metal ball 170. The plurality of first common electrodes 124 are arranged in multiple rows, and the first signal line 132 is connected to each row of the plurality of first common electrodes 124 arranged in the multiple rows. On the first base substrate 122, the second port a2 is located on one side of the plurality of first common electrodes 124 arranged in the multiple rows, and the second metal ball 170 is located on the other side of the plurality of first common electrodes 124 arranged in the multiple rows.

[0150] In some embodiments, the first port a1 includes a first sub-port a11 and a second sub-port a12. The first end of the first signal line 132 is connected to the first sub-port a11, the second end of the first signal line 132 is connected to the second sub-port a12, and the first signal line 132 surrounds the first region 1222. The detection terminal b is located on a side of the first sub-port a11 away from the second sub-port a12, or the detection terminal b is located on a side of the second sub-port a12 away from the first sub-port a11. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The first end of the second signal line 134 is connected to the third sub-port a21, and the second end of the second signal line 134 is connected to the fourth sub-port a22. The detection terminal b, the first sub-port a11, and the second sub-port a12 are all located between the third sub-port a21 and the fourth sub-port a22. The detection line 150 and the first signal line 132 are all located within the area surrounding the second signal line 134.

[0151] In some embodiments, the detection port b includes a first detection port b1 and a second detection port b2, and the detection line 150 includes a first detection signal line 1502 and a second detection signal line 1504. The first port a1 includes a first sub-port a11 and a second sub-port a12. The first end of the first signal line 132 is connected to the first sub-port a11, and the second end of the first signal line 132 is connected to the second sub-port a12. The first signal line 132 surrounds the first region 1222. The first sub-port a11 and the second sub-port a12 are located between the first detection port b1 and the second detection port b2. The first end of the first detection signal line 1502 is connected to the first detection port b1, and the first end of the second detection signal line 1504 is connected to the second detection port b2. The second end of the first detection signal line 1502 and the second end of the second detection signal line 1504 are configured to connect to the first signal line 132 or the second signal line 134. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The first end of the second signal line 134 is connected to the third sub-port a21, and the second end of the second signal line 134 is connected to the fourth sub-port a22. The first detection port b1, the second detection port b2, the first sub-port a11, and the second sub-port a12 are all located between the third sub-port a21 and the fourth sub-port a22. The first detection signal line 1502, the second detection signal line 1504, and the first signal line 132 are all located within the surrounding range of the second signal line 134.

[0152] In some embodiments, the processor 18 is configured to: detect a first voltage through the first detection port b1 and a second voltage through the second detection port b2 during a first period of time, and use an average of the first and second voltages as the voltage of the common signal line 130 .

[0153] In some embodiments, the difference between the voltage of the compensation electrical signal and the voltage of the preset electrical signal is equal to the difference between the voltage of the preset electrical signal and the voltage of the common signal line 130 .

[0154] In the embodiment of the present application, the display panel 10 includes a plurality of pixel electrodes 128, a common electrode 102 (including an array substrate common electrode and a color filter substrate common electrode), a common signal line 130, a detection line 150, and a processor 18. The plurality of pixel electrodes 128 are coupled with the common electrode 102 to form a capacitor. The common signal line 130 is connected between the output terminal a of the processor 18 and the common electrode 102. The detection line 150 is connected between the detection terminal b of the processor 18 and the common signal line 130. When the display panel 10 is in operation, the processor 18 can output a preset electrical signal to the common signal line 130 during a first period, thereby outputting the preset electrical signal to the common electrode 102. Simultaneously, the processor 18 can also detect the voltage of the common signal line 130 via the detection line 150, thereby detecting voltage changes on the common electrode 102. The processor 18 can output a compensation electrical signal to the common signal line 130 during a second period. When the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal. In this way, the voltage variation of the common electrode 102 can be compensated. The display panel 10 can detect and compensate for the voltage variation of the common electrode of the array substrate and the common electrode of the color filter substrate, thereby solving the horizontal crosstalk problem of the display panel 10 and improving the display effect of the display panel 10.

[0155] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A display panel comprising a processor, an array substrate, and a color filter substrate aligned with the array substrate; the array substrate comprising a base substrate and a plurality of pixel electrodes, a plurality of first common electrodes, a first signal line, a second signal line, a first detection signal line, and a second detection signal line located on the base substrate; the color filter substrate comprising a second common electrode; one of the plurality of first common electrodes being coupled to one of the plurality of pixel electrodes to form a capacitor, and the second common electrode being coupled to each of the plurality of pixel electrodes to form a capacitor; It is characterized in that Along an extension direction of the base substrate, the base substrate includes a first area and a second area surrounding the first area; the plurality of pixel electrodes and the plurality of first common electrodes are all located in the first area; the first signal line, the second signal line, and the detection line are all located in the second area; orthographic projections of the first signal line, the second signal line, and the detection line on the base substrate do not intersect with each other; The processor has a detection end and an output end, wherein the output end includes a first port and a second port; the detection end includes a first detection port and a second detection port; The first port includes a first sub-port and a second sub-port; a first end of the first signal line is connected to the first sub-port, a second end of the first signal line is connected to the second sub-port, and the first signal line surrounds the first area; the first signal line is also connected to the plurality of first common electrodes; The first sub-port and the second sub-port are located between the first detection port and the second detection port, a first end of the first detection signal line is connected to the first detection port, a first end of the second detection signal line is connected to the second detection port, a second end of the first detection signal line is connected to the first signal line or the second signal line, and a second end of the second detection signal line is connected to the first signal line or the second signal line; the output end and the second end of the first detection signal line are located on opposite sides of the first region, and the output end and the second end of the second detection signal line are located on opposite sides of the first region; The second port includes a third sub-port and a fourth sub-port, the first end of the second signal line is connected to the third sub-port, the second end of the second signal line is connected to the fourth sub-port, and the second signal line is further connected to the second common electrode; the first detection port, the second detection port, the first sub-port, and the second sub-port are all located between the third sub-port and the fourth sub-port, and the first detection signal line, the second detection signal line, and the first signal line are all located within a surrounding range of the second signal line; The processor has multiple working cycles, each of which includes a first time period and a second time period; during the first time period, the processor outputs a preset electrical signal through the first port and the second port, and detects the voltage of the first signal line and / or the second signal line through the first detection port and the second detection port to obtain the voltage of the common signal line; during the second time period, the processor outputs a compensation electrical signal through the first port and / or the second port according to the voltage of the common signal line; wherein, when the voltage of the common signal line is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal, and the difference between the voltage of the compensation electrical signal and the voltage of the preset electrical signal is equal to the difference between the voltage of the preset electrical signal and the voltage of the common signal line; the second time period is after the first time period, and the starting time of the second time period is the ending time of the first time period.

2. The display panel according to claim 1, wherein During the second period, the processor outputs a compensation electrical signal through the first port according to the voltage of the common signal line, so that the first port and the first signal line form a first compensation channel for compensating the voltage of the first signal line.

3. The display panel according to claim 1, wherein During the second period, the processor outputs a compensation electrical signal through the second port according to the voltage of the common signal line, so that the second port and the second signal line form a second compensation channel for compensating the voltage of the second signal line.

4. The display panel according to any one of claims 1 to 3, wherein: The processor is configured to: detect a first voltage through the first detection port and a second voltage through the second detection port within a first time period; and use an average value of the first voltage and the second voltage as the voltage of the common signal line.

5. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 4, wherein the display device further comprises a backlight source, and the display panel is located on the light-emitting side of the backlight source so that the backlight source provides light for the display panel.

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