A dynamically reconfigurable multi-core heterogeneous digital signal processing hardware system based on the VPX standard

Abstract

This invention discloses a dynamically reconfigurable multi-core heterogeneous digital signal processing hardware system based on the VPX standard, relating to the design of high-speed, high-reliability digital signal processing systems. This system implements heterogeneous parallel signal computation and processing. External data can be transmitted via a VPX connector, Ethernet module, or optical module to an FPGA processor module and a DSP processor module for computation. Applications requiring high computing power can use the DSP for computation, while applications with hardware-programmable algorithms can use the FPGA for computation. Furthermore, the board-to-board connection module supports onboard expansion. The hardware system supports online dynamic reconfiguration, remote loading, fault status monitoring, and self-repair.

Description

Technical Field

[0001] The present invention relates to the field of high-speed and high-reliability digital signal processing system design. Background Art

[0002] Modern airborne digital signal processing systems are typically characterized by large amounts of input data, complex operating modes, and high signal processing volumes. Consequently, a real-time digital signal processing system requires multiple processors to operate in parallel, simultaneously distributing data at high speed and interacting with large amounts of data. Previous-generation signal processing hardware systems struggled to meet the requirements for real-time processing, as well as the high reliability, fault tolerance, and self-repair capabilities of electronic systems in aerospace environments. With the rapid development of large-scale integrated circuit technology, high-speed parallel processing, and various advanced algorithms, the use of high-speed DSP and FPGA chips to build parallel processing systems has become a trend. However, designing high-performance signal processing systems is challenging, requiring long R&D cycles and considerable development costs. Therefore, the best approach to shortening development cycles and reducing costs is to develop standard modules and establish a universal, scalable, and dynamically reconfigurable, high-reliability signal processing platform. Summary of the Invention

[0003] To address the problems of low data transmission efficiency, limited versatility, insufficient scalability, and low fault tolerance faced by previous-generation signal processing modules, this paper designs a dynamically reconfigurable multi-core heterogeneous digital signal processing hardware system based on the VPX standard, leveraging current airborne digital signal processing systems. Compared to other systems, this system boasts high computing power, extensive storage space, a rich set of external high-speed interfaces, strong compatibility, ease of development, robustness against harsh environments, and high reliability. This hardware system primarily receives data transmitted from a VPX bus-based backplane, computes and outputs real-time processed results, and supports online dynamic reconfiguration, remote loading, fault status monitoring, and self-repair.

[0004] The present invention relates to a multi-core heterogeneous digital signal processing hardware system based on the VPX standard. The system mainly comprises an FPGA processor module, a DSP processor module, a VPX connector, an SRIO switch module, an Ethernet module, an optical module, a power management module, a clock management module, a storage module, a BMC management module, a CAN bus controller, and a board-to-board connection module. The FPGA processor module comprises three FPGAs: FPGA1, FPGA2, and FPGA3; the DSP processor module comprises two DSPs: DSP1 and DSP2; the storage module comprises a FLASH module and a DDR3 module; the VPX connector is respectively connected to: FPGA1, Ethernet module, FPGA2, FPGA3, and CAN bus controller; the ... A1, FPGA2, and DSP1 are interconnected, FPGA1 and FPGA2 are interconnected, FPGA1, FPGA2, and DSP2 are interconnected, and FPGA1, FPGA2, FPGA3, DSP1, and DSP2 are all connected to the SRIO switch module; DSP1 and DSP2 are both connected to the Ethernet module, and FPGA3 is also separately connected to the Ethernet module, CAN bus controller, BMC management module, clock management module, power management module, DSP1, DSP2, FPGA1, and FPGA2; the DSP1, DSP2, and FPGA3 are all provided with corresponding FLASH modules and DDR3 modules, and FPGA1 and FPGA2 are both provided with corresponding FLASH modules and board-to-board connectors.

[0005] Furthermore, the FPGA1 and FPGA2 are connected to the VPX connector via LVDS, GTX, and LVCMOS respectively, the Ethernet module is connected to the VPX connector via GTX, and the FPGA3 is connected to the VPX connector via LVCMOS, CAN, and GPIO;

[0006] DSP1 is interconnected with FPGA1 and FPGA2 through EMIF bus;

[0007] DSP2 is interconnected with FPGA1 and FPGA2 through EMIF bus;

[0008] FPGA1 and FPGA2 are interconnected through 16 sets of LVDS interfaces for transmission and reception, and one set of 4X GTX high-speed transmission interfaces.

[0009] Both FPCGA1 and FPCA2 provide 16 groups of LVDS interfaces for transmitting and receiving, 1 group of 4X GTX interfaces for high-speed transmission, and 56-transmit and 12-receive LVCMOS interfaces for the VPX interface;

[0010] FPGA1 is connected to the board-to-board connector through a 12-pair LVDS interface and a 36-bit LVCMOS interface;

[0011] FPGA2 is connected to the board-to-board connector through a 12-pair LVDS interface and a 36-bit LVCMOS interface;

[0012] FPGA1, FPGA2, and FPGA3 are connected to the SRIO switch module through two groups of 4X interfaces respectively;

[0013] DSP1 and DSP2 are connected to the SRIO switch module via a set of 4X SRIO interfaces respectively;

[0014] The SRIO switch chip provides four groups of 4X SRIO interfaces to connect to the optical modules;

[0015] FPGA3 is connected to the Ethernet module through a set of SGMII interfaces;

[0016] DSP1 and DSP2 each have one set of SGMII interfaces connected to the Ethernet module;

[0017] The Ethernet module provides one 1000BASE-T interface and four SGMII external interfaces to connect to the VPX interface module;

[0018] The CAN bus controller is connected to FPGA3 and the VPX connector;

[0019] The clock management module provides clocks for each module in the system and is controlled by FPGA3 for clock distribution;

[0020] The power management module is controlled by FPGA3 to turn on and off the power supply;

[0021] FPGA3 is connected to FPGA1 and FPGA2 via Selectmap interface, 8 pairs of LVDS interfaces and 9 LVCOMS interfaces;

[0022] FPGA3 is connected to DSP1 and DSP2 through GPIO interface and SPI interface;

[0023] FPGA1, FPGA2, FPGA3, DSP1, and DSP2 are each connected to a Flash module; DSP1, DSP2, and FPGA3 are each connected to a DDR3 module;

[0024] FPGA1 and FPGA2 have the same interface and consistent pin assignments; DSP1 and DSP2 have the same interface and consistent pin assignments.

[0025] This invention enables heterogeneous parallel signal computing and processing. External data can be transmitted via VPX connectors, Ethernet modules, or optical modules to FPGA and DSP processor modules for computation. Applications requiring high computing power can use the DSP for computation, while applications with hardware-programmable algorithms can use the FPGA for computation. Furthermore, a board-to-board connection module supports onboard expansion. This invention provides a design solution for modern airborne high-speed digital signal processing systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a diagram of the system connection structure of the present invention. DETAILED DESCRIPTION

[0027] The present invention relates to a multi-core heterogeneous digital signal processing hardware system based on the VPX standard. The system primarily comprises an FPGA processor module, a DSP processor module, a VPX connector, an SRIO switch module, an Ethernet module, an optical module, a power management module, a clock management module, a storage module, a BMC management module, a CAN controller module, and a board-to-board connection module. The FPGA processor module comprises three FPGAs: FPGA1, FPGA2, and FPGA3; the DSP processor module comprises two DSPs: DSP1 and DSP2; and the storage module comprises a FLASH module and a DDR3 module. An external host can access the FPGA and DSP processor modules via the VPX connector, the Ethernet module, and the optical module. Serial high-speed data communication between the FPGA and DSP processor modules can be performed via the SRIO switch module. The system implements heterogeneous parallel signal computing and processing. External data can be transmitted to the FPGA and DSP processor modules via the VPX connector, the Ethernet module, or the optical module for computation. Applications requiring high computing power can use the DSP for computation, while applications requiring hardware-programmable algorithms can use the FPGA for computation. Furthermore, the board-to-board connection module supports onboard expansion. The present invention provides a design solution for modern airborne high-speed digital signal processing systems.

[0028] Main features:

[0029] (1) Online upgrade function

[0030] a) FPGA1 and FPGA2 have the function of completing online program upgrade via SRIO bus:

[0031] b) DSP1 and DSP2 have the function of completing online program upgrade via SRIO bus;

[0032] c) FPGA3 is capable of receiving online upgrade programs from FPGA1, FPGA2, and FPGA3 via Ethernet and can complete the online upgrade function of the three FPGAs;

[0033] d) DSP1 and DSP2 receive the online upgrade program of their respective chips through Ethernet and complete the online upgrade function of their respective chips.

[0034] (2) Remote loading function

[0035] a) FPGA3 is capable of receiving the operating files and programs of FPGA1 and FPGA2 via Ethernet and can complete the remote loading of FPGA1 and FPGA2;

[0036] b) DSP1 and DSP2 receive the operating files of their respective chips through Ethernet and complete the remote loading of their respective chips.

[0037] (3) SRIO switching function

[0038] The system has RIO switching function, RapidIO interconnection standard is V2.1, rate is 5Gbps, and the module adopts 4X switching.

[0039] The specific connections are as follows:

[0040] a) FPGA1, FPGA2, and FPGA3 each have two groups of 4X SRIO interfaces connected to the switch chip;

[0041] b) DSP1 and DSP2 each have a set of 4X SRIO interfaces connected to the switch chip;

[0042] c) The switching chip provides four groups of 4X SRIO external optical switching interfaces;

[0043] d) FPGA1, 2, DSP1, 2 and switching chip have the RIO dynamic network access capability.

[0044] (4) Ethernet switching function

[0045] The module has Ethernet switching function and 100 / 1000BASE Mbps self-adaptive function. The specific connection is as follows:

[0046] a) FPGA3 has a set of SGMII interfaces connected to the switch chip;

[0047] b) DSP1 and DSP2 each have one set of SGMII interfaces connected to the switch chip;

[0048] c) The switching chip provides one set of 1000BASE-T external interfaces;

[0049] d) The switch chip provides four sets of SGMII external interfaces.

[0050] (5) Low power mode configurable function

[0051] After receiving the control command from the CAN bus, FPGA3 can control the power consumption of the chips on the board and put them into sleep mode to save power. The specific operations are as follows:

[0052] a) In low-power mode, FPGA3 cuts off the working clocks of FPGA1 and FPGA2 by controlling the clock distribution circuit;

[0053] b) In low power mode, FPGA3 cuts off the working clocks of DSP1 and DSP2 by controlling the clock distribution circuit;

[0054] c) In low power mode, FPGA3 resets DSP1 and DSP2;

[0055] d) In low power mode, FPGA3 resets the RIO switch chip.

[0056] (6) Reset function

[0057] a) The module has a hard reset interface. The reset interface uses a ground / open signal. When FPGA3 receives an external signal for more than 500ms,

[0058] When the signal is low, the entire board is hard reset and the ground / open signal needs to be debounced;

[0059] b) FPGA3 can receive the reset command of the CAN bus and reset DSP1, DSP2, FPGA1, FPGA2 separately or collectively;

[0060] c) DSP1 and DSP2 provide soft reset interfaces for software to implement soft reset.

[0061] (7) Clock shutdown function:

[0062] a) FPGA3 can shut down the 100MHz clocks of FPGA1 and FPGA2 separately by controlling the clock management module;

[0063] b) FPGA3 can shut down the 32.512MHz clocks of FPGA1 and FPGA2 respectively by controlling the clock management module.

[0064] c) FPGA3 can shut down the 50MHz clocks of DSP1 and DSP2 respectively by controlling the clock management module.

[0065] (8) Clock switching function requirements

[0066] a) When the module is powered on, all module clocks use the internal local clock by default;

[0067] b) FPGA3 can receive external ground / open signals. When receiving an external low-level signal lasting more than 500ms, the clock management module switches the system's 100MHz internal clock to the external clock. The ground / open signal needs to be debounced.

[0068] (9) Health management function

[0069] a) The BMC module itself can collect information such as temperature and voltage, and report it through the CAN bus;

[0070] b) The BMC module has an over-temperature protection function. The thresholds of each temperature point of the module can be set. When the threshold value is exceeded, the module can prompt an alarm and protect the over-temperature chip;

[0071] c) The BMC module has an overvoltage protection function. The thresholds of each voltage point of the module can be set. When the threshold value is exceeded, the module can prompt an alarm and protect the overvoltage chip:

[0072] d) The BMC module itself has reporting and recording functions such as power-on self-test, periodic self-test, maintenance self-test, status information, and fault logs.

[0073] Chip and interface implementation:

[0074] (1) DSP selection and technical indicators

[0075] a) Model: TMS320C6678, compatible with domestic chip FT-M6678;

[0076] b) Main frequency: 1GHz;

[0077] c) Operation mode: 32-bit, Big Endian mode by default, configurable to Little Endian mode;

[0078] d) Input clock: 50MHz;

[0079] e) DDR3: ≥4GB, 64-bit bit width; operating frequency not less than 533MHz;

[0080] f) FLASH: no less than 64MB, supports up to 8 program versions, each program space 8MB, Flash

[0081] The three high-order address lines are connected to FPGA3 for program switching, and the hardware design is compatible with 128M Flash.

[0082] (2) FPGA1 and FPGA2 selection and technical indicators

[0083] a) Model: XC7K325T-2FFG900, compatible with domestic chip JFM7K325T;

[0084] b) BPI FLASH: 2256MB, 16-bit width, supports storage of 8 program versions, each with 16MB of space. The upper 3 address lines of the BPI Flash are connected to FPGA3 for program switching. The program loading method adopts asynchronous loading mode.

[0085] (3) FPGA3 selection and technical indicators

[0086] a) Model: XC7Z045-2FFG900I, compatible with domestically produced chip FMQL45T900;

[0087] b) QSPI FLASH: 2128MB, supports 8 program versions, each with 16MB of space.

[0088] (4) RIO switch chip selection and design requirements

[0089] a) Model: 80HCPS1848, compatible with domestic chip NMS1800;

[0090] b) Mode: 4X;

[0091] c) Transmission rate: Line rate 5Gbps;

[0092] (4) Photoelectric conversion module requirements

[0093] a) Working wavelength: 850nm;

[0094] b) Single channel transmission rate: 10.3125Gbps;

[0095] c) Model: HTG8503-MH-T001YY.

[0096] (5) Clock design

[0097] The module clock is divided into internal local clock and external input clock. The specific clock design requirements are as follows:

[0098] External input clock:

[0099] a) The clock distribution circuit receives an external 32.512MHz high-stability MLVDS clock and distributes it to FPGA1 and FPGA2 via LVDS.

[0100] b) The clock distribution circuit receives an external 100MHz high-stability MLVDS clock and can distribute the clock to FPGA1, FPGA2, FPGA3, DSP1, and DSP2 via LVDS;

[0101] Internal local clock:

[0102] a) The module has a 50MHz clock internally, which is directly distributed to FPGA3;

[0103] b) The module has a 100MHz clock inside, which is distributed to FPGA1 and FPGA2 through the clock distribution circuit;

[0104] c) The module has a 100MHz clock inside, which is converted into a 50MHz clock through the clock distribution circuit and distributed to DSP1, DSP2, and CAN bus controller;

[0105] d) The RIO ports of FPGA1, FPGA2, DSP1, DSP2 and the RIO switch chip clock inside the module all use a 156.25MHz high-precision clock with a clock stability of no less than 30ppm;

[0106] e) The Ethernet switching core uses a 25MHz high-precision clock with a clock stability of less than 30ppm;

[0107] Interface design:

[0108] (1) Optical module fiber interface:

[0109] a) Transmission rate: Line rate 5Gbps;

[0110] b) Mode: 4X;

[0111] c) Bus protocol standard: RapidIO Interconnect Specification V2.1;

[0112] d) Quantity: The switch chip provides 4 4X RapidIO fiber optic interfaces.

[0113] e) Light wavelength: 850nm;

[0114] f) Fiber type: multimode fiber;

[0115] g) Effective transmission bandwidth: single-channel 4x no less than 14Gbps; dual-channel 4x simultaneous transmission no less than 28Gbps

[0116] (2) GTX interface

[0117] a) Transmission rate: Line rate 2.5Gbps, 5Gbps optional, 5Gbps default rate;

[0118] b) Mode: 1X, 2X, 4X are configurable;

[0119] c)Transmission protocol: Aurora.

[0120] d) Quantity: 4, 1 group for FPGA1 and FPGA2 to connect to the outside world; 1 group for FPGA1 and FPGA2 to connect to each other;

[0121] (3) 1000BASE-T interface

[0122] a) Transmission rate: 100 / 1000Mbps adaptive;

[0123] b) Quantity: 1 set;

[0124] c) Bus protocol standard: IEEE 802.3 standard.

[0125] (4) SGMII interface

[0126] a) Transmission rate: Line rate 1.25Gbps;

[0127] b) Quantity: 4 groups;

[0128] c) Bus protocol standard: IEEE 802.3 standard.

[0129] (5) LVDS interface

[0130] a) Interface electrical characteristics comply with: TIAEIA-644LVDS specification;

[0131] b) Chip selection: Domestic chips compatible with MAX9122 and 9123;

[0132] c) Transmission content: asynchronous serial port and discrete interface;

[0133] d) Speed: ≤500Mbps;

[0134] e) The LVDS differential signal defined by the LRM connector is connected to the FPGA in single-ended form after being buffered;

[0135] (6) LVCMOS discrete control line interface

[0136] a) Signal level: LVCMOS level 3.3V;

[0137] b) Driving capability: 212mA;

[0138] c) Transmission content: control signals with high real-time requirements;

[0139] d) For the input LVCMOS signal, you need to reserve pull-up and pull-down resistors, and assemble the hardware according to the pull-up assembly:

[0140] (7) RS232 interface

[0141] a) Connect chips: DSP1, DSP2, FPGA3;

[0142] b) Quantity: 4 groups, each group is forked to the debug connector and the backplane connector;

[0143] c) Chip selection: SM3232, a domestically produced chip compatible with MAX3232;

[0144] d) Transmission content: debug serial port.

[0145] (8)CAN bus

[0146] a) Bus protocol standard: CAN bus 2.0 general design specification, compatible with ISO11898 CAN bus standard;

[0147] b) Quantity: 2 ways;

[0148] c) Chip selection: Domestic chip SM65HVD230D compatible with SN65HVD230;

[0149] d) Speed: ≤1Mbps.

[0150] (9)JTAG interface

[0151] a) Interface type: debug interface;

[0152] b) Quantity: 5 (one group each for FPGA1, FPGA2, FPGA3, DSP1, and DSP2).

[0153] (10) RapidIO interface

[0154] a) Transmission rate: Line rate 5Gbps;

[0155] b) Mode: 4X;

[0156] c) Bus protocol standard: RapidIO Interconnect Specification V2.1;

[0157] d) Quantity: 6 groups;

[0158] e) DSP effective transmission bandwidth: no less than 12 Gbps; FPGA effective transmission bandwidth: no less than 14 Gbps for single-channel 4X transmission; no less than 28 Gbps for dual-channel 4xX transmission.

[0159] (11)EMIF interface

[0160] a) Bus width: 16 bits;

[0161] b) Working mode: BigEndian mode, supports both asynchronous and synchronous working modes, and DMA communication is guaranteed to be no less than 100Mbps;

[0162] c) Interconnection relationship: The EMIF bus of DSP1 is connected to FPGA1 and FPGA2 respectively; the EMIF bus of DSP2 is connected to FPGA1 and FPGA2 respectively.

Claims

1. A dynamically reconfigurable multi-core heterogeneous digital signal processing hardware system based on the VPX standard, the system comprising an FPGA processor module, a DSP processor module, a VPX connector, an SRIO switch module, an Ethernet module, an optical module, a power management module, a clock management module, a storage module, a BMC management module, a CAN bus controller, and a board-to-board connection module; wherein the FPGA processor module comprises three FPGAs: FPGA1, FPGA2, and FPGA3; the DSP processor module comprises two DSPs: DSP1 and DSP2; the storage module comprises a FLASH module and a DDR3 module; the VPX connector is respectively connected to: FPGA1, Ethernet module, FPGA2, FPGA3, and CAN bus controller; ... A1, FPGA2, and DSP1 are interconnected, FPGA1 and FPGA2 are interconnected, FPGA1, FPGA2, and DSP2 are interconnected, and FPGA1, FPGA2, FPGA3, DSP1, and DSP2 are all connected to the SRIO switch module; DSP1 and DSP2 are both connected to the Ethernet module, and FPGA3 is also separately connected to the Ethernet module, CAN bus controller, BMC management module, clock management module, power management module, DSP1, DSP2, FPGA1, and FPGA2; DSP1, DSP2, and FPGA3 are all provided with corresponding FLASH modules and DDR3 modules, and FPGA1 and FPGA2 are also provided with corresponding FLASH modules and board-to-board connectors; The clock management module provides clocks for each module in the system and is controlled by FPGA3 for clock distribution; The power management module is controlled by FPGA3 to turn on and off the power supply; FPGA3 is connected to FPGA1 and FPGA2 via Selectmap interface, 8 pairs of LVDS interfaces and 9 LVCOMS interfaces; FPGA3 is connected to DSP1 and DSP2 through GPIO interface and SPI interface; FPGA1 and FPGA2 have the same interface and consistent pin assignments; DSP1 and DSP2 have the same interface and consistent pin assignments.

2. The dynamically reconfigurable multi-core heterogeneous digital signal processing hardware system based on the VPX standard according to claim 1, characterized in that: The FPGA1 and FPGA2 are connected to the VPX connector via LVDS, GTX, and LVCMOS respectively, the Ethernet module is connected to the VPX connector via GTX, and FPGA3 is connected to the VPX connector via LVCMOS, CAN, and GPIO; DSP1 is interconnected with FPGA1 and FPGA2 through EMIF bus; DSP2 is interconnected with FPGA1 and FPGA2 through EMIF bus; FPGA1 and FPGA2 are interconnected through 16 sets of LVDS interfaces for transmission and reception, and one set of 4X GTX high-speed transmission interfaces. Both FPCGA1 and FPCA2 provide 16 groups of LVDS interfaces for transmission and reception, 1 group of 4X GTX interfaces for high-speed transmission, and 56-transmit and 12-receive LVCMOS interfaces for connection to the VPX interface; FPGA1 is connected to the board-to-board connector through a 12-pair LVDS interface and a 36-bit LVCMOS interface; FPGA2 is connected to the board-to-board connector through a 12-pair LVDS interface and a 36-bit LVCMOS interface; FPGA1, FPGA2, and FPGA3 are connected to the SRIO switch module through two groups of 4X interfaces respectively; DSP1 and DSP2 are connected to the SRIO switch module via a set of 4X SRIO interfaces respectively; The SRIO switch chip provides four groups of 4X SRIO interfaces to connect to the optical modules; FPGA3 is connected to the Ethernet module through a set of SGMII interfaces; DSP1 and DSP2 each have one set of SGMII interfaces connected to the Ethernet module; The Ethernet module provides one 1000BASE-T interface and four SGMII external interfaces to connect to the VPX interface module; The CAN bus controller is connected to FPGA3 and the VPX connector.

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