PCIe (Peripheral Component Interconnect Express) equipment function failure positioning method, system and server

Abstract

The invention provides a PCIe device function failure positioning method and system and a server, and relates to the technical field of computer hardware resource management. The method comprises the following steps: a firmware layer constructs a mapping relation between a physical location identifier and a logic device identifier based on a hardware connection topology, and pre-stores the mapping relation to a substrate management controller; in an equipment initialization stage, logic equipment identification information of current equipment is transmitted to a substrate management controller in real time; the baseboard management controller inquires the mapping relation according to the received logic device identifier, and determines a corresponding physical position identifier; and outputting the physical position information corresponding to the logic equipment identifier which is finally processed through a preset interface of the substrate management controller so as to indicate the physical position of the failed equipment. According to the method, the dynamic association of the physical position and the logic information is realized in an equipment initialization stage, and the problem of a physical position blind area caused by no response of equipment is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware resource management, and in particular to a method, system and server for locating PCIe device function failure. Background Art

[0002] In recent years, with the rapid development of high-performance computing and intelligent hardware, PCIe (Peripheral Component Interconnect Express) devices have been widely used in computer systems, such as GPUs, accelerator cards, network cards, and RAID cards. To ensure system reliability, the PCIe Specification (SPEC) defines multiple layers of error detection and recovery mechanisms, including encoding checksums at the physical layer, link CRC checks at the link layer, end-to-end CRC checks at the transaction layer, and Advanced Error Reporting (AER). During normal device operation, these mechanisms can intervene through the driver or firmware to detect error status and locate faulty devices.

[0003] In the prior art, the initialization process for PCIe devices typically includes the following steps: After the device is powered on or receives a reset signal (PERST#), it enters the Detect phase, resetting registers and state machines to their initial values; through Link Training, it completes device detection, rate negotiation, and bandwidth configuration, entering the L0 state; during the boot process, the BIOS scans the PCIe bus and enumerates devices, allocating resources and loading the device firmware (in either Legacy or UEFI format). During the system operation phase, error handling is typically led by the firmware or device driver, which analyzes error status information at each level to locate the fault.

[0004] However, the above technology has significant limitations: when a PCIe device fails completely during the BIOS initialization phase (such as the POST process) due to hardware compatibility issues, abnormal signal quality, or firmware loading failure, the device will be unable to respond to PCIe protocol operations. At this time, the PCIe Root, PCIe Bridge, and PCIe Switch cannot access the device. The error detection mechanisms of the physical layer, link layer, and transaction layer cannot capture valid information due to the lack of device response. The AER mechanism also fails because the device has not completed initialization. For example, in a multi-device scenario, if a device fails to initialize and causes the system to hang, neither the host nor the baseboard management controller (BMC) can obtain error logs. Operations and maintenance personnel need to plug and unplug devices one by one or perform repeated restart tests to locate the faulty device, which greatly reduces production testing efficiency and seriously affects user experience. Summary of the Invention

[0005] The purpose of the present invention is to provide a method, system and server for locating PCIe device functional failure to solve the problem raised in the above background technology: the physical location of the fault cannot be located when the PCIe device fails to respond due to complete failure during the initialization phase.

[0006] To achieve the above object, according to one aspect of the present invention, a method for locating a PCIe device failure is provided, the method comprising:

[0007] The firmware layer constructs a mapping relationship between the physical location identifier and the logical device identifier based on the hardware connection topology and pre-stores it in the baseboard management controller;

[0008] During the device initialization phase, the logical device identification information of the current device is transmitted to the baseboard management controller in real time;

[0009] The baseboard management controller queries the mapping relationship according to the received logical device identifier and determines the corresponding physical location identifier;

[0010] The physical location information corresponding to the last processed logical device identifier is outputted through a preset interface of the baseboard management controller to indicate the physical location of the failed device.

[0011] In a possible implementation, the device initialization phase includes:

[0012] Perform bus enumeration to discover all PCIe devices and establish device topology information;

[0013] Generate a mapping table of physical location identifiers and logical device identifiers according to the device topology information and pre-store it in a baseboard management controller;

[0014] Perform resource allocation and driver loading operations on each PCIe device in sequence;

[0015] In one possible implementation, the resource allocation and driver loading operations include:

[0016] Dynamically allocate system resources for the current device and send the logical device identifier to the baseboard management controller after the allocation is completed;

[0017] Load device firmware and execute initialization routines;

[0018] The uninitialized device queue is detected cyclically, and the resource allocation step is repeated when there are unprocessed devices.

[0019] In a possible implementation, the method further includes:

[0020] Transmitting status characteristic information during the initialization process to the baseboard management controller in real time;

[0021] Comprehensive diagnostic information including the logical device identifier, the physical location identifier, and the status characteristic information is output through the preset interface.

[0022] In a possible implementation, the logical device identification information includes at least one combination of information in a topological address consisting of a bus domain number, a bus number, a device number, and a function number.

[0023] In a possible implementation, the physical location identifier includes at least one physical location information of a rack number of the pluggable module, a backplane slot number, and a hot-swap controller channel identifier.

[0024] In a possible implementation, the access method of the preset interface includes but is not limited to graphical user interface display and command line instruction parsing.

[0025] According to another aspect of an embodiment of the present disclosure, a system for locating a PCIe device failure is provided, the system comprising:

[0026] A firmware layer module, the firmware layer module is used to generate a mapping relationship between a physical location identifier and a logical device identifier based on the hardware topology and pre-store it in the baseboard management controller; the firmware layer module is also used to transmit the logical device identifier information of the current device to the baseboard management controller in real time during the device initialization phase;

[0027] A baseboard management controller is used to query the mapping relationship based on the received logical device identifier and determine the corresponding physical location identifier; the baseboard management controller is also used to output the physical location information corresponding to the last processed logical device identifier through a preset interface to indicate the physical location of the failed device.

[0028] According to another aspect of an embodiment of the present disclosure, a server is provided, the server including the system for locating a PCIe device failure according to the above aspect, and the server further including:

[0029] A processor, configured to execute hardware topology construction and initialization operations of the firmware layer module;

[0030] a PCIe bus connecting the processor and a plurality of PCIe devices, for establishing device topology information during bus enumeration;

[0031] A non-volatile storage medium, configured to store a mapping relationship between a physical location identifier and a logical device identifier received by the baseboard management controller;

[0032] A pluggable backplane module, comprising a standardized slot structure corresponding to the physical location identifier, for carrying the PCIe device and providing hot-swap support;

[0033] The baseboard management controller communicates with the firmware layer module through an out-of-band management protocol, and integrates a management interface independent of the operating system as the preset interface.

[0034] In one possible implementation, the PCIe device includes a graphics processing unit, a network interface card, a memory card, or a hardware acceleration card.

[0035] The above one or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:

[0036] A method for locating a PCIe device functional failure is provided in an embodiment of the present invention. The method pre-constructs a mapping relationship between a physical location identifier and a logical device identifier through a firmware layer, and transmits the logical identifier information to a baseboard management controller in real time during the device initialization phase. Therefore, even if the device is unable to respond to PCIe protocol operations due to complete failure, the baseboard management controller can still independently parse the corresponding physical location identifier through the mapping relationship, thereby breaking through the limitation of traditional reliance on the device to actively report the error status. The method realizes the dynamic association of physical location and logical information during the device initialization phase, solves the problem of physical location blind spots caused by unresponsive devices, does not need to rely on the PCIe link layer or transaction layer error detection mechanism, significantly improves the efficiency of failure location in multi-device scenarios, reduces manual troubleshooting costs, and enhances the reliability and real-time performance of system operation and maintenance.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A flowchart of a method for locating a PCIe device failure according to an exemplary embodiment is provided;

[0039] Figure 2 A detailed flow chart of a device initialization phase of a method for locating a PCIe device function failure according to an exemplary embodiment;

[0040] Figure 3 A detailed flow chart of resource allocation and driver loading operations of a method for locating a PCIe device function failure according to an exemplary embodiment is provided;

[0041] Figure 4 A schematic diagram of the structure of a positioning system module for locating a PCIe device failure according to an exemplary embodiment is provided;

[0042] Figure 5The present invention is a schematic diagram of the composition structure of a PCIe configuration module of a server provided according to an exemplary embodiment.

[0043] Explanation of reference numerals: 100, firmware layer module; 200, baseboard management controller; 300, processor; 400, PCIe bus; 500, non-volatile storage medium; 600, pluggable backplane module. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0045] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, like numbers in different figures represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of systems and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0046] Figure 1 A flowchart of a method for locating a PCIe device failure according to an exemplary embodiment is provided. Figure 1 As shown, the method includes the following steps:

[0047] In step S100, the firmware layer constructs a mapping relationship between the physical location identifier and the logical device identifier based on the hardware connection topology, and pre-stores it in the baseboard management controller;

[0048] Among them, the hardware connection topology refers to the physical connection method of PCIe devices in the system, including the slot position, link layer, connection relationship, etc. of each device; during the system startup process, the firmware layer will perform a PCIe bus scanning process to identify all connected PCIe devices. The firmware layer will record the physical connection information of each device, such as slot number, link speed, link width, etc.

[0049] Each PCIe device's physical location in the hardware connection topology is assigned a unique identifier, known as a physical location identifier. Examples include slot numbers ("Slot1," "Slot2," ...,"SlotN"), link layer levels ("Link1," "Link2," ...,"LinkN"), and other identifiers (such as the device's physical location coordinates on the motherboard). Each PCIe device is assigned a logical device identifier within the system, such as a device name ("Device1," "Device2," ...,"DevN"), a device number ("Dev001," "Dev002," ...,"DevN"), and other identifiers (such as the device's MAC address or UUID). The firmware layer associates the physical location identifier with the logical device identifier to form a mapping table, for example: "Slot1" → "Device1," "Slot2" → "Device2," ...,"SlotN" → "DevN."

[0050] The firmware layer can transmit the mapping relationship data to the baseboard management controller via an internal bus or a dedicated interface. For example, the firmware layer packages the mapping relationship table into a format suitable for transmission, such as JSON, XML, or binary format, and sends the data to the baseboard management controller via a bus such as SPI, I2C, or LPC. After receiving the mapping relationship data, the baseboard management controller stores it in non-volatile memory, which can include flash memory, EEPROM, or other storage media.

[0051] In step S200, during the device initialization phase, the logical device identification information of the current device is transmitted to the baseboard management controller in real time; the device initialization phase refers to the process of the PCIe device entering the normal working state from the power-off or reset state. For example, in the device initialization phase, first, after the device receives the power-on signal or reset signal, it enters the initialization process. Then, the link training is performed between the device and the host to negotiate the link speed, width and other parameters. Then, the device is enumerated, the system identifies the device, allocates resources (such as memory address, interrupt number, etc.), and finally loads the device firmware (such as UEFI driver) to make the device enter an operational state. During the device enumeration process, the BIOS or UEFI firmware will assign a logical device identifier to each PCIe device. The firmware layer can obtain this identification information through the internal interface or API and pass it to the baseboard management controller.

[0052] The firmware layer can communicate with the baseboard management controller via an internal bus (such as SPI, I2C, LPC, etc.), transmitting logical device identification information in real time. For example, using the SPI bus, the firmware layer can encapsulate the logical device identification information into a message frame and send it to the baseboard management controller via the SPI interface. Alternatively, some systems may be equipped with dedicated communication interfaces for data exchange between the firmware layer and the baseboard management controller. The firmware layer can use these dedicated interfaces to transmit logical device identification information in real time.

[0053] In step S300, the baseboard management controller queries the mapping relationship based on the received logical device identifier and determines the corresponding physical location identifier; specifically, after receiving the logical device identifier, the baseboard management controller will first parse the logical device identifier to extract the logical device identifier from the received data, such as "Device1", and then the baseboard management controller searches for an entry matching the logical device identifier in the mapping relationship table, for example, searching for the physical location identifier corresponding to "Device1" in the mapping table. If a matching entry is found, the baseboard management controller will determine the corresponding physical location identifier, such as "Slot1". If no matching entry is found, the baseboard management controller needs to handle the abnormal situation, for example, it can record the logical device identifier for which no match is found or notify the operation and maintenance personnel or the monitoring system for further processing.

[0054] In step S400, the physical location information corresponding to the last processed logical device identifier is output through the preset interface of the baseboard management controller to indicate the physical location of the failed device. The preset interface can be a common output interface, such as a serial port (SerialPort), a network interface (NetworkInterface), a dedicated communication interface, a log file (LogFile), etc. When the PCIe device completely fails during the initialization phase, the user can still read the physical location information corresponding to the last processed logical device identifier through the preset interface, so as to quickly locate the physical location of the failed device, thereby improving the reliability and operation and maintenance efficiency of the system.

[0055] The above steps pre-build the mapping relationship between the physical location identifier and the logical device identifier through the firmware layer, and transmit the logical identification information to the baseboard management controller in real time during the device initialization phase. Even if the device cannot respond to PCIe protocol operations due to complete failure, the baseboard management controller can still independently resolve the corresponding physical location identifier through the mapping relationship, thereby breaking through the limitation of traditional reliance on devices to actively report error status. This method realizes the dynamic association of physical location and logical information during the device initialization phase, solves the physical location blind spot problem caused by unresponsive equipment, and does not need to rely on the PCIe link layer or transaction layer error detection mechanism, significantly improving the failure location efficiency in multi-device scenarios, reducing manual troubleshooting costs, and enhancing the reliability and real-time performance of system operation and maintenance.

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0057] In one possible implementation, see Figure 2 , the device initialization phase includes:

[0058] In step S210, bus enumeration is performed to discover all PCIe devices and establish device topology information; bus enumeration is a key step in the device initialization phase, which aims to identify all PCIe devices in the system and build the connection relationship and hierarchical structure between these devices. Specifically, the system scans all possible PCIe slots and devices one by one through the PCIe bus controller. For each existing device, the system collects device information such as device identification information, device configuration information or link information, wherein the device identification information may include vendor ID, device ID, class code, etc.; the device configuration information may include the functional configuration of the device, such as memory mapping address, interrupt number, etc.; the link information may include the link speed, link width, etc. of the device.

[0059] Device topology information specifically includes device hierarchical relationships, link connection relationships, link speeds, and widths. The device hierarchy consists of the root complex, PCIe switches, and endpoint devices. The root complex is the starting point of the PCIe topology, connecting the processor and PCIe devices. Switches support PCIe channel expansion to support multiple PCIe ports, expanding the PCIe topology. Endpoint devices are actual PCIe devices, such as GPUs, network adapters, and storage devices. For example, establishing device topology information involves: the system constructing a PCIe device hierarchy based on scan results; determining the physical connection relationships between devices, such as which device is connected to which port, the link direction, and the topology; and determining the transmission speed and number of lanes for each link, such as link speeds of 2.5GT / s, 5GT / s, 8GT / s, and 16GT / s, and link widths of x1, x4, x8, and x16. The system can represent device topology information using appropriate data structures, such as tree structures or graph structures.

[0060] In step S220, a mapping table between physical location identifiers and logical device identifiers is generated based on the device topology information and pre-stored in the baseboard management controller. Specifically, first, the system analyzes the device topology information established in step S210 to determine the physical connection location and link information of each device. Then, a physical location identifier is assigned to each device, for example, a device connected to Slot1 is assigned "Slot1", a device connected to Slot2-Port1 is assigned "Slot2-Port1", and a device connected to Switch1-Link2 is assigned "Switch1-Link2". A logical device identifier is assigned to each device. For example, a device named Device1 is assigned "Device1", a device named Device2 is assigned "Device2", and a device named Device3 is assigned "Device3". Finally, a mapping relationship between physical location identifiers and logical device identifiers is established, for example: "Slot1" → "Device1", "Slot2-Port1" → "Device2", "Switch1-Link2" → "Device3". The firmware layer transmits the mapping table data to the baseboard management controller, which receives and stores the data.

[0061] In step S230, resource allocation and driver loading operations are sequentially performed on each PCIe device. Resource allocation refers to allocating system resources to each PCIe device to ensure that the device can communicate and exchange data with the system. The system can allocate memory address space, interrupt number, and other resources to each PCIe device. For example, the memory address range 0xE0000000-0xEFFFFFFF and interrupt number 10 are allocated to Device1. Driver loading refers to loading the corresponding driver for each PCIe device to enable it to interact with the operating system and applications. The system can search the driver database for the corresponding driver based on the device's vendor ID and device ID. For example, if the driver "DriverA" for Device1 is found, the system then loads "DriverA" into memory and calls its initialization function. The driver starts Device1, putting it into operation.

[0062] In one possible implementation, see Figure 3 , resource allocation and driver loading operations include:

[0063] In step S231, system resources are dynamically allocated to the current device, and after the allocation is completed, the logical device identifier is sent to the baseboard management controller; it can be understood that dynamic resource allocation means that during the device initialization process, system resources such as memory address space, interrupt number, DMA channel, etc. are dynamically allocated to the device according to the actual needs of the device. After the resource allocation is completed, the logical device identifier of the current device is sent to the baseboard management controller so that the baseboard management controller can track the initialization status of the device and obtain the logical device identifier of the current device from the device topology information.

[0064] In step S232, the device firmware is loaded and the initialization routine is executed; the device firmware is software provided by the device manufacturer to control the behavior and function of the device, and the initialization routine is part of the device firmware and is used to initialize the hardware components and software configuration of the device.

[0065] In step S233, the uninitialized device queue is checked cyclically. If any unprocessed device exists, the resource allocation step is repeated. For example, a check is performed cyclically to see if any PCIe device has not completed initialization. If so, the next PCIe device is selected and steps S231 to S233 are repeated. If no unprocessed device exists, the system proceeds to the next stage of the startup process.

[0066] Through the detailed steps described above, the system can sequentially perform resource allocation and driver loading operations for each PCIe device in step S230. This method ensures that each device obtains the necessary system resources and loads the corresponding firmware and driver, enabling it to function properly. Furthermore, by looping through the queue of uninitialized devices, the system can process all devices that require initialization and handle any errors that may arise during the initialization process, thereby improving system reliability and stability.

[0067] In one possible implementation, the method further includes:

[0068] The status characteristic information of the initialization process is transmitted to the baseboard management controller in real time; the status characteristic information refers to the status and characteristic information of the device at each stage during the PCIe device initialization process, such as the initialization stage status, error information, performance indicators or other status information; the initialization stage status is used to indicate which initialization stage the current device is in, such as: Detect stage, Link Training stage, Configuration stage, Initialization stage, Ready stage, Failed stage, etc.; error information is used to indicate errors encountered by the device during the initialization process, such as hardware errors, firmware errors, configuration errors, etc.; performance indicators are used to indicate performance-related indicators of the device, such as link speed, link width, throughput, etc.; other status information is used to indicate other status information of the device, such as power status, temperature, voltage, etc.

[0069] Comprehensive diagnostic information, including logical device identification, physical location identification, and status characteristics, is output through a pre-set interface. Through the detailed steps described above, the system monitors device status in real time during device initialization and outputs comprehensive diagnostic information to the baseboard management controller. This approach ensures that if a device fails completely and becomes incapable of responding to PCIe protocol operations, operators or monitoring systems can obtain detailed device status information through the baseboard management controller, allowing them to quickly locate and resolve issues, thereby improving system reliability and maintainability.

[0070] In one possible embodiment, the logical device identification information includes at least one combination of information in a topological address consisting of a bus domain number, a bus number, a device number, and a function number. It is understandable that in a PCIe topology, a device is typically uniquely identified by a bus domain number (Domain), a bus number (Bus), a device number (Device), and a function number (Function). This identification method is called a topological address (Routing ID), wherein the bus domain number is used to identify different PCIe domains (Domain). In a complex system, there may be multiple PCIe domains, each of which may contain multiple buses, devices, and functions; the bus number is used to identify a PCIe bus (Bus), and each PCIe domain may contain multiple buses; the device number is used to identify a PCIe device (Device) connected to a specific bus; and the function number is used to identify different functions (Function) in a device. A PCIe device may contain multiple functions, for example, a multi-function device may serve as a network adapter and a storage controller at the same time. In this embodiment, the logical device identification information may be composed of one or more combinations of bus domain numbers, bus numbers, device numbers, and function numbers according to actual needs. By using at least one combination of information in the topological address as logical device identification information and establishing a mapping relationship between it and the physical location identification, this method ensures the uniqueness and traceability of the device identification, providing a reliable basis for subsequent fault location and diagnosis.

[0071] In one possible implementation, the physical location identifier includes at least one of the physical location information of the rack number, backplane slot number, and hot-swappable controller channel identifier of the pluggable module. In a complex server or data center environment, PCIe devices usually exist in the form of pluggable modules, such as PCIe expansion cards, GPU accelerator cards, network interface cards, etc. In order to accurately locate these devices, the physical location identifier may include physical location information such as the rack number, backplane slot number, and hot-swappable controller channel identifier; wherein the rack number is used to identify the rack (Rack) where the device is located. In a data center or large server environment, it usually contains multiple racks, each of which can accommodate multiple servers or devices; the backplane slot number is used to identify the specific slot position of the device on the server backplane (Backplane). The backplane is a circuit board inside a server that connects to various expansion cards. Backplane slot numbers are used to precisely locate the physical location of devices within the server, for example, which slot is connected to which device. Hot-swap controller channel identifiers identify the channel of the hot-swap controller to which a device is connected, facilitating management and control of device insertion and removal. The hot-swap controller allows devices to be inserted or removed without shutting down the system power. In the above embodiment, the physical location identifier can be composed of one or more combinations of physical location information, such as the rack number, backplane slot number, and hot-swap controller channel identifier, as needed.

[0072] In one possible embodiment, the access method of the preset interface includes but is not limited to graphical user interface display and command line instruction parsing. The preset interface is an interface provided by the baseboard management controller (BMC) or other management modules for outputting and managing device information. Through the preset interface, the user or system can access the physical location identification, logical device identification, status characteristic information and other diagnostic information of the device. The access method of the preset interface can include multiple forms, of which the graphical user interface (GUI) and command line instruction parsing are two common methods. Specifically, a graphical user interface is an interface method that interacts with the user through graphical elements (such as windows, icons, buttons, menus, etc.), which enables the user to intuitively view and manage device information through the graphical user interface; a command line interface (CLI) is an interface method that interacts with the system by entering text commands. The command line interface is suitable for scenarios that require precise control and efficient operation. In addition to the graphical user interface and command line interface, the preset interface can also access the web interface provided by the baseboard management controller through a web browser for device management and monitoring.

[0073] Reference Figure 4 The present disclosure further provides a system for locating a PCIe device failure, comprising:

[0074] The firmware layer module 100 is used to generate a mapping relationship between a physical location identifier and a logical device identifier based on the hardware topology and pre-store it in the baseboard management controller 200. The firmware layer module 100 is also used to transmit the logical device identifier information of the current device to the baseboard management controller 200 in real time during the device initialization phase.

[0075] The baseboard management controller 200 is used to query the mapping relationship based on the received logical device identification and determine the corresponding physical location identification; the baseboard management controller 200 is also used to output the physical location information corresponding to the last processed logical device identification through a preset interface to indicate the physical location of the failed device.

[0076] Through the collaborative work of the firmware layer module 100 and the baseboard management controller 200 (baseboard management controller 200), even if the device is unable to respond to PCIe protocol operations due to complete failure, the baseboard management controller 200 can still independently resolve the corresponding physical location identifier through the mapping relationship, thereby breaking through the traditional limitation of relying on the device to actively report the error status; the system realizes the dynamic association of physical location and logical information during the device initialization phase, solves the physical location blind spot problem caused by the unresponsive device, and does not need to rely on the PCIe link layer or transaction layer error detection mechanism, significantly improving the failure location efficiency in multi-device scenarios, reducing manual troubleshooting costs, and enhancing the reliability and real-time performance of system operation and maintenance.

[0077] Reference Figure 5 The present invention further provides a server, including the PCIe device function failure positioning system provided in the above embodiment, further comprising:

[0078] Processor 300, used to execute hardware topology construction and initialization operations of firmware layer module 100; processor 300 is the core computing unit of the server, responsible for executing various computing tasks;

[0079] PCIe bus 400 connects the processor 300 and multiple PCIe devices and is used to establish device topology information during bus enumeration. PCIe bus 400 is a high-speed serial bus inside the server and is used to connect the processor 300 and multiple PCIe devices.

[0080] The non-volatile storage medium 500 is used to store the mapping relationship between the physical location identifier and the logical device identifier received by the baseboard management controller 200, and the non-volatile storage medium 500 is connected to the baseboard management controller 200;

[0081] The pluggable backplane module 600 includes a standardized slot structure corresponding to a physical location identifier, and is used to carry PCIe devices and provide hot-plug support; PCIe devices may include a graphics processing unit, a network interface card, a memory card, or a hardware acceleration card.

[0082] The baseboard management controller 200 communicates with the firmware layer module 100 through an out-of-band management protocol, and integrates a management interface independent of the operating system as a preset interface.

[0083] As the system boots up, the processor 300 begins executing firmware code, performing a hardware topology scan and device initialization. The firmware layer module 100 constructs a mapping relationship between physical location identifiers and logical device identifiers and pre-stores this information in the baseboard management controller 200. The PCIe bus 400 performs a bus enumeration process to establish device topology information. The processor 300 allocates system resources, loads device drivers and firmware, and the firmware layer module 100 transmits logical device identification information to the baseboard management controller 200 in real time. Through the collaborative work of the processor 300, PCIe bus 400, non-volatile storage medium 500, pluggable backplane module 600, and baseboard management controller 200, the server can quickly locate the physical location of a device in the event of a device failure, thereby improving the server's reliability and maintainability.

[0084] Anything not described in detail in the present invention is well known to those skilled in the art.

[0085] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A method for locating a PCIe device failure, characterized in that: The following steps are involved: The firmware layer constructs a mapping relationship between the physical location identifier and the logical device identifier based on the hardware connection topology and pre-stores it in the baseboard management controller; During the device initialization phase, the logical device identification information of the current device is transmitted to the baseboard management controller in real time; The baseboard management controller queries the mapping relationship according to the received logical device identifier and determines the corresponding physical location identifier; The physical location information corresponding to the last processed logical device identifier is outputted through a preset interface of the baseboard management controller to indicate the physical location of the failed device.

2. A method for locating a PCIe device failure according to claim 1, characterized in that: The device initialization phase includes: Perform bus enumeration to discover all PCIe devices and establish device topology information; Generate a mapping table of physical location identifiers and logical device identifiers according to the device topology information and pre-store it in a baseboard management controller; Resource allocation and driver loading operations are performed on each PCIe device in sequence.

3. A method for locating a PCIe device failure according to claim 2, characterized in that: The resource allocation and driver loading operations include: Dynamically allocate system resources for the current device and send the logical device identifier to the baseboard management controller after the allocation is completed; Load device firmware and execute initialization routines; The uninitialized device queue is detected cyclically, and the resource allocation step is repeated when there are unprocessed devices.

4. The method for locating a PCIe device failure according to claim 1, wherein: The method further comprises: Transmitting status characteristic information during the initialization process to the baseboard management controller in real time; Comprehensive diagnostic information including the logical device identifier, the physical location identifier, and the status characteristic information is output through the preset interface.

5. The method for locating a PCIe device failure according to claim 1, wherein: The logical device identification information includes at least one combination of information of a topological address consisting of a bus domain number, a bus number, a device number, and a function number.

6. The method for locating a PCIe device failure according to claim 1, wherein: The physical location identifier includes at least one physical location information of a rack number of the pluggable module, a backplane slot number, and a hot-swap controller channel identifier.

7. The method for locating a PCIe device failure according to claim 1, wherein: The access method of the preset interface includes but is not limited to graphical user interface display and command line instruction parsing.

8. A system for locating PCIe device failure, characterized in that: include: A firmware layer module, the firmware layer module is used to generate a mapping relationship between a physical location identifier and a logical device identifier based on the hardware topology and pre-store it in the baseboard management controller; the firmware layer module is also used to transmit the logical device identifier information of the current device to the baseboard management controller in real time during the device initialization phase; A baseboard management controller is used to query the mapping relationship based on the received logical device identifier and determine the corresponding physical location identifier; the baseboard management controller is also used to output the physical location information corresponding to the last processed logical device identifier through a preset interface to indicate the physical location of the failed device.

9. A server, characterized in that: The system for locating a PCIe device failure according to claim 8 further comprises: A processor, configured to execute hardware topology construction and initialization operations of the firmware layer module; a PCIe bus connecting the processor and a plurality of PCIe devices, for establishing device topology information during bus enumeration; A non-volatile storage medium, configured to store a mapping relationship between a physical location identifier and a logical device identifier received by the baseboard management controller; A pluggable backplane module, comprising a standardized slot structure corresponding to the physical location identifier, for carrying the PCIe device and providing hot-swap support; The baseboard management controller communicates with the firmware layer module through an out-of-band management protocol, and integrates a management interface independent of the operating system as the preset interface.

10. The server according to claim 9, wherein: The PCIe device includes a graphics processing unit, a network interface card, a memory card or a hardware acceleration card.

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