USB integrated circuit, test platform and operation method of USB integrated circuit

Abstract

The present invention provides a USB integrated circuit, a test platform, and an operating method for the USB integrated circuit. The USB integrated circuit includes a USB port physical layer circuit, a first channel adapter, a second channel adapter, a routing circuit, and a USB transport layer circuit. The USB port physical layer circuit is used to transmit differential signals between the USB integrated circuit and an external device. When the USB integrated circuit operates in a test mode, the routing circuit electrically connects the first channel adapter to the USB port physical layer circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second channel adapter to the USB port physical layer circuit. The USB transport layer circuit couples the first channel adapter and the second channel adapter.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to a Universal Serial Bus (USB) integrated circuit, a test platform, and an operating method of the USB integrated circuit. Background Art

[0002] USB is a standard for connecting computer systems and external devices. USB has multiple specifications based on transmission speed and connection method. For the USB4 V2 Gen4 specification, the signal is encoded using pulse-amplitude modulation (PAM).

[0003] On the other hand, during the development phase of electronic devices, electronic devices that implement the USB4 V2 Gen4 specification can be tested using programmable logic devices (PLDs). However, current PLDs support a limited range of transmission standards and are unable to test signals that comply with the USB4 V2 Gen4 specification.

[0004] It should be noted that the content in the "Prior Art" section is intended to assist in understanding the present invention. Some (or all) of the content disclosed in the "Prior Art" section may not be known to those skilled in the art. The content disclosed in the "Prior Art" section does not imply that such content was known to those skilled in the art prior to the filing of this application. Summary of the Invention

[0005] An embodiment of the present invention provides a USB integrated circuit capable of performing tests on a device under test that applies the USB4 V2 Gen4 specification.

[0006] A USB integrated circuit according to an embodiment of the present invention includes a first USB port physical layer circuit, a first channel adapter, a second channel adapter, a routing circuit, and a USB transport layer circuit. The first USB port physical layer circuit is used to transmit differential signals between the USB integrated circuit and an external device. The routing circuit couples the first USB port physical layer circuit, the first channel adapter, and the second channel adapter. When the USB integrated circuit operates in a test mode, the routing circuit electrically connects the first channel adapter to the first USB port physical layer circuit. When the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second channel adapter to the first USB port physical layer circuit. The USB transport layer circuit couples the first channel adapter and the second channel adapter.

[0007] An embodiment of the present invention also provides a test platform. The test platform is used to test a USB integrated circuit to be tested. The test platform includes a test machine and a USB integrated circuit. The test machine is used to generate a test pattern. The USB integrated circuit is coupled to the test machine to receive a first downstream signal that complies with the USB4 V2 specification. The first downstream signal includes a test pattern. The USB integrated circuit is also coupled to the USB integrated circuit to be tested to provide a second downstream signal that complies with the USB4 V1 specification. The test pattern generated by the test machine is transmitted to the USB integrated circuit to be tested through the USB integrated circuit. The USB integrated circuit includes a first USB port physical layer circuit, a first channel adapter, a routing circuit, and a USB transport layer circuit. The first USB port physical layer circuit is used to transmit a differential signal between the USB integrated circuit and the test machine. The routing circuit couples the first USB port physical layer circuit and the first channel adapter. When the USB integrated circuit operates in test mode, the routing circuit electrically connects the first channel adapter to the first USB port physical layer circuit. The USB transport layer circuit is coupled to the first channel adapter.

[0008] An embodiment of the present invention also provides an operating method for a USB integrated circuit. The operating method for the USB integrated circuit includes the following operations: transmitting a differential signal between the USB integrated circuit and an external device through a first USB port physical layer circuit of the USB integrated circuit; when the USB integrated circuit operates in a test mode, electrically connecting a first channel adapter of the USB integrated circuit to the first USB port physical layer circuit through a routing circuit of the USB integrated circuit, wherein the routing circuit couples the first USB port physical layer circuit and the first channel adapter, and the USB transport layer circuit of the USB integrated circuit couples the first channel adapter; and when the USB integrated circuit operates in a working mode, electrically connecting a second channel adapter of the USB integrated circuit to the first USB port physical layer circuit through the routing circuit, wherein the routing circuit and the USB transport layer circuit couple the second channel adapter.

[0009] Based on the above, the USB integrated circuit, test platform and USB integrated circuit operation method of the embodiments of the present invention can transmit application-specific data that complies with the USB4 V2 Gen4 specification through the USB port physical layer circuit and the channel adapter to perform tests on the USB integrated circuit under test.

[0010] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a circuit block diagram of a USB integrated circuit according to an embodiment of the present invention.

[0012] Figure 2 FIG. 4 is a flow chart of an operation method of a USB integrated circuit according to an embodiment of the present invention.

[0013] Figure 3 FIG. 4 is a circuit block diagram of a USB integrated circuit according to another embodiment of the present invention.

[0014] Figure 4 FIG. 4 is a circuit block of a USB integrated circuit according to another embodiment of the present invention.

[0015] Figure 5 FIG. 4 is a circuit block diagram of a test platform according to an embodiment of the present invention.

[0016] Figure 6 FIG. 4 is a schematic diagram of a transport layer packet according to an embodiment of the present invention.

[0017]

Explanation of symbols

[0018] 100, 300, 400_1~400_2, 500: USB integrated circuit

[0019] 110: USB port physical layer circuit

[0020] 120, 320: routing circuit

[0021] 131~132: Channel adapter

[0022] 140:USB transport layer circuit

[0023] 310, 410_1~410_2, 510: USB4 V2 port physical layer circuit

[0024] 321: Multiplexer

[0025] 322: Demultiplexer

[0026] 331-332, 431_1-431_2, 432_1-432_2, 531: USB4 V2 channel adapter

[0027] 330, 430_1~430_2, 530, 630: Data converter

[0028] 340, 540: USB4 V2 transport layer circuit

[0029] 351-352, 551-554: USB4 V1 channel adapter

[0030] 361-362, 561-564: USB4 V1 port physical layer circuit

[0031] 470, 570: test machine

[0032] 480, 580: USB integrated circuit under test

[0033] 50:Test platform

[0034] 611~614: USB4 V1 port physical layer circuit

[0035] 640: Programmable Logic Circuit

[0036] D1~D4: Electronic devices

[0037] HD: Header field

[0038] L1~L2: Line

[0039] PL: Payload field

[0040] S11~S12, S14, S21~S24, S31~S34: Differential signal

[0041] S210~S240: Steps

[0042] T00, T01, T02: ternary digital signal

[0043] TLP: Transport Layer Packet DETAILED DESCRIPTION

[0044] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Reference numerals will be used to identify identical or similar elements in different figures. These embodiments represent only a portion of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are merely examples within the scope of the present invention.

[0045] Figure 11 is a circuit block diagram of a USB integrated circuit according to an embodiment of the present invention. In some embodiments, the USB integrated circuit 100 can be used in the upstream-facing port (UFP) circuit of a USB hub to connect to a USB host. In other embodiments, the USB integrated circuit 100 can be used in the UFP circuit of a USB device to connect to a USB host or a USB hub. In other embodiments, the USB integrated circuit 100 can be used in the downstream-facing port (DFP) circuit of a USB host to connect to a USB device or a USB hub. In still other embodiments, the USB integrated circuit 100 can be used in the DFP circuit of a USB hub to connect to a USB device. Alternatively, in some embodiments, the USB integrated circuit 100 can be used in a test platform to perform tests in conjunction with a programmable logic device (PLD). In some embodiments, the USB integrated circuit 100 can also be used in other electronic devices to independently perform tests and / or other operations.

[0046] exist Figure 1 In the illustrated embodiment, the USB integrated circuit 100 includes a USB port physical layer circuit 110, a routing circuit 120, lane adapters 131 and 132, and a USB transport layer circuit 140. Routing circuit 120 is coupled to the USB port physical layer circuit 110. Routing circuit 120 is also coupled to lane adapters 131 and 132. Lane adapter 131 is coupled to one of the multiple transmission ports of the USB transport layer circuit 140. Lane adapter 132 is coupled to another of the multiple transmission ports of the USB transport layer circuit 140.

[0047] In this embodiment, the USB port physical layer circuit 110 is a port physical layer circuit that complies with the USB4 V2 specification. The USB4 V2 specification includes the USB4 V2 Gen2 specification, the USB4 V2 Gen3 specification, and the USB4 V2 Gen4 specification. In this embodiment, the USB port physical layer circuit 110 is suitable for coupling to an external device (not shown) via a USB connector. Figure 1 According to the actual design, the USB connector (not shown) Figure 1) can be a USB Type-C (also known as USB-C) connector. The USB port physical layer circuit 110 can be compatible with external devices that comply with other USB specifications prior to the USB4 V2 specification. Examples of these other USB specifications (hereinafter referred to as compatible USB specifications) include the USB4 V1 specification and the USB3 specification, including the USB3 Gen1 specification and the USB3 Gen2 specification.

[0048] In this embodiment, channel adapter 131 is a "Vendor Specific Adapter" that complies with the USB4 V2 specification. Channel adapter 131 processes application-specific data (ASD) between routing circuit 120 and USB transport layer circuit 140 to implement manufacturer-specific applications (e.g., testing). The ASD complies with the USB4 V2 specification or compatible USB specifications.

[0049] In this embodiment, the channel adapter 132 is a channel adapter that complies with the USB4 V2 specification. The channel adapter 132 can be a standard specification adapter to process data that complies with the USB4 V2 specification or a compatible USB specification between the routing circuit 120 and the USB transport layer circuit 140.

[0050] Figure 2 FIG. 4 is a flow chart of an operation method of a USB integrated circuit according to an embodiment of the present invention. Figure 2 The operation method shown is applicable to Figure 1 The USB integrated circuit 100 is shown. Figure 1 The various components of the embodiment are described in detail Figure 2 The operation method is shown. Figure 2 The instructions for the operation methods shown can also be applied by analogy to Figure 3 The USB integrated circuit 300 shown, Figure 4 The USB integrated circuits 400_1 to 400_2 are connected to (or connected to) Figure 5 A USB integrated circuit 500 in a test platform 50 is shown.

[0051] Please refer to Figure 1 and Figure 2 In step S210, the USB port physical layer circuit 110 can transmit data between the USB integrated circuit 100 and the external device (not shown). Figure 1). In this embodiment, the differential signals S11-S12 may be pulse-amplitude modulation (PAM) signals that comply with the USB4 V2 specification. In some embodiments, the differential signals S11-S12 comply with compatible USB specifications.

[0052] For example, differential signals S11 and S12 can be three-level PAM signals (i.e., PAM3 signals) that comply with the USB4 V2 specification. At each point in time, a PAM3 signal can exhibit any of three signal states. Compared to a non-return-to-zero (NRZ) signal, which has two level states (e.g., 0 or 1), the PAM3 differential signals S11 (S12) require 1.5 bits to represent the raw data at a single point in time.

[0053] In this embodiment, the USB port physical layer circuit 110 can convert the differential signal S11 into ternary digital signals T00, T01, T02, ... Specifically, the USB port physical layer circuit 110 can format the differential signal S11 to convert it from an analog signal (PAM3 signal) into a digital signal (ternary signal). The differential signal S12 can refer to the description of the differential signal S11 and be deduced accordingly, so it will not be repeated here.

[0054] In this embodiment, the USB integrated circuit 100 can selectively operate in a test mode or a working mode. Specifically, the routing circuit 120 is controlled by a processor (not shown) of the USB integrated circuit 100. Figure 1 ) to switch the operation mode of the USB integrated circuit 100.

[0055] When the USB integrated circuit 100 operates in the test mode (the determination result of step S220 is "test mode"), the USB integrated circuit 100 may proceed to step S230. In step S230, the routing circuit 120 may electrically connect the channel adapter 131 to the USB port physical layer circuit 110. At this time, the routing circuit 120 may transmit ternary digital signals T00, T01, T02, ... between the channel adapter 131 and the USB port physical layer circuit 110. In this embodiment, the USB integrated circuit 100 operating in the test mode may perform at least one function. For example, when the USB integrated circuit 100 operates in the test mode, a test machine (USB host or test mode determination device) connected to the USB integrated circuit 100 or the USB integrated circuit 100 may test a device under test coupled to the USB integrated circuit 100 to determine whether the function of the device under test is abnormal.

[0056] For example, in some embodiments, during an analog test in a test mode, the test mode determination device may determine whether the differential signal S11 or (AND) S12 of the device under test complies with a required transmission specification (e.g., the USB4 V2Gen4 specification) based on the differential signal S11 or (AND) S12 (e.g., a PAM3 signal) transmitted between the device under test and the USB port physical layer circuit 110. In some embodiments, during a logic test in a test mode, the test mode determination device may determine whether the device under test can operate normally based on the ternary digital signals T00, T01, T02, ... transmitted back from the device under test.

[0057] When the USB integrated circuit 100 is operating in the working mode (the result of step S220 is "working mode"), the USB integrated circuit 100 may proceed to step S240. In step S240, the routing circuit 120 may electrically connect the channel adapter 132 to the USB port physical layer circuit 110. At this time, the routing circuit 120 may transmit ternary digital signals T00, T01, T02, ... between the channel adapter 132 and the USB port physical layer circuit 110. In this embodiment, the USB integrated circuit 100 operating in the working mode may perform at least one function, and apply this at least one function to an electronic device coupled to the USB integrated circuit 100.

[0058] It is worth mentioning here that even if the device under test (such as a programmable logic device) coupled to the USB integrated circuit 100 does not support the transmission standard of the USB4 V2 Gen4 specification, the USB integrated circuit 100 can format the differential signal compliant with the USB4 V2 Gen4 specification into a ternary digital signal through the USB port physical layer circuit 110, and the USB integrated circuit 100 can transmit the formatted application-specific data compliant with the USB4 V2 Gen4 specification through the channel adapter 131 to perform testing.

[0059] Figure 3 FIG is a circuit block diagram of a USB integrated circuit according to another embodiment of the present invention. Figure 3 , in this embodiment, Figure 3 The USB integrated circuit 300 shown can refer to Figure 1 The related description of the USB integrated circuit 100 can be deduced by analogy.

[0060] Figure 3 The USB integrated circuit 300 with Figure 1The difference between the USB integrated circuit 100 and the USB integrated circuit 300 is that the USB integrated circuit 300 further includes USB4 V1 channel adapters 351-352 and USB4 V1 port physical layer circuits 361-362. On the other hand, in order to facilitate the description of the content of this application, Figure 1 The USB port physical layer circuit 110 is Figure 3 It is renamed as USB4 V2 port physical layer circuit 310, Figure 1 The channel adapters 131-132 are Figure 3 are renamed as USB4 V2 channel adapters 331 to 332, and Figure 1 The USB transport layer circuit 140 is Figure 3 It is renamed as USB4 V2 transport layer circuit 340.

[0061] In this embodiment, the routing circuit 320 of the USB integrated circuit 300 includes a multiplexer 321 and a demultiplexer 322. In this embodiment, an input end of the demultiplexer 322 is coupled to an output end of the USB4 V2 port physical layer circuit 310. A first output end of the demultiplexer 322 is coupled to an input end of a USB4 V2 channel adapter 331. A second output end of the demultiplexer 322 is coupled to an input end of the USB4 V2 channel adapter 332. In this embodiment, an output end of the multiplexer 321 is coupled to an input end of the USB4 V2 port physical layer circuit 310. A first input end of the multiplexer 321 is coupled to an output end of the USB4 V2 channel adapter 331. A second input end of the multiplexer 321 is coupled to an output end of the USB4 V2 channel adapter 332.

[0062] In this embodiment, when the USB integrated circuit 300 operates in the test mode, the demultiplexer 322 is controlled by the processor (not shown) of the USB integrated circuit 300. Figure 3 ) to couple the output of the USB4 V2 port physical layer circuit 310 to the input of the USB4 V2 channel adapter 331. On the other hand, when the USB integrated circuit 300 operates in the test mode, the multiplexer 321 is also controlled by the processor to couple the input of the USB4 V2 port physical layer circuit 310 to the output of the USB4 V2 channel adapter 331. It should be noted that when the USB integrated circuit 300 operates in the test mode, the demultiplexer 322 and the multiplexer 321 can selectively electrically connect the USB4 V2 port physical layer circuit 310 to the USB4 V2 channel adapter 331 to transmit application-specific data for testing.

[0063] In this embodiment, when the USB integrated circuit 300 operates in the working mode, the demultiplexer 322 is controlled by the processor of the USB integrated circuit 300 to couple the output of the USB4 V2 port physical layer circuit 310 to the input of the USB4 V2 channel adapter 332. On the other hand, when the USB integrated circuit 300 operates in the working mode, the multiplexer 321 is also controlled by the processor to couple the input of the USB4 V2 port physical layer circuit 310 to the output of the USB4 V2 channel adapter 332. It should be noted that when the USB integrated circuit 300 operates in the working mode, the demultiplexer 322 and the multiplexer 321 can selectively electrically connect the USB4 V2 port physical layer circuit 310 to the USB4 V2 channel adapter 332 to transmit working data.

[0064] In this embodiment, the USB4 V2 transport layer circuit 340 is coupled between the USB4 V2 channel adapters 331-332 and the USB4 V1 channel adapters 351-352. Specifically, a first input terminal of the USB4 V2 transport layer circuit 340 is coupled to the output terminal of the USB4 V2 channel adapter 331. A second input terminal of the USB4 V2 transport layer circuit 340 is coupled to the output terminal of the USB4 V2 channel adapter 332. Furthermore, a first output terminal of the USB4 V2 transport layer circuit 340 is coupled to the input terminal of the USB4 V1 channel adapter 351. A second output terminal of the USB4 V2 transport layer circuit 340 is coupled to the input terminal of the USB4 V1 channel adapter 352.

[0065] In this embodiment, when the USB integrated circuit 300 operates in the test mode, the USB4 V2 transport layer circuit 340 is controlled by the processor of the USB integrated circuit 300 to couple the USB4 V2 channel adapter 331 to the USB4 V1 channel adapter 351 or 352. In this embodiment, when the USB integrated circuit 300 operates in the working mode, the USB4 V2 transport layer circuit 340 is controlled by the processor to couple the USB4 V2 channel adapter 332 to the USB4 V1 channel adapter 351 or 352.

[0066] In this embodiment, the USB4 V1 channel adapters 351-352 are further coupled one-to-one to the USB4 V1 port physical layer circuits 361-362. Specifically, the output of the USB4 V1 channel adapter 351 is coupled to the input of the USB4 V1 port physical layer circuit 361. The output of the USB4 V1 channel adapter 352 is coupled to the input of the USB4 V1 port physical layer circuit 362.

[0067] In this embodiment, USB4 V1 channel adapter 351 is a channel adapter that complies with the USB4 V1 specification. In this embodiment, USB4 V1 channel adapter 351 may be a standard adapter to process data that complies with the USB4 V1 specification between USB4 V1 channel adapter 351 and USB4 V2 transport layer circuit 340. The description of USB4 V1 channel adapter 352 can be similar to that of USB4 V1 channel adapter 351 and will not be repeated here.

[0068] In this embodiment, the USB integrated circuit 300 can also transmit data between the USB integrated circuit 300 and another external device (not shown) through the USB4 V1 port physical layer circuits 361-362. Figure 3 ). In this embodiment, the USB4 V1 port physical layer circuit 361 can be compatible with another external device that complies with a standard that predates the USB4 V1 standard (e.g., the USB3 standard). In this embodiment, the differential signals S21-S22 comply with the USB4 V1 standard. In some embodiments, the differential signals S21-S22 comply with the compatible USB3 standard. The USB4 V1 port physical layer circuit 362 can refer to the relevant description of the USB4 V1 port physical layer circuit 361 and be deduced by analogy, so it will not be repeated here.

[0069] In this embodiment, the USB4 V2 channel adapters 331 - 332 , the USB4 V2 transport layer circuit 340 , and the USB4 V1 channel adapters 351 - 352 may be integrated into a data converter 330 .

[0070] As shown in the various embodiments described above, when the USB integrated circuit 300 operates in test mode, the data converter 330 can process application-specific data compliant with the USB4 V2 specification via the USB4 V2 channel adapter 331 and distribute this application-specific data to the USB4 V1 channel adapter 351 or 352 via the USB4 V2 transport layer circuit 340. Assuming that the USB4 V1 channel adapter 351 is selected, the data converter 330 can convert this application-specific data into application-specific data compliant with the USB4 V1 specification via the USB4 V1 channel adapter 351 for transmission to the USB4 V1 port physical layer circuit 361. The data converter 330 can also operate in the reverse direction, converting application-specific data compliant with the USB4 V1 specification into application-specific data compliant with the USB4 V2 specification, as described above and by analogy, and thus will not be repeated here.

[0071] On the other hand, as shown in the various embodiments described above, when the USB integrated circuit 300 operates in the working mode, the data converter 330 can also convert data between the USB4 V2 specification and the USB4 V1 specification through the USB4 V2 channel adapter 332 and the above-mentioned related components. The above description of the data converter 330 and the USB4 V2 channel adapter 332 can be referred to and deduced by analogy, and thus will not be repeated here.

[0072] Figure 4 FIG is a circuit block of a USB integrated circuit according to another embodiment of the present invention. Figure 4 In this embodiment, the USB integrated circuits 400_1 and 400_2 are coupled to each other and have the same circuit configuration. Figure 4 The USB integrated circuit 400_1 or (and) 400_2 shown can refer to Figure 1 The USB integrated circuit 100 and Figure 3 The relevant description of the USB integrated circuit 300 shown in FIG. Figure 4 Some components and / or component numbers of the USB integrated circuits 400_1 ˜ 400_2 are omitted.

[0073] Figure 4 The USB integrated circuit 400_1 and Figure 3 The difference between the USB integrated circuit 300 and the USB integrated circuit 400_1 is that when the USB integrated circuit 400_1 operates in test mode, because only the USB4 V2 channel adapter 431_1 is enabled and the USB4 V2 channel adapter 432_1 is disabled, the USB integrated circuit 400_1 can transmit a pair of differential signals S11 between the USB integrated circuit 400_1 and the external device (i.e., the test machine 470) via the USB4 V2 port physical layer circuit 410_1, but not the other pair of differential signals S12. The USB integrated circuit 400_2 transmits another pair of differential signals S14 between the USB integrated circuit 400_1 and the test machine 470 via the USB4 V2 port physical layer circuit 410_2.

[0074] In this embodiment, when the USB integrated circuit 400_1 operates in the test mode, the USB4 V2 channel adapter 431_1 of the USB integrated circuit 400_1 is coupled to the USB4 V2 channel adapter 431_2 of the USB integrated circuit 400_2, and both are controlled by the processors (not shown) in the respective USB integrated circuits 400_1 and 400_2. Figure 4 ) to operate synchronously, such as Figure 3 The relevant description of the USB4 V2 channel adapter 331 has been given, so it will not be repeated here.

[0075] It should be noted that when USB integrated circuit 400_1 operates in test mode, USB integrated circuit 400_1 can process differential signal S11 between USB integrated circuit 400_1 and test equipment 470 via USB4 V2 port physical layer circuit 410_1, and USB integrated circuit 400_2 can also process differential signal S14 between USB integrated circuit 400_2 and test equipment 470 via USB4 V2 port physical layer circuit 410_2. On the other hand, when USB integrated circuit 400_1 operates in test mode, USB integrated circuit 400_1 can process formatted differential signal S11 via USB4 V2 channel adapter 431_1 of data converter 430_1, and USB integrated circuit 400_2 can also simultaneously process formatted differential signal S14 via USB4 V2 channel adapter 431_2 of data converter 430_2.

[0076] As a result, in the test mode, even if only one transmission channel is enabled between the data converter 430_1 and the USB4 V2 port physical layer circuit 410_1, by synchronously operating the two USB4 V2 channel adapters 431_1-431_2, the USB integrated circuits 400_1-400_2 can transmit four differential signals S21-S24 compliant with the USB4 V1 specification between the USB integrated circuits 400_1-400_2 and another external device (i.e., the USB integrated circuit under test 480).

[0077] Figure 5 FIG is a circuit block diagram of a test platform according to an embodiment of the present invention. Figure 5 In this embodiment, the test platform 50 includes a test machine 570 and a USB integrated circuit 500, and the test platform 50 is capable of testing a USB integrated circuit under test 580. In this embodiment, the test machine 570 may be a USB host. The test machine 570 may generate at least one test pattern. The test pattern may be a hardware description language (HDL). The test pattern may describe the function of a logic circuit, so that the USB integrated circuit under test 580 performs specific operations according to the test pattern to test whether the corresponding function of the USB integrated circuit under test 580 has malfunctioned.

[0078] In this embodiment, a USB integrated circuit 500 is coupled between a test machine 570 and a USB integrated circuit under test 580. Specifically, an input terminal of the USB integrated circuit 500 is coupled to the test machine 570 to receive downstream signals S11-S12. In this embodiment, downstream signals S11 and / or S12 may be differential signals compliant with the USB4 V2 specification (e.g., PAM3 signals compliant with the USB4 V2 Gen4 specification) and include test patterns. On the other hand, an output terminal of the USB integrated circuit 500 is coupled to the USB integrated circuit under test 580 to provide downstream signals S21-S24. In this embodiment, downstream signals S21, S22, S23, and / or S24 may be differential signals compliant with the USB4 V1 specification (e.g., ternary signals compliant with the USB4 V1 specification) and include test patterns. Therefore, the test patterns generated by the test machine 570 are transmitted to the USB integrated circuit under test 580 via the USB integrated circuit 500.

[0079] In this embodiment, Figure 5 The USB integrated circuit 500 shown can refer to Figure 1 The USB integrated circuit 100 shown, Figure 3 The USB integrated circuit 300 and Figure 4 The relevant description of the USB integrated circuit 400_1 to 400_2 shown in FIG. Figure 5 Some components and / or component numbers of the USB integrated circuit 500 are omitted (for example, the routing circuit is not shown). Figure 5 ).

[0080] Figure 5 The USB integrated circuit 500 with Figure 3 The difference between the USB integrated circuit 500 and the USB integrated circuit 300 is that the USB integrated circuit 500 further includes USB4 V1 channel adapters 553-554 and USB4 V1 port physical layer circuits 563-564, which add two additional channels to transmit two additional downstream signals S23-S24 between the USB integrated circuit 500 and another external device (i.e., the USB integrated circuit under test 580). The USB4 V1 channel adapters 553-554 can refer to the relevant description of the USB4 V1 channel adapter 351 and can be deduced by analogy, so they are not repeated here. The USB4 V1 port physical layer circuits 563-564 can refer to the relevant description of the USB4 V1 port physical layer circuit 361 and can be deduced by analogy, so they are not repeated here.

[0081] It should be noted that in this embodiment, the USB integrated circuit 500 may be a test-specific integrated circuit, and thus the USB integrated circuit 500 may only include the USB4 V2 channel adapter 531 and ignore the standard adapter that complies with the USB4 V2 specification (e.g., Figure 3 channel adapter 332).

[0082] In this embodiment, the data converter 530 can encapsulate the ternary digital signals T00, T01, T02, ... to reduce the delay of the ternary digital signals T00, T01, T02, ... in transmission within the USB integrated circuit 500 and (and) between the USB integrated circuit 500 and the USB integrated circuit under test 580.

[0083] Specifically, please refer to Figure 6 . Figure 6 is a schematic diagram of a transport layer packet according to an embodiment of the present invention. In this embodiment, the channel adapter 531 encapsulates the ternary digital signals T00, T01, T02, ... into multiple transport layer packets (Transport Layer Package) TLPs that correspond one-to-one to the USB4 V1 channel adapters 551-554. In this embodiment, the header field (Header) of each transport layer packet TLP includes batch information to indicate the address of the corresponding USB4V1 channel adapter 551-554. The payload field (Payload) of each transport layer packet TLP includes multiple columns to carry the corresponding data.

[0084] For example, the channel adapter 531 sequentially fills the first column of the columns of each transport layer packet TLP with the ternary digital signals t0-t384. After the first column is filled, the channel adapter 531 sequentially fills the second column of the columns of each transport layer packet TLP with the ternary digital signals t512-t896, and so on.

[0085] In this embodiment, the channel adapter 531 transmits these encapsulated transport layer packets TLPs to the USB4 V2 transport layer circuit 540. The USB4 V2 transport layer circuit 540 transmits each transport layer packet TLP to the corresponding USB4 V1 channel adapters 551-554 based on the header field of each transport layer packet TLP. It should be noted that in this embodiment, the USB4 V2 transport layer circuit 540 can align transport layer packets TLPs with the same header field and transmit each of these transport layer packets TLPs simultaneously and one-to-one to the USB4 V1 channel adapters 551-554. The channel adapters 131, 331, 431_1, and / or 431_2 of the various embodiments described above can also implement the content of this embodiment, so they will not be repeated here.

[0086] In this embodiment, the USB integrated circuit 580 under test can be a programmable logic device, such as a field programmable gate array (FPGA). In this embodiment, the USB integrated circuit 580 under test includes USB4 V1 port physical layer circuits 611-614, a data converter 630, and a programmable logic circuit 640.

[0087] In this embodiment, the input end of the USB4 V1 port physical layer circuit 611 is coupled to the output end of the USB4 V1 port physical layer circuit 561. The output end of the USB4 V1 port physical layer circuit 611 is coupled to one of the multiple input ends of the data converter 630. In this embodiment, the USB4 V1 port physical layer circuit 611 is a port physical layer circuit that complies with the USB4 V1 specification. In this embodiment, the USB integrated circuit 580 under test can transmit the downstream signal S21 between the USB integrated circuit 580 under test and the USB integrated circuit 500 through the USB4 V1 port physical layer circuit 611. The USB4 V1 port physical layer circuit 611 can also transmit the downstream signal S21 to the data converter 630. The USB4 V1 port physical layer circuits 612 to 614 can refer to the relevant description of the USB4 V1 port physical layer circuit 611 and be deduced by analogy, so they will not be repeated here.

[0088] In this embodiment, the data converter 630 is further coupled to the programmable logic circuit 640. The data converter 630 can decapsulate (restore) the ternary digital signals T00, T01, T02, ... that have been encapsulated into transport layer packets TLP, and transmit the decapsulated ternary digital signals T00, T01, T02, ... to the programmable logic circuit 640. The data converter 630 and the data converter 530 perform the reverse operation, and the above description of the data converter 530 can be referred to and analogized, so the description is not repeated here.

[0089] It should be noted that if Figure 5 As shown in the transmission path between lines L1 and L2, the test platform 50 can transmit ternary digital signals T00, T01, T02, ... between the USB4V2 port physical layer circuit 510 and the programmable logic circuit 640.

[0090] In this embodiment, the programmable logic circuit 640 is further coupled to a plurality of electronic devices D1-D4. These electronic devices D1-D4 may be, for example, a USB4 device D1 compliant with the USB4 V1 specification and / or the USB4 V2 specification, a USB3 device D2 compliant with the USB3 specification, a PCI Express (PCIe) device D3 compliant with the PCIe specification, and a DisplayPort (DP) device D4 compliant with the DisplayPort (DP) specification. The number of electronic devices D1-D4 and the transmission specifications in this embodiment are merely examples and are not intended to be limiting.

[0091] In this embodiment, the USB integrated circuit under test 580 can perform required testing operations based on the ternary digital signals T00, T01, T02, ... via the programmable logic circuit 640. Therefore, the USB integrated circuit under test 580 can transmit differential signals S31-S34 that comply with different transmission standards between the programmable logic circuit 640 and the aforementioned electronic devices D1-D4. Furthermore, the USB integrated circuit under test 580 can also transmit the tested ternary digital signals T00, T01, T02, ... back to the test machine 570 via the USB integrated circuit 500.

[0092] It should be noted that in this embodiment, when the USB integrated circuit 500 is operating in a test mode (e.g., analog testing), the test machine 570 can determine whether an analog function of the USB integrated circuit 580 under test has malfunctioned based on the differential signals S21-S24 (e.g., PAM3 signals or encoded signals compliant with other transmission standards) transmitted between the USB integrated circuit 580 under test and the electronic devices D1-D4. Furthermore, when the USB integrated circuit 500 is operating in a test mode (e.g., logic testing), the test machine 570 can also determine whether a logical function of the USB integrated circuit 580 under test has malfunctioned based on the ternary digital signals T00, T01, T02, ... transmitted back from the USB integrated circuit 580 under test.

[0093] In summary, the USB integrated circuit, test platform, and USB integrated circuit operating method according to embodiments of the present invention can transmit application-specific data compliant with the USB4 V2 Gen4 specification through a USB port physical layer circuit and a channel adapter to test the USB integrated circuit under test. In some embodiments, the USB integrated circuit, test platform, and USB integrated circuit operating method can also encapsulate ternary digital signals into multiple transport layer packets to reduce signal transmission delay.

[0094] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A USB integrated circuit, comprising: A first USB port physical layer circuit for transmitting differential signals between the USB integrated circuit and an external device; First channel adapter; Second channel adapter; a routing circuit coupled to the first USB port physical layer circuit, the first channel adapter, and the second channel adapter, wherein when the USB integrated circuit operates in a test mode, the routing circuit electrically connects the first channel adapter to the first USB port physical layer circuit, and when the USB integrated circuit operates in a working mode, the routing circuit electrically connects the second channel adapter to the first USB port physical layer circuit; as well as A USB transport layer circuit is coupled to the first channel adapter and the second channel adapter. The first channel adapter is a vendor-specific adapter that complies with the USB4 V2 specification, and the second channel adapter is a channel adapter that complies with the USB4 V2 specification. The differential signal includes a pulse amplitude modulation signal with three level states, and the first USB port physical layer circuit is used for converting the differential signal into a ternary digital signal.

2. The USB integrated circuit of claim 1 , further comprising: a plurality of third channel adapters coupled to the USB transport layer circuit; as well as A plurality of second USB port physical layer circuits are coupled to the third channel adapters in a one-to-one manner. 3 . The USB integrated circuit of claim 1 , wherein when the USB integrated circuit operates in the test mode, the second channel adapter is disabled, and the first channel adapter is coupled to the third channel adapter to operate synchronously with the third channel adapter.

4. The USB integrated circuit of claim 1 , further comprising: A plurality of third-channel adapters are coupled to the USB transport layer circuit, wherein the first USB port physical layer circuit is used to convert a plurality of differential signals between the USB integrated circuit and the external device into a plurality of ternary digital signals, the first-channel adapter encapsulates these ternary digital signals into a plurality of transport layer packets corresponding one-to-one to the third-channel adapters, and the USB transport layer circuit transmits each of these transport layer packets to a corresponding one of the third-channel adapters.

5. The USB integrated circuit of claim 4 , wherein the header fields of the transport layer packets include batch information, the payload field of each of the transport layer packets includes a plurality of columns, the first channel adapter sequentially fills the ternary digital signals into a first column of the columns of each of the transport layer packets, and after the first columns are filled, the first channel adapter sequentially fills the ternary digital signals into a second column of the columns of each of the transport layer packets.

6. The USB integrated circuit of claim 1 , wherein the routing circuit comprises: a demultiplexer having an input coupled to an output of the first USB port physical layer circuit, wherein the first output of the demultiplexer is coupled to the input of the first channel adapter, and the second output of the demultiplexer is coupled to the input of the second channel adapter. When the USB integrated circuit operates in the test mode, the demultiplexer couples the output of the first USB port physical layer circuit to the input of the first channel adapter, and when the USB integrated circuit operates in the working mode, the demultiplexer couples the output of the first USB port physical layer circuit to the input of the second channel adapter. as well as A multiplexer having an output end coupled to the input end of the first USB port physical layer circuit, wherein the first input end of the multiplexer is coupled to the output end of the first channel adapter, and the second input end of the multiplexer is coupled to the output end of the second channel adapter. When the USB integrated circuit operates in the test mode, the multiplexer couples the input end of the first USB port physical layer circuit to the output end of the first channel adapter, and when the USB integrated circuit operates in the working mode, the multiplexer couples the input end of the first USB port physical layer circuit to the output end of the second channel adapter.

7. A test platform for testing a USB integrated circuit to be tested, the test platform comprising: A test machine for generating at least one test pattern; as well as A USB integrated circuit is coupled to the test machine to receive a first downstream signal that complies with the USB4 V2 specification, wherein the first downstream signal includes the test pattern. The USB integrated circuit is further coupled to the USB integrated circuit under test to provide a second downstream signal that complies with the USB4 V1 specification. The test pattern generated by the test machine is transmitted to the USB integrated circuit under test via the USB integrated circuit. The USB integrated circuit includes: A first USB port physical layer circuit is used to transmit a differential signal between the USB integrated circuit and the test machine; First channel adapter; a routing circuit coupled to the first USB port physical layer circuit and the first channel adapter, wherein when the USB integrated circuit operates in a test mode, the routing circuit electrically connects the first channel adapter to the first USB port physical layer circuit; and A USB transport layer circuit is coupled to the first channel adapter. The first channel adapter is a manufacturer-specific adapter that complies with the USB4 V2 specification. The differential signal includes a pulse amplitude modulation signal with three level states, and the first USB port physical layer circuit is used for converting the differential signal into a ternary digital signal.

8. The test platform as claimed in claim 7, wherein the USB integrated circuit further comprises: a plurality of third channel adapters coupled to the USB transport layer circuit; as well as A plurality of second USB port physical layer circuits are coupled to the third channel adapters in a one-to-one manner. 9 . The test platform as claimed in claim 8 , wherein the second USB port physical layer circuits are used to couple to the USB integrated circuit under test. 10 . The test platform as claimed in claim 7 , wherein the first USB port physical layer circuit is used to couple to the test machine.

11. The test platform of claim 7 , wherein the USB integrated circuit further comprises a plurality of third channel adapters coupled to the USB transport layer circuit, the first USB port physical layer circuit being configured to convert a plurality of differential signals between the USB integrated circuit and the test equipment into a plurality of ternary digital signals, the first channel adapter encapsulating the ternary digital signals into a plurality of transport layer packets corresponding one-to-one to the third channel adapters, and the USB transport layer circuit transmitting each of the transport layer packets to a corresponding one of the third channel adapters.

12. The test platform of claim 11 , wherein the header fields of the transport layer packets include batch information, the payload field of each of the transport layer packets includes a plurality of columns, the first channel adapter sequentially fills the ternary digital signals into a first column of the columns of each of the transport layer packets, and after the first columns are filled, the first channel adapter sequentially fills the ternary digital signals into a second column of the columns of each of the transport layer packets.

13. A method for operating a USB integrated circuit, comprising: transmitting a differential signal between the USB integrated circuit and an external device through a first USB port physical layer circuit of the USB integrated circuit; When the USB integrated circuit operates in a test mode, a first channel adapter of the USB integrated circuit is electrically connected to the first USB port physical layer circuit via a routing circuit of the USB integrated circuit, wherein the routing circuit couples the first USB port physical layer circuit and the first channel adapter, and a USB transport layer circuit of the USB integrated circuit is coupled to the first channel adapter; as well as When the USB integrated circuit operates in a working mode, the second channel adapter of the USB integrated circuit is electrically connected to the first USB port physical layer circuit through the routing circuit, wherein the routing circuit and the USB transport layer circuit are coupled to the second channel adapter. The first channel adapter is a vendor specific adapter that complies with the USB4 V2 specification, and the second channel adapter is a channel adapter that complies with the USB4 V2 specification. The differential signal includes a pulse amplitude modulation signal having three level states, and the operating method further includes: The differential signal is converted into a ternary digital signal by the first USB port physical layer circuit.

14. The operating method of claim 13 , wherein the USB integrated circuit further comprises a plurality of third channel adapters, the third channel adapters being coupled to the USB transport layer circuit, and the operating method further comprises: The first USB port physical layer circuit converts a plurality of differential signals between the USB integrated circuit and the external device into a plurality of ternary digital signals; Encapsulating the ternary digital signals into a plurality of transport layer packets corresponding one-to-one to the third channel adapters through the first channel adapter; as well as Each of the transport layer packets is transmitted by the USB transport layer circuit to a corresponding one of the third channel adapters.

15. The operating method of claim 14 , wherein the header field of the transport layer packets includes batch information, the payload field of each of the transport layer packets includes a plurality of columns, and the operating method further comprises: The first channel adapter sequentially fills the ternary digital signals into the first column of the columns of each of the transport layer packets; as well as After the first columns are filled, the first channel adapter sequentially fills the ternary digital signals into the second column of each of the columns of the transport layer packets.

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