A multi-mode fast switching processing board, processing system and processing method

Abstract

The present invention discloses a multi-mode fast switching processing board, a processing system and a processing method; the multi-mode fast switching processing board is provided with an FPGA chip and a PCIe bus connection port, a plurality of pins of the FPGA chip are directly and electrically connected to a plurality of wiring terminals of the PCIe bus connection port, and the PCIe bus connection port is used to connect to a host computer; the FPGA chip has a built-in PCIe bus IP core, and a PCIe drive connection can be established with the host computer in real time by configuring the PCIe bus IP core; the present invention establishes a PCIe drive connection with the host computer in real time through the PCIe bus IP core, directly and electrically connects a plurality of pins of the FPGA chip with the PCIe bus connection port, eliminates the use of an MCU controller and a PCI / PCIe driver chip, simplifies the hardware design, reduces the use of hardware, and greatly reduces the cost.

Description

Technical Field

[0001] The present invention relates to the field of satellite measurement and control technology, and in particular to a multi-mode fast switching processing board, a processing system and a processing method. Background Art

[0002] With the continuous development of aerospace and satellite technology, satellite measurement and control has also experienced a variety of systems and modes such as S-band unified carrier measurement and control (USB), spread spectrum non-coherent measurement and control, integrated measurement and control data transmission, and frequency hopping measurement and control. The onboard transponder and the corresponding measurement and control ground inspection equipment are also developing in the direction of multi-mode.

[0003] The existing satellite measurement and control ground inspection equipment based on CPCI / VPX / PXI bus generally includes a chassis, a host computer, a baseband processing board, up and down converters, etc. Figure 1 As shown, the host computer X1 exchanges data with the baseband processing board X2 through the CPCI / VPX / PXI bus X3. The baseband processing board X2 usually has a PCI / PCIe driver chip X21, an FPGA chip X22, and an MCU / DSP controller X23. The FPGA chip X22 can load different bit files to switch different ground detection modes. This method includes an MCU controller and a PCI / PCIe driver chip, etc., and the hardware structure is complex and the cost is also high. Summary of the Invention

[0004] The main technical problem solved by the present invention is to provide a multi-mode fast switching processing board to solve the problems of complex hardware structure and high cost in mode switching.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a multi-mode fast switching processing board, including: an FPGA chip and a PCIe bus connection port are arranged on the multi-mode fast switching processing board, multiple pins of the FPGA chip are directly electrically connected to multiple wiring terminals of the PCIe bus connection port, and the PCIe bus connection port is used to connect to a host computer; the FPGA chip has a built-in PCIe bus IP core, and by configuring the PCIe bus IP core, a PCIe driver connection can be established with the host computer in real time.

[0006] Preferably, a storage chip is also provided on the multi-mode fast switching processing board, the storage chip is electrically connected to the FPGA chip, and a plurality of project files are stored on the storage chip; the project file corresponds to the working mode on the host computer, and when the working mode is switched, the host computer disables the driver of the FPGA chip and controls the FPGA chip to load the corresponding project file through the PCIe bus connection port; after the loading of the project file is completed, the host computer enables the driver of the FPGA chip and re-establishes the communication interaction between the FPGA chip and the host computer.

[0007] Preferably, the storage space of the memory chip includes a plurality of sub-intervals, each of the sub-intervals corresponds to one of the project files, and the project file includes a first address, and the first address corresponds to the physical address of the sub-interval.

[0008] Preferably, the multi-mode fast switching processing board is electrically connected to the host computer via a PCIe bus.

[0009] Preferably, the storage chip is electrically connected to the FPGA chip via an SPI connection line.

[0010] Preferably, switching software and a driver are provided in the host computer. The switching software can select the working mode, query the current mode, determine whether the project file of the selected working mode corresponds to the currently loaded project file, enable and disable the driver, and the driver is used to establish a connection between the host computer and the FPGA chip.

[0011] Preferably, the FPGA chip is provided with an XDMA IP CORE configuration module, an AXI4 protocol conversion module, an ICAP control module and an ICAP IP configuration module; the XDMAIP CORE configuration module is connected to the AXI4 protocol conversion module, the AXI4 protocol conversion module is connected to the ICAP control module, and the ICAP control module is connected to the ICAP IP configuration module.

[0012] Preferably, a clock module for frequency division is provided in the FPGA chip, and the clock module is connected to the AXI4 protocol conversion module.

[0013] The present invention also provides a multi-mode fast switching processing system, comprising:

[0014] A host computer, and switching software and a driver program provided within the host computer; the switching software being capable of selecting an operating mode, querying a current mode, determining whether a project file for the selected operating mode corresponds to a currently loaded project file, and enabling and disabling a driver program, the driver program being used to establish a connection between the host computer and the FPGA chip;

[0015] FPGA chip, and an XDMA IP CORE configuration module, AXI4 protocol conversion module, ICAP control module and ICAP IP configuration module provided in the FPGA chip; the XDMA IP CORE configuration module is connected to the AXI4 protocol conversion module, the AXI4 protocol conversion module is connected to the ICAP control module, and the ICAP control module is connected to the ICAP IP configuration module;

[0016] A memory chip, and a plurality of project files stored in the memory chip; the project files correspond to the working modes on the host computer; the host computer controls the FPGA chip to load the corresponding project files;

[0017] PCIe bus, used to electrically connect the host computer and the FPGA chip;

[0018] The SPI connection line is used to electrically connect the FPGA chip and the memory chip.

[0019] The present invention also provides a multi-mode fast switching processing method, comprising the steps of:

[0020] Establish a PCIe bus connection between the FPGA chip on the multi-mode fast switching processing board and the host computer;

[0021] Selecting a working mode on the host computer and querying the project file currently loaded on the FPGA chip;

[0022] Determine whether the currently loaded project file corresponds to the project file of the selected working mode. If so, the selected working mode is enabled on the host computer. If not, the FPGA chip loads the project file corresponding to the working mode from the storage chip electrically connected thereto. After the project file corresponding to the working mode is loaded, reload the driver of the FPGA chip. Determine again whether the currently loaded project file corresponds to the project file of the selected working mode.

[0023] The beneficial effects of the present invention are as follows: the present invention establishes a PCIe driver connection with the host computer in real time through the PCIe bus IP core, directly and electrically connects multiple pins of the FPGA chip to the PCIe bus connection port, eliminates the use of the MCU controller and the PCI / PCIe driver chip, simplifies the hardware design, reduces the use of hardware, and greatly reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the connection method between FPGA chip and host computer in the existing technology;

[0025] Figure 2 This is a schematic diagram of the hardware connection structure of an embodiment of a multi-mode fast switching processing board according to the present invention;

[0026] Figure 3 This is a schematic diagram of software control connections for a multi-mode fast switching processing board according to an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of software settings of an embodiment of a multi-mode fast switching processing board according to the present invention;

[0028] Figure 5 is a flow chart of an embodiment of a multi-mode fast switching processing system according to the present invention;

[0029] Figure 6 FIG. 1 is a flow chart of an embodiment of a multi-mode fast switching processing method according to the present invention. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present invention.

[0031] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification are intended solely for the purpose of describing specific embodiments and are not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0032] Figure 2An embodiment of a multi-mode fast switching processing board 1 of the present invention is shown, comprising: an FPGA chip 11 and a PCIe bus connection port 12 are provided on the multi-mode fast switching processing board 1, multiple pins of the FPGA chip 11 are directly electrically connected to multiple terminals of the PCIe bus connection port 12, and the PCIe bus connection port 12 is used to connect to a host computer 3; the FPGA chip 11 has a built-in PCIe bus IP core 111, and by configuring the PCIe bus IP core 111, a PCIe driver connection can be established with the host computer 3 in real time.

[0033] The present invention establishes a PCIe driver connection with the host computer 3 in real time through the PCIe bus IP core 111, directly and electrically connects multiple pins of the FPGA chip 11 with the PCIe bus connection port 12, eliminates the use of the MCU controller and PCI / PCIe driver chip, simplifies the hardware design, reduces the use of hardware, and greatly reduces costs.

[0034] Preferably, the multi-mode fast switching processing board 1 is electrically connected to the host computer 3 via a PCIe bus 2. The PCIe bus 2 enables data exchange between the host computer 3 and the FPGA chip 11.

[0035] When the MCU controller and PCI / PCIe driver chip are removed, there is a problem of cumbersome driving control of the FPGA chip 11. When the working mode is switched, the operating system of the host computer 3 needs to be restarted to re-establish the communication interaction between the FPGA chip 11 and the host computer 3. This method is inefficient and affects the normal use of the host computer 3.

[0036] Preferably, a storage chip 13 is also provided on the multi-mode fast switching processing board 1, and the storage chip 13 is electrically connected to the FPGA chip 11, and multiple project files 1301 are stored on the storage chip 13; the project file 1301 corresponds to the working mode on the host computer 3. When the working mode needs to be switched, the host computer 3 disables the driver 302 of the FPGA chip 11 and controls the FPGA chip 11 through the PCIe bus connection port 12 to load the corresponding project file 1301; after the loading of the project file 1301 is completed, the host computer 3 enables the driver 302 of the PCIe bus IP core 111 in the FPGA chip 11 to establish communication interaction between the FPGA chip 11 and the host computer 3. This is because, when a new project file is loaded, the hardware circuit structure of the FPGA chip is changed. The PCIe bus interface state corresponding to the original circuit cannot be applied to the PCIe bus interface state corresponding to the newly loaded circuit. Therefore, it is necessary to clear the PCIe bus interface state corresponding to the original circuit and reset the initial state of the PCIe bus interface. Here, only the host computer 3 needs to re-enable the driver for the PCIe bus IP core once, so that the newly loaded circuit inside the FPGA chip corresponding to the currently loaded project file is aligned with the initial state of the PCIe bus IP core. Then, the host computer can normally access the newly loaded circuit inside the FPGA chip through the PCIe bus IP core. This method does not require the host computer to restart, but only requires re-enabling the driver for the PCIe bus IP core once when switching and loading the running project file, thereby improving the work efficiency between loading the project file and directly using it.

[0037] A plurality of project files 1301 are stored in the memory chip 13; the project files 1301 correspond to the working modes on the host computer 3, and the working modes include S-band unified carrier measurement and control (USB), spread spectrum non-coherent measurement and control, measurement and control data transmission integration, frequency hopping measurement and control, etc. The project files 1301 correspond to the above working modes. After selecting a working mode on the host computer 3, the host computer 3 controls the FPGA chip 11 through the PCIe bus connection port 12 to load the corresponding project file 1301. After the project file 1301 is loaded, the host computer 3 enables the driver 302 of the FPGA chip 11 and re-establishes the communication interaction between the FPGA chip 11 and the host computer 3. In this way, there is no need to restart the operating system of the host computer 3 to load the project file 1301, which can greatly improve the convenience of switching working modes and reduce the time of restarting the host computer 3.

[0038] Preferably, the memory chip 13 is electrically connected to the FPGA chip 11 via an SPI connection line. The FPGA chip 11 is provided with an SPI interface 112 . The SPI connection line connects the memory chip 13 and the FPGA chip 11 via the SPI interface 112 .

[0039] The present invention includes both hardware connection innovation and software control innovation. The above content is the hardware connection innovation of the present invention, and the following content is the software control innovation of the hardware of the present invention.

[0040] like Figure 3 As shown, the host computer 3 is further provided with switching software 301 and a driver 302. The switching software 301 can select the working mode, query the current mode, determine whether the project file 1301 of the selected working mode corresponds to the currently loaded project file 1301, and enable or disable the driver 302. The driver 302 is used to establish a connection between the host computer 3 and the FPGA chip 11.

[0041] Preferably, multiple working modes and mode selections are set in the switching software 301. The working modes can be named as: mode 1, mode 2, mode 3, ..., mode n. After selecting a working mode, click the mode selection to switch the mode.

[0042] Preferably, the host computer 3 is further provided with application control software corresponding to the working mode, and the application control software is used to control the business functions corresponding to the working mode.

[0043] Furthermore, the FPGA chip 11 is provided with an XDMA IP CORE (physical address) configuration module 1101 , an AXI4 (Advanced Extensible Interface) protocol conversion module 1103 , an ICAP (Internet Content Modification) control module 1104 and an ICAP IP (Internet Address Modification) configuration module 1105 .

[0044] Preferably, the XDMA IP CORE configuration module 1101 is used to configure the PCIe bus IP core 111 and set the mapping space of the PCIe bus IP core 111 to enable data interaction between the host computer 3 and the FPGA chip 11 .

[0045] Preferably, the AXI4 protocol conversion module 1103 is used to convert the interface of the PCIe bus IP core 111 into a common interface with only read / write enable, address, and data, so as to facilitate the transmission of the parameters of the ICAP control module 1104 configured in the host computer 3 to the ICAP control module 1104 and facilitate the reading of the ICAP control module 1104.

[0046] Preferably, the ICAP control module 1104 sends an instruction to the ICAP IP configuration module 1105 to start the ICAP IP configuration module 1105, configure the specified operating mode address for the ICAP IP configuration module 1105, and display the current operating mode. The ICAP control module 1104 can display a flag value of the current operating mode, which includes characteristic information of the current operating mode. The switching software 301 can obtain the flag value of the current operating mode through the PCIe bus 2 to determine the currently loaded operating mode and its corresponding project file 1301.

[0047] Preferably, an ICAP IP core is further provided on the FPGA chip 11 , and the ICAP IP configuration module 1105 is used to select the ICAPIP core to select and load the project file 1301 in the storage chip 13 .

[0048] Before using the FPGA chip 11, it is first configured. The PCIe bus IP core 111 is configured via the XDMA IP CORE configuration module 1101 to enable data exchange between the host computer 3 and the FPGA chip 11. The host computer 3 reads data from the ICAP control module 1104 via the AXI4 protocol conversion module 1103. The ICAP control module 1104 sends instructions to the ICAP IP configuration module 1105, which configures the ICAP IP core and establishes a connection between the FPGA chip 11 and the storage chip 13. Once the above configuration and connection are established, the host computer 3 can selectively load the project file 1301 to switch the operating mode.

[0049] Furthermore, a clock module 1102 for frequency division is provided in the FPGA chip 11 , and the clock module 1102 can be connected to the AXI4 protocol conversion module 1103 .

[0050] like Figure 4 As shown, the project file 1301 further corresponds to the operating mode, dividing the storage space of the memory chip 13 into multiple sub-intervals. Each sub-interval corresponds to a project file 1301. The project file 1301 includes a first address, which corresponds to the physical address of the sub-interval in the storage space. The first address also corresponds to the name of the operating mode. For example, the first address can be: Addr_1, Addr_2, Addr_3, ..., Addr_n, and the corresponding operating modes are: Mode 1, Mode 2, Mode 3, ..., Mode n.

[0051] The configuration of the memory chip 13 is illustrated by way of example: three operating modes are set, each corresponding to three project files 1301, each with a file size of 6M, 6.9M, and 16M, respectively. A memory chip 13 with a size of 32M can be divided into three sub-intervals. The sizes of the three sub-intervals are 7M, 7M, and 18M, respectively, and the physical addresses of the three areas are 0x0000_0000, 0x0070_0000, and 0x00E0_0000, respectively. The three generated project files 1301 can be placed in the corresponding areas. The ICAP control module 1104 names the project file 1301 stored in the area with the physical address 0x0000_0000 as Mode 1. Similarly, the project files 1301 in the remaining two areas are named Mode 2 and Mode 3, respectively.

[0052] The corresponding FPGA chip 11 loads the project file 1301 in the following manner: the ICAP control module 1104 outputs a flag value, which serves as a status indicator signal, indicating which mode the chip is currently in. Upon powering on, the FPGA chip 11 defaults to loading the project file 1301 at 0x0000_0000. At this point, the host computer 3 accesses the status indicator signal from the ICAP IP control module 1104 and obtains a flag value of "01." "01" is the characteristic information of the project file 1301, indicating that the chip is currently in mode 1. To switch to mode 2, the switching software 301 sends the mode identifier "02" to the FPGA chip 11. Upon receiving the "02" mode identifier, the ICAP IP control module 1104 configures the address 0x0070_0000 into the ICAP IP configuration module 1105 and starts the ICAP IP configuration module 1105. After the ICAP IP configuration module 1105 is started, the project file 1301 at the address 0x0070_0000 is reloaded from the storage chip 13 .

[0053] The present invention also provides a multi-mode fast switching processing system, comprising:

[0054] A host computer 3, and switching software 301 and a driver 302 provided in the host computer 3; the switching software 301 can select an operating mode, query the current mode, determine whether the project file 1301 of the selected operating mode corresponds to the currently loaded project file 1301, and enable and disable the driver 302, the driver 302 being used to establish a connection between the host computer 3 and the FPGA chip 11;

[0055] FPGA chip 11, and XDMA IP CORE configuration module 1101, AXI4 protocol conversion module 1103, ICAP control module 1104 and ICAP IP configuration module 1105 provided in the FPGA chip 11; the XDMA IP CORE configuration module 1101 is connected to the AXI4 protocol conversion module 1103, the AXI4 protocol conversion module 1103 is connected to the ICAP control module 1104, and the ICAP control module 1104 is connected to the ICAP IP configuration module 1105;

[0056] A memory chip 13, and a plurality of project files 1301 stored in the memory chip 13; the project files 1301 correspond to the working modes on the host computer 3; the host computer 3 controls the FPGA chip 11 to load the corresponding project files 1301;

[0057] PCIe bus 2, used to electrically connect the host computer 3 and the FPGA chip 11;

[0058] The SPI connection line is used to electrically connect the FPGA chip 11 and the memory chip 13.

[0059] The operation process of a multi-mode fast switching processing system is as follows: Figure 5 As shown, first, the host computer 3 and the FPGA chip 11 are electrically connected via the PCIe bus 2, and the FPGA chip 11 and the storage chip 13 are electrically connected via the SPI connection line. After the hardware connection is established, data exchange can be performed. Then, the operating mode is selected by switching software 301, and it is determined whether the selected operating mode corresponds to the currently loaded project file 1301. If so, the selected operating mode is enabled. If not, the switching software 301 first disables the driver 302, and the project file 1301 corresponding to the selected operating mode is loaded from the storage chip 13 via the FPGA chip 11. The project file 1301 is reloaded. After loading is complete, the driver 302 is reloaded and enabled, and the connection between the host computer 3 and the FPGA chip 11 is reestablished. Then, it is determined whether the selected operating mode corresponds to the currently loaded project file 1301. If so, the selected operating mode is enabled. The switching of the operating mode is completed. This eliminates the need to restart the operating system of the host computer 3 to load the project file 1301, greatly improving the convenience of switching the operating mode and reducing the time required to restart the host computer 3.

[0060] Based on the above hardware connection and software control settings, such as Figure 6 As shown, the present invention also provides a multi-mode fast switching processing method, comprising the steps of:

[0061] Step S1: Establishing a PCIe bus 2 connection between the FPGA chip 11 on the multi-mode fast switching processing board 1 and the host computer 3;

[0062] Step S2: Selecting a working mode on the host computer 3 and querying the project file 1301 currently loaded on the FPGA chip 11;

[0063] Step S3: Determine whether the currently loaded project file 1301 corresponds to the project file 1301 of the selected mode. If not, the FPGA chip 11 loads the project file 1301 corresponding to the working mode from the storage chip 13 electrically connected thereto; after the loading of the project file 1301 corresponding to the working mode is completed, reload the driver 302 of the FPGA chip 11; again determine whether the currently loaded project file 1301 corresponds to the project file 1301 of the selected mode; if they correspond, the selected working mode is enabled on the host computer 3.

[0064] The present invention establishes a real-time PCIe driver connection with the host computer through an FPGA chip, eliminating the need for an MCU controller and PCI / PCIe driver chip. This simplifies the hardware design, reduces hardware usage, and significantly reduces costs. Furthermore, there is no need to restart the host computer's operating system to load project files, greatly improving the convenience of switching operating modes and reducing the time required to restart the host computer.

[0065] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-mode fast switching processing board, characterized in that: An FPGA chip and a PCIe bus connection port are provided on the multi-mode fast switching processing board. Multiple pins of the FPGA chip are directly and electrically connected to multiple terminals of the PCIe bus connection port. The PCIe bus connection port is used to connect to a host computer. The FPGA chip has a built-in PCIe bus IP core. By configuring the PCIe bus IP core, a PCIe driver connection can be established with the host computer in real time. A storage chip is also provided on the multi-mode fast switching processing board, which is electrically connected to the FPGA chip and stores multiple project files. The project files correspond to the working modes on the host computer. When the working mode is switched, the host computer disables the driver of the FPGA chip and controls the FPGA chip to load the corresponding project files through the PCIe bus connection port. After the project files are loaded, the host computer enables the driver of the FPGA chip and re-establishes the communication interaction between the FPGA chip and the host computer.

2. The multi-mode fast switching processing board according to claim 1, characterized in that: The storage space of the memory chip includes a plurality of sub-intervals, each of the sub-intervals corresponds to one of the project files, and the project file includes a first address, and the first address corresponds to a physical address of the sub-interval.

3. The multi-mode fast switching processing board according to claim 1, characterized in that: The multi-mode fast switching processing board is electrically connected to the host computer via a PCIe bus.

4. The multi-mode fast switching processing board according to claim 1, characterized in that: The memory chip is electrically connected to the FPGA chip via an SPI connection line.

5. The multi-mode fast switching processing board according to claim 1, characterized in that: The host computer is provided with switching software and a driver. The switching software can select the working mode, query the current mode, determine whether the project file of the selected working mode corresponds to the currently loaded project file, and enable and disable the driver. The driver is used to establish a connection between the host computer and the FPGA chip.

6. The multi-mode fast switching processing board according to claim 1, characterized in that: The FPGA chip is provided with an XDMA IP CORE configuration module, an AXI4 protocol conversion module, an ICAP control module and an ICAP IP configuration module; the XDMA IP CORE configuration module is connected to the AXI4 protocol conversion module, the AXI4 protocol conversion module is connected to the ICAP control module, and the ICAP control module is connected to the ICAP IP configuration module.

7. The multi-mode fast switching processing board according to claim 6, characterized in that: A clock module for frequency division is provided in the FPGA chip, and the clock module is connected to the AXI4 protocol conversion module.

8. A multi-mode fast switching processing system, characterized in that: include: A host computer, and switching software and a driver provided in the host computer; The switching software can select an operating mode, query the current mode, determine whether the project file of the selected operating mode corresponds to the currently loaded project file, and enable and disable a driver, which is used to establish a connection between the host computer and the FPGA chip; FPGA chip, and an XDMA IP CORE configuration module, an AXI4 protocol conversion module, an ICAP control module, and an ICAP IP configuration module provided in the FPGA chip; the XDMA IP CORE configuration module is connected to the AXI4 protocol conversion module, the AXI4 protocol conversion module is connected to the ICAP control module, and the ICAP control module is connected to the ICAP IP configuration module; A memory chip, and a plurality of engineering files stored in the memory chip; the engineering files correspond to the working modes on the host computer; The host computer controls the FPGA chip to load the corresponding engineering file; A PCIe bus is used to electrically connect the host computer and the FPGA chip, and the FPGA chip is directly electrically connected to the PCIe bus; The SPI connection line is used to electrically connect the FPGA chip and the memory chip.

9. A multi-mode fast switching processing method for a multi-mode fast switching processing board according to claim 1, characterized in that: Including steps: Establishing a PCIe bus connection between the FPGA chip on the multi-mode fast switching processing board and the host computer; Selecting a working mode on the host computer and querying the project file currently loaded on the FPGA chip; Determine whether the currently loaded project file corresponds to the project file of the selected working mode. If so, the selected working mode is enabled on the host computer. If not, the FPGA chip loads the project file corresponding to the working mode from the storage chip electrically connected thereto. After the project file corresponding to the working mode is loaded, reload the driver of the FPGA chip. Determine again whether the currently loaded project file corresponds to the project file of the selected working mode.

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