A method of testing a semiconductor chip set, a semiconductor chip set, and a measuring device

Abstract

The embodiment of the present disclosure provides a kind of semiconductor chip group test method, semiconductor chip group and measuring device, wherein test method includes: semiconductor chip group includes n chips and the bonding interface between n chips, bonding interface includes the interface to be measured, n chips include the chip i to be measured on the interface to be measured, wherein 1≤i≤n, chip i to be measured is offset pre-set size in the direction parallel to bonding interface relative to other chips;The thickness of the chip i to be measured is measured, and measurement result t is obtained;The bonding area of the interface to be measured is measured, and measurement result S is obtained;Along the direction perpendicular to bonding interface, push force F is applied to chip i to be measured, to make chip i to be measured crack at interface to be measured;The vertical distance la between the action point of push force and other chips is determined, and the crack length a of chip i to be measured is determined;Determine the bonding energy Gc of the interface to be measured based on at least part of the parameters obtained by the above method.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a testing method for semiconductor chipsets, a semiconductor chipset, and a measuring device. Background Technology

[0002] In the fabrication of semiconductor structures, bonding multiple wafers or chips is a crucial technique. After completing the bonding process for multiple wafers or chips, in order to evaluate the degree of interface bonding between wafers or chips, it is necessary to quantitatively assess the wafer interface bonding energy or chip interface bonding energy, which characterizes the degree of interface bonding.

[0003] However, conventional methods for evaluating wafer interface bonding energy or chip interface bonding have significant limitations when evaluating products with thinner thicknesses. Summary of the Invention

[0004] This disclosure provides a method for testing semiconductor chipsets, including:

[0005] A semiconductor chipset is provided, the semiconductor chipset including n bonded chips and a bonding interface located between the n chips, the bonding interface including a test interface, the n chips including a test chip i located on the test interface, wherein 1≤i≤n, and the test chip i is offset by a preset size relative to the other chips in a direction parallel to the bonding interface.

[0006] The thickness of the chip i under test is measured to obtain the measurement result t;

[0007] The bonding area of ​​the interface to be tested is measured to obtain the measurement result S;

[0008] A thrust F is applied to the chip under test i in a direction perpendicular to the bonding interface, so as to cause a crack to be generated in the chip under test i at the interface under test;

[0009] The vertical distance la between the point of application of the thrust and other chips is measured, and the crack length a of the chip i under test is measured.

[0010] The bonding energy Gc of the interface under test is determined based on at least some of the following parameters: chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a.

[0011] In some embodiments, the chip under test i is offset by a preset size relative to other chips in a direction parallel to the bonding interface; including:

[0012] The chip under test i is offset by a preset size relative to other chips along the X-axis; or, the chip under test i is offset by a preset size relative to other chips along the Y-axis; wherein the X-axis and Y-axis are parallel to the bonding interface and perpendicular to each other.

[0013] In some embodiments, the preset size does not exceed 2 / 3 of the chip's size in the X-axis direction; or, the preset size does not exceed 2 / 3 of the chip's size in the Y-axis direction.

[0014] In some embodiments, the thickness t of the chip under test i is greater than 20 μm.

[0015] In some embodiments, a semiconductor chipset is provided, including:

[0016] An initial semiconductor chipset is provided, the initial semiconductor chipset comprising n bonded chips, the projections of the n chips in a direction perpendicular to the bonding interface overlapping each other;

[0017] Select chip i to be tested, 1≤i≤n, and chip i to be tested is located on the side of other chips;

[0018] Other chips are removed by a preset size in a direction parallel to the bonding interface, so that the chip under test i is offset by a preset size relative to other chips in a direction parallel to the bonding interface.

[0019] In some embodiments, after determining the bonding energy Gc of the interface under test based on at least some of the parameters including the chip thickness t, the bonding area S of the interface under test, the thrust F, the vertical distance la, and the crack length a, the testing method further includes:

[0020] Select the chip to be tested as i+k, where 1≤i+k≤n-1;

[0021] Remove other chips located on one side of the chip under test i+k, so that the chip under test i+k is located on the edge side of the remaining chips;

[0022] The remaining chip is removed by a preset size in a direction parallel to the bonding interface, so that the chip under test i+k is offset by a preset size relative to the remaining chip in a direction parallel to the bonding interface.

[0023] In some embodiments, a semiconductor chipset is provided, including:

[0024] A semiconductor chipset is provided, the semiconductor chipset comprising n bonded chips, some of the chips being offset by a preset size relative to the other chips on one or both sides in a direction parallel to the bonding interface, and at least one of the chips being defined as chip i under test, 1≤i≤n.

[0025] In some embodiments, before applying a thrust F to the chip under test i in a direction perpendicular to the bonding interface, the testing method further includes:

[0026] A fixing fixture is provided, the fixing fixture including a first fixing device and a second fixing device, the first fixing device including a first plane, the second fixing device including a second plane, the first plane and the second plane being arranged face to face and parallel to each other; wherein, the height of the first fixing device is greater than the height of the second fixing device;

[0027] One side of the semiconductor chipset is fixed on the first plane of the first fixing device, and the upper surface of the chip under test i protrudes upward relative to the upper surface of the first fixing device;

[0028] The other side of the semiconductor chip assembly is fixed to the second plane of the second fixing device, and the upper surface of the second fixing device is lower than the upper surface of the other chips.

[0029] In some embodiments, in the direction perpendicular to the bonding interface, the distance between the chip under test i and the second fixing device is less than the distance between the chip under test i and the first fixing device.

[0030] In some embodiments, applying a thrust F to the chip under test i in a direction perpendicular to the bonding interface includes:

[0031] A thrust F is applied to the chip under test i in the direction from the first fixing device to the second fixing device, so as to cause the chip under test i to develop a crack at the interface under test.

[0032] This disclosure also provides a semiconductor chipset, which includes n bonded chips and bonding interfaces located between the n chips. The bonding interfaces include a test interface, and the n chips include a test chip i located on the test interface, wherein 1≤i≤n, and the test chip i is offset by a preset size relative to the other chips in a direction parallel to the bonding interfaces.

[0033] In some embodiments, the chip under test (DUT) i is offset by a preset size relative to other chips in a direction parallel to the bonding interface; including: the chip under test i is offset by a preset size relative to other chips along the X-axis; or, the chip under test i is offset by a preset size relative to other chips along the Y-axis; wherein the X-axis and Y-axis are parallel to the bonding interface and perpendicular to each other.

[0034] In some embodiments, the preset size does not exceed 2 / 3 of the chip's size in the X-axis direction, or the preset size does not exceed 2 / 3 of the chip's size in the Y-axis direction.

[0035] This disclosure also provides a measurement device for a semiconductor chipset, including:

[0036] A fixing clamp includes a first fixing device and a second fixing device. The first fixing device includes a first plane, and the second fixing device includes a second plane. The first plane and the second plane are arranged face to face and parallel to each other. The height of the first fixing device is greater than the height of the second fixing device.

[0037] A thrust device for applying a thrust to the semiconductor chipset to cause cracks in the semiconductor chipset;

[0038] An infrared camera is used to measure the length of cracks generated in the semiconductor chipset.

[0039] In some embodiments, the thrust device applies a thrust F to the semiconductor chip assembly in a direction from the first fixing device to the second fixing device to cause cracks in the semiconductor chip assembly.

[0040] The bonding area of ​​the interface under test is measured using the infrared camera device to obtain parameter S; and,

[0041] The infrared camera device is used to determine the vertical distance between the point of application of the thrust and other chips to obtain parameter 1a, and the crack length generated by the semiconductor chip group is measured to obtain parameter 2a.

[0042] The present disclosure provides a semiconductor chipset testing method, a semiconductor chipset, and a measuring device. The testing method includes: providing a semiconductor chipset comprising n bonded chips and bonding interfaces between the n chips, each bonding interface including a test interface; the n chips including a test chip i located on the test interface, where 1 ≤ i ≤ n; the test chip i being offset by a preset dimension relative to the other chips in a direction parallel to the bonding interface; measuring the thickness of the test chip i to obtain a measurement result t; measuring the bonding area of ​​the test interface to obtain a measurement result S; applying a thrust F to the test chip i in a direction perpendicular to the bonding interface to cause a crack in the test chip i at the test interface; determining the vertical distance la between the thrust application point and other chips, and determining the crack length a of the test chip i; and determining the bonding energy Gc of the test interface based on at least some of the parameters selected from the chip thickness t, the bonding area S of the test interface, the thrust F, the vertical distance la, and the crack length a. In this embodiment of the disclosure, since the chip under test (i) can be any one of n chips, when it is necessary to test the bonding energy of any bonding interface, it is only necessary to offset one chip located on the bonding interface (the interface under test) relative to the other chips by a preset size in the step of providing the semiconductor chipset. This facilitates appropriate operations on the chip, such as applying a pushing force to induce a crack. Then, based on at least a portion of the parameters obtained after applying the pushing force to the chip, the bonding energy information of the bonding interface (the interface under test) can be obtained. In other words, the method provided by this embodiment of the disclosure helps to achieve directional testing of the bonding energy of any bonding interface in a semiconductor chipset formed by bonding multiple chips.

[0043] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart of a semiconductor chipset testing method provided in this disclosure embodiment;

[0046] Figures 2 to 6 A process flow diagram of a testing method for a semiconductor chipset structure provided in an embodiment of this disclosure;

[0047] Figures 7 to 10 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in an embodiment of this disclosure;

[0048] Figure 11 and Figure 12 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment;

[0049] Figure 13 and Figure 14 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment;

[0050] Figures 15 to 17 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in an embodiment of this disclosure;

[0051] Figures 18 to 19 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment. Detailed Implementation

[0052] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0054] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] In the fabrication of semiconductor structures, it is often necessary to bond multiple chips onto a substrate. Before bonding these chips, bonding connections must be established between them. To evaluate the degree of interfacial bonding between chips, it is necessary to quantitatively assess the chip interfacial bonding energy, which characterizes the bonding degree. For example, methods such as crack propagation diffusion, thrust shear, and tensile testing can be used to quantitatively assess the bonding energy.

[0059] However, in practice, the crack propagation diffusion method and the thrust shear method have high requirements for chip thickness, making it impossible to quantitatively evaluate thinner chips. While the tensile method is less demanding on chip thickness, it is only applicable to cases with a single bonding interface. Therefore, it can be seen that conventional methods for quantitatively evaluating bonding energy have significant limitations.

[0060] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0061] This disclosure provides a method for testing semiconductor chipsets, such as... Figure 1 As shown, the test method includes the following steps:

[0062] Step S101: Provide a semiconductor chipset, which includes n bonded chips and bonding interfaces between the n chips. The bonding interfaces include interfaces under test. The n chips include chip under test i located on the interface under test, where 1≤i≤n. The chip under test i is offset by a preset size relative to the other chips in a direction parallel to the bonding interfaces.

[0063] Step S102: Measure the thickness of the chip i under test and obtain the measurement result t;

[0064] Step S103: Measure the bonding area of ​​the interface to be measured and obtain the measurement result S;

[0065] Step S104: Apply a thrust F to the chip under test i in a direction perpendicular to the bonding interface to cause a crack to be generated at the interface of the chip under test i.

[0066] Step S105: Measure the vertical distance la between the point of application of the thrust and other chips, and measure the crack length a of the chip i under test;

[0067] Step S106: Determine the bonding energy Gc of the interface under test based on at least some of the parameters among chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a.

[0068] In this embodiment of the disclosure, since the chip under test (i) can be any one of n chips, when it is necessary to test the bonding energy of any bonding interface, it is only necessary to offset one chip located on the bonding interface (the interface under test) relative to the other chips by a preset size in the step of providing the semiconductor chipset. This facilitates appropriate operations on the chip, such as applying a pushing force to induce a crack. Then, based on at least a portion of the parameters obtained after applying the pushing force to the chip, the bonding energy information of the bonding interface (the interface under test) can be obtained. In other words, the method provided by this embodiment of the disclosure helps to achieve directional testing of the bonding energy of any bonding interface in a semiconductor chipset formed by bonding multiple chips.

[0069] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0070] Figure 1 A flowchart of a semiconductor chipset testing method provided in this disclosure embodiment; Figures 2 to 6 A process flow diagram of a testing method for a semiconductor chipset structure provided in an embodiment of this disclosure;

[0071] Figures 7 to 10 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in an embodiment of this disclosure; Figure 11 and Figure 12 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment; Figure 13 and Figure 14 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment; Figures 15 to 17 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in an embodiment of this disclosure; Figures 18 to 19 A process flow diagram of a testing method for another structure of a semiconductor chipset provided in this disclosure embodiment.

[0072] The testing method for semiconductor chipsets provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0073] First, execute step S101, as follows: Figure 2 , Figure 8 , Figure 11 and Figure 16As shown, a semiconductor chipset is provided, which includes n bonded chips and bonding interfaces between the n chips. The bonding interfaces include a test interface A, and the n chips include a test chip i located on the test interface A, where 1≤i≤n. The test chip i is offset by a preset size L relative to the other chips in a direction parallel to the bonding interfaces.

[0074] Here, the n chips in the semiconductor chipset are numbered as chip 1, chip 2, chip 3, chip 4... chip n-1, chip n-1, chip n. A bonding interface is provided between every two chips; for example, bonding interfaces are provided between chip 1 and chip 2, between chip n-2 and chip n-1, and between chip n-1 and chip n.

[0075] Understandably, both n and i are positive integers greater than or equal to 1. In some specific embodiments, n can be a positive integer greater than or equal to 2.

[0076] In some embodiments, such as Figure 2 As shown, in the direction parallel to the bonding interface, chip n is offset by a preset size L relative to other chips. That is, in this embodiment, chip n serves as chip i under test, which will be the target of the subsequent test method, while the bonding interface located between chip n and chip n-1 serves as interface A under test.

[0077] Understandably, by setting the chip under test i (chip n) to be offset by a preset distance L relative to other chips in a direction parallel to the bonding interface, when subsequent testing methods are executed, such as when force is applied to the chip under test i (chip n), the chip under test i (chip n) will bend, crack, etc., causing a certain degree of separation between the chip under test i (chip n) and the interface under test A. Under the same other parameters, this separation can reflect the degree of bonding of the interface under test A to a certain extent.

[0078] As can be seen, in this embodiment of the present disclosure, the design of offsetting the chip under test i (chip n) relative to other chips by a preset distance in a direction parallel to the bonding interface provides convenient conditions for the semiconductor chipset to test the bonding degree of any selected bonding interface (the interface under test).

[0079] In some embodiments, the chip under test i is offset by a preset size L relative to other chips in a direction parallel to the bonding interface; including:

[0080] The chip under test (I) is offset by a preset size L relative to other chips along the X-axis; or, the chip under test (I) is offset by a preset size L relative to other chips along the Y-axis; wherein the X-axis and Y-axis are parallel to the bonding interface and perpendicular to each other.

[0081] In some embodiments, the preset size L does not exceed 2 / 3 of the chip's size in the X-axis direction; or, the preset size L does not exceed 2 / 3 of the chip's size in the Y-axis direction.

[0082] In practice, when the chip is rectangular, the X and Y axes can be set on the edge of the chip. However, this is not the only limitation; when the chip has other shapes, the X and Y axes can be set in other positions as needed.

[0083] Here, the design of the offset preset size is mainly to meet the operational requirements of applying a thrust to the chip under test when the subsequent test method is executed.

[0084] In practice, the preset dimension L can be a value greater than 2mm, 2.5mm, or 3mm. However, it is not limited to these values; the preset dimension L can also be other larger or smaller values. There are no specific restrictions here, and any dimension that can meet the requirements for applying thrust to the chip under test can be used as the preset dimension.

[0085] Understandably, by setting the preset size to not exceed 2 / 3 of the chip's size in the X-axis or Y-axis direction, sufficient bonding strength can be ensured between the chip under test and other unoffset chips, preventing the chip under test from detaching from other unoffset chips and causing test interruption.

[0086] In the embodiments of this disclosure, the location and number of the chip under test (DUT) i in the semiconductor chipset, as well as the acquisition of DUT i, can include various scenarios. For example, DUT i can be located at the edge of n chips, such as DUT i being chip n or chip 1; or, DUT i can be located in the middle region of n chips, such as DUT i being any one of chip 2 to chip n-1; or, DUT i can include multiple chips; or, DUT i may require a series of subsequent process operations to obtain.

[0087] The following will combine Figure 2 , Figure 7 and Figure 8 , Figure 11 , Figure 15 and Figure 16 Before executing the test method, further detailed explanations are provided regarding the relevant information of the chip under test i in different semiconductor chipsets.

[0088] In some embodiments, such as Figure 2 As shown, the chip under test i is located at the edge of the n chips. In this embodiment, the chip under test i is the same as chip n.

[0089] Understandably, in this embodiment, the chip under test (DUT) i is located at the edge of the n chips, allowing for direct testing of DUT i in actual operation, simplifying the testing steps and saving operation time. Understandably, when DUT i is chip 1, the testing steps can also be simplified, saving operation time.

[0090] In other embodiments, such as Figure 7 and Figure 8 As shown, the chip under test i is located in the middle region of n chips, and it can be any one of chip 2 to chip n-1. Taking chip under test i as chip n-1 as an example, the semiconductor chipset provided includes:

[0091] An initial semiconductor chipset is provided, which includes n chips, and the chip under test i is located in the middle region of the n chips;

[0092] Remove a portion of length D from chip n located on the side of chip i (chip n-1) to obtain a semiconductor chipset.

[0093] Here, the removal criterion for length D can be that when the semiconductor chipset is subsequently placed on the fixture, the upper surface of chip n is not higher than the upper surface of the lower side of the fixture.

[0094] Similarly, when the chip under test (i) offset by a preset size relative to other chips is any one of chip 2 to chip n-2, the same method can be used to obtain the target chip that can be directly used for testing before the test method is executed. In this case, it is only necessary to remove a portion of the length from the other chips located on one side of the chip under test (i).

[0095] Thus, it can be seen that in the two embodiments above, the chip under test (DUT) can be located either at the edge of the n chips or in the middle of the n chips; that is, the DUT can be any one of the n chips. Since the separation between the DUT and the selected bonding interface (i.e., the interface under test) when force is applied can reflect the bonding degree of the interface under test A to some extent, it is only necessary to offset one chip located on the interface under test relative to the other chips by a preset size during the sample provision stage to provide the necessary conditions for evaluating the bonding degree of a pre-selected bonding interface.

[0096] In some other embodiments, such as Figure 11 As shown, a semiconductor chipset is provided, including:

[0097] A semiconductor chipset is provided, comprising n bonded chips, some of which are offset by a preset size relative to the other chips on one or both sides in a direction parallel to the bonding interface, and at least one of the chips is defined as chip i under test, 1≤i≤n.

[0098] As shown in the figure, in this embodiment, some chips are offset by a predetermined size relative to other chips on both sides parallel to the bonding interface. For example, chip 1 is offset by a predetermined size L on one side of chip 2, while chip 3 is offset by a predetermined size L on the other side of chip 2. Chip n is offset by a predetermined size L on one side of chip n-1, and chip n-2 is offset by a predetermined size L on the other side of chip n-1. This design is equivalent to using other chips, such as chip 2 or chip n-1, as reference chips, and then offsetting the chips located on both sides of them by a predetermined size L to their respective sides.

[0099] It is understood that, in this embodiment, by pre-setting chips with a preset offset size on each bonding interface, the bonding degree of all bonding interfaces can be evaluated by providing only one sample in actual operation.

[0100] However, it is not limited to this. It should be noted that, although Figure 11 The illustration only shows the case where there is only one reference chip, but in actual operation, the number of reference chips can be unlimited. Figure 11 There are limitations, such as the number of reference chips being 2, 3, 4 or other quantities, which can be flexibly determined according to the requirements.

[0101] Additionally, it should be noted that because the chips on both sides of the reference chip are offset in two directions, the overlapping area of ​​the chips on both sides of the reference chip in the direction perpendicular to the bonding interface is small. In order to avoid test interruption due to chip detachment, in actual operation, the chips on both sides of the reference chip in the direction perpendicular to the bonding interface can also be offset by a preset size in the direction parallel to the bonding interface and on one side of the reference chip.

[0102] In yet another embodiment of this disclosure, such as Figure 15 and Figure 16 As shown, a semiconductor chipset is provided, including:

[0103] An initial semiconductor chipset is provided, comprising n bonded chips, the projections of the n chips in a direction perpendicular to the bonding interface overlapping each other;

[0104] Select chip i to be tested, 1≤i≤n, and chip i to be tested is located to the side of other chips;

[0105] Remove the preset size L from other chips in a direction parallel to the bonding interface, so that the chip under test i is offset by the preset size L relative to other chips in a direction parallel to the bonding interface.

[0106] As can be seen from the embodiments of this disclosure, the projections of the n chips of the initial semiconductor chipset in the direction perpendicular to the bonding interface overlap, maximizing the bonding between adjacent chips and providing high stability. This effectively prevents test interruptions caused by chip detachment during testing. Furthermore, in this embodiment, the operator can randomly specify the interface to be tested, which facilitates obtaining typical and representative evaluation results. Once the interface to be tested is specified, the chip to be tested can be obtained by removing a preset size from the other chips on the side of the chip to be tested located on that interface. Then, by performing appropriate operations on the chip to be tested, the bonding degree of the interface can be evaluated. This method has the advantages of simplicity and ease of implementation, and can obtain typical and representative evaluation results.

[0107] Next, step S102 is executed to measure the thickness of the chip i under test and obtain the measurement result t.

[0108] In some embodiments, the thickness t of the chip under test i is greater than 20 μm. For example, dimensions such as 25 μm or 30 μm. It can be seen that the method using embodiments of this disclosure can be applied to the testing of bonding energy at bonding interfaces formed from chips with relatively thin thicknesses.

[0109] However, this is not the only limitation. It is understood that the thickness of the chip i under test can also be other dimensions, such as 50μm, 100μm, or even greater. In other words, the method of this disclosure is not only applicable to the testing of bonding energy of bonding interfaces formed by thinner chips, but also applicable to the testing of bonding energy of bonding interfaces formed by thicker chips, and has a wider range of applications.

[0110] In practice, tools for measuring the thickness of the chip under test include, but are not limited to, laser measuring instruments.

[0111] Next, step S103 is executed to measure the bonding area of ​​the interface A to be measured, and the measurement result S is obtained.

[0112] In practice, an infrared camera can be used to measure the bonding area of ​​the interface A under test in order to obtain the value S of the bonding area.

[0113] Then, proceed to step S104, as follows: Figure 6 , Figure 10 , Figure 12 and Figure 17 As shown, a thrust is applied to the chip under test i in a direction perpendicular to the bonding interface to cause a crack to be generated at the interface A of the chip under test i.

[0114] In some embodiments, such as Figure 3 and Figure 4As shown, before applying a thrust F to the chip i under test in a direction perpendicular to the bonding interface, the test method further includes:

[0115] A fixing clamp 10 is provided, which includes a first fixing device 11 and a second fixing device 12. The first fixing device 11 includes a first plane S1, and the second fixing device 12 includes a second plane S2. The first plane S1 and the second plane S2 are arranged facing each other and are parallel to each other. The height of the first fixing device 11 is greater than the height of the second fixing device 12.

[0116] One side of the semiconductor chipset is fixed on the first plane S1 of the first fixing device 11, and the upper surface of the chip under test i protrudes upward relative to the upper surface of the first fixing device 11.

[0117] The other side of the semiconductor chipset is fixed on the second plane S2 of the second fixing device 12, and the upper surface of the second fixing device 12 is lower than the upper surface of the other chips.

[0118] Optionally, in some embodiments, the upper surface of other chips may be flush with the upper surface of the first fixing device 11. However, this is not a limitation; in some other embodiments, the upper surface of other chips may protrude or be slightly lower than the upper surface of the first fixing device 11, and no specific limitation is made here.

[0119] Understandably, in some embodiments, the distance between the chip under test i and the second fixing device 12 in the direction perpendicular to the bonding interface is less than the distance between the chip under test i and the first fixing device 11.

[0120] Here, since the chip under test i will bend and deform during the subsequent application of a pushing force, sufficient space needs to be reserved on the side of the chip under test i that will bend and deform to obtain the expected deformation effect. In this embodiment of the present disclosure, the design that the distance between the chip under test i and the second fixing device 12 is smaller than the distance between the chip under test i and the first fixing device 11 perfectly meets this requirement, reserving sufficient space for the bending deformation that the chip under test i will undergo.

[0121] In some embodiments, such as Figure 6 , Figure 10 , Figure 12 and Figure 17 As shown, a thrust F is applied to the chip under test i in a direction perpendicular to the bonding interface, including:

[0122] A thrust F is applied to the chip under test i in the direction from the first fixing device 11 to the second fixing device 12, so that a crack is generated in the chip under test i at the interface A under test.

[0123] In practice, such as Figure 5 and Figure 9 As shown, before applying a thrust F to the chip under test i in a direction perpendicular to the bonding interface, the method may further include the step of providing a thrust device 2. The thrust device 2 can be used to apply a thrust F to the chip under test i to cause the chip under test i to bend and deform, thereby achieving the effect of creating a crack in the chip under test i at the interface A under test.

[0124] Next, proceed to step S105, as follows: Figure 6 , Figure 10 , Figure 12 and Figure 17 As shown, the vertical distance la between the point of application of the thrust and other chips is measured, and the crack length a of the chip i under test is measured.

[0125] In some embodiments, measuring the vertical distance la between the point of application of the thrust and other chips, and measuring the crack length a of the chip i under test, includes:

[0126] Provide infrared camera device 3;

[0127] The vertical distance 1a between the point of application of the thrust and other chips is measured by infrared camera device 3.

[0128] The crack length a of the chip i under test is determined by infrared camera device 3.

[0129] In actual operation, measuring the vertical distance la between the point of application of the thrust and other chips can refer to the vertical distance between the lowest point of the thrust device 2 and other chips when the chip under test i undergoes bending deformation.

[0130] Thus, by performing steps 102 to 105, multiple parameters for characterizing the bonding energy of the interface under test can be obtained, namely chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a.

[0131] Finally, step S106 is performed to determine the bonding energy Gc of the interface under test based on at least some of the parameters among chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a.

[0132] In some embodiments, the bonding energy Gc of the interface under test can be determined by the following method, for example: substituting some parameters, such as chip thickness t, vertical distance la and crack length a, into the following relationship (1), and calculating the bonding energy Gc:

[0133]

[0134] Where E is the Young's modulus of the chip i under test.

[0135] However, this is not the only option. It is understood that in other embodiments, other formulas may be used to calculate the bonding energy Gc of the interface under test and thereby evaluate the degree of bonding of the interface under test.

[0136] In other words, the method provided by this disclosure can obtain multiple parameters. When it is necessary to evaluate the bonding energy of the bonding interface, the operator can select the required parameters according to the actual situation, substitute them into the appropriate formula, and then calculate to obtain the bonding energy information of the bonding interface, which has great flexibility.

[0137] It is understood that in this embodiment of the present disclosure, when there is more than one chip under test, after completing the above multiple steps to obtain the bonding energy of the interface under test, the remaining chips can be subjected to appropriate reprocessing processes to obtain other chips under test, and the bonding energy information of other bonding interfaces can be obtained by measuring the other chips under test.

[0138] For example, after completing Figure 11 and Figure 16 After testing the bonding energy of interface A in the provided structure, the following operations can be performed:

[0139] In some embodiments, such as Figure 13 and Figure 14 As shown, after determining the bonding energy Gc of the chip i under test based on at least some of the parameters among chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a, the test method may further include the following operations:

[0140] Select chip n-2 as chip i to be tested;

[0141] Remove a certain length from chip n, which has developed cracks;

[0142] Remove part of the length D from chip n-1;

[0143] After rotating the semiconductor chipset 180°, it is fixed onto the fixing fixture 10.

[0144] In the direction perpendicular to the bonding interface, the distance between the chip under test i (chip n-2) and the second fixing device 12 is less than the distance between the chip under test i (chip n-2) and the first fixing device 11.

[0145] In practice, removing a certain length of the cracked chip n results in a chip n with a flat shape, facilitating subsequent fixation of the semiconductor chip assembly on the fixing device. The standard for this length removal is: before the semiconductor chip assembly is rotated 180°, when placed on the fixing fixture, the upper surface of the remaining chip n should not be higher than the upper surface of the second fixing device. For chip n-1, the standard for removing a portion of the length D is: when the semiconductor chip assembly is rotated 180° and then placed on the fixing fixture, the upper surface of the remaining chip n-1 should not be higher than the upper surface of the second fixing device.

[0146] Next, steps 102 to 106 can be performed to test the bonding energy of the bonding interface (interface A under test) where the chip under test i (chip n-2) is located.

[0147] In this embodiment, a similar method can be used to perform multiple cyclic operations to test the bonding energy of multiple or all bonding interfaces.

[0148] In some embodiments, such as Figure 18 As shown, after determining the bonding energy Gc of the chip i under test based on at least some of the parameters among chip thickness t, bonding area S of the interface under test, thrust F, vertical distance la, and crack length a, the test method further includes:

[0149] Select the chip to be tested as i+k, where 1≤i+k≤n-1;

[0150] Remove other chips located on one side of the chip under test i+k so that the chip under test i+k is located on the edge side of the remaining chips;

[0151] The remaining chip is removed by a preset size L in a direction parallel to the bonding interface, so that the chip under test i+k is offset by the preset size L relative to the remaining chip in a direction parallel to the bonding interface.

[0152] Understandably, here, both i and k are positive integers.

[0153] Next, steps 102 to 106 can be performed to test the bonding energy of the bonding interface (interface A under test) where the chip i+k (chip i+k) is located.

[0154] In this embodiment, a similar method can be used to perform multiple cyclic operations to test the bonding energy of multiple or all bonding interfaces.

[0155] As can be seen, in this embodiment, the number of chips under test in the semiconductor chipset can be multiple, that is, the number of interfaces under test can also be multiple. After the evaluation of one interface under test is completed, the next chip under test is selected first, and then all other chips located on one side of the next chip under test are removed. Then, the remaining chips are removed by removing the preset size to obtain the next chip under test.

[0156] This embodiment allows for testing multiple chips using a single sample preparation followed by a multi-step removal process. Furthermore, provided the chip length allows, the method is applicable to continuous operations from chip n, chip n-1, chip n-2… chip 2 up to chip 1. In other words, under certain conditions, this method can evaluate the bonding strength of all bonding interfaces, offering simplicity and ease of implementation. More importantly, this method can comprehensively evaluate the bonding strength of each bonding interface in a semiconductor chipset using only a single sample.

[0157] This disclosure also provides a semiconductor chipset, such as... Figure 2 , Figure 8 , Figure 11 and Figure 16 As shown, the semiconductor chipset includes n bonded chips and bonding interfaces between the n chips. The bonding interface includes a test interface A, and the n chips include a test chip i located on the test interface A, where 1≤i≤n. The test chip i is offset by a preset size L relative to the other chips in a direction parallel to the bonding interface.

[0158] In a semiconductor chipset, a chip located at the bonding interface (the interface under test) is offset by a predetermined size relative to other chips. This facilitates appropriate manipulation of the chip, such as applying a force to cause bending deformation, thereby obtaining parameters that can provide feedback on the bonding degree of the bonding interface (the interface under test), including but not limited to thickness and crack length. Since the chip under test i in this embodiment can be any one of n chips, the bonding interface for evaluating bonding energy can also be any one of the bonding interfaces included in the semiconductor chipset. In other words, using the semiconductor chipset provided in this embodiment facilitates directional testing of the bonding energy of any bonding interface.

[0159] In some embodiments, the chip under test (DUT) i is offset by a preset size L relative to other chips in a direction parallel to the bonding interface; including: the chip under test i is offset by a preset size L relative to other chips along the X-axis; or, the chip under test i is offset by a preset size L relative to other chips along the Y-axis; wherein the X-axis and Y-axis are parallel to the bonding interface and perpendicular to each other.

[0160] In some embodiments, the preset size L does not exceed 2 / 3 of the chip's size in the X-axis direction, or the preset size L does not exceed 2 / 3 of the chip's size in the Y-axis direction.

[0161] In practice, when the chip is rectangular, the X and Y axes can be set on the edge of the chip. However, this is not the only limitation; when the chip has other shapes, the X and Y axes can be set in other positions as needed.

[0162] Here, the design of the offset preset size is mainly to meet the operational requirements of applying a thrust to the chip under test when the subsequent test method is executed.

[0163] In practice, the preset dimension L can be a value greater than 2mm, 2.5mm, or 3mm. However, it is not limited to these values; the preset dimension L can also be other larger or smaller values. There are no specific restrictions here, and any dimension that can meet the requirements for applying thrust to the chip under test can be used as the preset dimension.

[0164] Understandably, by setting the preset size to no more than 2 / 3 of the chip's size in the X-axis or Y-axis direction, sufficient bonding strength can be ensured between the chip under test and other unoffset chips, preventing the chip under test from detaching from other unoffset chips during the test and causing test interruption.

[0165] This disclosure also provides a measurement device for semiconductor chipsets, such as... Figure 6 As shown, it includes:

[0166] The fixing clamp 10 includes a first fixing device 11 and a second fixing device 12. The first fixing device 11 includes a first plane S1, and the second fixing device includes a second plane S2. The first plane S1 and the second plane S2 are arranged facing each other and are parallel to each other. The height of the first fixing device 11 is greater than the height of the second fixing device 12.

[0167] Thrust device 2, which is used to apply thrust to the semiconductor chipset to cause cracks in the semiconductor chipset;

[0168] Infrared camera device 3 is used to measure the length of cracks generated in semiconductor chipsets.

[0169] In some embodiments, the thrust device 2 applies a thrust F to the semiconductor chip assembly in the direction from the first fixing device 11 to the second fixing device 12 to cause cracks in the semiconductor chip assembly.

[0170] The bonding area of ​​the interface A under test is measured using an infrared camera 3 to obtain parameter S; and,

[0171] Infrared camera device 3 is used to measure the vertical distance between the point of application of the thrust and other chips to obtain parameter la, and the crack length generated by the semiconductor chip group is measured to obtain parameter a.

[0172] The measuring device provided in this disclosure can obtain multiple parameters for characterizing the bonding energy of semiconductor chipsets. It has the advantages of being simple and easy to implement, and can be applied to various types of semiconductor chipsets.

[0173] In summary, the testing method, semiconductor chipset, and measuring device provided in this disclosure are applicable to situations where a semiconductor chipset contains one or more interfaces to be tested. The interface to be tested can be located in either the edge region or the middle region. In other words, the method provided in this disclosure can perform directional testing of the bonding energy of any bonding interface in a semiconductor chipset formed by bonding multiple chips. Furthermore, the testing method provided in this disclosure has greater flexibility and is applicable to the testing of the bonding energy of semiconductor chipsets with various structural types.

[0174] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to various semiconductor structures, and is not limited thereto. The embodiments of the semiconductor chipset testing method provided in this disclosure belong to the same concept as the embodiments of the semiconductor chipset and measuring device; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0175] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of testing a semiconductor chip set, characterized by, include: A semiconductor chipset is provided, the semiconductor chipset including n bonded chips and a bonding interface located between the n chips, the bonding interface including a test interface, the n chips including a test chip i located on the test interface, wherein 1≤i≤n, and the test chip i is offset by a preset size relative to the other chips in a direction parallel to the bonding interface. The thickness of the chip i under test is measured to obtain the measurement result t; The bonding area of ​​the interface to be tested is measured to obtain the measurement result S; A thrust F is applied to the chip under test i in a direction perpendicular to the bonding interface, so as to cause a crack to be generated in the chip under test i at the interface under test; The vertical distance la between the point of application of the thrust and other chips is measured, and the crack length a of the chip i under test is measured. The bonding energy Gc of the interface under test is determined based on at least some of the parameters, including the chip thickness t, the bonding area S of the interface under test, the thrust F, the vertical distance la, and the crack length a. Among them, semiconductor chipsets are provided, including: An initial semiconductor chipset is provided, the initial semiconductor chipset comprising n bonded chips, the projections of the n chips in a direction perpendicular to the bonding interface overlapping each other; Select chip i to be tested, 1≤i≤n, and chip i to be tested is located on the side of other chips; Other chips are removed by a preset size in a direction parallel to the bonding interface, so that the chip under test i is offset by a preset size relative to other chips in a direction parallel to the bonding interface.

2. The test method of claim 1, wherein, The chip under test i is offset by a preset size relative to other chips in a direction parallel to the bonding interface; including: The chip under test i is offset by a preset size relative to other chips along the X-axis; or, the chip under test i is offset by a preset size relative to other chips along the Y-axis; wherein the X-axis and Y-axis are parallel to the bonding interface and perpendicular to each other.

3. The test method of claim 2, wherein, The preset size does not exceed 2 / 3 of the chip's size in the X-axis direction; or, the preset size does not exceed 2 / 3 of the chip's size in the Y-axis direction.

4. The test method of claim 1, wherein, The thickness t of the chip i under test is greater than 20 μm.

5. The test method of claim 1, wherein, After determining the bonding energy Gc of the interface under test based on at least some of the parameters including the chip thickness t, the bonding area S of the interface under test, the thrust F, the vertical distance la, and the crack length a, the testing method further includes: Select the chip to be tested as i+k, where 1≤i+k≤n-1; Remove other chips located on one side of the chip under test i+k, so that the chip under test i+k is located on the edge side of the remaining chips; The remaining chip is removed by a preset size in a direction parallel to the bonding interface, so that the chip under test i+k is offset by a preset size relative to the remaining chip in a direction parallel to the bonding interface.

6. The test method according to any one of claims 1 to 5, characterized in that, Before applying a thrust F to the chip under test i in a direction perpendicular to the bonding interface, the test method further includes: A fixing fixture is provided, the fixing fixture including a first fixing device and a second fixing device, the first fixing device including a first plane, the second fixing device including a second plane, the first plane and the second plane being arranged face to face and parallel to each other; wherein, the height of the first fixing device is greater than the height of the second fixing device; One side of the semiconductor chipset is fixed on the first plane of the first fixing device, and the upper surface of the chip under test i protrudes upward relative to the upper surface of the first fixing device; The other side of the semiconductor chip assembly is fixed to the second plane of the second fixing device, and the upper surface of the second fixing device is lower than the upper surface of the other chips.

7. The test method according to claim 6, characterized in that, In the direction perpendicular to the bonding interface, the distance between the chip under test i and the second fixing device is less than the distance between the chip under test i and the first fixing device.

8. The test method according to claim 7, characterized in that, Applying a thrust F to the chip under test i in a direction perpendicular to the bonding interface includes: A thrust F is applied to the chip under test i in the direction from the first fixing device to the second fixing device, so as to cause the chip under test i to develop a crack at the interface under test.

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