Super junction trench gate terminal structure and method of manufacturing the same

Abstract

The application provides a super-junction trench gate terminal structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate with an epitaxial layer formed thereon; performing at least two times of ion implantation processes to form a type region in the epitaxial layer; forming a trench gate structure; forming a body region in the type region and the epitaxial layer outside the type region; forming a first heavily doped region in the body region outside the type region; forming a pillar region at the bottom of the body region outside the type region; forming a second heavily doped region; and forming a metal electrode. The type region is formed in the epitaxial layer by multiple-step high-energy ion implantation, the epitaxial layer is compensated by the type region, and the epitaxial layer is mutually depleted with the type region, so as to reduce the doping concentration of the epitaxial layer, improve the withstand voltage of the terminal, and further improve the overall withstand voltage of the device by using the floating trench gate structure in the type region.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a superjunction trench gate termination structure and its fabrication method. Background Technology

[0002] Super Junction Double-Diffused MOS (SJ-DMOS) is widely used in power supplies, lighting, and other fields due to its high voltage withstand capability and low on-resistance. The termination structure of SJ-DMOS is crucial for the voltage withstand capability and reliability of the superjunction. Because the cell region is much larger than the termination region, it can withstand a larger current. Therefore, the termination structure typically needs to have a higher voltage withstand capability than the cell region, so that the breakdown point occurs in the cell region, which helps improve the overall reliability of the device.

[0003] However, the conventional superjunction trench gate termination structure is prone to premature breakdown of the device termination surface due to process deviations such as the width, spacing, and concentration of the superjunction pillars at the triangular electric field peak at the PN pillar interface, which is detrimental to the overall high voltage breakdown resistance of the device. Summary of the Invention

[0004] This application provides a superjunction trench gate terminal structure and its fabrication method, which can solve the problem of poor high-voltage breakdown resistance of conventional superjunction trench gate terminal structures.

[0005] On one hand, embodiments of this application provide a method for fabricating a superjunction trench gate termination structure, including:

[0006] A substrate is provided on which an epitaxial layer is formed;

[0007] Perform at least two ion implantation processes to form a type region in the epitaxial layer;

[0008] The epitaxial layer is etched to form a plurality of trenches in the epitaxial layer in and outside the type region;

[0009] A trench grid structure is formed, wherein the trench grid structure fills the trench;

[0010] An ion implantation process is performed to form a bulk region in the type region and in the epitaxial layer outside the type region;

[0011] An ion implantation process is performed to form a first heavily doped region in the body region outside the type region;

[0012] An ion implantation process is performed to form a pillar region at the bottom of the body region outside the type region;

[0013] Etch the first heavily doped region outside the type region, the body region, and part of the trench gate structure to form an opening;

[0014] An ion implantation process is performed to form a second heavily doped region in the bottom wall and part of the sidewall of the opening in the first heavily doped region and the body region;

[0015] A metal electrode is formed, which fills the opening.

[0016] Optionally, in the fabrication method of the superjunction trench gate termination structure, during each ion implantation process to form the type region in the epitaxial layer, the ion implantation energy is 400 keV to 3000 keV; the ion implantation dose is 1.0E12 atoms / cm. 2 ~1.0E13 atoms / cm 2 .

[0017] Optionally, in the method for fabricating the superjunction trench gate termination structure, after forming the second heavily doped region and before forming the metal electrode, the method further includes:

[0018] Impurity ions in the semiconductor structure after the formation of the second doped region are activated by thermal annealing.

[0019] Optionally, in the method for fabricating the superjunction trench gate terminal structure, the junction depth of the body region is less than or equal to the depth of the trench.

[0020] Optionally, in the fabrication method of the superjunction trench gate terminal structure, the substrate has an N-type conductivity; the dopant ions in the epitaxial layer have an N-type conductivity; the dopant ions in the type region have a P-type conductivity; the dopant ions in the bulk region have a P-type conductivity; the dopant ions in the first heavily doped region have an N-type conductivity; the dopant ions in the pillar region have a P-type conductivity; and the dopant ions in the second heavily doped region have a P-type conductivity.

[0021] On the other hand, embodiments of this application also provide a superjunction trench gate termination structure, including:

[0022] A substrate on which an epitaxial layer is formed;

[0023] The type region is located in the epitaxial layer, wherein at least two ion implantation processes are performed to form the type region in the epitaxial layer;

[0024] A trench gate structure, wherein the trench gate structure is located in the type region and in the epitaxial layer outside the type region;

[0025] A body region, which is located in the type region and in the epitaxial layer outside the type region;

[0026] The first doped region is located in the body region outside the type region;

[0027] The pillar region is located at the bottom of the body region outside the type region;

[0028] Metal electrode, the metal electrode being located in the first heavily doped region and the body region outside the type region, and on a portion of the trench gate structure surface outside the type region;

[0029] The second doped region is located in the body region at the bottom of the metal electrode.

[0030] Optionally, in the superjunction trench gate termination structure, during each ion implantation process to form a type region in the epitaxial layer, the ion implantation energy is 400 keV to 3000 keV; the ion implantation dose is 1.0E12 atoms / cm². 2 ~1.0E13 atoms / cm 2 .

[0031] Optionally, in the superjunction trench gate terminal structure, the junction depth of the body region is less than or equal to the depth of the trench.

[0032] Optionally, in the superjunction trench gate termination structure, the substrate has an N-type conductivity; the dopant ions in the epitaxial layer have an N-type conductivity; the dopant ions in the type region have a P-type conductivity; the dopant ions in the body region have a P-type conductivity; the dopant ions in the first heavily doped region have an N-type conductivity; the dopant ions in the pillar region have a P-type conductivity; and the dopant ions in the second heavily doped region have a P-type conductivity.

[0033] The technical solution of this application has at least the following advantages:

[0034] This application performs at least two ion implantation processes to form a type region in the epitaxial layer. Through multi-step high-energy ion implantation, the type region is formed in the epitaxial layer, compensating for the epitaxial layer and mutually depleting it. This significantly reduces the concentration of the terminal drift region (the epitaxial layer), thereby reducing the doping concentration of the epitaxial layer and improving the breakdown voltage of the terminal. Simultaneously, the floating trench gate structure in the type region further enhances the overall breakdown voltage of the device. Compared to traditional superjunction terminal structures, where the triangular electric field peak at the PN pillar interface is easily affected by process deviations such as the width, spacing, and concentration of the superjunction pillars, leading to premature breakdown at the device terminal surface, the superjunction trench gate terminal structure provided in this application has a larger PN junction curvature radius and better process reliability.

[0035] Furthermore, the superjunction trench gate termination structure provided in this application does not change with the cell breakdown voltage, and can independently optimize the cell region and termination region of the DMOS device, reducing optimization difficulty and shortening the development time.

[0036] Furthermore, the fabrication method of the superjunction trench gate termination structure provided in this application is compatible with conventional DMOS device processes. There are no technical difficulties in implementing the fabrication process, and it will not increase the cost of fabricating DMOS devices. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a flowchart of the fabrication method of the superjunction trench gate terminal structure according to an embodiment of the present invention;

[0039] Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the superjunction trench gate terminal structure according to an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram comparing the BV curves of a traditional superjunction trench gate terminal structure and the BV curves of a superjunction trench gate terminal structure according to an embodiment of the present invention.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 1-Substrate, 2-Epipolar layer, 3-Gate dielectric layer, 4-Polysilicon gate, 5-Bulk region, 6-First heavily doped region, 7-Pillar region, 8-Second heavily doped region, 9-Metal electrode, 10-Type region. Detailed Implementation

[0043] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0046] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0047] This application provides a method for fabricating a superjunction trench gate terminal structure, referencing... Figure 1 , Figure 1 This is a flowchart illustrating the fabrication method of the superjunction trench gate termination structure according to an embodiment of the present invention. Specifically, refer to... Figures 2-5 , Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of preparing the superjunction trench gate terminal structure according to an embodiment of the present invention.

[0048] The fabrication method of the superjunction trench gate terminal structure includes:

[0049] Step S10: As Figure 2 As shown, a substrate 1 is provided, on which an epitaxial layer 2 is formed. In this embodiment, the conductivity type of the substrate 1 can be N-type; a drift region is formed in the entire epitaxial layer 2, and the conductivity type of the doped ions in the drift region can be N-type.

[0050] Step S20: As Figure 2 As shown, at least two ion implantation processes are performed to form type region 10 in the epitaxial layer 2. Specifically, the dopant ions in type region 10 are of P-type conductivity. In this embodiment, six to eight P-type impurity ion (e.g., boron ion) implantation processes are performed to form type region 10 in the epitaxial layer 2.

[0051] Furthermore, during each ion implantation process to form the type region 10 in the epitaxial layer 2, the ion implantation energy can be 400 keV to 3000 keV; the ion implantation dose can be 1.0E12 atoms / cm. 2 ~1.0E13 atoms / cm 2 .

[0052] Step S30: As Figure 3 As shown, the epitaxial layer 2 is etched to form a plurality of trenches in the epitaxial layer 2 in the type region 10 and outside the type region 10;

[0053] Step S40: As Figure 3 As shown, a trench gate structure is formed, which fills the trench. Specifically, the steps of forming the trench gate structure may include: forming a gate dielectric layer 3 covering the sidewalls and bottom wall of the trench; and filling the remaining space of the trench with a polysilicon gate 4.

[0054] In this embodiment, the gate dielectric layer 3 can be formed in the trench by thermal oxidation or deposition.

[0055] Furthermore, the step of filling the remaining space in the trench with the polysilicon gate 4 may include:

[0056] The remaining space in the trench is filled with polycrystalline silicon material;

[0057] The polysilicon material extending beyond the surface of the epitaxial layer 2 at the top of the trench is removed by CMP grinding to form the polysilicon gate 4.

[0058] Step S50: As Figure 4As shown, an ion implantation process is performed to form a body region 5 in the type region 10 and in the epitaxial layer 2 outside the type region 10. Specifically, the dopant ions in the body region 5 are P-type. In this embodiment, ion implantation and annealing push-well processes can be used to implant P-type impurity ions to form a P-type body region 5. In this embodiment, the junction depth of the body region 5 is less than or equal to the depth of the trench.

[0059] Step S60: As Figure 4 As shown, an ion implantation process is performed to form a first heavily doped region 6 in the body region 5 outside the type region 10. Specifically, the conductivity type of the dopant ions in the first heavily doped region 6 is N-type. In this embodiment, N-type impurity ions are implanted to form the first heavily doped region 6 located on the surface of the P-type body region 5, which is the source region.

[0060] Step S70: As Figure 4 As shown, an ion implantation process is performed to form a pillar region 7 at the bottom of the body region 6 outside the type region 10. Specifically, the conductivity type of the doped ions in the pillar region is P-type. In this embodiment, photolithography, etching, and ion implantation processes are used to implant P-type impurity ions with different energies and doses, selectively implanting P-type impurity ions between the trench gate structures to form the P-Pillar region 7.

[0061] Step S80: As Figure 5 As shown, the first heavily doped region 6 and the body region 5 outside the type region 10 are etched to form the opening of the contact hole. At the same time, a portion of the trench gate structure outside the type region 10 (excluding the trench gate structure outside the type region 10 that is close to the type region 10, the rest of the trench gate structures outside the type region 10) are etched to form shallower openings. That is, shallower openings are formed on the surface of the trench gate structure (the polysilicon gate 4) away from the type region 10, and deeper openings are formed in the first heavily doped region 6 and the body region 5 outside the type region 10.

[0062] In this embodiment, in the same etching process, openings of different depths can be formed according to different opening depth requirements.

[0063] Step S90: Perform an ion implantation process to form a second heavily doped region 8 in the bottom wall and part of the sidewall of the opening in the first heavily doped region 6 and the body region 5 (on the surface of the body region 5 outside the type region 10). Specifically, the conductivity type of the dopant ions in the second heavily doped region is P-type. In this embodiment, P-type impurity ions with different energies and doses are implanted to form the second heavily doped region 8 on the surface of the body region 5 outside the type region 10.

[0064] Furthermore, after forming the second doped region 8, the fabrication method of the superjunction trench gate termination structure may further include:

[0065] Impurity ions in each region of the semiconductor structure after the formation of the second doped region 8 are activated by thermal annealing.

[0066] Step S100: Form a metal electrode 9, which fills the openings in the first heavily doped region 6 and the body region 5, as well as the shallower openings on the surface of the polysilicon gate 4.

[0067] It is worth noting that the trench gate structures in the type region are all floating and do not require metal electrodes to be brought out. In other words, the trench gate structures in the type region are all floating trench gate structures.

[0068] refer to Figure 6 , Figure 6 This is a schematic diagram comparing the BV curves of a traditional superjunction trench gate termination structure and the BV curves of the superjunction trench gate termination structure according to an embodiment of the present invention. From... Figure 6 As can be seen, the BV of the traditional structure / structure1 is 84.3V, while the BV of the superjunction trench gate termination structure (new structure / structure2) of this invention is 96.9V. This application performs at least two ion implantation processes to form the type region 10 in the epitaxial layer 2, that is, by multi-step high-energy ion implantation, the type region 10 is formed in the epitaxial layer 2. The type region 10 compensates for the epitaxial layer 2, mutually depleting with the epitaxial layer 2 (N-epi), thereby significantly reducing the concentration of the terminal N-type drift region (the epitaxial layer 2), thus reducing the doping concentration of the epitaxial layer 2 to improve the breakdown voltage of the termination. Simultaneously, the floating trench gate structure in the type region further improves the overall breakdown voltage of the device. Compared to the traditional superjunction termination structure, where the triangular electric field peak at the PN pillar interface is easily affected by process deviations such as the width, spacing, and concentration between the superjunction pillars, leading to premature breakdown of the device termination surface, the superjunction trench gate termination structure provided in this application has a larger PN junction curvature radius and better process reliability.

[0069] Furthermore, the superjunction trench gate termination structure provided in this application does not change with the cell breakdown voltage, and can independently optimize the cell region and termination region of the DMOS device, reducing optimization difficulty and shortening the development time.

[0070] Furthermore, the fabrication method of the superjunction trench gate termination structure provided in this application is compatible with conventional DMOS device processes. There are no technical difficulties in implementing the fabrication process, and it will not increase the cost of fabricating DMOS devices.

[0071] Based on the same inventive concept, embodiments of this application also provide a superjunction trench gate termination structure, such as... Figure 5 As shown, the superjunction trench gate termination structure includes:

[0072] Substrate 1, wherein an epitaxial layer 2 is formed on substrate 1;

[0073] Type region 10, located in the epitaxial layer 2, wherein at least two ion implantation processes are performed to form type region 10 in the epitaxial layer 2;

[0074] A trench gate structure, wherein the trench gate structure is located in the type region 10 and in the epitaxial layer 2 outside the type region 10;

[0075] Body region 5, which is located in the type region 10 and in the epitaxial layer 2 outside the type region 10;

[0076] The first doped region 6 is located in the body region 5 outside the type region 10;

[0077] Pillar area 7, the pillar area 7 is located at the bottom of the body area 5 outside the type area 10;

[0078] Metal electrode 9, which is located in the first heavily doped region 8 and the body region 5 outside the type region 10;

[0079] The second doped region 8 is located in the body region 5 at the bottom of the metal electrode 9.

[0080] In this embodiment, six to eight P-type impurity ion (e.g., boron ion) implantation processes are performed to form type region 10 in the epitaxial layer 2. During each ion implantation process to form type region 10 in the epitaxial layer 2, the ion implantation energy can be 400 keV to 3000 keV; the ion implantation dose can be 1.0E12 atoms / cm². 2 ~1.0E13 atoms / cm 2 .

[0081] In this embodiment, the substrate 1 has an N-type conductivity; the dopant ions in the epitaxial layer 2 (drift region) have an N-type conductivity; the dopant ions in the type region 10 have a P-type conductivity; the dopant ions in the body region 5 have a P-type conductivity; the dopant ions in the first heavily doped region 6 have an N-type conductivity; the dopant ions in the pillar region 7 have a P-type conductivity; and the dopant ions in the second heavily doped region 8 have a P-type conductivity.

[0082] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a superjunction trench gate terminal structure, characterized in that, include: A substrate is provided on which an epitaxial layer is formed; Perform at least two ion implantation processes to form a type region in the epitaxial layer; The epitaxial layer is etched to form a plurality of trenches in the epitaxial layer in and outside the type region; A trench grid structure is formed, the trench grid structure fills the trench, wherein the type area is adjacent to the trench grid structure outside the type area; An ion implantation process is performed to form a bulk region in the type region and in the epitaxial layer outside the type region; An ion implantation process is performed to form a first heavily doped region in the body region outside the type region; An ion implantation process is performed to form a pillar region at the bottom of the body region outside the type region; Etch the first heavily doped region outside the type region, the body region, and part of the trench gate structure to form an opening; An ion implantation process is performed to form a second heavily doped region in the bottom wall and part of the sidewall of the opening in the first heavily doped region and the body region; A metal electrode is formed, which fills the opening.

2. The method for fabricating the superjunction trench gate terminal structure according to claim 1, characterized in that, During each ion implantation process to form a type region in the epitaxial layer, the ion implantation energy is 400 keV to 3000 keV; the ion implantation dose is 1.0E12 atoms / cm². 2 ~1.0E13 atoms / cm 2 .

3. The method for fabricating the superjunction trench gate terminal structure according to claim 1, characterized in that, The fabrication method of the superjunction trench gate termination structure, after the formation of the second doped region and before the formation of the metal electrode, further includes: Impurity ions in the semiconductor structure after the formation of the second doped region are activated by thermal annealing.

4. The method for fabricating the superjunction trench gate terminal structure according to claim 1, characterized in that, The depth of the body region is less than or equal to the depth of the trench.

5. The method for fabricating the superjunction trench gate terminal structure according to claim 1, characterized in that, The substrate has an N-type conductivity; the dopant ions in the epitaxial layer have an N-type conductivity; the dopant ions in the type region have a P-type conductivity; the dopant ions in the bulk region have a P-type conductivity; the dopant ions in the first heavily doped region have an N-type conductivity; the dopant ions in the pillar region have a P-type conductivity; and the dopant ions in the second heavily doped region have a P-type conductivity.

6. A superjunction trench gate terminal structure, characterized in that, include: A substrate on which an epitaxial layer is formed; The type region is located in the epitaxial layer, wherein at least two ion implantation processes are performed to form the type region in the epitaxial layer; A trench gate structure is located in the type region and in the epitaxial layer outside the type region, wherein the type region is adjacent to the trench gate structure outside the type region; A body region, which is located in the type region and in the epitaxial layer outside the type region; The first doped region is located in the body region outside the type region; The pillar region is located at the bottom of the body region outside the type region; Metal electrode, the metal electrode being located in the first heavily doped region and the body region outside the type region, and on a portion of the trench gate structure surface outside the type region; The second doped region is located in the body region at the bottom of the metal electrode.

7. The superjunction trench gate terminal structure according to claim 6, characterized in that, During each ion implantation process to form a type region in the epitaxial layer, the ion implantation energy is 400 keV to 3000 keV; the ion implantation dose is 1.0E12 atoms / cm². 2 ~1.0E13 atoms / cm 2 .

8. The superjunction trench gate terminal structure according to claim 6, characterized in that, The depth of the body region is less than or equal to the depth of the trench.

9. The superjunction trench gate terminal structure according to claim 6, characterized in that, The substrate has an N-type conductivity; the dopant ions in the epitaxial layer have an N-type conductivity; the dopant ions in the type region have a P-type conductivity; the dopant ions in the bulk region have a P-type conductivity; the dopant ions in the first heavily doped region have an N-type conductivity; the dopant ions in the pillar region have a P-type conductivity; and the dopant ions in the second heavily doped region have a P-type conductivity.

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