Power semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a power semiconductor device and a preparation method thereof, and belongs to the field of semiconductor power electronics. The power semiconductor device comprises an epitaxial wafer, an anode electrode and a cathode electrode; the epitaxial wafer comprises a substrate and a buffer layer, a GaN layer, an AlGaN layer, a GaN cap layer and a SiN protective layer formed on the substrate in sequence; the anode electrode and the cathode electrode are spaced apart from each other, and both the anode electrode and the cathode electrode are embedded in the AlGaN layer and the GaN cap layer; the anode electrode comprises a GaN part and a Schottky metal electrode part stacked in sequence in the epitaxial growth direction; and the cathode electrode comprises a heavily doped N-type GaN part and an ohmic metal electrode part stacked in sequence in the epitaxial growth direction. The present disclosure can improve the electric field distribution and improve the reliability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor power electronics, and in particular to a power semiconductor device and its fabrication method. Background Technology

[0002] Power semiconductor devices are power electronic devices, mainly used in high-power electronic devices for power conversion and control circuits in power equipment.

[0003] In related technologies, power semiconductor devices mainly include epitaxial wafers, anodes, and cathodes, with both anodes and cathodes connected to the epitaxial wafer.

[0004] However, uneven electric field distribution is prone to occur in power semiconductor devices, which can lead to current congestion at the anode and cathode. Summary of the Invention

[0005] This disclosure provides an epitaxial wafer for a power semiconductor device and a method for fabricating the same, which can improve electric field distribution and increase reliability. The technical solution is as follows:

[0006] On one hand, embodiments of this disclosure provide a power semiconductor device, which includes an epitaxial wafer, a positive electrode, and a negative electrode;

[0007] The epitaxial wafer includes a substrate and a buffer layer, a GaN layer, an AlGaN layer, a GaN cap layer, and a SiN protective layer sequentially formed on the substrate;

[0008] The anode and cathode are spaced apart from each other, and both the anode and cathode are embedded in the AlGaN layer and the GaN cap layer. The anode includes a GaN portion and a Schottky metal electrode portion stacked sequentially in the epitaxial growth direction, and the cathode includes a heavily doped N-type GaN portion and an ohmic metal electrode portion stacked sequentially in the epitaxial growth direction.

[0009] In one implementation of this disclosure, the GaN portion is located within the AlGaN layer;

[0010] The Schottky metal electrode portion is located partly within the AlGaN layer and partly within the GaN cap layer.

[0011] In one implementation of this disclosure, the GaN portion and the GaN layer are spaced apart from each other, and the distance between the side of the GaN portion near the GaN layer and the side of the AlGaN layer near the GaN cap layer is 1nm-15nm.

[0012] In one implementation of this disclosure, in the direction from the Schottky metal electrode portion to the GaN portion, the anode is inclined toward the cathode on the side facing the cathode.

[0013] In one implementation of this disclosure, the heavily doped N-type GaN portion is located within the AlGaN layer;

[0014] One part of the ohmic metal electrode is located within the AlGaN layer, and the other part is located within the GaN cap layer.

[0015] In one implementation of this disclosure, the heavily doped N-type GaN portion is in contact with the GaN layer.

[0016] In one implementation of this disclosure, in the direction from the ohmic metal electrode portion to the heavily N-doped GaN portion, the cathode electrode is inclined toward the anode electrode on the side facing the anode electrode.

[0017] On the other hand, this disclosure also provides a method for fabricating a power semiconductor device, the method comprising:

[0018] Provide a substrate;

[0019] A buffer layer, a GaN layer, an AlGaN layer, a GaN cap layer, and a SiN protective layer are epitaxially grown sequentially on the substrate.

[0020] A positive electrode is provided, and the positive electrode is embedded in the AlGaN layer and the GaN cap layer, such that the GaN part and the Schottky metal electrode part of the positive electrode are stacked sequentially in the epitaxial growth direction.

[0021] A cathode is provided and embedded within the AlGaN layer and the GaN cap layer, such that the heavily doped N-type GaN portion and the ohmic metal electrode portion of the cathode are stacked sequentially in the epitaxial growth direction.

[0022] In one implementation of this disclosure, the AlGaN layer and the GaN cap layer are periodically and alternately stacked, and the number of alternation periods between the AlGaN layer and the GaN cap layer is 1-6.

[0023] In one implementation of this disclosure, the Al molar content of the AlGaN layer is 0.07-0.30, and the thickness of the AlGaN layer is 10nm-40nm;

[0024] The thickness of the GaN cap layer is 5nm-30nm.

[0025] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0026] Since both the anode and cathode are embedded within the AlGaN layer and GaN cap layer, the embedded electrodes improve carrier transport behavior. Furthermore, because the cathode comprises a heavily doped N-type GaN portion and an ohmic metal electrode portion, the heavily doped N-type GaN portion can be used as an intermediary to achieve good ohmic contact between the ohmic metal electrode portion and the epitaxial wafer. Moreover, since the anode comprises a GaN portion and a Schottky metal electrode portion, and the GaN portion has a high work function, it is difficult to form an ohmic contact with the Schottky metal electrode portion. Therefore, this not only increases the potential barrier but also avoids electric field concentration at the anode, preventing localized breakdown. Additionally, because the epitaxial wafer includes a GaN cap layer and a SiN protective layer, it is protected from leakage current caused by surface adsorption and interface changes, further improving the reliability of the power semiconductor device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a power semiconductor device provided in an embodiment of this disclosure;

[0029] Figure 2 This is a flowchart of a method for fabricating a power semiconductor device according to an embodiment of this disclosure;

[0030] Figure 3 This is a flowchart of another method for fabricating a power semiconductor device provided in this disclosure embodiment;

[0031] Figure 4 This is a schematic diagram illustrating the fabrication process of a power semiconductor device according to an embodiment of this disclosure;

[0032] Figure 5 This is a schematic diagram illustrating the fabrication process of a power semiconductor device according to an embodiment of this disclosure;

[0033] Figure 6 This is a schematic diagram illustrating the fabrication process of a power semiconductor device according to an embodiment of this disclosure;

[0034] Figure 7 This is a schematic diagram illustrating the fabrication process of a power semiconductor device according to an embodiment of this disclosure;

[0035] Figure 8 This is a schematic diagram of the fabrication process of a power semiconductor device provided in an embodiment of this disclosure.

[0036] Example in the image is as follows:

[0037] 10. Epitaxial wafer;

[0038] 110. Substrate; 120. Buffer layer; 130. GaN layer; 140. AlGaN layer; 150. GaN cap layer; 160. SiN protective layer;

[0039] 20. Anode;

[0040] 210. GaN section; 220. Schottky metal electrode section;

[0041] 30. Cathode;

[0042] 310. Heavy N-doped GaN section; 320. Ohmic metal electrode section. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0044] Power semiconductor devices are power electronic devices, mainly used in high-power electronic devices for power conversion and control circuits in power equipment.

[0045] Currently, with the shrinking size and limitations of physical properties, silicon devices have reached their physical limits. To further improve device performance, new materials must be developed. Wide bandgap materials such as SiC, GaN, AlN, and diamond have attracted widespread attention from the industry due to their advantages in high-density power and high-temperature adaptability. SiC-based power devices have already been commercially available in high-voltage and high-power applications. Among these wide bandgap materials, GaN has a higher electron mobility than SiC and a higher breakdown electric field strength than Si. GaN-based devices are expected to meet the needs of advanced power device systems, including RF and power conversion equipment applications.

[0046] Power diodes are crucial components in power conversion and inverters. Due to the excellent physicochemical properties of GaN, GaN-based power diodes can significantly improve conversion efficiency and reduce power loss. Since 2000, GaN-based rectifiers have become a hot research area. Because of the lack of minority carrier accumulation and lower barrier height, GaN Schottky diodes operate at higher frequencies with lower operating conditions, giving them an advantage over PN junction diodes. However, semi-vertical GaN Schottky diodes suffer from uneven current distribution, leading to current congestion and affecting the application of the semi-vertical structure.

[0047] To address the aforementioned technical problems, this disclosure provides a power semiconductor device. Figure 1 This is a schematic diagram of the power semiconductor device. (See attached diagram) Figure 1 In this embodiment, it includes an epitaxial wafer 10, a positive electrode 20, and a negative electrode 30.

[0048] The epitaxial wafer 10 includes a substrate 110 and a buffer layer 120, a GaN layer 130, an AlGaN layer 140, a GaN cap layer 150, and a SiN protective layer 160 sequentially formed on the substrate 110. Anode 20 and cathode 30 are spaced apart from each other, and both are embedded within the AlGaN layer 140 and the GaN cap layer 150. Anode 20 includes a GaN portion 210 and a Schottky metal electrode portion 220 sequentially stacked in the epitaxial growth direction, and cathode 30 includes a heavily doped N-type GaN portion 310 and an ohmic metal electrode portion 320 sequentially stacked in the epitaxial growth direction.

[0049] In this embodiment, since both the anode 20 and cathode 30 are embedded within the AlGaN layer and GaN cap layer, the embedded electrodes improve carrier transport behavior. Furthermore, since the cathode 30 includes a heavily doped N-type GaN portion 310 and an ohmic metal electrode portion 320, the heavily doped N-type GaN portion 310 can be used as an intermediary to achieve good ohmic contact between the ohmic metal electrode portion 320 and the epitaxial wafer 10. Moreover, since the anode 20 includes a GaN portion 210 and a Schottky metal electrode portion 220, and the GaN portion 210 has a high work function, it is difficult to form an ohmic contact with the Schottky metal electrode portion 220. Therefore, this not only increases the potential barrier but also avoids electric field concentration at the anode 20, preventing localized breakdown. Additionally, since the epitaxial wafer 10 includes a GaN cap layer 150 and a SiN protective layer 160, the epitaxial wafer 10 is protected from leakage current caused by surface adsorption and interface changes, further improving the reliability of the power semiconductor device.

[0050] As mentioned above, the embedded anode 20 and cathode 30 are key to improving the electric field distribution. The anode 20 and cathode 30 will be described in detail below.

[0051] In this embodiment, the GaN portion 210 is located within the AlGaN layer 140, and the Schottky metal electrode portion 220 is partially located within the AlGaN layer 140 and partially located within the GaN cap layer 150.

[0052] In the above implementation, the contact between the GaN portion 210 and the Schottky metal electrode portion 220 is located within the AlGaN layer 140. On the one hand, this improves the local concentration of the reverse electric field, and on the other hand, the local heterojunction achieves the adjustment of the electric field, which is uniformly distributed under the Schottky layer, effectively increasing the breakdown voltage while reducing the operating voltage during forward conduction.

[0053] For example, the GaN portion 210 and the GaN layer 130 are spaced apart from each other, and the distance between the side of the GaN portion 210 near the GaN layer 130 and the side of the AlGaN layer 140 near the GaN cap layer 150 is 1nm-15nm.

[0054] In the above implementation, the GaN portion 210 penetrates the GaN cap layer 150 and is inserted into the AlGaN layer 140. The insertion depth of the GaN portion 210 in the AlGaN layer 140 is 1nm-15nm, which can ensure sufficient and stable contact between the anode 20 and the AlGaN layer 140.

[0055] In this embodiment, in the direction from the Schottky metal electrode portion 220 to the GaN portion 210, the anode 20 is inclined toward the cathode 30 on the side facing the cathode 30.

[0056] In the above implementation, the longitudinal section of the anode 20 is a right-angled trapezoid. The upper base of the trapezoid is the side of the Schottky metal electrode portion 220 away from the GaN portion 210, and the lower base is the side of the GaN portion 210 away from the Schottky metal electrode portion 220. The height of the trapezoid is away from the cathode 30 and perpendicular to the AlGaN layer 140. The sloping side of the trapezoid is close to the cathode 30 and inclined towards the AlGaN layer 140, which is the inclined side of the anode 20. This design increases the contact area between the anode 20 and the epitaxial wafer 10, thereby improving the electric field distribution at the anode 20 and cathode 30, preventing the appearance of sharp points in local locations, and greatly contributing to the stability of the reliability of power semiconductor devices at high temperatures.

[0057] In this embodiment, the heavily N-doped GaN portion 310 is located within the AlGaN layer 140, and the ohmic metal electrode portion 320 is partly located within the AlGaN layer 140 and partly located within the GaN cap layer 150.

[0058] In the above implementation, the contact between the heavily doped N-type GaN portion 310 and the ohmic metal electrode portion 320 is better, which can effectively reduce the contact resistance and thus facilitate the uniform distribution of the electric field.

[0059] For example, the heavily doped N-type GaN portion 310 is in contact with the GaN layer 130.

[0060] In the above implementation, the side of the heavily doped N-type GaN portion 310 furthest from the ohmic metal electrode portion 320 contacts the side of the GaN layer 130 closest to the AlGaN layer 140. This design not only ensures sufficient and stable contact between the cathode 30 and the AlGaN layer 140, but also reduces the contact resistance, thereby facilitating a uniform distribution of the electric field.

[0061] In this embodiment, in the direction from the ohmic metal electrode portion 320 to the heavily N-doped GaN portion 310, the cathode 30 is inclined toward the anode 20 on the side facing the anode 20.

[0062] In the above implementation, the longitudinal section of the cathode 30 is a right-angled trapezoid. The upper base of the trapezoid is the side of the ohmic metal electrode portion 320 away from the heavily doped N-type GaN portion 310, and the lower base is also the side of the heavily doped N-type GaN portion 310 away from the ohmic metal electrode portion 320. The height of the trapezoid is away from the anode 20 and perpendicular to the AlGaN layer 140. The sloping side of the trapezoid is close to the anode 20 and inclined towards the AlGaN layer 140, which is the inclined side of the cathode 30. This design increases the contact area between the cathode 30 and the epitaxial wafer 10, thereby improving the electric field distribution at the cathode 30 and anode 20, preventing the appearance of sharp points in local locations, and greatly contributing to the stability of the reliability of power semiconductor devices at high temperatures.

[0063] In this embodiment, the tilting direction of the anode 20 is opposite to that of the cathode 30, which makes the bottom distance between the anode 20 and the cathode 30 smaller and the top distance larger, thereby increasing the contact area between the anode 20 and the cathode 30 and the epitaxial wafer 10.

[0064] For example, the substrate 110 can be a single crystal material such as sapphire, silicon wafer, quartz wafer, silicon carbide, diamond, or GaAs, InP, AlN, GaN, etc., and its size can be 2 inches or larger. The substrate 110 can be a flat substrate 110 or a patterned substrate 110.

[0065] As an example, in this embodiment of the disclosure, the substrate 110 is a sapphire substrate 110. The sapphire substrate 110 is a commonly used substrate 110, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 110 or a flat sapphire substrate 110.

[0066] Figure 2 This is a flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of the present disclosure. This method is capable of fabricating... Figure 1 The power semiconductor device shown. Combined with... Figure 2 In this embodiment, the preparation method includes:

[0067] Step 201: Provide a substrate 110.

[0068] Step 202: Epitaxially grow a buffer layer 120, a GaN layer 130, an AlGaN layer 140, a GaN cap layer 150, and a SiN protective layer 160 sequentially on the substrate 110.

[0069] Step 203: Provide a positive electrode 20 and embed the positive electrode 20 into the AlGaN layer 140 and the GaN cap layer 150, such that the GaN portion 210 and the Schottky metal electrode portion 220 of the positive electrode 20 are stacked sequentially in the epitaxial growth direction.

[0070] Step 204: Provide a cathode 30 and embed the cathode 30 into the AlGaN layer 140 and the GaN cap layer 150, such that the heavily doped N-type GaN portion 310 and the ohmic metal electrode portion 320 of the cathode 30 are stacked sequentially in the epitaxial growth direction.

[0071] Since both the anode 20 and cathode 30 are embedded within the AlGaN layer and GaN cap layer, the embedded electrodes improve carrier transport behavior. Furthermore, because the cathode 30 includes a heavily doped N-type GaN portion 310 and an ohmic metal electrode portion 320, the heavily doped N-type GaN portion 310 can be used as an intermediary to achieve good ohmic contact between the ohmic metal electrode portion 320 and the epitaxial wafer 10. Moreover, since the anode 20 includes a GaN portion 210 and a Schottky metal electrode portion 220, and the GaN portion 210 has a high work function, it is difficult to form an ohmic contact with the Schottky metal electrode portion 220. Therefore, this not only increases the potential barrier but also avoids electric field concentration at the anode 20, preventing localized breakdown. Additionally, because the epitaxial wafer 10 includes a GaN cap layer 150 and a SiN protective layer 160, the epitaxial wafer 10 is protected from leakage current caused by surface adsorption and interface changes, further improving the reliability of the power semiconductor device.

[0072] Figure 3 A flowchart illustrating another method for fabricating a power semiconductor device provided in this disclosure, the method being capable of fabricating... Figure 1 The power semiconductor device shown. Combined with... Figure 3 In this embodiment, the preparation method includes:

[0073] Step 301: Provide a substrate 110.

[0074] For example, the substrate 110 can be a single crystal material such as sapphire, silicon wafer, quartz wafer, silicon carbide, diamond, or GaAs, InP, AlN, GaN, etc., and its size can be 2 inches or larger. The substrate 110 can be a flat substrate 110 or a patterned substrate 110.

[0075] As an example, in this embodiment of the disclosure, the substrate 110 is a sapphire substrate 110. The sapphire substrate 110 is a commonly used substrate 110, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 110 or a flat sapphire substrate 110.

[0076] For example, the substrate 110 is annealed in a hydrogen atmosphere for 8 minutes to clean the surface of the substrate 110 at a temperature between 1000°C and 1200°C, and then nitrided.

[0077] For example, the temperature is 1100°C.

[0078] Step 302: Epitaxially grow a buffer layer 120 on substrate 110 (see...) Figure 4 ).

[0079] For example, a buffer layer 120 with a thickness of 0.5 μm to 2.0 μm is grown. The buffer layer includes a nucleation layer, a healing layer, and a thick layer. The nucleation layer can be a single layer of AlN, AlGaN, GaN, or InN, or a stack of AlN, AlGaN, GaN, and InN. The healing layer enables the connection and flattening of the granular nucleation layer. Subsequently, thick layer growth is performed, with a defect density of 10. 7 -10 8 cm -3 .

[0080] It should be noted that the quality of the final epitaxial wafer 10 will vary depending on the thickness of the buffer layer 120. If the buffer layer 120 is too thin, its surface will be relatively loose and rough, failing to provide a good template for the growth of subsequent structures. As the thickness of the buffer layer 120 increases, its surface gradually becomes denser and smoother, which is beneficial for the growth of subsequent structures. However, if the buffer layer 120 is too thick, its surface will be too dense, which is also detrimental to the growth of subsequent structures and will not reduce lattice defects in the epitaxial layer.

[0081] Step 303: Grow GaN layer 130 on buffer layer 120 (see...) Figure 5 ).

[0082] For example, a GaN layer 130 with a thickness of 2nm-10nm is grown, and the defect density is 10-1. 6 -10 7 cm -3 .

[0083] Step 304: Grow AlGaN layer 140 and GaN cap layer 150 on GaN layer 130 (see...) Figure 6 ).

[0084] For example, the Al molar content of Al in AlGaN layer 140 is 0.07-0.30, and the thickness of AlGaN layer 140 is 10nm-40nm.

[0085] For example, the thickness of the GaN cap layer 150 is 5nm-30nm.

[0086] In this embodiment, the AlGaN layer 140 and the GaN cap layer 150 are periodically stacked and grown alternately, and the number of alternation periods of the AlGaN layer 140 and the GaN cap layer 150 is 1-6.

[0087] Step 305: Grow a SiN protective layer 160 on the GaN cap layer 150 (see...) Figure 7 ).

[0088] In this embodiment, after the SiN protective layer 160 is grown, the epitaxial wafer 10 is grown, and after the epitaxial wafer 10 is cooled to room temperature, it is taken out and processed into a chip through semiconductor processes such as cleaning, deposition, photolithography and etching.

[0089] Step 306: Provide a positive electrode 20, embedding the positive electrode 20 into the AlGaN layer 140 and the GaN cap layer 150, such that the GaN portion 210 and the Schottky metal electrode portion 220 of the positive electrode 20 are sequentially stacked in the epitaxial growth direction (see...). Figure 8 ).

[0090] In this embodiment, the anode 20 includes a connected GaN portion 210 and a Schottky metal electrode portion 220. The GaN portion 210 is located within the AlGaN layer 140, and a portion of the Schottky metal electrode portion 220 is located within the AlGaN layer 140, while another portion is located within the GaN cap layer 150.

[0091] In the above implementation, the contact between the GaN portion 210 and the Schottky metal electrode portion 220 is located within the AlGaN layer 140. On the one hand, this improves the local concentration of the reverse electric field, and on the other hand, the local heterojunction achieves the adjustment of the electric field, which is uniformly distributed under the Schottky layer, effectively increasing the breakdown voltage while reducing the operating voltage during forward conduction.

[0092] In this embodiment, in the direction from the Schottky metal electrode portion 220 to the GaN portion 210, the anode 20 is inclined toward the cathode 30 on the side facing the cathode 30.

[0093] In the above implementation, the longitudinal section of the anode 20 is a right-angled trapezoid. The upper base of the trapezoid is the side of the Schottky metal electrode portion 220 away from the GaN portion 210, and the lower base is the side of the GaN portion 210 away from the Schottky metal electrode portion 220. The height of the trapezoid is away from the cathode 30 and perpendicular to the AlGaN layer 140. The sloping side of the trapezoid is close to the cathode 30 and inclined towards the AlGaN layer 140, which is the inclined side of the anode 20. This design increases the contact area between the anode 20 and the epitaxial wafer 10, thereby improving the electric field distribution at the anode 20 and cathode 30, preventing the appearance of sharp points in local locations, and greatly contributing to the stability of the reliability of power semiconductor devices at high temperatures.

[0094] Step 307: Provide a cathode 30, embedding the cathode 30 into the AlGaN layer 140 and the GaN cap layer 150, such that the heavily doped N-type GaN portion 310 and the ohmic metal electrode portion 320 of the cathode 30 are sequentially stacked in the epitaxial growth direction (see...). Figure 1 ).

[0095] In this embodiment, the cathode 30 includes a heavily doped N-type GaN portion 310 and an ohmic metal electrode portion 320 connected together. The heavily doped N-type GaN portion 310 is located within the AlGaN layer 140, and a portion of the ohmic metal electrode portion 320 is located within the AlGaN layer 140 and another portion is located within the GaN cap layer 150.

[0096] In the above implementation, the contact between the heavily doped N-type GaN portion 310 and the ohmic metal electrode portion 320 is better, which can effectively reduce the contact resistance and thus facilitate the uniform distribution of the electric field.

[0097] In this embodiment, in the direction from the ohmic metal electrode portion 320 to the heavily N-doped GaN portion 310, the cathode 30 is inclined toward the anode 20 on the side facing the anode 20.

[0098] In the above implementation, the longitudinal section of the cathode 30 is a right-angled trapezoid. The upper base of the trapezoid is the side of the ohmic metal electrode portion 320 away from the heavily doped N-type GaN portion 310, and the lower base is also the side of the heavily doped N-type GaN portion 310 away from the ohmic metal electrode portion 320. The height of the trapezoid is away from the anode 20 and perpendicular to the AlGaN layer 140. The sloping side of the trapezoid is close to the anode 20 and inclined towards the AlGaN layer 140, which is the inclined side of the cathode 30. This design increases the contact area between the cathode 30 and the epitaxial wafer 10, thereby improving the electric field distribution at the cathode 30 and anode 20, preventing the appearance of sharp points in local locations, and greatly contributing to the stability of the reliability of power semiconductor devices at high temperatures.

[0099] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0100] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A power semiconductor device, characterized in that, It includes an epitaxial wafer (10), a positive electrode (20), and a negative electrode (30); The epitaxial wafer (10) includes a substrate (110) and a buffer layer (120), a GaN layer (130), an AlGaN layer (140), a GaN cap layer (150) and a SiN protective layer (160) sequentially formed on the substrate (110); The anode (20) and the cathode (30) are spaced apart from each other. Both the anode (20) and the cathode (30) are embedded in the AlGaN layer (140) and the GaN cap layer (150). The anode (20) includes a GaN portion (210) and a Schottky metal electrode portion (220) stacked sequentially in the epitaxial growth direction. The GaN portion (210) is located in the AlGaN layer (140). A portion of the Schottky metal electrode portion (220) is located in the AlGaN layer (140), and another portion is located in the GaN cap layer (150). The contact between the GaN portion (210) and the Schottky metal electrode portion (220) is located in the AlGaN layer (140). The cathode (30) includes a heavily doped N-type GaN portion (310) and an ohmic metal electrode portion (320) stacked sequentially in the epitaxial growth direction.

2. The power semiconductor device according to claim 1, characterized in that, The GaN portion (210) and the GaN layer (130) are spaced apart from each other. The distance between the side of the GaN portion (210) near the GaN layer (130) and the side of the AlGaN layer (140) near the GaN cap layer (150) is 1nm-15nm.

3. The power semiconductor device according to claim 1, characterized in that, In the direction from the Schottky metal electrode portion (220) to the GaN portion (210), the anode (20) is inclined toward the cathode (30) on the side facing the cathode (30).

4. The power semiconductor device according to claim 1, characterized in that, The heavily doped N-type GaN portion (310) is located within the AlGaN layer (140); One part of the ohmic metal electrode portion (320) is located within the AlGaN layer (140), and the other part is located within the GaN cap layer (150).

5. The power semiconductor device according to claim 4, characterized in that, The heavily N-doped GaN section (310) is in contact with the GaN layer (130).

6. The power semiconductor device according to claim 4, characterized in that, In the direction from the ohmic metal electrode portion (320) to the heavily N-doped GaN portion (310), the cathode electrode (30) is inclined toward the anode electrode (20) on the side facing the anode electrode (20).

7. A method for fabricating a power semiconductor device, characterized in that, include: A substrate (110) is provided; A buffer layer (120), a GaN layer (130), an AlGaN layer (140), a GaN cap layer (150), and a SiN protective layer (160) are epitaxially grown sequentially on the substrate (110); A positive electrode (20) is provided and embedded in the AlGaN layer (140) and GaN cap layer (150), such that the GaN portion (210) and the Schottky metal electrode portion (220) of the positive electrode (20) are stacked sequentially in the epitaxial growth direction. The GaN portion (210) is located in the AlGaN layer (140), and a portion of the Schottky metal electrode portion (220) is located in the AlGaN layer (140) and another portion is located in the GaN cap layer (150). The contact between the GaN portion (210) and the Schottky metal electrode portion (220) is located in the AlGaN layer (140). A cathode (30) is provided and embedded in the AlGaN layer (140) and GaN cap layer (150), such that the heavily doped N-type GaN portion (310) and the ohmic metal electrode portion (320) of the cathode (30) are stacked sequentially in the epitaxial growth direction.

8. The preparation method according to claim 7, characterized in that, The AlGaN layer (140) and the GaN cap layer (150) are periodically and alternately stacked, and the number of alternation periods of the AlGaN layer (140) and the GaN cap layer (150) is 1-6.

9. The preparation method according to claim 8, characterized in that, The Al molar content of the AlGaN layer (140) is 0.07-0.30, and the thickness of the AlGaN layer (140) is 10nm-40nm; The thickness of the GaN cap layer (150) is 5nm-30nm.

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