Light emitting diode and method for manufacturing light emitting diode

Abstract

The present application relates to the field of semiconductor technology, and specifically discloses a light emitting diode and a method for manufacturing the light emitting diode, wherein the light emitting diode comprises a strain compensation preparatory layer and a strain compensation matching light emitting region stacked on the strain compensation preparatory layer in a selective growth manner, wherein the strain compensation matching light emitting region has a first cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparatory layer and the strain compensation matching light emitting region, and the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light emitting region and the strain compensation preparatory layer are configured so that sufficient stress is generated in the strain compensation matching light emitting region, and the QCSE effect is utilized, so that the red shift amount generated by the QCSE effect in the strain compensation matching light emitting region is not less than 25nm. By the above method, the light efficiency of the light emitting diode can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, in particular to a light emitting diode and a method for manufacturing the light emitting diode. Background Art

[0002] Light-emitting diode (LED) is a photoelectric device that converts electrical energy into light energy and is widely used in lighting, backlighting and display.

[0003] The inventors of this application found in the long-term research and development process that the prior art usually uses chip technology to etch isolation grooves to prepare micro-LED chip units, which causes damage to the sidewalls of the micro-LED chip units and leads to loss of luminous efficiency. In addition, when the existing epitaxial process grows high-In component long-waveband materials, due to the instability of In-N bonds at high temperatures and the high desorption rate of In, the general growth temperature is not higher than 800°C. However, at low temperatures, the crystal quality deteriorates, which is not conducive to the LED device to obtain high light efficiency.

[0004] Therefore, it is necessary to design a light emitting diode that can improve the light efficiency. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a light emitting diode and a method for manufacturing the light emitting diode, which can improve the light efficiency of the light emitting diode.

[0006] On the one hand, the present application provides a light-emitting diode, which includes a strain compensation preparation layer and a strain compensation matching light-emitting region stacked on the strain compensation preparation layer in a selective growth manner, wherein the strain compensation matching light-emitting region has a first cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparation layer and the strain compensation matching light-emitting region, and the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light-emitting region and the strain compensation preparation layer are configured so as to generate sufficient stress in the strain compensation matching light-emitting region, utilize the QCSE effect, and thereby ensure that the red shift generated by the QCSE effect in the strain compensation matching light-emitting region is not less than 25 nm.

[0007] On the other hand, the present application provides a method for manufacturing a light-emitting diode, the manufacturing method comprising: providing a strain compensation preparatory layer; selectively growing a strain compensation matching light-emitting region on the strain compensation preparatory layer; wherein the strain compensation matching light-emitting region has a first cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparatory layer and the strain compensation matching light-emitting region, and the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light-emitting region and the strain compensation preparatory layer are configured so as to generate sufficient stress in the strain compensation matching light-emitting region, utilizing the QCSE effect, thereby causing the red shift generated by the QCSE effect in the strain compensation matching light-emitting region to be no less than 25 nm.

[0008] The beneficial effects of the present application are as follows: Different from the prior art, the strain compensation preparatory layer in the present application can be used to adjust the stress of the strain compensation matching light-emitting area, maintain the stress stability of the strain compensation matching light-emitting area, and reduce the defect density. At the same time, the present application utilizes the lattice mismatch between the strain compensation preparatory layer and the strain compensation matching light-emitting area and cooperates with the first cross-sectional size to achieve stress control of the strain compensation matching light-emitting area, and utilizes the QCSE effect to make the red shift of the strain compensation matching light-emitting area due to the QCSE effect not less than 25nm, thereby achieving the growth of the strain compensation matching light-emitting area at a relatively high temperature, improving the quality of the epitaxial layer, especially improving the quality of the epitaxial layer in the long wavelength band (such as red light, yellow light), thereby improving the light efficiency of the light-emitting diode. Further, the present application selectively grows the strain compensation matching light-emitting area stacked on the strain compensation preparatory layer, and no longer uses the chip process to etch the isolation groove to prepare the micro-LED chip unit, which can avoid the side wall damage of the micro-LED chip unit, improve the luminous efficiency, and improve the uniformity of the large-size epitaxial structure. In addition, the inventors of the present application can control the red shift of the strain compensation matching luminous areas in different growth areas by controlling the stress of the strain compensation matching luminous areas in different growth areas, thereby realizing RGB three-color monolithic integrated display. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0010] Figure 1 is a schematic structural diagram of a light emitting diode provided in the first embodiment of the present application;

[0011] Figure 2 is a schematic structural diagram of a light emitting diode provided in a second embodiment of the present application;

[0012] Figure 3 is a schematic structural diagram of a light emitting diode provided in the third embodiment of the present application;

[0013] Figure 4 is a schematic structural diagram of a light emitting diode provided in a fourth embodiment of the present application;

[0014] Figure 5 is a schematic structural diagram of a light emitting diode provided in a fifth embodiment of the present application;

[0015] Figure 6 is a schematic structural diagram of a light emitting diode provided in a sixth embodiment of the present application;

[0016] Figure 7 is a schematic structural diagram of a light emitting diode provided in the seventh embodiment of the present application;

[0017] Figure 8 is a schematic structural diagram of a light emitting diode provided in an eighth embodiment of the present application;

[0018] Fig. 9 is a schematic structural diagram of a light emitting diode provided in a ninth embodiment of the present application;

[0019] Fig.10 is a schematic structural diagram of a light emitting diode provided in the tenth embodiment of the present application;

[0020] Fig.11 It is a schematic flow chart of the method for manufacturing a light emitting diode provided in the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] like Figure 1 As shown, an embodiment of the present application provides a light emitting diode 10 , which includes: a strain compensation preparation layer 11 and a strain compensation matching light emitting region 12 stacked on the strain compensation preparation layer 11 in a selective growth manner.

[0023] Specifically, the strain compensation preparatory layer 11 is the growth substrate of the strain compensation matching light-emitting area 12. The function of the strain compensation preparatory layer 11 is to regulate the stress size of the strain compensation matching light-emitting area 12, maintain the stress stability of the strain compensation matching light-emitting area 12, and reduce the defect density.

[0024] The strain compensation preparation layer 11 is one or a combination of a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a superlattice layer, a pre-well preparation layer or a custom layer.

[0025] Optionally, the substrate includes, but is not limited to, one or more combinations of a sapphire substrate, a Si substrate, a SiC substrate, a GaN substrate, a ZnO substrate, an InP substrate, and a GaAs substrate.

[0026] Optionally, the intrinsic semiconductor layer may be an intrinsic GaN layer or an intrinsic InGaAlN layer.

[0027] Optionally, the N-type semiconductor layer may be an N-type GaN layer or an N-type InGaAlN layer.

[0028] Alternatively, the superlattice layer may be formed by repeatedly stacking a plurality of composite layers, each of which includes a plurality of nitride semiconductor layers. Each nitride semiconductor layer may have a different composition to have a different lattice constant. By repeatedly stacking a plurality of nitride semiconductor layers having different lattice constants, the superlattice layer may have a new lattice constant different from the lattice constant of the nitride semiconductor layer.

[0029] Optionally, the custom layer is Ga(X)N(Y) (where X=In, Al, B, Y=P, As, Sb, Bi) which may be doped or undoped.

[0030] The strain compensation matching light emitting area 12 is a semiconductor light emitting area 12 with quantum confined Stark effect (QCSE) grown on the strain compensation preparatory layer 11 and located in the growth area. The growth area refers to the area where the micro-LED unit is to be formed, and the growth area and the non-growth area are arranged alternately.

[0031] Optionally, the material system of the strain compensation matching light emitting region 12 is Ga(X)N(Y) (wherein X=In, Al, B, Y=P, As, Sb, Bi).

[0032] Optionally, the shape of the strain-compensated light-emitting area 12 can be square, circular, hexagonal, triangular, a custom shape, etc.

[0033] Optionally, the side length of the strain-compensated light-emitting area 12 can be 100 mm to 10 mm, 10 mm to 1 mm, 1 mm to 100 microns, 100 microns to 1 micron, 1 micron to 1 nanometer, and the interval is 10 mm to 1 mm, 1 mm to 100 microns, 100 microns to 1 micron, 1 micron to 1 nanometer.

[0034] Among them, the strain compensation matching light-emitting area 12 has a first cross-sectional dimension in the direction perpendicular to the stacking direction of the strain compensation preparatory layer 11 and the strain compensation matching light-emitting area 12. Different from the prior art, in the embodiment of the present application, the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light-emitting area 12 and the strain compensation preparatory layer 11 are set to generate sufficient stress in the strain compensation matching light-emitting area 12, utilizing the QCSE effect, so that the red shift generated by the QCSE effect in the strain compensation matching light-emitting area 12 is not less than 25nm.

[0035] It should be noted that in the present application, the lattice mismatch between the strain compensation matching light-emitting area 12 and the strain compensation preparatory layer 11 is less than the critical lattice mismatch threshold. The critical lattice mismatch threshold means that when the lattice mismatch is less than the critical lattice mismatch threshold, the difference between the lattice constants can be compensated by elastic deformation without generating dislocations and defects at the interface; when the lattice mismatch exceeds the critical lattice mismatch threshold, the dislocation and defect density at the interface will increase significantly.

[0036] Different from the prior art, the strain compensation preparatory layer 11 in the present application can be used to regulate the stress of the strain compensation matching light-emitting area 12, maintain the stress stability of the strain compensation matching light-emitting area 12, and reduce the defect density. At the same time, the present application utilizes the lattice mismatch between the strain compensation preparatory layer 11 and the strain compensation matching light-emitting area 12 and cooperates with the first cross-sectional size to achieve stress control of the strain compensation matching light-emitting area 12, and utilizes the QCSE effect to make the red shift of the strain compensation matching light-emitting area 12 due to the QCSE effect not less than 25nm, thereby achieving the growth of the strain compensation matching light-emitting area 12 at a relatively high temperature, improving the quality of the epitaxial layer, especially improving the quality of the epitaxial layer in the long wavelength band (such as red light and yellow light), thereby improving the light efficiency of the light-emitting diode 10. Furthermore, the present application selectively grows the strain compensation matching luminous area 12 stacked on the strain compensation preparatory layer 11, and no longer uses the chip process to etch the isolation groove to prepare the micro-LED chip unit, which can avoid the side wall damage of the micro-LED chip unit, improve the luminous efficiency, and improve the uniformity of the large-scale epitaxial structure, and effectively prevent the large-scale epitaxial structure from warping. In addition, the inventor of the present application can control the red shift of the strain compensation matching luminous area 12 in different growth areas by controlling the stress of the strain compensation matching luminous area 12 in different growth areas, thereby realizing RGB three-color monolithic integrated display.

[0037] In one embodiment, the red shift caused by the QCSE effect is not less than 50 nm.

[0038] In one embodiment, the red shift amount caused by the QCSE effect is not less than 100 nm.

[0039] In one embodiment, the red shift amount caused by the QCSE effect is not less than 200 nm.

[0040] Specifically, the red shift caused by the QCSE effect and the MQW size effect is not less than 200nm; the red shift caused by the strain compensation preparation layer 11 size effect and the QCSE effect is not less than 200nm; the red shift caused by the strain compensation preparation layer 11 size effect, the QCSE effect and the MQW size effect is not less than 300nm.

[0041] In one embodiment, the red shift amount caused by the QCSE effect is the difference between the actual peak wavelength generated by the strain-compensated matching light-emitting region 12 and the theoretical peak wavelength generated by the strain-compensated matching light-emitting region 12 in a stress-free state calculated based on the composition of the strain-compensated matching light-emitting region 12.

[0042] Specifically, when the material of the strain compensation matching light emitting area 12 is In x Ga 1-x N or Al x Ga 1-x When N, according to the bandgap bowing equation of relaxed unstrained alloy, in the stress-free state, the bandgap and the components satisfy the following formula:

[0043] E g (In x Ga 1-x N) = xE g (InN)+(1-x)E g (GaN)-bx(1-x)

[0044] =3.43-2.79x-1.4x(1-x);

[0045] E g (Al x Ga 1-x N) = xE g (AlN)+(1-x)E g (GaN)-bx(1-x)

[0046] =3.43+2.71xx(1-x).

[0047] Where b is the bending factor, for In x Ga 1-x N and Al x Ga 1-x N system, the empirical values ​​of b are 1.4 and 1.0 respectively. Therefore, the band gap E can be calculated based on the component x. g , and then according to formula E g =hc / λ≈1240 / λ, from E g The theoretical peak wavelength generated by the strain compensation matching light-emitting area 12 in a stress-free state can be calculated. In addition, according to the quantum confinement effect, as the thickness of the quantum well decreases, the emission wavelength will blue-shift and vary from material system to material system. In this application, the red shift amount caused by the QCSE effect is defined as the difference between the actual peak wavelength and the theoretical peak wavelength calculated by the above formula.

[0048] like Figure 2 As shown, in one embodiment, the strain compensation matching light-emitting area 12 is a quantum well layer 12, and the quantum well layer 12 includes a stacked well layer 122 and a barrier layer 121, wherein the lattice constant of the strain compensation preparation layer 11 is between the lattice constant of the well layer 122 and the lattice constant of the barrier layer 121.

[0049] In one embodiment, the lattice constants of the strain compensation preparation layer 11, the well layer 122 and the barrier layer 121 satisfy the following relationship:

[0050] a 1 3 2 or a 2 3 1

[0051] Among them, a 1 is the lattice constant of the well layer 122, a 2 is the lattice constant of the barrier layer 121, a 3 is the lattice constant of the strain compensation preparation layer 11 .

[0052] Specifically, the well layer 122 may be an InGaN well layer 122, the barrier layer 121 may be a GaN barrier layer 121, an AlGaN barrier layer 121 or an AlN barrier layer 121, and the strain compensation preparation layer 11 may be an InGaN strain compensation preparation layer 11 or an AlGaN strain compensation preparation layer 11. For example, Figure 3 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the GaN barrier layer 121 is 2 is 3.2 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 is 3.2 to 3.54 angstroms; Figure 4 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlGaN barrier layer 121 is 2 is 3.1 to 3.2 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 is 3.2 to 3.54 angstroms; Figure 5 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlGaN barrier layer 121 is 2 is 3.1 to 3.2 angstroms, and the lattice constant a of the AlGaN strain compensation preliminary layer 11 is 3 is 3.1 to 3.2 angstroms; Figure 6 As shown, the lattice constant a of the InGaN well layer 122 1 ​​​​is 3.2 to 3.54 angstroms, and the lattice constant a of the AlN barrier layer 121 is 2 is 3.1 angstroms, and the lattice constant a of the AlGaN strain compensation preliminary layer 11 is 3 is 3.1 to 3.2 angstroms; Figure 7 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlN barrier layer 121 is 2 is 3.1 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 It is 3.2 to 3.54 angstroms.

[0053] In one embodiment, if Figure 8 As shown, the light-emitting diode 10 further includes a substrate 14, on which a strain compensation preparation layer 11 is formed in a selective growth manner, and has a second cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparation layer 11 and the strain compensation matching light-emitting region 12, and the second cross-sectional dimension is the same as the first cross-sectional dimension.

[0054] Specifically, the substrate 14 includes, but is not limited to, one or more combinations of a sapphire substrate, a Si substrate, a SiC substrate, a GaN substrate, a ZnO substrate, an InP substrate, and a GaAs substrate.

[0055] Furthermore, if Figures 3 to 7 As shown, the light emitting diode 10 further includes a P-type semiconductor layer 13 , which is located on a side of the strain compensation matching light emitting region 12 away from the strain compensation preparatory layer 11 , and the P-type semiconductor layer 13 and the strain compensation matching light emitting region 12 are stacked.

[0056] The P-type semiconductor layer 13 includes but is not limited to one or more combinations of an electron blocking layer, a P-type GaN layer, and a P-type heavily doped ohmic contact layer.

[0057] like Figures 9-10 As shown, the P-type semiconductor layer 13 may include P-type semiconductor substructures located in the growth region and independent of each other; the P-type semiconductor layer 13 may also include P-type semiconductor substructures located in at least two growth regions and connected between the at least two growth regions, wherein the specific connection method is that at least one layer of the P-type semiconductor layer 13 in a certain growth region is in contact with at least one layer of the same properties of the P-type semiconductor layer 13 in another growth region.

[0058] In one embodiment, the lattice mismatch between the strain compensation matching light emitting region 12 and the strain compensation preliminary layer 11 is not less than 2%.

[0059] In one embodiment, the lattice mismatch between the strain compensation matching light emitting region 12 and the strain compensation preliminary layer 11 is not less than 3%.

[0060] In one embodiment, the lattice mismatch between the strain compensation matching light emitting region 12 and the strain compensation preliminary layer 11 is not less than 5%.

[0061] In one embodiment, the lattice mismatch between the strain compensation matching light emitting region 12 and the strain compensation preliminary layer 11 is not less than 10%.

[0062] In one embodiment, the lattice mismatch between the strain compensation matching light emitting region 12 and the strain compensation preliminary layer 11 is not less than 20%.

[0063] The lattice mismatch is defined as [(a 1 -a 3 ) / a 3 ]×100%, where a 1 is the lattice constant of the well layer, a 3 is the lattice constant of the strain compensation preparation layer 11 .

[0064] like Fig.11 As shown, the embodiment of the present application also provides a method for manufacturing the light emitting diode 10 of the above embodiment, the manufacturing method comprising:

[0065] S101: providing a strain compensation preparation layer 11.

[0066] Specifically, the strain compensation preparation layer 11 is one or a combination of a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a superlattice layer, a pre-well preparation layer or a custom layer.

[0067] Optionally, the substrate includes, but is not limited to, one or more combinations of a sapphire substrate, a Si substrate, a SiC substrate, a GaN substrate, a ZnO substrate, an InP substrate, and a GaAs substrate.

[0068] Optionally, the intrinsic semiconductor layer may be an intrinsic GaN layer or an intrinsic InGaAlN layer.

[0069] Optionally, the N-type semiconductor layer may be an N-type GaN layer or an N-type InGaAlN layer.

[0070] Alternatively, the superlattice layer may be formed by repeatedly stacking a plurality of composite layers, each of which includes a plurality of nitride semiconductor layers. Each nitride semiconductor layer may have a different composition to have a different lattice constant. By repeatedly stacking a plurality of nitride semiconductor layers having different lattice constants, the superlattice layer may have a new lattice constant different from the lattice constant of the nitride semiconductor layer.

[0071] Optionally, the custom layer is Ga(X)N(Y) (where X=In, Al, B, Y=P, As, Sb, Bi) which may be doped or undoped.

[0072] S102 : selectively growing a strain compensation matching light emitting region 12 on the strain compensation preliminary layer 11 .

[0073] Among them, the strain compensation matching light-emitting area 12 has a first cross-sectional dimension in the direction perpendicular to the stacking direction of the strain compensation preparatory layer 11 and the strain compensation matching light-emitting area 12, and the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light-emitting area 12 and the strain compensation preparatory layer 11 are set to generate sufficient stress in the strain compensation matching light-emitting area 12, and utilize the QCSE effect, so that the red shift generated by the strain compensation matching light-emitting area 12 due to the QCSE effect is not less than 25nm.

[0074] Specifically, a mask layer can be formed on the strain compensation preparation layer 11, and the strain compensation matching light-emitting area 12 can be selectively grown on the mask layer. The specific technical scheme is: a photoresist is coated on the strain compensation preparation layer 11, and after exposure and development, the photoresist on the growth area is retained, and a mask layer is deposited in the non-growth area, and then the photoresist is removed, or the mask layer material is first deposited, and then the photoresist is coated and exposed and developed, and the photoresist except the growth area is retained, and the mask layer in the growth area is removed by an etching process, and then the photoresist is removed; the strain compensation matching light-emitting area 12 is grown on the strain compensation preparation layer 11, and the mask layer in the non-growth area is removed to peel off the strain compensation matching light-emitting area 12 in the non-growth area. Among them, the material component of the mask layer can be metal (such as Ti, W, Mo, Mn, Cr, Ta, etc.), SiO 2 、Si 3 N 4 At least one of the mask layers may have a thickness of 10 mm to 1 mm, 1 mm to 100 μm, 100 μm to 1 μm, 1 μm to 1 nm, and a width of 10 mm to 1 mm, 1 mm to 100 μm, 100 μm to 1 μm, 1 μm to 1 nm.

[0075] In other embodiments, a dry etching process may be used to etch grooves in the non-growth area of ​​the strain compensation preparation layer 11, and the other areas are growth areas, and the strain compensation matching light-emitting area 12 is selectively grown on the strain compensation preparation layer 11 between the grooves. The depth of the groove is 10 mm to 1 mm, 1 mm to 100 μm, 100 μm to 1 μm, 1 μm to 1 nm, and the width of the groove is 10 mm to 1 mm, 1 mm to 100 μm, 100 μm to 1 μm, 1 μm to 1 nm.

[0076] In other embodiments, a groove is etched in the non-growth area of ​​the strain compensation preparation layer 11, and the other area is the growth area. The groove is filled with silicon dioxide until it is higher than the upper surface of the growth area to form a step with a certain height, and the strain compensation matching light-emitting area 12 is selectively grown on the upper surface of the growth area. The depth of the step is 10 mm to 1 mm, 1 mm to 100 μm, 100 μm to 1 μm, or 1 μm to 1 nm.

[0077] In one embodiment, the red shift amount caused by the QCSE effect is the difference between the actual peak wavelength generated by the strain-compensated matching light-emitting region 12 and the theoretical peak wavelength generated by the strain-compensated matching light-emitting region 12 in a stress-free state calculated based on the composition of the strain-compensated matching light-emitting region 12.

[0078] In one embodiment, the strain compensation matching light emitting region 12 is a quantum well layer 12 , which includes a stacked well layer 122 and a barrier layer 121 , wherein the lattice constant of the strain compensation preliminary layer 11 is between the lattice constant of the well layer 122 and the lattice constant of the barrier layer 121 .

[0079] The lattice constants of the strain compensation preparation layer 11, the well layer 122 and the barrier layer 121 satisfy the following relationship:

[0080] a 1 3 2 or a 2 3 1

[0081] Among them, a 1 is the lattice constant of the well layer 122, a 2 is the lattice constant of the barrier layer 121, a 3 is the lattice constant of the strain compensation preparation layer 11 .

[0082] Specifically, the well layer 122 may be an InGaN well layer 122, the barrier layer 121 may be a GaN barrier layer 121, an AlGaN barrier layer 121 or an AlN barrier layer 121, and the strain compensation preparation layer 11 may be an InGaN strain compensation preparation layer 11 or an AlGaN strain compensation preparation layer 11. For example, Figure 3 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the GaN barrier layer 121 is 2 is 3.2 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 is 3.2 to 3.54 angstroms; Figure 4 As shown, the lattice constant a of the InGaN well layer 122 1 ​​​​is 3.2 to 3.54 angstroms, and the lattice constant a of the AlGaN barrier layer 121 is 2 is 3.1 to 3.2 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 is 3.2 to 3.54 angstroms; Figure 5 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlGaN barrier layer 121 is 2 is 3.1 to 3.2 angstroms, and the lattice constant a of the AlGaN strain compensation preliminary layer 11 is 3 is 3.1 to 3.2 angstroms; Figure 6 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlN barrier layer 121 is 2 is 3.1 angstroms, and the lattice constant a of the AlGaN strain compensation preliminary layer 11 is 3 is 3.1 to 3.2 angstroms; Figure 7 As shown, the lattice constant a of the InGaN well layer 122 1 is 3.2 to 3.54 angstroms, and the lattice constant a of the AlN barrier layer 121 is 2 is 3.1 angstroms, and the lattice constant a of the InGaN strain compensation preliminary layer 11 is 3 It is 3.2 to 3.54 angstroms.

[0083] Different from the prior art, the strain compensation preparatory layer 11 in the present application can be used to adjust the stress of the strain compensation matching light-emitting area 12, maintain the stress stability of the strain compensation matching light-emitting area 12, and reduce the defect density. At the same time, the present application uses the lattice mismatch between the strain compensation preparatory layer 11 and the strain compensation matching light-emitting area 12 and cooperates with the first cross-sectional size to achieve stress control of the strain compensation matching light-emitting area 12, and uses the QCSE effect to make the red shift of the strain compensation matching light-emitting area 12 due to the QCSE effect not less than 25nm, thereby achieving the growth of the strain compensation matching light-emitting area 12 at a relatively high temperature, improving the quality of the epitaxial layer, especially improving the quality of the epitaxial layer in the long wavelength band (such as red light and yellow light), thereby improving the light efficiency of the light-emitting diode 10. Further, the present application selectively grows the strain compensation matching light-emitting area 12 stacked on the strain compensation preparatory layer 11, and no longer uses the chip process to etch the isolation groove to prepare the micro-LED chip unit, which can avoid the side wall damage of the micro-LED chip unit, improve the luminous efficiency, and improve the uniformity of the large-size epitaxial structure. In addition, the inventors of the present application can control the red shift of the strain compensation matching light-emitting area 12 in different growth areas by controlling the stress of the strain compensation matching light-emitting area 12 in different growth areas, thereby realizing RGB three-color monolithic integrated display.

[0084] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode includes a strain compensation preparatory layer and a strain compensation matching light-emitting region stacked on the strain compensation preparatory layer in a selective growth manner, wherein the strain compensation matching light-emitting region has a first cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparatory layer and the strain compensation matching light-emitting region, and the first cross-sectional dimension and the lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer are set such that sufficient stress is generated in the strain compensation matching light-emitting region, and by using the QCSE effect, the redshift amount generated by the strain compensation matching light-emitting region due to the QCSE effect is not less than 25 nm.

2. The light emitting diode according to claim 1, characterized in that: The redshift amount generated due to the QCSE effect is not less than 50 nm.

3. The light emitting diode according to claim 1, characterized in that: The redshift amount generated due to the QCSE effect is not less than 100 nm.

4. The light emitting diode according to claim 1, characterized in that: The redshift amount generated due to the QCSE effect is not less than 200 nm.

5. The light emitting diode according to claim 1, characterized in that: The redshift amount generated due to the QCSE effect is the difference between the actual peak wavelength generated by the strain compensation matching light-emitting region and the theoretical peak wavelength generated by the strain compensation matching light-emitting region in a stress-free state calculated according to the composition of the strain compensation matching light-emitting region.

6. The light emitting diode according to claim 1, characterized in that: The strain compensation matching light-emitting region is a quantum well layer, and the quantum well layer includes a well layer and a barrier layer stacked, wherein the lattice constant of the strain compensation preparatory layer is between the lattice constant of the well layer and the lattice constant of the barrier layer.

7. The light emitting diode according to claim 5, characterized in that: The lattice constants of the strain compensation preparatory layer, the well layer, and the barrier layer satisfy the following relationship: a1 < a3 < a2 or a2 < a3 < a1 Wherein, a1 is the lattice constant of the well layer, a2 is the lattice constant of the barrier layer, and a3 is the lattice constant of the strain compensation preparatory layer.

8. The light emitting diode according to claim 1, characterized in that: The strain compensation preparatory layer is one or a combination of a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a superlattice layer, a pre-well preparation layer, or a custom layer.

9. The light emitting diode according to claim 1, characterized in that: The light-emitting diode further includes a substrate, the strain compensation preparatory layer is formed on the substrate in a selective growth manner, and has a second cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparatory layer and the strain compensation matching light-emitting region, and the second cross-sectional dimension is the same as the first cross-sectional dimension.

10. The light emitting diode according to claim 1, characterized in that: The lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer is not less than 2%.

11. The light emitting diode according to claim 1, characterized in that: The lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer is not less than 3%.

12. The light emitting diode according to claim 1, characterized in that: The lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer is not less than 5%.

13. The light emitting diode according to claim 1, characterized in that: The lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer is not less than 10%.

14. The light emitting diode according to claim 1, characterized in that: The lattice mismatch amount between the strain compensation matching light-emitting region and the strain compensation preparatory layer is not less than 20%.

15. A method for manufacturing a light emitting diode, characterized in that: The manufacturing method includes: Providing a strain compensation preparatory layer; Selectively growing a strain compensation matching light-emitting region on the strain compensation preparatory layer; Among them, the strain compensation matching light-emitting area has a first cross-sectional dimension in a direction perpendicular to the stacking direction of the strain compensation preparatory layer and the strain compensation matching light-emitting area, and the first cross-sectional dimension and the lattice mismatch between the strain compensation matching light-emitting area and the strain compensation preparatory layer are set to generate sufficient stress in the strain compensation matching light-emitting area, utilizing the QCSE effect, so that the red shift generated by the QCSE effect in the strain compensation matching light-emitting area is not less than 25nm.

16. The manufacturing method according to claim 15, characterized in that: The red shift amount caused by the QCSE effect is the difference between the actual peak wavelength generated by the strain-compensated matching light-emitting region and the theoretical peak wavelength generated by the strain-compensated matching light-emitting region in a stress-free state calculated based on the composition of the strain-compensated matching light-emitting region.

17. The manufacturing method according to claim 15, characterized in that: The strain compensation matching light emitting region is a quantum well layer, and the quantum well layer includes a well layer and a barrier layer which are stacked, wherein the lattice constant of the strain compensation preparation layer is between the lattice constant of the well layer and the lattice constant of the barrier layer.

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