A DC-DC converter

Abstract

A DC-DC converter, characterized in that: the converter includes a mode switching unit, a first current detection unit, a second current detection unit, a third current detection unit, and a logic module; wherein, the mode switching unit is used to compare a reference voltage with the output voltage Vea of ​​an error amplifier to obtain a first control signal OUT1; the first current detection unit is used to generate a second control signal OUT2, and the second and third current detection units are used to generate a third control signal OUT3; the logic unit realizes the switching between light-load and heavy-load operating states of the converter based on the first control signal OUT1, and realizes the control of the on and off states of the power transistors in the converter under the light-load operating state based on the second control signal OUT2 and the third control signal OUT3. This invention enables the DC-DC converter to enter a light-load operating mode at a reasonable fixed load current point.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a DC-DC converter. Background Technology

[0002] DC-DC (Direct Current-Direct Current) converters are widely used in integrated circuits as voltage converters capable of transforming input voltage and efficiently outputting a fixed voltage. In boost converters,

[0003] DC-DC converters can provide two different operating modes, light load and heavy load, to improve their adaptability and meet the power supply needs of more diverse downstream loads. In existing technologies, when a DC-DC converter operates under light load, the peak value of the inductor current is clamped to a fixed minimum threshold current Ntrip and no longer decreases. Simultaneously, the on / off state of the power transistors in the converter is controlled by the light load operating mode, achieving normal inductor current output for one period and shielding the inductor current output for the next period, thus achieving relatively stable control of the output voltage through this cycle. In this invention, the period during which the inductor current is normally output is called the output interval, and the period during which the inductor current cannot be output is called the non-output interval.

[0004] In existing technologies, the switching point between light-load and heavy-load operating modes of DC-DC converters varies with the input and output voltages. Since the output ripple is relatively large when the DC-DC converter operates under light load, affecting applications, some applications require a constant switching point between light-load and heavy-load modes. Existing technologies cannot meet the needs of these specific applications.

[0005] Therefore, a new DC-DC converter is urgently needed. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a DC-DC converter that, by reasonably adjusting the minimum value of the inductor current, enables the DC-DC converter to enter a light-load operating mode at a reasonable fixed load current point.

[0007] The present invention adopts the following technical solution.

[0008] This invention relates to a DC-DC converter, comprising a clock generation circuit, a logic unit, a delay unit, a power transistor, an inductor, an output capacitor, a voltage divider resistor, and an error amplifier. The converter further comprises a mode switching unit, a first current detection unit, a second current detection unit, a third current detection unit, and a logic unit. The mode switching unit compares a reference voltage with the output voltage Vea of ​​the error amplifier to obtain a first control signal OUT1. The first current detection unit generates a second control signal OUT2, and the second and third current detection units generate a third control signal OUT3. The logic unit switches between light-load and heavy-load operating states based on the first control signal OUT1, and controls the on / off state of the power transistor in the converter under light-load operating conditions based on the second and third control signals OUT2 and OUT3.

[0009] Preferably, when the first control signal OUT1 is at a high level, the logic unit controls the converter to enter a light-load operating state, and the inductor current is shielded or output at a set interval; when the inductor current is at the output interval, the second control signal OUT2 and the third control signal OUT3 control the high-side power transistor to turn on and the low-side power transistor to turn off, thereby increasing the inductor current amplitude, or control the high-side power transistor to turn off and the low-side power transistor to turn on, thereby decreasing the inductor current amplitude.

[0010] Preferably, the mode switching unit includes a first comparator COMP1, with the non-inverting input terminal of the comparator COMP1 connected to a reference voltage V1, the negative input terminal connected to the output voltage Vea of ​​the error amplifier, and the output terminal generating a first control signal OUT1.

[0011] Preferably, the first current detection unit includes a current amplification circuit and a second comparator COMP2; wherein, the current amplification circuit is used to acquire the inductor current, convert it into a detection voltage OUT4, and output it to the positive input terminal of the second comparator COMP2; the negative input terminal of the second comparator is connected to the output voltage Vea of ​​the error amplifier, and the output terminal generates a second control signal OUT2, which is input to the logic unit. Preferably, the second current detection unit is used to acquire the inductor current and, based on the conversion coefficient... It is converted into an amplified current I2, and the amplified current is input to the third current detection unit.

[0012] Preferably, the third current detection unit includes an output voltage acquisition unit, an input voltage acquisition unit, a comparison unit, and an output mirror unit; wherein, the input terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the output voltage and the input voltage of the converter; the output terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the two input terminals of the comparison unit; the comparison unit generates a comparison current ICQ4 after comparison, and generates a detection current I1 after passing through the output mirror unit.

[0013] Preferably, the third current detection unit further includes two inverters connected in series, with the input terminals of the inverters connected to the output terminals of the second current detection unit and the third current detection unit, respectively; the output terminals of the inverters are connected to the logic unit.

[0014] Preferably, the output voltage acquisition unit includes an operational amplifier OPA1, a voltage divider resistor R4, and a mirror MOSFET, used to generate a first comparison current Vout / R4 based on the non-inverting input signal Vout of the operational amplifier OPA1; the input voltage acquisition unit includes an operational amplifier OPA2, a voltage divider resistor R5, and a mirror MOSFET, used to generate a second comparison current Vin / R5 based on the non-inverting input signal Vin of the operational amplifier OPA2.

[0015] Preferably, the comparison unit includes a base control transistor, first-stage symmetrical transistors Q2 and Q3, second-stage symmetrical transistors Q1 and Q4, a first-stage current source Iref, and a second-stage current source IX; wherein, the gate of the base control transistor is connected to the output terminal of the output voltage acquisition unit, the drain is connected to the power supply voltage, the source is connected to the base of the first-stage symmetrical transistors Q2 and Q3 and one end of the first-stage current source Iref, and the other end of the first-stage current source Iref is grounded; the collectors of the first-stage symmetrical transistors Q2 and Q3 are connected to the power supply voltage, the emitter of Q2 is grounded after passing through the second-stage current source IX, and the emitter of Q3 is connected to the output terminal of the input voltage acquisition unit; the bases of the second-stage symmetrical transistors Q1 and Q4 are connected to the emitters of the first-stage symmetrical transistors Q2 and Q3, and the emitters are grounded; the collector of Q1 is connected to the output terminal of the output voltage acquisition unit and the gate of the base control transistor, and the collector of Q4 is connected to the input terminal of the output mirror unit; the output mirror unit includes a mirror MOS transistor.

[0016] Preferably, the comparison unit generates the comparison current ICQ4 after the comparison is performed as follows:

[0017] ;in, , This is the output current of the secondary current source.

[0018] Preferably, when the converter is in light-load operating mode, the maximum amplitude of the inductor current is limited to [value missing]. Furthermore, the maximum amplitude of the load current is limited to a constant. .

[0019] The beneficial effect of the present invention is that, compared with the prior art, the DC-DC converter of the present invention can enter the light load operating mode at a reasonable fixed load current point by reasonably adjusting the minimum value of the inductor current.

[0020] The beneficial effects of the present invention also include:

[0021] 1. This invention employs only multiple current detection modules to control the on / off state of the power transistor. Combined with the existing logic for switching between heavy and light load operating modes of the logic unit, it covers the control signals for power transistor on / off in light load mode, thereby achieving dynamic control of the inductor current output amplitude. This method ensures that the inductor current can still adjust its amplitude according to the output and input voltages even under light load conditions, thus ensuring the converter's matching with the load circuit under light load conditions.

[0022] 2. In this invention, the parameters of each component in the third current detection unit are cleverly designed to ensure that the converter can flip when the load current is equal to a preset fixed current value. This allows the converter to predict at which load point it will enter the light load mode. Applications that are sensitive to output ripple can accurately avoid this load point without having to consider the influence of input and output voltage. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the output voltage ripple of a DC-DC converter in the prior art of this invention;

[0024] Figure 2 This is a schematic diagram of the principle of a DC-DC converter according to the present invention;

[0025] Figure 3 This is a circuit diagram of the first current detection unit in a DC-DC converter according to the present invention;

[0026] Figure 4 This is a circuit diagram of the second current detection unit in a DC-DC converter according to the present invention;

[0027] Figure 5 This is a schematic diagram of a portion of the circuitry in the third current detection unit of a DC-DC converter according to the present invention;

[0028] Figure 6 This is a schematic diagram of the output principle of the third control signal in the third current detection unit of a DC-DC converter according to the present invention. Detailed Implementation

[0029] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0030] Figure 1 This is a schematic diagram of the output voltage ripple of a DC-DC converter in the prior art of this invention. Figure 1 As shown, in existing technologies, DC-DC converters can operate in two different modes—light load and heavy load—based on the load condition. When the DC-DC converter operates under heavy load, the inductor current amplitude can be adjusted according to the load current to maintain a stable output voltage. When the downstream load requires less power, the DC-DC converter can enter a light load mode. In this mode, the inductor current amplitude is clamped at the minimum threshold current Ntrip; to maintain the operating state of the downstream load, the inductor current cannot decrease further. At this time, to prevent the output voltage from rising, the DC-DC converter can ensure a lower total output power by intermittently adjusting the inductor current output.

[0031] Therefore, in Figure 1 During the output interval, the inductor current oscillates, causing the output voltage to rise slowly. During the non-output interval, the inductor current is shielded, and the output voltage decreases slowly. With repeated cycles of output and non-output intervals, the output voltage fluctuates to a certain extent; that is, the output voltage ripple is larger in light-load mode than in heavy-load mode. For applications sensitive to output ripple, light-load mode needs to be avoided. However, current technology determines the load current point at which light-load mode is entered based on changes in input and output voltage, making it impossible to accurately predict the load current point.

[0032] In this invention, circuit designers aim to precisely switch the power transistors in the converter between on and off states under light load conditions based on the input and output voltages, thereby ensuring entry into light load mode under a fixed load current. Therefore, this invention provides a novel DC-DC converter.

[0033] Figure 2 This is a schematic diagram illustrating the principle of a DC-DC converter according to the present invention. Figure 2As shown, a DC-DC converter includes a clock generation circuit, a logic unit, a delay unit, a power transistor, an inductor, an output capacitor, a voltage divider resistor, and an error amplifier. The converter also includes a mode switching unit, a first current detection unit, a second current detection unit, a third current detection unit, and the logic unit itself. The mode switching unit compares a reference voltage with the output voltage Vea of ​​the error amplifier to obtain a first control signal OUT1. The first current detection unit generates a second control signal OUT2, and the second and third current detection units generate a third control signal OUT3. The logic unit switches between light-load and heavy-load operating states based on the first control signal OUT1, and controls the on / off state of the power transistor in the converter under light-load operating conditions based on the second and third control signals OUT2 and OUT3.

[0034] Understandably, in Figure 2 In the circuit shown, the first control signal OUT1 functions similarly to the switching control signal for light-load and heavy-load operating states in the prior art, both of which can control the circuit to switch between light-load and heavy-load states.

[0035] With the first control signal OUT1 controlling the circuit to enter the light load mode, the second and third control signals OUT2 and OUT3 can adjust the duration of the rise and fall of the inductor current in each clock cycle, so that the converter can adaptively achieve reasonable output under light load conditions regardless of the state of the downstream load.

[0036] Preferably, when the first control signal OUT1 is at a high level, the logic unit controls the converter to enter a light-load operating state, and the inductor current is shielded or output at a set interval; when the inductor current is at the output interval, the second control signal OUT2 and the third control signal OUT3 control the high-side power transistor to turn on and the low-side power transistor to turn off, thereby increasing the inductor current amplitude, or control the high-side power transistor to turn off and the low-side power transistor to turn on, thereby decreasing the inductor current amplitude.

[0037] Understandably, when the converter is under light load, the present invention aims to compare the second control signal OUT2, which contains information about the magnitude of the inductor current, and the third control signal OUT3, which contains information about the input voltage and the output voltage. This will cause the power transistor in the circuit to change its on or off state when the ratio of the output voltage to the input voltage is higher than a certain level, thereby causing the inductor current to change from gradually increasing to gradually decreasing.

[0038] In this way, the second control signal OUT2 and the third control signal OUT3 control the state of the power transistor, thereby adjusting the maximum amplitude of the inductor current in each output cycle. Fundamentally, according to the law of power conservation, the product of the converter's output voltage and load current is equal to the product of the input voltage and inductor current. Therefore, the changes in the ratio of output voltage to input voltage and the changes in the maximum amplitude of the inductor current, as mentioned above, are to some extent offset, allowing the circuit to accurately control the maximum amplitude of the load current in each cycle by flexibly controlling the amplitude of the inductor current.

[0039] Preferably, the mode switching unit includes a first comparator COMP1, with the non-inverting input terminal of the comparator COMP1 connected to a reference voltage V1, the negative input terminal connected to the output voltage Vea of ​​the error amplifier, and the output terminal generating a first control signal OUT1.

[0040] In this circuit, the mode switching unit can acquire the feedback voltage Vfb through the existing error amplifier in the converter. After Vfb is compared with a reference voltage Vref, the output voltage Vea of ​​the error amplifier is realized. This output voltage Vea, after being compared with the reference voltage V1, realizes the output of the first control signal.

[0041] Specifically, when the voltage division of Vfb (the output voltage Vout) is large, the first control signal OUT1 will be in a high-level state, and the circuit will switch from a heavy-load state to a light-load state. Conversely, when the output voltage is low, the output of the first control signal OUT1 will also be in a low-level state, and this low-level control logic unit will implement the circuit's heavy-load operating mode. In other words, when the first control signal OUT1 is in a high-level state, it simultaneously shields the control signals of both the high-side and low-side power transistors, causing both to be in a cutoff state. At this time, the inductor current will not be output, and the circuit is in a non-output interval.

[0042] Preferably, the first current detection unit includes a current amplification circuit and a second comparator COMP2; wherein, the current amplification circuit is used to collect the inductor current and convert it into a detection voltage OUT4 and output it to the positive input terminal of the second comparator COMP2; the negative input terminal of the second comparator is connected to the output voltage Vea of ​​the error amplifier, and the output terminal generates a second control signal OUT2 and inputs it into the logic unit.

[0043] Figure 3 This is a circuit diagram of the first current detection unit in a DC-DC converter according to the present invention. Figure 3As shown, the current amplification circuit can be a circuit consisting of a current mirror and a voltage divider resistor. One end of the current mirror, the MOSFET Mn2, is connected to the low-side power transistor Mn0 of the converter via a mirror connection; that is, the gates of Mn0 and Mn2 are interconnected, and their sources are both grounded. Therefore, the current mirror can receive the proportional current of the low-side power transistor, which is the proportional current of the inductor current. Furthermore, this current passes through the voltage divider resistor, which then generates a detection voltage OUT4 based on changes in the inductor current. Comparing this detection voltage with the output voltage Vea of ​​the error amplifier generates the second control signal OUT2.

[0044] Specifically, assuming the amplification factor of the output voltage of the first current detection unit for the inductor current is... Then when the inductor current After input, the output voltage of the first current detection unit is Therefore, when When the voltage is greater than Vea, the second control signal OUT2 is high; otherwise, it is low. When the second control signal OUT2 is low, the logic unit in the circuit executes the original logic to switch the power transistor. When the output of the second control signal OUT2 is high, it is necessary to determine the state of another control signal OUT3.

[0045] For the present invention, the first current detection unit can also be implemented using other circuits in the prior art, as long as they can achieve the current detection function.

[0046] Preferably, the second current detection unit is used to collect the inductor current, convert it into an amplified current I2, and input the amplified current to the third current detection unit.

[0047] Figure 4 This is a circuit diagram of the second current detection unit in a DC-DC converter according to the present invention. Figure 4 As shown, the second current detection unit can be composed of a mirror unit, which can mirror the drain current of the low-side power transistor of the converter, that is, mirror the inductor current into an amplified current I2. In one embodiment of the present invention, it can be assumed that the amplification factor of the second current detection unit is 1. Therefore, the output of this unit becomes .

[0048] Preferably, the third current detection unit includes an output voltage acquisition unit, an input voltage acquisition unit, a comparison unit, and an output mirror unit; wherein, the input terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the output voltage and the input voltage of the converter; the output terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the two input terminals of the comparison unit; the comparison unit generates a comparison current ICQ4 after comparison, and generates a detection current I1 after passing through the output mirror unit.

[0049] Understandably, the design concept of the third current detection unit is to realize the output of the detection current I1 through the output voltage, the input voltage and a current source of a fixed size. The detection current I1 can be compared with the amplified current I2, so that the circuit can output the state flipping control signal OUT3 based on whether the amplified current is greater than the detection current I1.

[0050] Preferably, the third current detection unit further includes two inverters connected in series, with the input terminals of the inverters connected to the output terminals of the second current detection unit and the third current detection unit, respectively; the output terminals of the inverters are connected to the logic unit.

[0051] Figure 6 This is a schematic diagram illustrating the output principle of the third control signal in the third current detection unit of a DC-DC converter according to the present invention. Figure 6 As shown, when the detected current I1 is greater than the amplified current I2, the third control signal OUT3 can reach a low level after a delay. If the detected current I1 is less than the amplified current I2, the third control signal OUT3 will be high. When the third control signal OUT3 is low, the circuit operates according to the original logic of the logic unit. However, if the second and third control signals OUT2 and OUT3 are both high, the energy at the input of the converter is greater than that at the output. The logic unit will control the gate of the power transistor to turn off the high-side power transistor (Mp0) and turn on the low-side power transistor (Mn0). At this time, the inductor current of the converter will gradually decrease. When the clock signal reaches the next cycle pulse, the high-side power transistor will turn on again, and the low-side power transistor will turn off again, causing the inductor current to rise again.

[0052] It should be noted that when OUT1 is high, both the NMOS and PMOS power transistors are turned off. When OUT1 is low, the functions of OUT2 and OUT3 are as described above.

[0053] Figure 5 This is a schematic diagram of a portion of the circuitry in the third current detection unit of a DC-DC converter according to the present invention. Figure 5As shown, preferably, the output voltage acquisition unit includes an operational amplifier OPA1, a voltage divider resistor R4, and a mirror MOSFET, used to generate a first comparison current Vout / R4 based on the non-inverting input signal Vout of the operational amplifier OPA1; the input voltage acquisition unit includes an operational amplifier OPA2, a voltage divider resistor R5, and a mirror MOSFET, used to generate a second comparison current Vin / R5 based on the non-inverting input signal Vin of the operational amplifier OPA2.

[0054] Understandably, in the output voltage acquisition unit, the OPA1 negative feedback method is connected to the gate and source of the MOSFET. When the voltage at the positive input terminal of OPA1 is Vout, the MOSFET turns on, thus making the voltage at the negative input terminal equal to Vout. Under the action of the resistor, this unit can generate... A constant current. Similarly, the current of the input voltage acquisition unit is... .

[0055] Preferably, the comparison unit includes a base control transistor, first-stage symmetrical transistors Q2 and Q3, second-stage symmetrical transistors Q1 and Q4, a first-stage current source Iref, and a second-stage current source IX; wherein, the gate of the base control transistor is connected to the output terminal of the output voltage acquisition unit, the drain is connected to the power supply voltage, the source is connected to the base of the first-stage symmetrical transistors Q2 and Q3 and one end of the first-stage current source Iref, and the other end of the first-stage current source Iref is grounded; the collectors of the first-stage symmetrical transistors Q2 and Q3 are connected to the power supply voltage, the emitter of Q2 is grounded after passing through the second-stage current source IX, and the emitter of Q3 is connected to the output terminal of the input voltage acquisition unit; the bases of the second-stage symmetrical transistors Q1 and Q4 are connected to the emitters of the first-stage symmetrical transistors Q2 and Q3, and the emitters are grounded; the collector of Q1 is connected to the output terminal of the output voltage acquisition unit and the gate of the base control transistor, and the collector of Q4 is connected to the input terminal of the output mirror unit, which includes a mirror MOS transistor.

[0056] For this circuit, the comparator unit can input and compare the first and second comparison currents generated above. Specifically, depending on the circuit connection method, the base-controlled source voltage can be calculated using two different methods. On one hand, this voltage is equal to the sum of the base-emitter Vbe of symmetrical transistors Q1 and Q2; on the other hand, it can also be equal to the sum of the Vbe of symmetrical transistors Q3 and Q4.

[0057] Therefore, the following equation can be derived:

[0058]

[0059] Because the base control transistor remains on under the influence of the output voltage acquisition unit, its source voltage is relatively high, which sufficiently ensures the on-state operation of symmetrical transistors Q1 to Q4. Therefore, the emitter current of Q1 is approximately equal to the base current of Q1, which is also the output current of the output voltage acquisition unit. The emitter current of Q2 is equal to the current of current source IX. Similarly, the emitter current of Q3 is equal to the output current of the input voltage acquisition unit. The source current of Q4 is determined by Q1, Q2, and Q3.

[0060] in addition, The calculation formula is: ,in It is the threshold voltage of the transistor. For collector current, This is the saturation current. We can assume that the four transistors Q1 to Q4 are exactly the same model, therefore their threshold voltage and saturation current are also the same.

[0061] Therefore, the above formula can be transformed as follows:

[0062]

[0063]

[0064] Simplifying the above formula, we get

[0065]

[0066] From this we can obtain

[0067]

[0068] If the output mirror unit also has a certain magnification ratio, and this magnification ratio is similar to... Multiplication equals the ratio of the current mirror. Then the output current of the output mirror unit can be .

[0069] Comparing the amplified current I2 and the detection current I1, we can find that when they are equal, then...

[0070]

[0071] Therefore, it can be concluded that there should be a time point at which the output interval transitions between the output interval and the non-output interval in the light-load mode of this circuit. According to the power conservation principle of the converter, we have .

[0072] therefore, because and All of these are controllable and fixed, independent of input and output voltages. Therefore, when entering light load mode... The size is fixed.

[0073] Preferably, when the converter is in light-load operating mode, the maximum amplitude of the inductor current is limited to [value missing]. Therefore, the load point Iload that enters light load mode is limited to a constant. ;in, The magnification ratio of the output mirror unit and The product of.

[0074] The beneficial effect of this invention is that, compared with the prior art, the DC-DC converter of this invention can achieve a light-load operating mode at a fixed load current point by reasonably adjusting the minimum value of IL. Since this fixed load point does not change with the input and output voltages, it is more convenient for subsequent applications.

[0075] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A DC-DC converter, comprising a clock generation circuit, a logic unit, a delay unit, a power transistor, an inductor, an output capacitor, a voltage divider resistor, and an error amplifier, characterized in that: The converter further includes a mode switching unit, a first current detection unit, a second current detection unit, a third current detection unit, and a logic unit; The mode switching unit is used to compare the reference voltage V1 with the output voltage Vea of ​​the error amplifier to obtain the first control signal OUT1. The first current detection unit is used to generate the second control signal OUT2, and the second current detection unit and the third current detection unit are used to generate the third control signal OUT3; The first current detection unit includes a current amplifier circuit and a second comparator COMP2; wherein, The current amplification circuit is used to collect the inductor current, convert it into a detection voltage OUT4, and output it to the non-inverting input of the second comparator COMP2. The negative inverting input of the second comparator COMP2 is connected to the output voltage Vea of ​​the error amplifier, and the output generates a second control signal OUT2, which is then input to the logic unit. The second current detection unit is configured to collect an inductance current and convert the inductance current into an amplified current I2 according to a conversion coefficient The amplified current I2 is input to the third current detection unit. The logic unit controls the switching between light-load and heavy-load operating states of the converter based on the first control signal OUT1, and controls the on and off states of the power transistors in the converter under the light-load operating state based on the second control signal OUT2 and the third control signal OUT3.

2. A DC-DC converter according to claim 1, characterized in that: When the first control signal OUT1 is at a high level, the logic unit controls the converter to enter a light-load operating state, and the inductor current is shielded or output at set intervals. When the inductor current is in the output interval, the second control signal OUT2 and the third control signal OUT3 control the high-side power transistor to turn on and the low-side power transistor to turn off, thereby increasing the amplitude of the inductor current, or control the high-side power transistor to turn off and the low-side power transistor to turn on, thereby decreasing the amplitude of the inductor current.

3. A DC-DC converter according to claim 2, characterized in that: The mode switching unit includes a first comparator COMP1, with a reference voltage V1 connected to the positive input terminal and an error amplifier output voltage Vea connected to the negative input terminal, and a first control signal OUT1 generated at the output terminal.

4. A DC-DC converter according to claim 3, characterized in that: The third current detection unit includes an output voltage acquisition unit, an input voltage acquisition unit, a comparison unit, and an output mirror unit; wherein... The input terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the output voltage of the converter and the input voltage of the converter; The output terminals of the output voltage acquisition unit and the input voltage acquisition unit are respectively connected to the two input terminals of the comparison unit; The comparison unit generates a comparison current ICQ4 after comparison, and then generates a detection current I1 after passing through the output mirror unit.

5. A DC-DC converter according to claim 4, characterized in that: The third current detection unit also includes two inverters connected in series, and the input terminals of the two inverters connected in series are connected to the output terminal of the second current detection unit and the output terminal of the third current detection unit. The outputs of the two inverters connected in series are connected to the logic unit.

6. A DC-DC converter according to claim 4, characterized in that: The output voltage acquisition unit includes an operational amplifier OPA1, a voltage divider resistor R4, and a mirror MOS transistor, and is used to generate a first comparison current Vout / R4 based on the non-inverting input signal Vout of the operational amplifier OPA1. The input voltage acquisition unit includes an operational amplifier OPA2, a voltage divider resistor R5, and a mirror MOS transistor, which is used to generate a second comparison current Vin / R5 based on the positive input signal Vin of the operational amplifier OPA2.

7. A DC-DC converter according to claim 6, characterized in that: The comparison unit includes a base control transistor, first-stage symmetrical transistors Q2 and Q3, second-stage symmetrical transistors Q1 and Q4, a first-stage current source Iref, and a second-stage current source IX; wherein... The gate of the base control transistor is connected to the output terminal of the output voltage acquisition unit, the drain is connected to the power supply voltage, the source is connected to the base of the first-stage symmetrical transistors Q2 and Q3, and one end of the first-stage current source Iref, and the other end of the first-stage current source Iref is grounded. The collectors of the first-stage symmetrical transistors Q2 and Q3 are connected to the power supply voltage. The emitter of Q2 is grounded after passing through the second-stage current source IX. The emitter of Q3 is connected to the output terminal of the input voltage acquisition unit. The bases of the secondary symmetrical transistors Q1 and Q4 are connected to the emitters of the primary symmetrical transistors Q2 and Q3, respectively, and the emitters are grounded. The collector of Q1 is connected to the output terminal of the output voltage acquisition unit and the gate of the base control transistor. The collector of Q4 is connected to the input terminal of the output mirror unit. The output mirror unit includes a mirror MOS transistor.

8. A DC-DC converter according to claim 7, characterized in that: The comparison unit generates a comparison current ICQ4 after comparison as follows: ； in, , The output current of the secondary current source IX is denoted as .

9. A DC-DC converter according to claim 8, characterized in that: When the converter is in light-load operating mode, the maximum amplitude of the inductor current is limited to 1. Furthermore, the maximum amplitude of the load current is limited to a constant. The amplification factor of the second current detection unit is .

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