Shift register unit and driving method thereof, gate driving circuit, and display substrate

Abstract

A shift register unit is provided, comprising: an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide a signal of a first clock signal line (CK1) or a first power line (VGH) to a first control node (P1) under the control of a second clock signal line (CB1), a first input terminal (INPUT1) and a second control node (P2). The first control circuit is configured to provide a signal of a first power line (VGH) or a second power line (VGL) to a first output terminal (OUT1) under the control of the first control node (P1) and the second control node (P2). The second control circuit is configured to provide a signal of a first power line (VGH) or a second power line (VGL) to a second output terminal (OUT2) under the control of the first output terminal (OUT1). The output circuit is configured to output a valid level signal of a first power line (VGH) or a second power line (VGL) to a third output terminal (OUT3) under the control of a control signal line (CSL) and a second output terminal (OUT2). In one frame time, the duration of the effective level signal provided by the third output terminal (OUT3) is longer than the duration of the effective level signal provided by the second output terminal (OUT2).

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display substrate. Background Art

[0002] Organic Light Emitting Diode (OLED) has the advantages of ultra-thin, wide viewing angle, active light emission, high brightness, continuously adjustable light color, low cost, fast response speed, low power consumption, wide operating temperature range and flexible display. It has gradually become a promising next-generation display technology and has received more and more attention. According to different driving modes, OLED can be divided into passive matrix drive (PM) type and active matrix drive (AM) type. AMOLED is a current-driven device that uses independent thin film transistors (TFT) to control each sub-pixel. Each sub-pixel can be driven to emit light continuously and independently. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display substrate.

[0005] On the one hand, an embodiment of the present disclosure provides a shift register unit, including: an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is connected to a first clock signal line, a second clock signal line, a first input terminal, a first power line, a first control node and a second control node, and is configured to provide a signal of the first input terminal to the second control node under the control of the first clock signal line, and to provide a signal of the first clock signal line or the first power line to the first control node under the control of the second clock signal line, the first input terminal and the second control node. The first control circuit is connected to the first control node, the second control node, the first power line, the second power line and the first output terminal, and is configured to provide a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node. The second control circuit is connected to the first power line, the second power line, the first output terminal and the second output terminal, and is configured to provide an effective level signal of the first power line or the second power line to the second output terminal under the control of the first output terminal. The output circuit is connected to the control signal line, the first power line, the second power line, the second output terminal and the third output terminal, and is configured to output the effective level signal of the first power line or the second power line to the third output terminal under the control of the control signal line and the second output terminal. Within one frame time, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

[0006] In some exemplary embodiments, the output signal of the first output terminal is opposite in phase to the output signal of the second output terminal. The second output terminal and the third output terminal provide effective level signals with opposite polarities, and within a frame time, the third output terminal alternately outputs the effective level signal of the first power line or the second power line.

[0007] In some exemplary embodiments, the valid level signal provided to the third output terminal within one frame time includes: a first time period and a second time period separated. The first time period is configured to output the valid level signal of the second power line to the third output terminal under the control of the control signal line. The second time period is configured to output the valid level signal of the second power line to the third output terminal under the control of the second output terminal.

[0008] In some exemplary embodiments, the output circuit includes: a first output subcircuit and a second output subcircuit. The first output subcircuit is connected to the control signal line, the first power line, the second output terminal and the third output terminal, and is configured to provide the third output terminal with an effective level signal of the first power line under the control of the control signal line and the second output terminal. The second output subcircuit is connected to the control signal line, the second power line, the second output terminal and the third output terminal, and is configured to provide the third output terminal with an effective level signal of the second power line under the control of the control signal line and the second output terminal.

[0009] In some exemplary embodiments, the first output subcircuit includes: a first transistor and a second transistor. The control electrode of the first transistor is connected to the control signal line, the first electrode of the first transistor is connected to the first power line, and the second electrode of the first transistor is connected to the first electrode of the second transistor; the control electrode of the second transistor is connected to the second output terminal, and the second electrode of the second transistor is connected to the third output terminal. The second output subcircuit includes: a third transistor and a fourth transistor. The control electrode of the third transistor is connected to the second output terminal, the first electrode of the third transistor is connected to the second power line, and the second electrode of the third transistor is connected to the third output terminal; the control electrode of the fourth transistor is connected to the control signal line, the first electrode of the fourth transistor is connected to the second power line, and the second electrode of the fourth transistor is connected to the third output terminal.

[0010] In some exemplary embodiments, the second control circuit includes: a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is connected to the first output terminal, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the second output terminal. The control electrode of the sixth transistor is connected to the first output terminal, the first electrode of the sixth transistor is connected to the second power line, and the second electrode of the sixth transistor is connected to the second output terminal.

[0011] In some exemplary embodiments, the input circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a first capacitor. The control electrode of the seventh transistor is connected to the second electrode of the eighth transistor and the second electrode of the ninth transistor, the first electrode of the seventh transistor is connected to the first clock signal line, and the second electrode of the seventh transistor is connected to the first control node. The control electrode of the eighth transistor is connected to the first input terminal, and the first electrode of the eighth transistor is connected to the first power line. The control electrode of the ninth transistor is connected to the second clock signal line, and the first electrode of the ninth transistor is connected to the first power line. The control electrode of the tenth transistor is connected to the first clock signal line, the first electrode of the tenth transistor is connected to the first input terminal, and the second electrode of the tenth transistor is connected to the second control node. The control electrode of the eleventh transistor is connected to the second control node, the first electrode of the eleventh transistor is connected to the first power line, and the second electrode of the eleventh transistor is connected to the first control node. The first electrode of the first capacitor is connected to the control electrode of the seventh transistor, and the second electrode of the first capacitor is connected to the first clock signal line.

[0012] In some exemplary embodiments, the first control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a second capacitor, and a third capacitor. The control electrode of the twelfth transistor is connected to the second power line, the first electrode of the twelfth transistor is connected to the second control node, and the second electrode of the twelfth transistor is connected to the control electrode of the thirteenth transistor. The first electrode of the thirteenth transistor is connected to the second power line, and the second electrode of the thirteenth transistor is connected to the first output terminal. The control electrode of the fourteenth transistor is connected to the first control node, the first electrode of the fourteenth transistor is connected to the first power line, and the second electrode of the fourteenth transistor is connected to the first output terminal. The first electrode of the second capacitor is connected to the control electrode of the thirteenth transistor, and the second electrode of the second capacitor is connected to the first output terminal. The first electrode of the third capacitor is connected to the control electrode of the fourteenth transistor, and the second electrode of the third capacitor is connected to the first power line.

[0013] In some exemplary embodiments, the third transistor, the fourth transistor and the sixth transistor are first semiconductor type transistors, and the first transistor, the second transistor, the fifth transistor, the seventh transistor to the fourteenth transistor are second semiconductor type transistors; the doping types of the first semiconductor type and the second semiconductor type are opposite.

[0014] In some example embodiments, the third transistor, the fourth transistor, and the sixth transistor are oxide thin film transistors.

[0015] On the other hand, an embodiment of the present disclosure provides a driving method of a shift register unit, which is applied to the shift register unit as described above. The driving method includes: the input circuit provides a signal of the first input terminal to the second control node under the control of the first clock signal line, and provides a signal of the first clock signal line or the first power line to the first control node under the control of the second clock signal line, the first input terminal and the second control node; the first control circuit provides a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node; the second control circuit provides a signal of the first power line or the second power line to the second output terminal under the control of the first output terminal; the output circuit outputs an effective level signal of the first power line or the second power line to the third output terminal under the control of the control signal line and the second output terminal. Within a frame time, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

[0016] In some exemplary embodiments, the output circuit, under the control of the control signal line and the second output terminal, outputs the valid level signal of the first power line or the second power line to the third output terminal, including: under the control of the control signal line, the output circuit outputs the valid level signal of the second power line to the third output terminal in a first time period within a frame time; under the control of the second output terminal, the output circuit outputs the valid level signal of the second power line to the third output terminal in a second time period spaced apart from the first time period within a frame time.

[0017] On the other hand, the embodiment of the present disclosure provides a gate driving circuit, comprising: a plurality of cascaded first shift register units, wherein the first shift register units are the shift register units described above, wherein the first input end of the first-stage first shift register unit is connected to the first initial signal line; the first input end of the n+1-stage first shift register unit is connected to the first output end of the n-stage first shift register unit, wherein n is an integer greater than 0.

[0018] In some exemplary embodiments, the gate drive circuit further includes: a plurality of cascaded second shift register units. The second shift register unit includes: a second input terminal, a fourth output terminal, and a fifth output terminal. The second input terminal of the first-stage second shift register unit is connected to the second initial signal line; the second input terminal of the n+1-stage second shift register unit is connected to the fourth output terminal of the n-stage second shift register unit; the fifth output terminal of the n-stage second shift register unit is connected to the control signal line of the n-stage first shift register unit, or the fourth output terminal of the n-stage second shift register unit is connected to the control signal line of the n-stage first shift register unit.

[0019] In some exemplary embodiments, the second shift register unit includes: a fifteenth transistor to a twenty-fourth transistor, a fourth capacitor, and a fifth capacitor. The control electrode of the fifteenth transistor is connected to the third clock signal line, the first electrode of the fifteenth transistor is connected to the second input terminal, and the second electrode of the fifteenth transistor is connected to the fourth control node. The control electrode of the sixteenth transistor is connected to the fourth control node, the first electrode of the sixteenth transistor is connected to the third clock signal line, and the second electrode of the sixteenth transistor is connected to the third control node. The control electrode of the seventeenth transistor is connected to the third clock signal line, the first electrode of the seventeenth transistor is connected to the second power line, and the second electrode of the seventeenth transistor is connected to the third control node. The control electrode of the eighteenth transistor is connected to the third control node, the first electrode of the eighteenth transistor is connected to the first power line, and the second electrode of the eighteenth transistor is connected to the fourth output terminal. The control electrode of the nineteenth transistor is connected to the second electrode of the twenty-second transistor, the first electrode of the nineteenth transistor is connected to the fourth clock signal line, and the second electrode of the nineteenth transistor is connected to the fourth output terminal. The control electrode of the twentieth transistor is connected to the third control node, the first electrode of the twentieth transistor is connected to the first power line, and the second electrode of the twentieth transistor is connected to the first electrode of the twenty-first transistor. The control electrode of the twenty-first transistor is connected to the fourth clock signal line, and the second electrode of the twenty-first transistor is connected to the fourth control node. The control electrode of the twenty-second transistor is connected to the second power supply line, the first electrode of the twenty-second transistor is connected to the fourth control node, and the second electrode of the twenty-second transistor is connected to the control electrode of the nineteenth transistor. The control electrode of the twenty-third transistor is connected to the fourth output terminal, the first electrode of the twenty-third transistor is connected to the second power supply line, and the second electrode of the twenty-third transistor is connected to the fifth output terminal. The control electrode of the twenty-fourth transistor is connected to the fourth output terminal, the first electrode of the twenty-fourth transistor is connected to the first power supply line, and the second electrode of the twenty-fourth transistor is connected to the fifth output terminal. The first electrode of the fourth capacitor is connected to the control electrode of the eighteenth transistor, and the second electrode of the fourth capacitor is connected to the first power supply line. The first electrode of the fifth capacitor is connected to the control electrode of the nineteenth transistor, and the second electrode of the fifth capacitor is connected to the fourth output terminal.

[0020] On the other hand, an embodiment of the present disclosure provides a display substrate, comprising: a display area and a peripheral area located around the display area. The display area is provided with a plurality of sub-pixels. The peripheral area is provided with a gate drive circuit. The gate drive circuit comprises: a plurality of cascaded first shift register units, the first shift register units being the shift register units described above. At least one sub-pixel comprises a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The nth-stage first shift register unit of the gate drive circuit is configured to provide a gate drive signal to the pixel circuit of the nth row of sub-pixels, wherein n is an integer greater than 0.

[0021] In some exemplary embodiments, the pixel circuit includes: a data writing subcircuit, a driving subcircuit, a storage subcircuit, a compensation subcircuit, a level holding subcircuit, a light emitting control subcircuit, a first initialization subcircuit, and a second initialization subcircuit. The data writing subcircuit is connected to the data line, the first scan line, and the second node, and is configured to write the signal of the data line to the storage subcircuit under the control of the first scan line. The driving subcircuit is connected to the third power line, the first node, and the third node, and is configured to output a driving current to the light emitting control subcircuit through the third node under the control of the first node. The storage subcircuit is connected to the first node and the second node. The level holding subcircuit is connected to the third power line and the second node, and is configured to maintain the potential of the second node. The compensation subcircuit is connected to the second scan line, the first node, and the third node, and is configured to compensate for the threshold voltage of the driving subcircuit under the control of the second scan line. The first initialization subcircuit is connected to the first reset signal line, the initial voltage line, and the first node, and is configured to initialize the first node under the control of the first reset signal line. The second initialization subcircuit is connected to the second reset signal line, the reference voltage line and the second node, and is configured to initialize the second node under the control of the second reset signal line. The light-emitting control subcircuit is connected to the light-emitting control line, the third node and the first electrode of the light-emitting element, and is configured to drive the light-emitting element to emit light according to the driving current under the control of the light-emitting control line. The second electrode of the light-emitting element is connected to the fourth power line. The writing time length of the data writing subcircuit writing the signal of the data line into the storage subcircuit is less than the threshold voltage compensation time length of the compensation subcircuit to the driving subcircuit. The third output end of the nth stage first shift register unit of the gate driving circuit is connected to the second reset signal line of the pixel circuit driving the nth row of sub-pixels; the second output end of the nth stage first shift register unit is connected to the second scan line of the pixel circuit driving the nth row of sub-pixels.

[0022] In some exemplary embodiments, the pixel circuit further includes: a third initialization subcircuit connected to a third reset signal line, an initial voltage line, and a first electrode of the light-emitting element, and configured to initialize the first electrode of the light-emitting element under the control of the third reset signal line. The third reset signal line connected to the pixel circuit of the nth row of sub-pixels is configured to be connected to the second reset signal line of the pixel circuit driving the n+1th row of sub-pixels.

[0023] In some exemplary embodiments, the data writing subcircuit includes: a data writing transistor, the control electrode of the data writing transistor is connected to the first scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the second node. The driving subcircuit includes: a driving transistor, the control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the third power line, and the second electrode of the driving transistor is connected to the third node. The storage subcircuit includes: a storage capacitor, the first electrode of the storage capacitor is connected to the first node, and the second electrode of the storage capacitor is connected to the second node. The level keeping subcircuit includes: a voltage stabilizing capacitor, the first electrode of the voltage stabilizing capacitor is connected to the second node, and the first electrode of the voltage stabilizing capacitor is connected to the third power line. The compensation subcircuit includes: a compensation transistor, the control electrode of the compensation transistor is connected to the second scan line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node. The light emission control subcircuit includes: a light emission control transistor, the control electrode of the light emission control transistor is connected to the light emission control line, the first electrode of the light emission control transistor is connected to the third node, and the second electrode of the light emission control transistor is connected to the first electrode of the light emitting element. The first initialization subcircuit includes: a first initialization transistor, the control electrode of the first initialization transistor is connected to the first reset signal line, the first electrode of the first initialization transistor is connected to the initial voltage line, and the second electrode of the first initialization transistor is connected to the first node. The second initialization subcircuit includes: a second initialization transistor, the control electrode of the second initialization transistor is connected to the second reset signal line, the first electrode of the second initialization transistor is connected to the reference voltage line, and the second electrode of the second initialization transistor is connected to the second node. The third initialization subcircuit includes: a third initialization transistor, the control electrode of the third initialization transistor is connected to the third reset signal line, the first electrode of the third initialization transistor is connected to the initial voltage line, and the second electrode of the third initialization transistor is connected to the first electrode of the light-emitting element.

[0024] In some exemplary embodiments, the compensation transistor and the first initialization transistor are first semiconductor type transistors, the driving transistor, the data writing transistor, the light emitting control transistor, the second initialization transistor and the third initialization transistor are second semiconductor type transistors; the doping types of the first semiconductor type and the second semiconductor type are opposite.

[0025] In some exemplary embodiments, the gate drive circuit further includes: a plurality of cascaded second shift register units. The second shift register unit includes: a second input terminal, a fourth output terminal, and a fifth output terminal. The second input terminal of the first-stage second shift register unit is connected to the second initial signal line; the second input terminal of the n+1-stage second shift register unit is connected to the fourth output terminal of the n-stage second shift register unit. The fourth output terminal of the n-stage second shift register unit is connected to the first scan line of the pixel circuit driving the n-2-th row of sub-pixels. The fifth output terminal of the n-stage second shift register unit is connected to the first reset signal line of the pixel circuit driving the n-th row of sub-pixels.

[0026] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above.

[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0029] Figure 1 is a schematic structural diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0030] Figure 2 is a schematic structural diagram of an output circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0031] Figure 3 is an equivalent circuit diagram of an output circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0032] Figure 4 is an equivalent circuit diagram of a second control circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0033] Figure 5 is an equivalent circuit diagram of an input circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0034] Figure 6 is an equivalent circuit diagram of a first control circuit of a shift register unit according to at least one embodiment of the present disclosure;

[0035] Figure 7 is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0036] Figure 8 for Figure 7 The working timing diagram of the shift register unit shown;

[0037] Fig. 9 is a flow chart of a driving method of a shift register unit according to at least one embodiment of the present disclosure;

[0038] Fig.10 A schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0039] Fig.11 is another schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0040] Fig.12 is an equivalent circuit diagram of a second shift register unit according to at least one embodiment of the present disclosure;

[0041] Fig.13 for Fig.12 The working timing diagram of the second shift register unit shown;

[0042] Fig.14 is another schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0043] Fig.15 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0044] Fig.16 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0045] Fig.17 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0046] Fig.18 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0047] Fig.19 for Fig.18 The working timing diagram of the pixel circuit shown;

[0048] Fig. 20 A top view of a sub-pixel in a display area of ​​at least one embodiment of the present disclosure;

[0049] Fig.21 for Fig. 20 Schematic diagram of the cross section along the QQ direction;

[0050] Fig. 22 A top view of a sub-pixel after forming a first semiconductor layer according to at least one embodiment of the present disclosure;

[0051] Fig.23 A top view of a sub-pixel after forming a first conductive layer according to at least one embodiment of the present disclosure;

[0052] Fig.24 A top view of a sub-pixel after forming a second semiconductor layer according to at least one embodiment of the present disclosure;

[0053] Fig.25 A top view of a sub-pixel after forming a second conductive layer according to at least one embodiment of the present disclosure;

[0054] Fig.26 is a top view of a sub-pixel after a fifth insulating layer is formed according to at least one embodiment of the present disclosure;

[0055] Fig. 27 is a top view of a sub-pixel after a third conductive layer is formed according to at least one embodiment of the present disclosure;

[0056] Fig.28 is another top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure;

[0057] Fig.29 for Fig.28 Schematic diagram of the cross section along the HH direction;

[0058] Fig.30 is a top view of a sub-pixel after a fifth insulating layer is formed according to at least one embodiment of the present disclosure;

[0059] Fig.31 is a top view of a sub-pixel after a third conductive layer is formed according to at least one embodiment of the present disclosure;

[0060] Fig.32 is a top view of a sub-pixel after a seventh insulating layer is formed according to at least one embodiment of the present disclosure;

[0061] Fig.33 is a top view of a sub-pixel after a fourth conductive layer is formed according to at least one embodiment of the present disclosure;

[0062] Fig.34 A schematic diagram of the connection between a gate driving circuit and a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Fig.35 is a top view of a first shift register unit according to at least one embodiment of the present disclosure;

[0064] Fig.36for Fig.35 Schematic diagram of the cross section along the PP direction;

[0065] Fig.37 is a top view of a first shift register unit after forming a first semiconductor layer according to at least one embodiment of the present disclosure;

[0066] Fig.38 is a top view of a first shift register unit after forming a first conductive layer according to at least one embodiment of the present disclosure;

[0067] Fig.39 is a top view of a first shift register unit after forming a second semiconductor layer according to at least one embodiment of the present disclosure;

[0068] Fig.40 is a top view of a first shift register unit after forming a second conductive layer according to at least one embodiment of the present disclosure;

[0069] Fig.41 is a top view of the first shift register unit after the fifth insulating layer is formed according to at least one embodiment of the present disclosure;

[0070] Fig.42 is a top view of a first shift register unit after a third conductive layer is formed according to at least one embodiment of the present disclosure;

[0071] Fig.43 is an equivalent circuit diagram of a third shift register unit according to at least one embodiment of the present disclosure;

[0072] Fig.44 for Fig.43 The working timing diagram of the third shift register unit shown;

[0073] Fig.45 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] The following will describe the embodiments of the present disclosure in detail with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0075] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0076] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure means a quantity of two or more.

[0077] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0078] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transfer electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0079] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0080] In the present disclosure, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is called the first electrode and the other electrode is called the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate of the transistor is called a control electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0081] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0082] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0083] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0084] In the present disclosure, the effective level signal includes a level signal that turns on a transistor. For example, the effective level signal that turns on a P-type transistor is a low level signal, and the effective level signal that turns on an N-type transistor is a high level signal.

[0085] The embodiment of the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display substrate. The shift register unit of the embodiment can provide a variety of different gate driving signals to the pixel circuit to improve the performance of the pixel circuit.

[0086] Figure 1 FIG. 1 is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure. Figure 1As shown, the shift register unit provided by the embodiment of the present disclosure includes: an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is connected to the first clock signal line CK1, the second clock signal line CB1, the first input terminal INPUT1, the first power line VGH, the first control node P1 and the second control node P2, and is configured to provide the signal of the first input terminal INPUT1 to the second control node P2 under the control of the first clock signal line CLK1, and to provide the signal of the first clock signal line CK1 or the first power line VGH to the first control node P1 under the control of the second clock signal line CB1, the first input terminal INPUT1 and the second control node P2. The first control circuit is connected to the first power line VGH, the second power line VGL, the first control node P1, the second control node P2 and the first output terminal OUT1, and is configured to provide the signal of the first power line VGH or the second power line VGL to the first output terminal OUT1 under the control of the first control node P1 and the second control node P2. The second control circuit is connected to the first power line VGH, the second power line VGL, the first output terminal OUT1 and the second output terminal OUT2, and is configured to provide the effective level signal of the first power line VGH or the second power line VGL to the second output terminal OUT2 under the control of the first output terminal OUT1. The output circuit is connected to the first power line VGH, the second power line VGL, the control signal line CSL, the second output terminal OUT2 and the third output terminal OUT3, and is configured to output the effective level signal of the first power line VGH or the second power line VGL to the third output terminal OUT3 under the control of the second output terminal OUT2 and the control signal line CSL. Within one frame time, the duration of the effective level signal provided by the third output terminal OUT3 is greater than the duration of the effective level signal provided by the second output terminal OUT2.

[0087] In some exemplary embodiments, the first power line VGH may continuously provide a high level signal, and the second power line VGL may continuously provide a low level signal. In some examples, the effective level signal provided by the third output terminal OUT3 is a low level signal provided by the second power line VGL, and the effective level signal provided by the second output terminal OUT2 may be a high level signal provided by the first power line VGH. However, this embodiment is not limited to this.

[0088] In some example embodiments, input signals of the first input terminal INPUT1 , the first clock signal line CK1 , the second clock signal line CB1 , and the control signal line CSL may be pulse signals.

[0089] In some exemplary embodiments, the phases of the output signal of the first output terminal OUT1 and the output signal of the second output terminal OUT2 are opposite. For example, the first input terminal of the first-stage shift register unit can be connected to the first initial signal line; the first output terminal of the n-th stage shift register unit can be connected to the first input terminal of the n+1-th stage shift register unit to provide an input signal to the n+1-th stage shift register unit, where n is an integer greater than 0. The output signal provided by the second output terminal can be configured to control the opening of an N-type transistor (e.g., an oxide thin film transistor) in a pixel circuit. However, this embodiment is not limited to this.

[0090] In some exemplary embodiments, the second output terminal OUT2 and the third output terminal OUT3 provide effective level signals with opposite polarities, and within a frame time, the third output terminal OUT3 outputs the effective level signal of the first power line VGH or the second power line VGL at intervals. In some examples, the output signal of the third output terminal can be the output signal of the second output terminal and the signal provided by the control signal line. For example, the output signal of the third output terminal can be configured to control the opening of a P-type transistor (e.g., a low-temperature polysilicon thin film transistor) in a pixel circuit. However, this embodiment is not limited to this.

[0091] In some exemplary embodiments, the valid level signal provided to the third output terminal OUT3 within one frame time includes: an interval of a first time period and a second time period. The first time period is configured to output the valid level signal of the second power line VGL to the third output terminal OUT3 under the control of the control signal line CSL. The second time period is configured to output the valid level signal of the second power line VGL to the third output terminal OUT3 under the control of the second output terminal OUT2. In some examples, the duration of the second time period is greater than the duration of the first time period. In some examples, the duration of the second time period is approximately equal to the duration of the second output terminal OUT2 providing the valid level signal.

[0092] In this exemplary embodiment, a variety of different output signals can be obtained through the first output terminal, the second output terminal and the third output terminal of the shift register unit, and these output signals can be provided to the pixel circuit as gate driving signals to improve the performance of the pixel circuit.

[0093] Figure 2 FIG. 1 is a schematic diagram of the structure of the output circuit of the shift register unit according to at least one embodiment of the present disclosure. Figure 2As shown, the output circuit in the shift register unit provided by this exemplary embodiment includes: a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is connected to the control signal line CSL, the first power line VGH, the second output terminal OUT2, and the third output terminal OUT3, and is configured to provide the effective level signal of the first power line VGH to the third output terminal OUT3 under the control of the control signal line CSL and the second output terminal OUT2. The second output sub-circuit is connected to the control signal line CSL, the second power line VGL, the second output terminal OUT2, and the third output terminal OUT3, and is configured to provide the effective level signal of the second power line VGL to the third output terminal OUT3 under the control of the control signal line CSL and the second output terminal OUT2.

[0094] In this exemplary embodiment, the output signal of the third output terminal can be different from the output signals of the first output terminal and the second output terminal through the first output sub-circuit and the second output sub-circuit, thereby providing a variety of different gate driving signals to the pixel circuit.

[0095] Figure 3 FIG. 1 is an equivalent circuit diagram of an output circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 3 As shown, the output circuit in the shift register unit provided by this exemplary embodiment includes a first output subcircuit and a second output subcircuit. The first output subcircuit includes: a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is connected to the control signal line CSL, the first electrode of the first transistor T1 is connected to the first power line VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is connected to the second output terminal OUT2, and the second electrode of the second transistor T2 is connected to the third output terminal OUT3. The second output subcircuit includes: a third transistor T3 and a fourth transistor T4. The control electrode of the third transistor T3 is connected to the second output terminal OUT2, the first electrode of the third transistor T3 is connected to the second power line VGL, and the second electrode of the third transistor T3 is connected to the third output terminal OUT3. The control electrode of the fourth transistor T4 is connected to the control signal line CSL, the first electrode of the fourth transistor T4 is connected to the second power line VGL, and the second electrode of the fourth transistor T4 is connected to the third output terminal OUT3.

[0096] In this exemplary embodiment, Figure 3 An exemplary structure of the output circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the output circuit is not limited thereto, as long as its function can be achieved.

[0097] Figure 4 FIG. 4 is an equivalent circuit diagram of a second control circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 4As shown, the second control circuit in the shift register unit provided by this exemplary embodiment includes: a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is connected to the first output terminal OUT1, the first electrode of the fifth transistor T5 is connected to the first power line VGH, and the second electrode of the fifth transistor T5 is connected to the second output terminal OUT2. The control electrode of the sixth transistor T6 is connected to the first output terminal OUT1, the first electrode of the sixth transistor T6 is connected to the second power line VGL, and the second electrode of the sixth transistor T6 is connected to the second output terminal OUT2.

[0098] In this exemplary embodiment, Figure 4 An exemplary structure of the second control circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the second control circuit is not limited thereto, as long as its function can be achieved.

[0099] Figure 5 FIG. 1 is an equivalent circuit diagram of an input circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 5 As shown, the input circuit in the shift register unit provided by this exemplary embodiment includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a first capacitor C1. The control electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9, the first electrode of the seventh transistor T7 is connected to the first clock signal line CK1, and the second electrode of the seventh transistor T7 is connected to the first control node P1. The control electrode of the eighth transistor T8 is connected to the first input terminal INPUT1, and the first electrode of the eighth transistor T8 is connected to the first power line VGH. The control electrode of the ninth transistor T9 is connected to the second clock signal line CB1, and the first electrode of the ninth transistor T9 is connected to the first power line VGH. The control electrode of the tenth transistor T10 is connected to the first clock signal line CK1, the first electrode of the tenth transistor T10 is connected to the first input terminal INPUT1, and the second electrode of the tenth transistor T10 is connected to the second control node P2. The control electrode of the eleventh transistor T11 is connected to the second control node P2, the first electrode of the eleventh transistor T11 is connected to the first power line VGH, and the second electrode of the eleventh transistor T11 is connected to the first control node P1. The first electrode of the first capacitor C1 is connected to the control electrode of the seventh transistor T7, and the second electrode of the first capacitor C1 is connected to the first electrode of the seventh transistor T7.

[0100] In this exemplary embodiment, Figure 5 An exemplary structure of the input circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the input circuit is not limited thereto, as long as its function can be achieved.

[0101] Figure 6FIG. 4 is an equivalent circuit diagram of a first control circuit of a shift register unit according to at least one embodiment of the present disclosure. Figure 6 As shown, the first control circuit in the shift register unit provided in this embodiment includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second capacitor C2 and a third capacitor C3. The control electrode of the twelfth transistor T12 is connected to the second power line VGL, the first electrode of the twelfth transistor T12 is connected to the second control node P2, and the second electrode of the twelfth transistor T12 is connected to the control electrode of the thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is connected to the second power line VGL, and the second electrode of the thirteenth transistor T13 is connected to the first output terminal OUT1. The control electrode of the fourteenth transistor T14 is connected to the first control node P1, the first electrode of the fourteenth transistor T14 is connected to the first power line VGH, and the second electrode of the fourteenth transistor T14 is connected to the first output terminal OUT1. The first electrode of the second capacitor C2 is connected to the control electrode of the thirteenth transistor T13, and the second electrode of the second capacitor C2 is connected to the first output terminal OUT1. The first electrode of the third capacitor C3 is connected to the control electrode of the fourteenth transistor T14, and the second electrode of the third capacitor C3 is connected to the first power line VGH.

[0102] In this exemplary embodiment, Figure 6 An exemplary structure of the first control circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the first control circuit is not limited thereto, as long as its function can be achieved.

[0103] Figure 7 FIG. 1 is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure. Figure 7 As shown, the shift register unit provided by this exemplary embodiment includes: an input circuit, a first control circuit, a second control circuit and an output circuit. Among them, the output circuit includes: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4. The second control circuit includes: a fifth transistor T5 and a sixth transistor T6. The input circuit includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a first capacitor C1. The first control circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second capacitor C2 and a third capacitor C3.

[0104] In the present exemplary embodiment, the control electrode of the first transistor T1 is connected to the control signal line CSL, the first electrode of the first transistor T1 is connected to the first power line VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is connected to the second output terminal OUT2, and the second electrode of the second transistor T2 is connected to the third output terminal OUT3. The control electrode of the third transistor T3 is connected to the second output terminal OUT2, the first electrode of the third transistor T3 is connected to the second power line VGL, and the second electrode of the third transistor T3 is connected to the third output terminal OUT3. The control electrode of the fourth transistor T4 is connected to the control signal line CSL, the first electrode of the fourth transistor T4 is connected to the second power line VGL, and the second electrode of the fourth transistor T4 is connected to the third output terminal OUT3. The control electrode of the fifth transistor T5 is connected to the first output terminal OUT1, the first electrode of the fifth transistor T5 is connected to the first power line VGH, and the second electrode of the fifth transistor T5 is connected to the second output terminal OUT2. The control electrode of the sixth transistor T6 is connected to the first output terminal OUT1, the first electrode of the sixth transistor T6 is connected to the second power line VGL, and the second electrode of the sixth transistor T6 is connected to the second output terminal OUT2. The control electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9, the first electrode of the seventh transistor T7 is connected to the first clock signal line CK1, and the second electrode of the seventh transistor T7 is connected to the first control node P1. The control electrode of the eighth transistor T8 is connected to the first input terminal INPUT1, and the first electrode of the eighth transistor T8 is connected to the first power line VGH. The control electrode of the ninth transistor T9 is connected to the second clock signal line CB1, and the first electrode of the ninth transistor T9 is connected to the first power line VGH. The control electrode of the tenth transistor T10 is connected to the first clock signal line CK1, the first electrode of the tenth transistor T10 is connected to the first input terminal INPUT1, and the second electrode of the tenth transistor T10 is connected to the second control node P2. The control electrode of the eleventh transistor T11 is connected to the second control node P2, the first electrode of the eleventh transistor T11 is connected to the first power line VGH, and the second electrode of the eleventh transistor T11 is connected to the first control node P1. The control electrode of the twelfth transistor T12 is connected to the second power line VGL, the first electrode of the twelfth transistor T12 is connected to the second control node P2, and the second electrode of the twelfth transistor T12 is connected to the control electrode of the thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is connected to the second power line VGL, and the second electrode of the thirteenth transistor T13 is connected to the first output terminal OUT1. The control electrode of the fourteenth transistor T14 is connected to the first control node P1, the first electrode of the fourteenth transistor T14 is connected to the first power line VGH, and the second electrode of the fourteenth transistor T14 is connected to the first output terminal OUT1.The first electrode of the first capacitor C1 is connected to the control electrode of the seventh transistor T7, and the second electrode of the first capacitor C1 is connected to the first electrode of the seventh transistor T7. The first electrode of the second capacitor C2 is connected to the control electrode of the thirteenth transistor T13, and the second electrode of the second capacitor C2 is connected to the first output terminal OUT1. The first electrode of the third capacitor C3 is connected to the control electrode of the fourteenth transistor T14, and the second electrode of the third capacitor C3 is connected to the first power line VGH.

[0105] In some exemplary embodiments, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are first semiconductor type transistors, the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 to the fourteenth transistor T14 are second semiconductor type transistors, and the doping types of the first semiconductor type and the second semiconductor type are opposite. In some examples, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are N-type thin film transistors, for example, oxide (Oxide) thin film transistors, such as indium gallium zinc oxide (IGZO, Indium Gallium Zinc Oxide) thin film transistors. The first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7 to the fourteenth transistor T14 are P-type thin film transistors, for example, low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) thin film transistors. In addition, the embodiment of the present disclosure can select a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized. This embodiment is not limited to this.

[0106] The technical solution of the embodiment of the present disclosure is further described below through the working process of the shift register unit. The working process of the first stage shift register unit is described below as an example, and the first input terminal INPUT1 of the first stage shift register unit is connected to the first initial signal line STV1. Figure 8 for Figure 7 The working timing diagram of the shift register unit is shown in FIG. Figure 7 and Figure 8 As shown, the shift register unit of this exemplary embodiment includes 14 transistor units (i.e., the first transistor T1 to the fourteenth transistor T14), 3 capacitor units (i.e., the first capacitor C1 to the third capacitor C3), 4 input terminals (i.e., the first clock signal line CK1, the second clock signal line CB2, the first input terminal INPUT1 and the control signal line CSL), 3 output terminals (i.e., the first output terminal OUT1, the second output terminal OUT2 and the third output terminal OUT3) and 2 power supply terminals (i.e., the first power supply line VGH and the second power supply line VGL). Among them, the first power supply line VGH continuously provides a high level signal, and the second power supply line VGL continuously provides a low level signal.

[0107] In some examples, the output signal of the second output terminal OUT2 can be configured to turn on an N-type thin film transistor in the pixel circuit, and the output signal of the third output terminal OUT3 can be configured to turn on a P-type thin film transistor in the pixel circuit. However, the present disclosure is not limited to this.

[0108] The operation process of the shift register unit provided by this exemplary embodiment includes the following eight stages.

[0109] In the first stage t11, the first clock signal line CK1 inputs a low level signal, the second clock signal line CB1 inputs a high level signal, the first initial signal line STV1 inputs a high level signal, and the control signal line CSL inputs a high level signal. The tenth transistor T10 is turned on, and the potential of the second control node P2 is pulled up. The eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are turned off, the seventh transistor T7 is turned on, and the potential of the first control node P1 is pulled down. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low level signal. The second transistor T2 and the fourth transistor T4 are turned on, the first transistor T1 and the third transistor T3 are turned off, and the third output terminal OUT3 outputs a low level signal.

[0110] In the second stage t12, the first clock signal line CK1 inputs a high level signal, the second clock signal line CB1 inputs a low level signal, the first initial signal line STV1 inputs a low level signal, and the control signal line CSL inputs a low level signal. The eighth transistor T8 and the ninth transistor T9 are turned on, the seventh transistor T7, the tenth transistor T10 and the eleventh transistor T11 are turned off, the first control node P1 is maintained at a low potential, and the second control node P2 is maintained at a high potential. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low level signal. The third transistor T3 and the fourth transistor T4 are turned off, the first transistor T1 and the second transistor T2 are turned on, and the third output terminal OUT3 outputs a high level signal.

[0111] In the third stage t13, the first clock signal line CK1 inputs a low level signal, the second clock signal line CB1 inputs a high level signal, the first initial signal line STV1 inputs a low level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned on, and the potential of the second control node P2 is pulled down. The eighth transistor T8 and the eleventh transistor T11 are turned on, the seventh transistor T7 and the ninth transistor T9 are turned off, and the potential of the first control node P1 is pulled up. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high level signal. The first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a low level signal.

[0112] In the fourth stage t14, the first clock signal line CK1 inputs a high level signal, the second clock signal line CB1 inputs a low level signal, the first initial signal line STV1 inputs a low level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned off, and the second control node P2 is maintained at a low potential. The eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are turned on, the seventh transistor T7 is turned off, and the first control node P1 is maintained at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high level signal. The first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a low level signal.

[0113] In the fifth stage t15, the first clock signal line CK1 inputs a low level signal, the second clock signal line CB1 inputs a high level signal, the first initial signal line STV1 inputs a low level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned on, and the second control node P2 is maintained at a low potential. The eighth transistor T8 and the eleventh transistor T11 are turned on, the ninth transistor T9 and the seventh transistor T7 are turned off, and the first control node P1 is maintained at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high level signal. The second transistor T2 and the fourth transistor T4 are turned off, the first transistor T1 and the third transistor T3 are turned on, and the third output terminal OUT3 outputs a low level signal.

[0114] In the sixth stage t16, the first clock signal line CK1 inputs a high level signal, the second clock signal line CB1 inputs a low level signal, the first initial signal line STV1 inputs a high level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned off, and the second control node P2 is maintained at a low potential. The eighth transistor T8 and the seventh transistor T7 are turned off, the ninth transistor T9 and the eleventh transistor T11 are turned on, and the first control node P1 is maintained at a high potential. The twelfth transistor T12 and the thirteenth transistor T13 are turned on, the fourteenth transistor T14 is turned off, and the first output terminal OUT1 outputs a low level signal. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the second output terminal OUT2 outputs a high level signal. The second transistor T2 and the fourth transistor T4 are turned off, the first transistor T1 and the third transistor T3 are turned on, and the third output terminal OUT3 outputs a low level signal.

[0115] In the seventh stage t17, the first clock signal line CK1 inputs a low level signal, the second clock signal line CB1 inputs a high level signal, the first initial signal line STV1 inputs a high level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned on, and the potential of the second control node P2 is pulled up. The eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are turned off, the seventh transistor T7 is turned on, and the potential of the first control node P1 is pulled down. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low level signal. The first transistor T1 and the second transistor T2 are turned on, the third transistor T3 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a high level signal.

[0116] In the eighth stage t18, the first clock signal line CK1 inputs a high level signal, the second clock signal line CB1 inputs a low level signal, the first initial signal line STV1 inputs a high level signal, and the control signal line CSL inputs a low level signal. The tenth transistor T10 is turned off, and the second control node P2 is maintained at a high potential. The eighth transistor T8, the seventh transistor T7 and the eleventh transistor T11 are turned off, the ninth transistor T9 is turned on, and the first control node P1 is maintained at a low potential. The twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 is turned off, and the first output terminal OUT1 outputs a high level signal. The fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the second output terminal OUT2 outputs a low level signal. The first transistor T1 and the second transistor T2 are turned on, the third transistor T3 and the fourth transistor T4 are turned off, and the third output terminal OUT3 outputs a high level signal.

[0117] After the eighth stage t18 , the seventh stage t17 and the eighth stage t18 may be repeated until the first input terminal INPUT1 inputs a low level signal and the control signal line CSL inputs a high level signal, and then restarts from the first stage.

[0118] According to the working process of the above-mentioned shift register unit, in the third stage t13 to the sixth stage t16, the first output terminal OUT1 outputs a low-level signal, the second output terminal OUT2 outputs a high-level signal, and the third output terminal OUT3 outputs a low-level signal, and in the first stage t11, the third output terminal OUT3 also outputs a low-level signal. In one frame time, the third output terminal OUT3 outputs a low-level signal at intervals. Among them, the phases of the output signals provided by the first output terminal OUT1 and the second output terminal OUT2 are opposite. The effective level signal provided by the second output terminal OUT2 is a high-level signal, and the effective level signal provided by the third output terminal OUT3 is a low-level signal, and in one frame time, the duration of the low-level signal output by the third output terminal OUT3 is greater than the duration of the high-level signal output by the second output terminal OUT2.

[0119] The disclosed embodiment also provides a driving method of a shift register unit. Fig. 9 FIG. 1 is a flow chart of a driving method of a shift register unit according to an embodiment of the present disclosure. Fig. 9 As shown, the driving method of the shift register unit provided in this embodiment is applied to the shift register unit provided in the above embodiments. The driving method provided in this embodiment may include the following steps.

[0120] Step S101: The input circuit provides a signal of the first input terminal to the second control node under the control of the first clock signal line, and provides a signal of the first clock signal line or the first power line to the first control node under the control of the second clock signal line, the first input terminal and the second control node;

[0121] Step S102: The first control circuit provides a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node;

[0122] Step S103: the second control circuit provides an effective level signal of the first power supply terminal or the second power supply line to the second output node under the control of the first output node;

[0123] Step S104: under the control of the control signal line and the second output terminal, the output circuit outputs the effective level signal of the first power line or the second power line to the third output terminal; within one frame time, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

[0124] In some exemplary embodiments, step S104 may include: the output circuit outputs the effective level signal of the second power line to the third output terminal in the first time period within a frame time under the control of the control signal line; the output circuit outputs the effective level signal of the second power line to the third output terminal in the second time period spaced apart from the first time period within a frame time under the control of the second output terminal. In this exemplary embodiment, the first time period and the second time period within a frame time are non-continuous, and the effective level signal of the first power line can be output to the third output terminal between the first time period and the second time period. In some examples, the duration of the first time period is less than the duration of the second time period.

[0125] The driving method of the shift register unit, the structure of the shift register unit and the working process thereof provided by this exemplary embodiment have been described in the above embodiments and will not be described again here.

[0126] The embodiment of the present disclosure also provides a gate driving circuit. Fig.10 FIG. 1 is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Fig.10 As shown, the gate driving circuit provided by this exemplary embodiment includes a plurality of cascaded first shift register units GOA1. The first shift register unit GOA1 is the shift register unit provided by the above embodiment, and its implementation principle and implementation effect are similar, so they are not repeated here.

[0127] In this exemplary embodiment, Fig.10 As shown, the first input terminal INPUT1 of the first stage first shift register unit is connected to the first initial signal line STV1. The first input terminal of the n+1th stage first shift register unit is connected to the first output terminal of the nth stage first shift register unit, where n is an integer greater than 0.

[0128] Fig.11 FIG. 1 is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Fig.11As shown, the gate drive circuit provided in this exemplary embodiment includes: a plurality of cascaded first shift register units GOA1 and a plurality of cascaded second shift register units GOA2. The first shift register unit GOA1 is the shift register unit provided in the above embodiment, and its implementation principle and implementation effect are similar, so it is not repeated here. The second shift register unit GOA2 includes: a second input terminal INPUT2, a fourth output terminal OUT4 and a fifth output terminal OUT5. Among them, the second input terminal of the first-level second shift register unit is connected to the second initial signal line STV2; the second input terminal of the n+1-th level second shift register unit is connected to the fourth output terminal of the n-th level second shift register unit. The fifth output terminal of the n-th level second shift register unit is connected to the control signal line CSL of the n-th level first shift register unit. Among them, n is an integer greater than 0. In this exemplary embodiment, the second shift register unit provides a control signal to the first shift register unit through the control signal line. However, this embodiment is not limited to this.

[0129] Fig.12 FIG. 1 is an equivalent circuit diagram of a second shift register unit according to at least one embodiment of the present disclosure. Fig.12As shown, the second shift register unit provided by this exemplary embodiment includes: a fifteenth transistor T15 to a twenty-fourth transistor T24, a fourth capacitor C4 and a fifth capacitor C5. The control electrode of the fifteenth transistor T15 is connected to the third clock signal line CK2, the first electrode of the fifteenth transistor T15 is connected to the second input terminal INPUT2, and the second electrode of the fifteenth transistor T15 is connected to the fourth control node P4. The control electrode of the sixteenth transistor T16 is connected to the fourth control node P4, the first electrode of the sixteenth transistor T16 is connected to the third clock signal line CK2, and the second electrode of the sixteenth transistor T16 is connected to the third control node P3. The control electrode of the seventeenth transistor T17 is connected to the third clock signal line CK2, the first electrode of the seventeenth transistor T17 is connected to the second power line VGL, and the second electrode of the seventeenth transistor T17 is connected to the third control node P3. The control electrode of the eighteenth transistor T18 is connected to the third control node P3, the first electrode of the eighteenth transistor T18 is connected to the first power line VGH, and the second electrode of the eighteenth transistor T18 is connected to the fourth output terminal OUT4. The control electrode of the nineteenth transistor T19 is connected to the second electrode of the twenty-second transistor T22, the first electrode of the nineteenth transistor T19 is connected to the fourth clock signal line CB2, and the second electrode of the nineteenth transistor T19 is connected to the fourth output terminal OUT4. The control electrode of the twentieth transistor T20 is connected to the third control node P3, the first electrode of the twentieth transistor T20 is connected to the first power line VGH, and the second electrode of the twentieth transistor T20 is connected to the first electrode of the twenty-first transistor T21. The control electrode of the twenty-first transistor T21 is connected to the fourth clock signal line CB2, and the second electrode of the twentieth transistor T21 is connected to the fourth control node P4. The control electrode of the twenty-second transistor T22 is connected to the second power line VGL, the first electrode of the twenty-second transistor T22 is connected to the fourth control node P4, and the second electrode of the twenty-second transistor T22 is connected to the control electrode of the nineteenth transistor T19. The control electrode of the twenty-third transistor T23 is connected to the fourth output terminal OUT4, the first electrode of the twenty-third transistor T23 is connected to the second power line VGL, and the second electrode of the twenty-third transistor T23 is connected to the fifth output terminal OUT5. The control electrode of the twenty-fourth transistor T24 is connected to the fourth output terminal OUT4, the first electrode of the twenty-fourth transistor T24 is connected to the first power line VGH, and the second electrode of the twenty-fourth transistor T24 is connected to the fifth output terminal OUT5. The first electrode of the fourth capacitor C4 is connected to the control electrode of the eighteenth transistor T18, and the second electrode of the fourth capacitor C4 is connected to the first power line VGH. The first electrode of the fifth capacitor C5 is connected to the control electrode of the nineteenth transistor T19, and the second electrode of the fifth capacitor C5 is connected to the fourth output terminal OUT4.

[0130] In some examples, the twenty-third transistor T23 in the second shift register unit is an N-type transistor, such as an oxide thin film transistor; the remaining transistors in the second shift register unit are P-type transistors, such as low temperature polycrystalline silicon thin film transistors. However, this embodiment is not limited to this.

[0131] The working process of the first-stage second shift register unit is taken as an example for description below. The second input terminal INPUT2 of the first-stage second shift register unit is connected to the second initial signal line STV2. Fig.13 for Fig.12 The working timing diagram of the second shift register unit is shown in FIG. Fig.12 and Fig.13 As shown, the second shift register unit of the exemplary embodiment includes 10 transistor units (i.e., the fifteenth transistor T15 to the twenty-fourth transistor T24), 2 capacitor units (i.e., the fourth capacitor C4 and the fifth capacitor C5), 3 input terminals (i.e., the third clock signal line CK2, the fourth clock signal line CB2, and the second input terminal INPUT2), 2 output terminals (i.e., the fourth output terminal OUT4 and the fifth output terminal OUT5), and 2 power supply terminals (i.e., the first power supply line VGH and the second power supply line VGL). Among them, the first power supply line VGH continuously provides a high level signal, and the second power supply line VGL continuously provides a low level signal.

[0132] In some examples, the output signal of the fourth output terminal OUT4 and the output signal of the fifth output terminal OUT5 have opposite phases. The output signal of the fourth output terminal OUT4 can be configured to turn on a P-type transistor in the pixel circuit, and the output signal of the fifth output terminal OUT5 can be configured to turn on an N-type transistor in the pixel circuit. However, the present disclosure is not limited to this.

[0133] The working process of the second shift register unit provided by this exemplary embodiment includes the following five stages.

[0134] In the first stage t21, the third clock signal line CK2 inputs a high level signal, the fourth clock signal line CB2 inputs a low level signal, and the second initial signal line STV2 inputs a high level signal. The seventeenth transistor T17, the fifteenth transistor T15, the sixteenth transistor T16, and the nineteenth transistor T19 are turned off, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the eighteenth transistor T18 are turned on, and the fourth output terminal OUT4 outputs a high level signal. The twenty-third transistor T23 is turned on, the twenty-fourth transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low level signal.

[0135] In the second stage t22, the third clock signal line CK2 inputs a low level signal, the fourth clock signal line CB2 inputs a high level signal, and the second initial signal line STV2 inputs a low level signal. The fifteenth transistor T15, the seventeenth transistor T17, the sixteenth transistor T16, the twenty-second transistor T22, the twentieth transistor T20, the eighteenth transistor T18, and the nineteenth transistor T19 are turned on, the twenty-first transistor T21 is turned off, and the fourth output terminal OUT4 outputs a high level signal. The twenty-third transistor T23 is turned on, the twenty-fourth transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low level signal.

[0136] In the third stage t23, the third clock signal line CK2 inputs a high level signal, the fourth clock signal line CB2 inputs a low level signal, and the second initial signal line STV2 inputs a high level signal. The fifteenth transistor T15, the seventeenth transistor T17, the twentieth transistor T20, and the eighteenth transistor T18 are turned off, the sixteenth transistor T16, the twenty-first transistor T21, the twenty-second transistor T22, and the nineteenth transistor T19 are turned on, and the fourth output terminal OUT4 outputs a low level signal. The twenty-third transistor T23 is turned off, the twenty-fourth transistor T24 is turned on, and the fifth output terminal OUT5 outputs a high level signal.

[0137] In the fourth stage t24, the third clock signal line CK2 inputs a low level signal, the fourth clock signal line CB2 inputs a high level signal, and the second initial signal line STV2 inputs a high level signal. The fifteenth transistor T15, the seventeenth transistor T17, the sixteenth transistor T16, the twentieth transistor T20, the eighteenth transistor T18, the twenty-second transistor T22, and the nineteenth transistor T19 are turned on, the twenty-first transistor T21 is turned off, and the fourth output terminal OUT4 outputs a high level signal. The twenty-third transistor T23 is turned on, the twenty-fourth transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low level signal.

[0138] In the fifth stage t25, the third clock signal line CK2 inputs a high level signal, the fourth clock signal line CB2 inputs a low level signal, and the second initial signal line STV2 inputs a high level signal. The fifteenth transistor T15, the seventeenth transistor T17, the sixteenth transistor T16, and the nineteenth transistor T19 are turned off, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the eighteenth transistor T18 are turned on, and the fourth output terminal OUT4 outputs a high level signal. The twenty-third transistor T23 is turned on, the twenty-fourth transistor T24 is turned off, and the fifth output terminal OUT5 outputs a low level signal.

[0139] After the fifth stage t25, the fourth stage t24 and the fifth stage t25 may be repeated until the second input terminal INPUT2 inputs a low level signal, and then restart.

[0140] According to the working process of the second shift register unit described above, in the third stage, the fourth output terminal OUT4 outputs a low level signal, and the fifth output terminal OUT5 outputs a high level signal. In the remaining stages, the fourth output terminal OUT4 outputs a high level signal, and the fifth output terminal OUT5 outputs a low level signal. The output signals provided by the fourth output terminal OUT4 and the fifth output terminal OUT5 of the second shift register unit of this exemplary embodiment have opposite phases. The output signal of the fifth output terminal of the n-th stage second shift register unit can be provided to the n-th stage first shift register unit through the control signal line CSL.

[0141] In some examples, the clock signal cycles provided by the third clock signal line and the fourth clock signal line may be the same, and may be the same as the clock signal cycles provided by the first clock signal line and the second clock signal line. According to the working process of the second shift register unit and the first shift register unit, it can be known that the duration of the effective level signal provided by the fifth output terminal of the second shift register unit is less than the duration of the effective level signal provided by the third output terminal of the first shift register unit. The effective level signal provided by the third output terminal of the first shift register unit can be configured to control the threshold voltage compensation duration of the pixel circuit, and the effective level signal provided by the fifth output terminal of the second shift register unit can be configured to control the data signal writing duration of the pixel circuit. By separately controlling the threshold voltage compensation and data signal writing of the pixel circuit, fast data writing and sufficient compensation of the threshold voltage can be achieved, thereby reducing display defects and improving display effects.

[0142] Fig.14 FIG. 1 is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. Fig.14As shown, the gate drive circuit provided by this exemplary embodiment includes: a plurality of cascaded first shift register units GOA1 and a plurality of cascaded second shift register units GOA2. The first shift register unit GOA1 is the shift register unit provided in the above embodiment, and its implementation principle and implementation effect are similar, so it is not repeated here. The second shift register unit GOA2 includes: a second input terminal INPUT2, a fourth output terminal OUT4 and a fifth output terminal OUT5. Among them, the second input terminal of the first-stage second shift register unit is connected to the second initial signal line STV2; the second input terminal of the n+1-stage second shift register unit is connected to the fourth output terminal of the n-stage second shift register unit. The fourth output terminal of the n-stage second shift register unit is connected to the control signal line CSL of the n-stage first shift register unit. Among them, n is an integer greater than 0. In some examples, the first transistor in the first shift register unit can be an N-type transistor, and the fourth transistor can be a P-type transistor. In this exemplary embodiment, the second shift register unit provides a control signal to the first shift register unit through the control signal line. However, this embodiment is not limited to this. For the remaining structures of the second shift register unit and the first shift register unit in this exemplary embodiment, reference may be made to the description of the aforementioned embodiments, and thus will not be described in detail herein.

[0143] Fig.15 FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig.15 As shown, the display substrate of this exemplary embodiment includes: a display area AA and a peripheral area BB located around the display area AA. The display area AA at least includes a plurality of pixel units arranged regularly, a plurality of gate lines extending along a first direction X (for example, including: scan lines, reset signal lines, and light-emitting control lines), and a plurality of data lines and power lines extending along a second direction Y. The first direction X and the second direction Y are located in the same plane, and the first direction X is perpendicular to the second direction Y.

[0144] In some examples, a pixel unit in the display area AA may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0145] In some examples, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a square pattern. However, this embodiment is not limited to this.

[0146] In some examples, the peripheral area BB may be provided with a timing controller, a data driving circuit, and a gate driving circuit. The gate driving circuit may be provided on opposite sides of the display area AA, respectively, and the timing controller and the data driving circuit may be provided on one side of the display area AA. However, this embodiment is not limited to this.

[0147] In some examples, the data driving circuit can provide a data signal to the sub-pixel through a data line. The gate driving circuit can provide a scan signal to the sub-pixel through a scan line, and provide a reset signal to the sub-pixel through a reset signal line, and provide a light-emitting control signal to the sub-pixel through a light-emitting control line. The timing controller can provide a driving signal to the data driving circuit and the gate driving circuit. Among them, the actions of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide the data driving circuit with grayscale data specifying the grayscale that should be displayed in the sub-pixel. The data driving circuit can provide a data signal of a potential corresponding to the grayscale data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuit via the data line.

[0148] Fig.16 FIG. 1 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. Fig.16As shown, the pixel circuit of this exemplary embodiment includes: a data writing subcircuit, a driving subcircuit, a storage subcircuit, a level holding subcircuit, a light emitting control subcircuit, a first initialization subcircuit and a second initialization subcircuit. The data writing subcircuit is connected to the data line DATA, the first scan line GT1 and the second node N2, and is configured to write the signal of the data line DATA to the storage subcircuit under the control of the first scan line GT1. The driving subcircuit is connected to the third power line VDD, the first node N1 and the third node N3, and is configured to output a driving current to the light emitting control subcircuit through the third node N3 under the control of the first node N1. The storage subcircuit is connected to the first node N1 and the second node N2. The level holding subcircuit is connected to the third power line VDD and the second node N2, and is configured to maintain the potential of the second node N2. The compensation subcircuit is connected to the second scan line GT2, the first node N1 and the third node N3, and is configured to compensate the threshold voltage of the driving subcircuit under the control of the second scan line GT2. The first initialization subcircuit is connected to the first reset signal line RST1, the initial voltage line INT and the first node N1, and is configured to initialize the first node N1 under the control of the first reset signal line RST1. The second initialization subcircuit is connected to the second reset signal line RST2, the reference voltage line REF and the second node N2, and is configured to initialize the second node N2 under the control of the second reset signal line RST2. The light emitting control subcircuit is connected to the light emitting control line EM, the third node N3 and the first electrode of the light emitting element, and is configured to drive the light emitting element to emit light according to the driving current under the control of the light emitting control line EM. The second electrode of the light emitting element is connected to the fourth power line VSS.

[0149] In some examples, the light emitting element may be an organic light emitting diode (OLED), the first electrode may be an anode, and the second electrode may be a cathode. However, this embodiment is not limited to this.

[0150] In some examples, the data writing subcircuit writes the signal of the data line DATA into the storage subcircuit for a shorter writing time than the compensation subcircuit compensates the threshold voltage of the driving subcircuit. This exemplary embodiment controls the data voltage writing time and the threshold voltage compensation time separately, and can reduce the data voltage writing time while ensuring the threshold voltage compensation time, thereby improving the refresh rate to support the application in high-resolution products, and can increase the threshold voltage compensation time so that the threshold compensation time is sufficient to reduce the display defect.

[0151] Fig.17 FIG. 2 is another schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. Fig.17As shown, the pixel circuit of this exemplary embodiment includes: a driving subcircuit, a light emitting control subcircuit, a data writing subcircuit, a storage subcircuit, a level holding subcircuit, a compensation subcircuit, a first initialization subcircuit, a second initialization subcircuit, and a third initialization subcircuit. The data writing subcircuit is connected to the data line DATA, the first scan line GT1, and the second node N2, and is configured to write the signal of the data line DATA to the storage subcircuit under the control of the first scan line GT1. The driving subcircuit is connected to the third power line VDD, the first node N1, and the third node N3, and is configured to output a driving current to the light emitting control subcircuit through the third node N3 under the control of the first node N1. The storage subcircuit is connected to the first node N1 and the second node N2. The level holding subcircuit is connected to the third power line VDD and the second node N2, and is configured to maintain the potential of the second node N2. The compensation subcircuit is connected to the second scan line GT2, the first node N1, and the third node N3, and is configured to compensate for the threshold voltage of the driving subcircuit under the control of the second scan line GT2. The first initialization subcircuit is connected to the first reset signal line RST1, the initial voltage line INT and the first node N1, and is configured to initialize the first node N1 under the control of the first reset signal line RST1. The second initialization subcircuit is connected to the second reset signal line RST2, the reference voltage line REF and the second node N2, and is configured to initialize the second node N2 under the control of the second reset signal line RST2. The light emitting control subcircuit is connected to the light emitting control line EM, the third node N3 and the first electrode of the light emitting element, and is configured to drive the light emitting element to emit light according to the driving current under the control of the light emitting control line EM. The second electrode of the light emitting element is connected to the fourth power line VSS. The third initialization subcircuit is connected to the first electrode of the light emitting element, the initial voltage line INT and the third reset signal line RST3, and is configured to initialize the light emitting element under the control of the third reset signal line RST3. The third reset signal line RST3(n) connected to the pixel circuit of the nth row of sub-pixels is configured to be connected to the second reset signal line RST2(n+1) driving the pixel circuit of the n+1th row of sub-pixels. However, this embodiment is not limited to this. In some examples, the third initialization subcircuit can be connected to the first electrode of the light-emitting element, the initial voltage line, and the second reset signal line, and configured to initialize the light-emitting element under the control of the second reset signal line.

[0152] Fig.18 FIG. 1 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Fig.18As shown, the pixel circuit of this exemplary embodiment includes: a driving subcircuit, a light emitting control subcircuit, a data writing subcircuit, a storage subcircuit, a level holding subcircuit, a compensation subcircuit, a first initialization subcircuit, a second initialization subcircuit and a third initialization subcircuit. The data writing subcircuit includes: a data writing transistor M4; the control electrode of the data writing transistor M4 is connected to the first scanning line GT1, the first electrode of the data writing transistor M4 is connected to the data line DATA, and the second electrode of the data writing transistor M4 is connected to the second node N2. The driving subcircuit includes: a driving transistor M3; the control electrode of the driving transistor M3 is connected to the first node N1, the first electrode of the driving transistor M3 is connected to the third power supply terminal VDD, and the second electrode of the driving transistor M3 is connected to the third node N3. The storage subcircuit includes: a storage capacitor Cst; the first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the second node N2. The level holding subcircuit includes: a voltage stabilizing capacitor Crt; the first electrode of the voltage stabilizing capacitor Crt is connected to the third power supply terminal VDD, and the second electrode of the voltage stabilizing capacitor Crt is connected to the second node N2. The compensation subcircuit includes: a compensation transistor M2; the control electrode of the compensation transistor M2 is connected to the second scan line GT2, the first electrode of the compensation transistor M2 is connected to the first node N1, and the second electrode of the compensation transistor M2 is connected to the third node N3. The light-emitting control subcircuit includes: a light-emitting control transistor M6; the control electrode of the light-emitting control transistor M6 is connected to the light-emitting control line EM, the first electrode of the light-emitting control transistor M6 is connected to the third node N3, and the second electrode of the light-emitting control transistor M6 is connected to the first electrode of the light-emitting element EL. The second electrode of the light-emitting element EL is connected to the fourth power line VSS. The first initialization subcircuit includes: a first initialization transistor M1; the control electrode of the first initialization transistor M1 is connected to the first reset signal line RST1, the first electrode of the first initialization transistor M1 is connected to the initial voltage line INT, and the second electrode of the first initialization transistor M1 is connected to the first node N1. The second initialization subcircuit includes: a second initialization transistor M5; the control electrode of the second initialization transistor M5 is connected to the second reset signal line RST2, the first electrode of the second initialization transistor M5 is connected to the reference voltage line REF, and the second electrode of the second initialization transistor M5 is connected to the second node N2. The third initialization subcircuit includes: a third initialization transistor M7; a control electrode of the third initialization transistor M7 is connected to a third reset signal line, a first electrode of the third initialization transistor M7 is connected to an initial voltage line INT, and a second electrode of the third initialization transistor M7 is connected to a first electrode of the light emitting element EL. The third reset signal line connected to the pixel circuit of the nth row of sub-pixels is configured to be connected to the second reset signal line RST2(n+1) of the pixel circuit driving the n+1th row of sub-pixels.

[0153] In some exemplary embodiments, the compensation transistor M2 and the first initialization transistor M1 of the pixel circuit are first semiconductor type transistors, and the driving transistor M3, the data writing transistor M4, the light emission control transistor M6, the second initialization transistor M5, and the third initialization transistor M7 are second semiconductor type transistors; the doping types of the first semiconductor type and the second semiconductor type are opposite. In some examples, the compensation transistor M2 and the first initialization transistor M1 of the pixel circuit are N-type thin film transistors, for example, oxide thin film transistors, such as IGZO thin film transistors; the driving transistor M3, the data writing transistor M4, the light emission control transistor M6, the second initialization transistor M5, and the third initialization transistor M7 of the pixel circuit are P-type thin film transistors, such as low-temperature polysilicon thin film transistors. However, this embodiment is not limited to this.

[0154] In the following, the compensation transistor M2 and the first initialization transistor M1 of the pixel circuit are N-type thin film transistors, and the other transistors are P-type thin film transistors. Fig.18 The working process of the pixel circuit shown is exemplarily described. Fig.19 for Fig.18 The working timing diagram of the pixel circuit is shown in FIG. Fig.18 As shown, the pixel circuit of this exemplary embodiment includes 7 transistor units (M1 to M7), 2 capacitor units (i.e., storage capacitor Cst to voltage-stabilizing capacitor Crt), 9 input terminals (i.e., data line DATA, first scan line GT1, second scan line GT2, light emitting control line EM, first reset signal line RST1, second reset signal line RST2, second reset signal line RST2(n+1), reference voltage line REF, initial voltage line INT), and 2 power supply terminals (i.e., third power supply line VDD and fourth power supply line VSS). Among them, the third power supply line VDD continuously provides a high-level signal, and the fourth power supply line VSS continuously provides a low-level signal.

[0155] In this exemplary embodiment, Fig.18 and Fig.19 As shown, the working process of the pixel circuit includes the following stages.

[0156] In the first stage S1, i.e., the reset stage, the first reset signal line RST1 provides a high level signal, the first initialization transistor M1 is turned on, and the voltage V N1 The initial voltage line INT provides an initial voltage Vint. The second reset signal line RST2 provides a low level signal, the second initialization transistor M5 is turned on, and the voltage V N2The reference voltage line REF provides the reference voltage Vref, the storage capacitor Cst is reset, and the original data voltage in the storage capacitor Cst is cleared. The first scan line GT1 provides a high-level signal, and the data writing transistor M4 is turned off; the second scan line GT2 provides a low-level signal, and the compensation transistor M2 is turned off; the light-emitting control line EM provides a high-level signal, and the light-emitting control transistor M6 is turned off. The control electrode voltage of the driving transistor M3 (i.e., the voltage V N1 ) is the initial voltage Vint provided by the initial voltage line INT, and the voltage V N2 The second reset signal line RST2(n+1) provides a high level signal, and the third initialization transistor M7 is turned off.

[0157] In the second stage S2, i.e., the compensation stage, the first reset signal line RST1 provides a low level signal, and the first initialization transistor M1 is turned off. The second reset signal line RST2 provides a low level signal, and the second initialization transistor M5 is turned on. The voltage V N2 The reference voltage Vref is still the same. The first scan line GT1 provides a high-level signal, and the data writing transistor M4 is turned off. The second scan line GT2 provides a high-level signal, and the compensation transistor M2 is turned on. The light-emitting control line EM provides a high-level signal, and the light-emitting control transistor M6 is turned off. The second reset signal line RST2 (n+1) provides an interval low-level signal, and the third initialization transistor M7 is turned on, and the initial voltage Vint provided by the initial voltage line INT is provided to the first electrode of the light-emitting element EL, and the first electrode of the light-emitting element EL is initialized.

[0158] At the beginning of the second phase S2, the voltage V provided by the third power line VDD VDD The difference between the voltage at the first node N1 and the threshold voltage Vth of the driving transistor M3 is greater than that of the first node N1. At this time, the driving transistor M3 is turned on, and the voltage of the third power line VDD flows into the first node N1 through the driving transistor M3 and the compensation transistor M2. Since the conduction time of the compensation transistor M2 is relatively long, the threshold voltage of the driving transistor M3 can be fully compensated. N1 Increase to V VDD +Vth, the driving transistor M3 is turned off, and the voltage V N1 V VDD +Vth, the voltage V of the second node N2 N2 is the reference voltage Vref, the voltage difference between the first node N1 and the second node N2 is V VDD +Vth-Vref.

[0159] In the third stage S3, i.e., the writing stage, the first reset signal line RST1 provides a low-level signal, and the first initialization transistor M1 is turned off; the second reset signal line RST2 provides a high-level signal, and the second initialization transistor M5 is turned off. The second scan line GT2 provides a high-level signal, and the compensation transistor M2 is turned off. The light-emitting control line EM provides a high-level signal, and the light-emitting control transistor M6 is turned off. The first scan line GT1 provides a low-level signal, the data writing transistor M4 is turned on, and the signal provided by the data line DATA is written to the second node N2, i.e., the voltage V of the second node N2. N2 The first capacitor C1 will produce a bootstrap effect to maintain the voltage difference between the two ends unchanged, and the voltage of the first node N1 will eventually become V due to the capacitor bootstrap effect. VDD +Vth+Vdata-Vref, so as to maintain the voltage difference between the first node N1 and the second node N2 at V VDD +Vth-Vref.

[0160] In the fourth stage S4, i.e., the light-emitting stage, the first reset signal line RST1 provides a low-level signal, and the first initialization transistor M1 is turned off. The second reset signal line RST2 provides a high-level signal, and the second initialization transistor M5 is turned off. The first scan line GT1 provides a high-level signal, and the data write transistor M4 is turned off. The second scan line GT2 provides a low-level signal, and the compensation transistor M2 is turned off. The second reset signal line RST2(n+1) provides a high-level signal, and the third initialization transistor M7 is turned off. The light-emitting control line EM provides a low-level signal, and the light-emitting control transistor M6 is turned on. The voltage difference between the third power line VDD and the first node N1 is Vth+Vdata-Vref, which is greater than the threshold voltage Vth of the driving transistor M3. At this time, the driving transistor M3 is turned on, and the light-emitting element EL emits light under the drive of the driving transistor M3. The light-emitting current of the light-emitting element EL is:

[0161] I=1 / 2uC ox W / L(Vgs-Vth) 2 =1 / 2uC ox W / L(V N1 -V VDD -V th ) 2

[0162] =1 / 2uC ox W / L(V VDD +Vth+Vdata-Vref-V VDD -V th ) 2

[0163] =1 / 2uC ox W / L(Vdata-Vref)2

[0164] Where, u is the channel mobility of the driving transistor, C ox is the channel capacitance per unit area of ​​the driving transistor, W and L are the channel width and channel length of the driving transistor respectively, and Vgs is the gate-source voltage of the driving transistor (ie, the difference between the gate voltage and the source voltage of the driving transistor).

[0165] It can be seen that the light-emitting current I is related to the power supply voltage V VDD It has nothing to do with the threshold voltage Vth, but only depends on the data voltage Vdata provided by the data line DATA and the reference voltage Vref provided by the reference voltage line REF, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, thereby ensuring uniform display brightness of the display substrate and improving the display effect.

[0166] In this example, the voltage V of the first node N1 at the above different stages is N1 and the voltage V of the second node N2 N2 As shown in Table 1.

[0167] Table 1

[0168] Phase 1 S1 Phase 2 S2 Stage 3 S3 Stage 4 <![CDATA[V N1 ]]> Vint <![CDATA[V VDD +Vth]]> <![CDATA[V VDD +Vth+Vdata-Vref]]> <![CDATA[V VDD +Vth+Vdata-Vref]]> <![CDATA[V N2 ]]> Vref Vref Vdata Vdata

[0169] In this exemplary embodiment, the effective level signal provided by the first scan line controls the writing duration of the data voltage provided by the data line (i.e., the conduction duration of the data writing transistor), and the pulse width is relatively narrow; the effective level signal provided by the second scan line controls the compensation duration of the threshold voltage (i.e., the conduction duration of the compensation transistor), and the pulse width is relatively wide. That is, the data voltage writing duration is less than the threshold voltage compensation duration, so that when the threshold voltage compensation duration is met, the data voltage writing duration can be reduced and the refresh rate can be improved. Moreover, the effective level signal provided by the third reset signal line controls the initialization duration of the light-emitting element, which is greater than the sum of the data voltage writing duration and the threshold voltage compensation duration, and the initialization duration is increased, which can increase the life of the light-emitting element, thereby increasing the life of the display substrate.

[0170] Fig. 20 The diagram is a top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure. Fig.21 for Fig. 20 Schematic diagram of the cross section along the QQ direction. Fig. 20 and Fig.21As shown, the display area of ​​the display substrate of the exemplary embodiment includes: a base substrate 30, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer and a third conductive layer sequentially arranged on the base substrate 30. Among them, the first insulating layer 31 is arranged between the base substrate 30 and the first semiconductor layer. The second insulating layer 32 is arranged between the first conductive layer and the first semiconductor layer. The third insulating layer 33 is arranged between the first conductive layer and the second semiconductor layer. The fourth insulating layer 34 is arranged between the second semiconductor layer and the second conductive layer. The fifth insulating layer 35 is arranged between the second conductive layer and the third conductive layer. In some examples, a flat layer, an anode layer, an organic insulating layer, a cathode layer and an encapsulation layer are arranged on the side of the fifth insulating layer 35 away from the base substrate 30. However, this embodiment is not limited to this.

[0171] In this exemplary embodiment, Fig. 20 The third initialization transistor M7 shown in FIG. 1 is included in the pixel circuit of the sub-pixels in the n-1th row, and the remaining transistors (ie, M1 to M6) are included in the pixel circuit of the sub-pixels in the nth row. Fig. 20 The third initialization transistor M7 is connected to the first electrode of the light emitting element of the sub-pixel in the n-1th row, and the light emitting control transistor M6 is connected to the first electrode of the light emitting element of the sub-pixel in the nth row.

[0172] Fig. 22 FIG. 1 is a top view of a sub-pixel after forming the first semiconductor layer according to at least one embodiment of the present disclosure. Figure 20 to Figure 22 As shown, the first semiconductor layer of the display area of ​​the exemplary embodiment at least includes: an active layer 540 of the data writing transistor M4, an active layer 530 of the driving transistor M3, an active layer 550 of the second initialization transistor M5, an active layer 570 of the third initialization transistor M7, and an active layer 560 of the light emission control transistor M6. The active layer 530 of the driving transistor M3 and the active layer 560 of the light emission control transistor M6 are an integrated structure.

[0173] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. In some examples, the active layer may include a channel region, a first doped region, and a second doped region. The channel region may not be doped with impurities and have semiconductor properties. The first doped region and the second doped region may be on both sides of the channel region and are doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor.

[0174] In some exemplary embodiments, Fig. 22As shown, the active layer 540 of the data writing transistor M4 includes a channel region 540a, and a first doping region 540b and a second doping region 540c located at both ends of the channel region 540a. The active layer 530 of the driving transistor M3 includes a channel region 530a, and a first doping region 530b and a second doping region 530c located at both ends of the channel region 530a. The active layer 550 of the second initialization transistor M5 includes a channel region 550a, and a first doping region 550b and a second doping region 550c located at both ends of the channel region 550a. The active layer 570 of the third initialization transistor M7 includes a channel region 570a, and a first doping region 570b and a second doping region 570c located at both ends of the channel region 570a. The active layer 560 of the light emission control transistor M6 includes a channel region 560a, and a first doping region 560b and a second doping region 560c located at both ends of the channel region 560a. The second doping region 530 c of the active layer 530 of the driving transistor M3 is connected to the second doping region 560 b of the active layer 560 of the light emission control transistor M6 .

[0175] In some exemplary embodiments, the first doping region or the second doping region of the active layer may be interpreted as a source electrode or a drain electrode of a transistor. For example, the source electrode of the driving transistor M3 may correspond to the periphery of the channel region 530a of the active layer 530 and the first doping region 530b doped with impurities; the drain electrode of the driving transistor M3 may correspond to the periphery of the channel region 530a of the active layer 530 and the second doping region 530c doped with impurities. In addition, a portion of the active layer between transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0176] Fig.23 FIG. 1 is a top view of a sub-pixel after forming a first conductive layer according to at least one embodiment of the present disclosure. Figure 20 to Figure 23 As shown, the first conductive layer of the display area of ​​the exemplary embodiment at least includes: a control electrode 541 of the data writing transistor M4, a control electrode 561 of the light emission control transistor M6, a control electrode 551 of the second initialization transistor M5, a control electrode 571 of the third initialization transistor M7, a control electrode 531 of the driving transistor M3, a first scan line GT1, a second reset signal line RST2, a light emission control line EM, a first electrode 581 of the storage capacitor Cst, and a first electrode 591 of the voltage stabilization capacitor Crt. The first scan line GT1 provides a first scan signal, the second reset signal line RST2 provides a second reset signal, and the light emission control line EM provides a light emission control signal.

[0177] In some exemplary embodiments, the control electrode 531 of the driving transistor M3 is an integral structure with the first electrode 581 of the storage capacitor Cst. The light emission control line EM is an integral structure with the control electrode 561 of the light emission control transistor M6. The control electrode 551 of the second initialization transistor M5 is an integral structure with the second reset signal line RST2, and the control electrode 571 of the third initialization transistor M7 of the pixel circuit of the n-1th row of sub-pixels is an integral structure with the second reset signal line RST2 connected to the pixel circuit of the nth row of sub-pixels.

[0178] Fig.24 FIG. 1 is a top view of a sub-pixel forming a second semiconductor layer according to at least one embodiment of the present disclosure. Figure 20 to Figure 24 As shown, the second semiconductor layer of the display area of ​​the exemplary embodiment includes at least: an active layer 520 of the compensation transistor M2 and an active layer 510 of the first initialization transistor M1. The active layer 520 of the compensation transistor M2 and the active layer 510 of the first initialization transistor M1 are an integrated structure. In the exemplary embodiment, the material of the second semiconductor layer may include a metal oxide, such as IGZO.

[0179] Fig.25 FIG. 1 is a top view of a sub-pixel after forming a second conductive layer according to at least one embodiment of the present disclosure. Figure 20 to Figure 25 As shown, the second conductive layer of the display area of ​​the exemplary embodiment at least includes: a control electrode 521 of the compensation transistor M2, a control electrode 511 of the first initialization transistor M1, a first reset signal line RST1, a second scan line GT2, a reference voltage line REF, a second electrode 582 of the storage capacitor Cst, and a second electrode 592 of the voltage stabilizing capacitor Crt. The first reset signal line RST1 provides a first reset signal, the second scan line GT2 provides a second scan signal, and the reference voltage line REF provides a reference voltage.

[0180] In some exemplary embodiments, the first reset signal line RST1 and the control electrode 511 of the first initialization transistor M1 are an integral structure. The second scan line GT2 and the control electrode 521 of the compensation transistor M2 are an integral structure. The second electrode 582 of the storage capacitor Cst and the second electrode 592 of the voltage stabilization capacitor Crt are an integral structure. The second electrode 582 of the storage capacitor Cst has a hollow area H. The orthographic projection of the hollow area H on the base substrate is located within the orthographic projection of the first electrode 581 of the storage capacitor Cst on the base substrate.

[0181] Fig.26 FIG. 1 is a top view of a sub-pixel after forming a fifth insulating layer according to at least one embodiment of the present disclosure. Figure 20 to Figure 26As shown, a plurality of vias are formed on the fifth insulating layer of the display area of ​​the exemplary embodiment. The plurality of vias include at least: first vias K19 to K26, second vias D19 to D22, third vias V6 to V8, and fourth vias F13 to F15. The fifth insulating layer 35, the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32 in the first via are etched away to expose the surface of the first semiconductor layer. The fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the second via are etched away to expose the surface of the first conductive layer. The fifth insulating layer 35 and the fourth insulating layer 34 in the third via are etched away to expose the surface of the second semiconductor layer. The fifth insulating layer 35 in the fourth via is etched away to expose the surface of the second conductive layer.

[0182] Fig. 27 FIG. 1 is a top view of a sub-pixel after forming a third conductive layer according to at least one embodiment of the present disclosure. Figures 20 to 27 As shown, the third conductive layer of the display area of ​​the exemplary embodiment at least includes: a third power line VDD, a data line DATA, an initial voltage line INT, a second electrode 533 of the driving transistor M3, a first electrode 522 and a second electrode 523 of the compensation transistor M2, a first electrode 512 of the first initialization transistor M1, a first electrode 552 and a second electrode 553 of the second initialization transistor M5, a second electrode 543 of the data writing transistor M4, and a scanning line connection electrode 600. The data line DATA provides a data signal, and the initial voltage line INT provides an initial voltage. Among them, the first electrode 522 of the compensation transistor M2 and the second electrode 533 of the driving transistor M3 are an integrated structure.

[0183] In some exemplary embodiments, the third power line VDD, the data line DATA, and the initial voltage line INT extend along the second direction Y. The first electrode 512 of the first initialization transistor M1 is connected to the first doping region 510b of the active layer 510 of the first initialization transistor M1 through the third via hole V8, and is connected to the first doping region 570b of the active layer 570 of the third initialization transistor M7 through the first via hole K26. The initial voltage line INT is connected to the first doping region 570b of the active layer 570 of the third initialization transistor M7 through the first via hole K25. The first electrode 512 of the first initialization transistor M1 is connected to the initial voltage line INT through the first doping region 570b of the active layer 570 of the third initialization transistor M7. The first electrode 522 of the compensation transistor M2 is connected to the first doping region 520b of the active layer 520 of the compensation transistor M2 through the third via hole V6. The second electrode 523 of the compensation transistor M2 is connected to the second doping region 520c of the active layer 520 of the compensation transistor M2 through the third via hole V7, and is connected to the first electrode 581 of the storage capacitor Cst through the second via hole D19. The second electrode 533 of the driving transistor M3 is connected to the second doping region 530c of the active layer 530 of the driving transistor M3 through the first via hole K20. The third power line VDD is connected to the first doping region 530b of the active layer 530 of the driving transistor M3 through the first via hole K19, and the third power line VDD is also connected to the first electrode 591 of the voltage stabilizing capacitor Crt through the second via hole D20. The first electrode 552 of the second initialization transistor M5 is connected to the first doping region 550b of the active layer 550 of the second initialization transistor M5 through the first via hole K23, and is connected to the reference voltage line REF through the fourth via hole F15. The second electrode 553 of the second initialization transistor M5 is connected to the second doping region 550c of the active layer 550 of the second initialization transistor M5 through the first via K24, and is connected to the second electrode 582 of the storage capacitor Cst through the fourth via F14. The second electrode 543 of the data write transistor M4 is connected to the second doping region 540c of the active layer 540 of the data write transistor M4 through the first via K21, and is connected to the second electrode 592 of the voltage stabilizing capacitor Crt through the fourth via F13. The data line DATA is connected to the first doping region 540b of the active layer 540 of the data write transistor M4 through the first via K22. The scan line connection electrode 600 is connected to the first scan line GT1 through the second via D21, and is connected to the control electrode 541 of the data write transistor M4 through the second via D22. In some examples, the second doping region 560c of the active layer 560 of the light emitting control transistor M6 can be connected to the first electrode of the light emitting element of the sub-pixel of this row. The second doping region 570 c of the active layer 570 of the third initialization transistor M7 may be connected to the first electrode of the light emitting element of the sub-pixel in the previous row.

[0184] In the pixel circuit provided by this exemplary embodiment, the compensation transistor M2 and the first initialization transistor M1 use IGZO thin film transistors with extremely small leakage current, so that the storage capacitor has a longer voltage holding time when driven at a low frequency. Data voltage writing and threshold voltage compensation are controlled by the first scan line and the second scan line respectively, and the data voltage writing time is short and the threshold voltage compensation time is long, which can meet the requirements of fast data writing and sufficient threshold voltage compensation when driven at a high frequency.

[0185] Fig.28 Another top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure. Fig.29 for Fig.28 Schematic diagram of the cross section along the HH direction. Fig.28 and Fig.29 As shown, the display area of ​​the display substrate of this exemplary embodiment includes: a base substrate 30, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on the base substrate 30. Among them, the first insulating layer 31 is arranged between the base substrate 30 and the first semiconductor layer. The second insulating layer 32 is arranged between the first semiconductor layer and the first conductive layer. The third insulating layer 33 is arranged between the first conductive layer and the second semiconductor layer. The fourth insulating layer 34 is arranged between the second semiconductor layer and the second conductive layer. The fifth insulating layer 35 is arranged between the second conductive layer and the third conductive layer. The sixth insulating layer 36 and the seventh insulating layer 37 are sequentially arranged between the third conductive layer and the fourth conductive layer.

[0186] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0187] In some exemplary embodiments, the first insulating layer 31 to the sixth insulating layer 36 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer 31 and the third insulating layer 33 are referred to as buffer layers, and the first insulating layer 31 is configured to improve the water and oxygen resistance of the substrate; the second insulating layer 32 and the fourth insulating layer 34 are referred to as gate insulation (GI) layers, the fifth insulating layer 35 is referred to as an interlayer insulation (ILD) layer, and the sixth insulating layer 36 is referred to as a passivation layer. The seventh insulating layer 37 may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The seventh insulating layer 37 is referred to as a first flat layer. In some examples, the side of the fourth conductive layer away from the substrate 30 is sequentially provided with a second flat layer, an anode layer, an organic insulating layer, a cathode layer and an encapsulation layer. However, this embodiment is not limited to this.

[0188] In this exemplary embodiment, Fig.28 The third initialization transistor M7 shown in FIG. 1 is included in the pixel circuit of the sub-pixels in the n-1th row, and the remaining transistors (ie, M1 to M6) are included in the pixel circuit of the sub-pixels in the nth row. Fig.28 The third initialization transistor M7 is connected to the first electrode of the light emitting element of the sub-pixel in the n-1th row, and the light emitting control transistor M6 is connected to the first electrode of the light emitting element of the sub-pixel in the nth row.

[0189] The top view of the first semiconductor layer in the display area of ​​this exemplary embodiment can be referred to as Fig. 22 As shown, the top view of the first conductive layer can refer to Fig.23 As shown, the top view of the second semiconductor layer can refer to Fig.24 As shown, the top view of the second conductive layer can refer to Fig.25 As shown, I will not repeat it here.

[0190] Fig.30 FIG. 1 is a top view of a sub-pixel after forming a fifth insulating layer according to at least one embodiment of the present disclosure. Figures 28 to 30 as well as Figure 22 to Figure 25As shown, a plurality of vias are formed on the fifth insulating layer of the display area of ​​the present exemplary embodiment. The plurality of vias include at least: first vias K19 to K28, second vias D19 to D22, third vias V6 to V8, and fourth vias F13 to F15. The fifth insulating layer 35, the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32 in the first via are etched away to expose the surface of the first semiconductor layer. The fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the second via are etched away to expose the surface of the first conductive layer. The fifth insulating layer 35 and the fourth insulating layer 34 in the third via are etched away to expose the surface of the second semiconductor layer. The fifth insulating layer 35 in the fourth via is etched away to expose the surface of the second conductive layer.

[0191] Fig.31 FIG. 1 is a top view of a sub-pixel after forming a third conductive layer according to at least one embodiment of the present disclosure. Figure 28 to Figure 31 as well as Figure 22 to Figure 25 As shown, the third conductive layer of the display area of ​​the exemplary embodiment at least includes: a data line DATA, an initial voltage line INT, a second electrode 533 of the driving transistor M3, a first electrode 522 and a second electrode 523 of the compensation transistor M2, a first electrode 512 of the first initialization transistor M1, a first electrode 552 and a second electrode 553 of the second initialization transistor M5, a second electrode 543 of the data writing transistor M4, a second electrode 562 of the light emitting control transistor M6, a second electrode 573 of the third initialization transistor M7, a scanning line connection electrode 600, and a power connection line 601. The data line DATA provides a data signal, and the initial voltage line INT provides an initial voltage. Among them, the first electrode 522 of the compensation transistor M2 and the second electrode 533 of the driving transistor M3 are an integrated structure.

[0192] In some exemplary embodiments, the power connection line 601, the data line DATA, and the initial voltage line INT extend along the second direction Y. The first electrode 512 of the first initialization transistor M1 is connected to the first doping region 510b of the active layer 510 of the first initialization transistor M1 through the third via hole V8, and is connected to the first doping region 570b of the active layer 570 of the third initialization transistor M7 through the first via hole K26. The initial voltage line INT is connected to the first doping region 570b of the active layer 570 of the third initialization transistor M7 through the first via hole K25. The first electrode 512 of the first initialization transistor M1 is connected to the initial voltage line INT through the first doping region 570b of the active layer 570 of the third initialization transistor M7. The first electrode 522 of the compensation transistor M2 is connected to the first doping region 520b of the active layer 520 of the compensation transistor M2 through the third via hole V6. The second electrode 523 of the compensation transistor M2 is connected to the second doping region 520c of the active layer 520 of the compensation transistor M2 through the third via hole V7, and is connected to the first electrode 581 of the storage capacitor Cst through the second via hole D19. The second electrode 533 of the driving transistor M3 is connected to the second doping region 530c of the active layer 530 of the driving transistor M3 through the first via hole K20. The power connection line 601 is connected to the first doping region 530b of the active layer 530 of the driving transistor M3 through the first via hole K19, and the power connection line 601 is also connected to the first electrode 591 of the voltage stabilizing capacitor Crt through the second via hole D20. The first electrode 552 of the second initialization transistor M5 is connected to the first doping region 550b of the active layer 550 of the second initialization transistor M5 through the first via hole K23, and is connected to the reference voltage line REF through the fourth via hole F15. The second electrode 553 of the second initialization transistor M5 is connected to the second doping region 550c of the active layer 550 of the second initialization transistor M5 through the first via hole K24, and is connected to the second electrode 582 of the storage capacitor Cst through the fourth via hole F14. The second electrode 543 of the data write transistor M4 is connected to the second doping region 540c of the active layer 540 of the data write transistor M4 through the first via hole K21, and is connected to the second electrode 592 of the voltage stabilizing capacitor Crt through the fourth via hole F13. The data line DATA is connected to the first doping region 540b of the active layer 540 of the data write transistor M4 through the first via hole K22. The scan line connection electrode 600 is connected to the first scan line GT1 through the second via hole D21, and is connected to the control electrode 541 of the data write transistor M4 through the second via hole D22. The second electrode 563 of the light emission control transistor M6 is connected to the second doping region 560c of the active layer 560 of the light emission control transistor M6 through the first via hole K28. The second electrode 573 of the third initialization transistor M7 is connected to the second doping region 570 c of the active layer 570 of the third initialization transistor M7 through the first via hole K27 .

[0193] Fig.32 FIG. 1 is a top view of a sub-pixel after forming a seventh insulating layer according to at least one embodiment of the present disclosure. Figure 28 to Figure 32 as well as Figure 22 to Figure 25 As shown, a plurality of vias are formed on the seventh insulating layer of the display area of ​​the exemplary embodiment. The plurality of vias at least include: fifth vias J1 to J4. The seventh insulating layer 37 and the sixth insulating layer 36 in the fifth via are etched away to expose the surface of the third conductive layer. Among them, the fifth via J1 exposes the surface of the second pole 573 of the third initialization transistor M7. The fifth via J2 exposes the surface of the second pole 563 of the light emitting control transistor M6. The fifth vias J3 and J4 are arranged in sequence along the second direction Y, and expose the surface of the power connection line 601.

[0194] Fig.33 FIG. 1 is a top view of a sub-pixel after forming a fourth conductive layer according to at least one embodiment of the present disclosure. Figures 28 to 33 as well as Figure 22 to Figure 25 As shown, the fourth conductive layer of the display area of ​​the exemplary embodiment includes at least: a third power line VDD, a first anode connection electrode 701 and a second anode connection electrode 702. The third power line VDD extends in the first direction X and the second direction Y to form a mesh structure to reduce resistance. The third power line VDD is connected to the power connection line 601 through the fifth vias J3 and J4. The first anode connection electrode 701 is connected to the second pole 573 of the third initialization transistor M7 through the fifth via J1. The second anode connection electrode 702 is connected to the second pole 563 of the light emitting control transistor M6 through the fifth via J2. In some examples, the first anode connection electrode 701 can be connected to the first pole of the light emitting element of the previous row of sub-pixels, and the second anode connection electrode 702 can be connected to the first pole of the light emitting element of the sub-pixel of the current row.

[0195] In some exemplary embodiments, the gate driving circuit of the peripheral area can provide the pixel circuit of the display area with a first scan signal, a second scan signal, a first reset signal, a second reset signal, and a light emitting control signal. In some examples, the gate driving circuit may include: a plurality of cascaded first shift register units, a plurality of cascaded second shift register units, and a plurality of cascaded third shift register units. The first shift register unit can provide the second scan signal to the pixel circuit of the display area through the second scan line, and provide the second reset signal to the pixel circuit through the second reset signal line; the second shift register unit can provide the first scan signal to the pixel circuit of the display area through the first scan line, and provide the first reset signal to the pixel circuit through the first reset signal line; the third shift register unit can provide the light emitting control signal to the pixel circuit of the display area through the light emitting control line.

[0196] Fig.34FIG. 1 is a schematic diagram showing the connection between the gate driving circuit and the pixel circuit in at least one embodiment of the present disclosure. Fig.34 As shown, the nth-stage first shift register unit RST2_GOA(n) can provide the second reset signal RST2(n) and the second scan signal GT2(n) to the pixel circuit of the nth-row sub-pixel PL(n). The nth-stage second shift register unit RST1_GOA(n) can provide the first reset signal RST1(n) to the pixel circuit of the nth-row sub-pixel PL(n), and provide the first scan signal GT1(n-2) to the pixel circuit of the n-2th-row sub-pixel PL(n-2). The nth-stage third shift register unit EM_GOA(n) can provide the light emitting control signal EM(n) to the pixel circuit of the nth-row sub-pixel PL(n). Wherein, n is an integer greater than 0.

[0197] In some exemplary embodiments, the equivalent circuit diagram of the first shift register unit may be as follows: Figure 7 As shown, the equivalent circuit diagram of the second shift register unit can be as follows Fig.12 The connection relationship between the first shift register unit and the second shift register unit can be as follows: Fig.11 However, this embodiment is not limited to this.

[0198] In some exemplary embodiments, the third output terminal of the n-th stage first shift register unit is connected to the second reset signal line of the pixel circuit driving the n-th row of sub-pixels, and is connected to the third reset signal line driving the n-1-th row of sub-pixels. The second output terminal of the n-th stage first shift register unit is connected to the second scan line of the pixel circuit driving the n-th row of sub-pixels. The fifth output terminal of the n-th stage second shift register unit is connected to the first reset signal line of the pixel circuit driving the n-th row of sub-pixels, and the fourth output terminal of the n-th stage second shift register unit is connected to the first scan line of the pixel circuit driving the n-2-th row of sub-pixels.

[0199] The gate driving circuit provided in this exemplary embodiment has a simplified structure and can provide a variety of different gate driving signals to the pixel circuit through three shift register units, thereby improving the performance of the pixel circuit.

[0200] Fig.35 FIG. 4 is a top view of a first shift register unit according to at least one embodiment of the present disclosure. Fig.36 for Fig.35 The equivalent circuit diagram of the first shift register unit of this exemplary embodiment is as follows: Figure 7As shown. Among them, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 in the first shift register unit are N-type transistors and are IGZO thin film transistors, and the remaining transistors in the first shift register unit are P-type transistors and are low-temperature polycrystalline silicon thin film transistors.

[0201] In some exemplary embodiments, such as Fig.35 and Fig.36 As shown, in a plane perpendicular to the display substrate, the peripheral area of the display substrate may include: a substrate 30, a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate 30. Among them, a first insulating layer 31 is disposed between the substrate 30 and the first semiconductor layer. A second insulating layer 32 is disposed between the first conductive layer and the first semiconductor layer. A third insulating layer 33 is disposed between the first conductive layer and the second semiconductor layer. A fourth insulating layer 34 is disposed between the second semiconductor layer and the second conductive layer. A fifth insulating layer 35 is disposed between the second conductive layer and the third conductive layer.

[0202] Fig.37 This is a top view of the first shift register unit after forming the first semiconductor layer according to at least one embodiment of the present disclosure. As Figure 35 to Figure 37 shown, the first semiconductor layer in the peripheral area may have a curved or bent shape. The first semiconductor layer in the peripheral area at least includes: an active layer 110 of the first transistor T1, an active layer 120 of the second transistor T2, an active layer 150 of the fifth transistor T5, an active layer 170 of the seventh transistor T7, an active layer 180 of the eighth transistor T8, an active layer 190 of the ninth transistor T9, an active layer 200 of the tenth transistor T10, an active layer 210 of the eleventh transistor T11, an active layer 220 of the twelfth transistor T12, an active layer 230 of the thirteenth transistor T13, and an active layer 240 of the fourteenth transistor T14.

[0203] In some exemplary embodiments, the active layer 110 of the first transistor T1 and the active layer 120 of the second transistor T2 are an integral structure, for example, in a long strip shape. The active layer 180 of the eighth transistor T8 and the active layer 190 of the ninth transistor T9 are an integral structure, for example, in a "U" shape. The active layer 200 of the tenth transistor T10 and the active layer 220 of the twelfth transistor T12 are an integral structure, for example, in a "└" shape.

[0204] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include a channel region, a first doped region, and a second doped region. The channel region may not be doped with impurities and has semiconductor characteristics. The first doped region and the second doped region may be on both sides of the channel region and doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor. The first doped region or the second doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. For example, the source electrode of the first transistor T1 may correspond to the periphery of the channel region 110a of the active layer 110 and the first doped region 110b doped with impurities; the drain electrode of the first transistor T1 may correspond to the periphery of the channel region 110a of the active layer 110 and the second doped region 110c doped with impurities. In addition, the portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0205] Fig.38 FIG. 1 is a top view of a first shift register unit after forming a first conductive layer according to at least one embodiment of the present disclosure. Figures 35 to 38 As shown, the first conductive layer in the peripheral area at least includes: a control electrode 111 of the first transistor T1, a control electrode 121 of the second transistor T2, a control electrode 151 of the fifth transistor T5, a control electrode 171 of the seventh transistor T7, a control electrode 181 of the eighth transistor T8, a control electrode 191 of the ninth transistor T9, a control electrode 201 of the tenth transistor T10, a control electrode 211 of the eleventh transistor T11, a control electrode 221 of the twelfth transistor T12, a control electrode 231 of the thirteenth transistor T13, a control electrode 241 of the fourteenth transistor T14, a first electrode 251 of the first capacitor C1, a first electrode 261 of the second capacitor C2, a first electrode 271 of the third capacitor C3, a first connecting electrode 281, a first output terminal OUT1, a second output terminal OUT2 and a third output terminal OUT3.

[0206] In some exemplary embodiments, the control electrode 121 of the second transistor T2 and the second output terminal OUT2 may be an integral structure. The control electrode 111 of the first transistor T1 is located between the control electrode 121 of the second transistor T2 and the second output terminal OUT2. The extension directions of the control electrode 111 of the first transistor T1, the control electrode 121 of the second transistor T2, and the second output terminal OUT2 are parallel to each other. The third output terminal OUT3 is located on the side of the control electrode 121 of the second transistor T2 away from the control electrode 111 of the first transistor T1. The extension direction of the third output terminal OUT3 is parallel to the extension direction of the control electrode 111 of the first transistor T1. The first output terminal OUT1 is located on the side of the control electrode 151 of the fifth transistor T5 away from the second output terminal OUT2. The first output terminal OUT1 is, for example, a "┐" type.

[0207] In some exemplary embodiments, the control electrode 171 of the seventh transistor T7 and the first electrode 251 of the first capacitor C1 may be an integral structure. The control electrode 231 of the thirteenth transistor T13 and the first electrode 261 of the second capacitor C2 may be an integral structure. The control electrode 241 of the fourteenth transistor T14 and the first electrode 271 of the third capacitor C3 may be an integral structure. The control electrode 221 of the twelfth transistor T12 and the first connection electrode 281 are an integral structure.

[0208] Fig.39 FIG. 1 is a top view of a first shift register unit after forming a second semiconductor layer according to at least one embodiment of the present disclosure. Figure 35 to Figure 39 As shown, the second semiconductor layer in the peripheral region may have a curved or bent shape. The second semiconductor layer in the peripheral region includes at least: an active layer 130 of the third transistor T3, an active layer 140 of the fourth transistor T4, and an active layer 160 of the sixth transistor T6. In some examples, the material of the second semiconductor layer includes IGZO.

[0209] In some exemplary embodiments, the active layer 130 of the third transistor T3 and the active layer 140 of the fourth transistor T4 are an integrated structure, for example, in a "ㄇ" shape. The active layer 130 of the third transistor T3 includes a channel region 130a, a first doping region 130b and a second doping region 130c located on both sides of the channel region 130a. The active layer 140 of the fourth transistor T4 includes a channel region 140a, a first doping region 140b and a second doping region 140c located on both sides of the channel region 140a. The second doping region 130c of the active layer 130 of the third transistor T3 is connected to the second doping region 140c of the active layer 140 of the fourth transistor T4. The active layer 130 of the third transistor T3 and the active layer 140 of the fourth transistor T4 are located on the side of the third output terminal OUT3 away from the second output terminal OUT2. The active layer 160 of the sixth transistor T6 is located on the side of the active layer 130 of the third transistor T3 close to the first electrode 261 of the second capacitor C2. The active layer 160 of the sixth transistor T6 includes a channel region 160 a , and a first doping region 160 b and a second doping region 160 c located at both sides of the channel region 160 a .

[0210] Fig.40 FIG. 1 is a top view of a first shift register unit after forming a second conductive layer according to at least one embodiment of the present disclosure. Figures 35 to 40 As shown, the second conductive layer in the peripheral area at least includes: a control electrode 131 of the third transistor T3, a control electrode 141 of the fourth transistor T4, a control electrode 161 of the sixth transistor T6, a second electrode 252 of the first capacitor C1, a second electrode 262 of the second capacitor C2, a second electrode 272 of the third capacitor C3, a second connecting electrode 282, a third connecting electrode 283, and a control signal line CSL.

[0211] In some exemplary embodiments, the projection of the second electrode 262 of the second capacitor C2 on the substrate covers the projection of the first electrode 261 of the second capacitor C2 on the substrate. The projection of the second electrode 272 of the third capacitor C3 on the substrate covers the projection of the first electrode 271 of the third capacitor C3 on the substrate. The projection of the control signal line CSL on the substrate is located on the side of the projection of the first connection electrode 281 on the substrate away from the second capacitor C2 and the third capacitor C3. The extension directions of the second connection electrode 282 and the third connection electrode 283 are parallel to each other.

[0212] Fig.41 FIG. 1 is a top view of the first shift register unit after the fifth insulating layer is formed according to at least one embodiment of the present disclosure. Figures 35 to 41 As shown, a plurality of vias are formed on the fifth insulating layer 35 in the peripheral area. The plurality of vias include at least: first vias K11 to K18, second vias D1 to D18, third vias V1 to V5, and fourth vias F1 to F12. The fifth insulating layer 35, the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32 in the first vias K11 to K18 are etched away to expose the surface of the first semiconductor layer. The fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the second vias D1 to D18 are etched away to expose the surface of the first conductive layer. The fifth insulating layer 35 and the fourth insulating layer 34 in the third vias V1 to V5 are etched away to expose the surface of the second semiconductor layer. The fifth insulating layer 35 in the fourth vias F1 to F12 is etched away to expose the surface of the second conductive layer.

[0213] Fig.42 FIG. 1 is a top view of a first shift register unit after forming a third conductive layer according to at least one embodiment of the present disclosure. Figures 35 to 42As shown, the third conductive layer in the peripheral area at least includes: a first electrode 112 of the first transistor T1, a second electrode 123 of the second transistor T2, a first electrode 132 and a second electrode 133 of the third transistor T3, a first electrode 142 and a second electrode 143 of the fourth transistor T4, a first electrode 152 and a second electrode 153 of the fifth transistor T5, a first electrode 162 and a second electrode 163 of the sixth transistor T6, a first electrode 172 and a second electrode 173 of the seventh transistor T7, a first electrode 182 of the eighth transistor T8, a first electrode 192 and a second electrode 193 of the ninth transistor T9, The first electrode 202 of the tenth transistor T10, the first electrode 212 and the second electrode 213 of the eleventh transistor T11, the first electrode 222 and the second electrode 223 of the twelfth transistor T12, the first electrode 232 and the second electrode 233 of the thirteenth transistor T13, the first electrode 242 and the second electrode 243 of the fourteenth transistor T14, the fourth connecting electrode 284, the fifth connecting electrode 285, the sixth connecting electrode 286, the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the first power line VGH and the second power line VGL.

[0214] In some exemplary embodiments, the first electrode 112 of the first transistor T1 is connected to the first doping region 110b of the active layer 110 of the first transistor T1 through the first via K1. The second electrode 123 of the second transistor T2 is connected to the second doping region 120c of the active layer 120 of the second transistor T2 through the first via K2, and is connected to the third output terminal OUT3 through the second via D3. The fourth connection electrode 284 is connected to the control electrode 141 of the first transistor T1 through the second via D1, is connected to the control electrode 141 of the fourth transistor T4 through the fourth via F1, and is connected to the control signal line CSL through the fourth via F4. The first electrode 142 of the fourth transistor T4 is connected to the first doping region 140b of the active layer 140 of the fourth transistor T4 through the third via V2, and is connected to the first connection electrode 281 through the second via D6. The first electrode 132 of the third transistor T3 is connected to the first doping region 130b of the active layer 130 of the third transistor T3 through the third via hole V3, and is connected to the first connection electrode 281 through the second via hole D7. The second electrode 133 of the third transistor T3 is connected to the second doping region 130c of the active layer 130 of the third transistor T3 and the second doping region 140c of the active layer 140 of the fourth transistor T4 through the third via hole V1. The second electrode 123 of the second transistor T2, the second electrode 133 of the third transistor T3, and the second electrode 143 of the fourth transistor T4 are an integrated structure.

[0215] In some exemplary embodiments, the first electrode 152 of the fifth transistor T5 is connected to the first doping region 150b of the active layer 150 of the fifth transistor T5 through the first via K3. The second electrode 153 of the fifth transistor T5 is connected to the second doping region 150c of the active layer 150 of the fifth transistor T5 through the first via K4, and is connected to the control electrode 121 and the second output terminal OUT2 of the second transistor T2 through the second via D2. The first electrode 162 of the sixth transistor T6 is connected to the first doping region 160b of the active layer 160 of the sixth transistor T6 through the third via V4, and is connected to the first connection electrode 281 through the second via D8. The second electrode 163 of the sixth transistor T6 is connected to the second doping region 160c of the active layer 160 of the sixth transistor T6 through the third via V5, and is connected to the control electrode 131 of the third transistor T3 through the fourth via F2. The second electrode 153 of the fifth transistor T5 and the second electrode 163 of the sixth transistor T6 are an integral structure.

[0216] In some exemplary embodiments, the first electrode 172 of the seventh transistor T7 is connected to the first doping region 170b of the active layer 170 of the seventh transistor T7 through the first via hole K6, connected to the second electrode 252 of the first capacitor C1 through the fourth via hole F5, and connected to the control electrode 201 of the tenth transistor T10 through the second via hole D12. The second electrode 173 of the seventh transistor T7 is connected to the second doping region 170c of the active layer 170 of the seventh transistor T7 through the first via hole K5, and connected to the control electrode 241 of the fourteenth transistor T14 through the second via hole D18. The first electrode 182 of the eighth transistor T8 is connected to the first doping region 180b of the active layer 180 of the eighth transistor T8 through the first via hole K7, and connected to the third connection electrode 283 through the fourth via hole F9. The sixth connection electrode 286 is connected to the control electrode 181 of the eighth transistor T8 through the second via hole D10, and connected to the second connection electrode 282 through the fourth via hole F7. The first electrode 192 of the ninth transistor T9 is connected to the first doped region 190b of the active layer 190 of the ninth transistor T9 through the first via K8. The second electrode 193 of the ninth transistor T9 is connected to the second doped region 190c of the active layer 190 of the ninth transistor T9 through the first via K9, and is connected to the first electrode 251 of the first capacitor C1 through the second via D9. The second clock signal line CB1 is connected to the control electrode 191 of the ninth transistor T9 through the second via D11. The first electrode 202 of the tenth transistor T10 is connected to the first doped region 200b of the active layer 200 of the tenth transistor T10 through the first via K10, and is connected to the second connection electrode 282 through the fourth via F6. The first electrode 202 of the tenth transistor T10 is an integral structure with the first input terminal INPUT1. The first clock signal line CK1 is connected to the control electrode 201 of the tenth transistor T10 through the second via D13. The first electrode 212 of the eleventh transistor T11 is connected to the first doping region 201b of the active layer 201 of the eleventh transistor T11 through the first via hole K12, and is connected to the third connection electrode 283 through the fourth via hole F8. The second electrode 213 of the eleventh transistor T11 is connected to the second doping region 201c of the active layer 201 of the eleventh transistor T11 through the first via hole K11. The second electrode 173 of the seventh transistor T7 and the second electrode 213 of the eleventh transistor T11 are an integral structure.

[0217] In some exemplary embodiments, the first electrode 222 of the twelfth transistor T12 is connected to the first doping region 220b of the active layer 220 of the twelfth transistor T12 through the first via hole K13, and is connected to the control electrode 211 of the eleventh transistor T11 through the second via hole D14. The second electrode 223 of the twelfth transistor T12 is connected to the second doping region 220c of the active layer 220 of the twelfth transistor T12 through the first via hole K14, and is connected to the control electrode 231 of the thirteenth transistor T13 through the second via hole D17. The first electrode 232 of the thirteenth transistor T13 is connected to the first doping region 230b of the active layer 230 of the thirteenth transistor T13 through three first via holes K15 arranged side by side, and is connected to the first connection electrode 281 through the second via hole D16. The second electrode 233 of the thirteenth transistor T13 is connected to the second doping region 230c of the active layer 230 of the thirteenth transistor T13 through three first via holes K16 arranged side by side, and is connected to the second electrode 262 of the second capacitor C2 through three fourth via holes F10 arranged side by side. The first electrode 242 of the fourteenth transistor T14 is connected to the first doping region 240b of the active layer 240 of the fourteenth transistor T14 through three first via holes K17 arranged side by side, and is connected to the third connection electrode 283 through the fourth via hole F9. The second electrode 243 of the fourteenth transistor T14 is connected to the second doping region 240c of the active layer 240 of the fourteenth transistor T14 through three first via holes K18 arranged side by side. The second electrode 243 of the fourteenth transistor T14 is an integral structure with the second electrode 233 of the thirteenth transistor T13.

[0218] In some exemplary embodiments, the second power line VGL is connected to the first connection electrode 281 through the second via D15. The first power line VGH is connected to the second electrode 272 of the second capacitor C2 through three vertically arranged fourth vias F12. The first power line VGH is an integral structure with the first electrode 122 of the first transistor T1, the first electrode 152 of the fifth transistor T5, the first electrode 182 of the eighth transistor T8, the first electrode 192 of the ninth transistor T9, and the first electrode 242 of the fourteenth transistor.

[0219] In some exemplary embodiments, the extension directions of the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the second power line VGL, and the first power line VGH are parallel to each other and perpendicular to the extension direction of the control signal line CSL. For example, the first initial signal line STV1, the first clock signal line CK1, the second clock signal line CB1, the second power line VGL, and the first power line VGH are arranged in sequence along the horizontal direction and all extend along the vertical direction; the control signal line CSL extends along the horizontal direction.

[0220] The first shift register unit provided in this exemplary embodiment can provide a second reset signal and a second scan signal to the pixel circuit in the display area. The second reset signal provided by the first shift register unit in this exemplary embodiment can maintain the voltage of the second node of the pixel circuit in the reset phase and the compensation phase.

[0221] Fig.43 FIG. 1 is an equivalent circuit diagram of a third shift register unit according to at least one embodiment of the present disclosure. Fig.43As shown, the third shift register unit provided by this exemplary embodiment includes: a 25th transistor T25 to a 34th transistor T34, a 6th capacitor C6, a 7th capacitor C7 and an 8th capacitor C8. The control electrode of the 25th transistor T25 is connected to the 5th clock signal line CK3, the first electrode of the 25th transistor T25 is connected to the 3rd input terminal INPUT3, and the second electrode of the 25th transistor T25 is connected to the 6th control node P6. The control electrode of the 26th transistor T26 is connected to the 6th control node P6, the first electrode of the 26th transistor T26 is connected to the 5th clock signal line CK3, and the second electrode of the 26th transistor T26 is connected to the 5th control node P5. The control electrode of the 27th transistor T27 is connected to the 5th clock signal line CK3, the first electrode of the 27th transistor T27 is connected to the 2nd power line VGL, and the second electrode of the 27th transistor T27 is connected to the 5th control node P5. The control electrode of the 28th transistor T28 is connected to the 6th clock signal line CB3, the first electrode of the 28th transistor T28 is connected to the 29th transistor T29, and the second electrode of the 28th transistor T28 is connected to the 6th control node P6. The control electrode of the twenty-ninth transistor T29 is connected to the fifth control node P5, and the first electrode of the twenty-ninth transistor T29 is connected to the first power line VGH. The control electrode of the thirtieth transistor T30 is connected to the fifth control node P5, the first electrode of the thirtieth transistor T30 is connected to the sixth clock signal line CB3, and the second electrode of the thirtieth transistor T30 is connected to the first electrode of the thirty-first transistor T31. The control electrode of the thirty-first transistor T31 is connected to the sixth clock signal line CB3, and the second electrode of the thirty-first transistor T31 is connected to the seventh control node P7. The control electrode of the thirty-second transistor T32 is connected to the sixth control node P6, the first electrode of the thirty-second transistor T32 is connected to the first power line VGH, and the second electrode of the thirty-second transistor T32 is connected to the seventh control node P7. The control electrode of the thirty-third transistor T33 is connected to the seventh control node P7, the first electrode of the thirty-third transistor T33 is connected to the first power line VGH, and the second electrode of the thirty-third transistor T33 is connected to the sixth output terminal OUT6. The control electrode of the thirty-fourth transistor T34 is connected to the sixth control node P6, the first electrode of the thirty-fourth transistor T34 is connected to the second power line VGL, and the second electrode of the thirty-fourth transistor T34 is connected to the sixth output terminal OUT6. The first electrode of the sixth capacitor C6 is connected to the control electrode of the thirtieth transistor T30, and the second electrode of the sixth capacitor C6 is connected to the second electrode of the thirtieth transistor T30. The first electrode of the seventh capacitor C7 is connected to the control electrode of the thirty-third transistor T33, and the second electrode of the seventh capacitor C7 is connected to the first power line VGH. The first electrode of the eighth capacitor C8 is connected to the control electrode of the thirty-fourth transistor T34, and the second electrode of the eighth capacitor C8 is connected to the sixth clock signal line CB3.

[0222] The following description is made by taking the example that the 25th transistor T25 to the 34th transistor T34 are all P-type transistors. The description is made by taking the first-stage third shift register unit as an example. The third input terminal INPUT3 of the first-stage third shift register unit is connected to the third initial signal line STV3. Fig.44 for Fig.43 The working timing diagram of the third shift register unit is shown in FIG. Fig.43 and Fig.44 As shown, the third shift register unit of the exemplary embodiment includes 10 transistor units (i.e., the 25th transistor T25 to the 34th transistor T34), 3 capacitor units (i.e., the 6th capacitor C6 to the 8th capacitor C8), 3 input terminals (i.e., the 5th clock signal line CK3, the 6th clock signal line CB3 and the 3rd input terminal INPUT3), 1 output terminal (i.e., the 6th output terminal OUT6) and 2 power supply terminals (i.e., the 1st power supply line VGH and the 2nd power supply line VGL). Among them, the 1st power supply line VGH continuously provides a high level signal, and the 2nd power supply line VGL continuously provides a low level signal.

[0223] like Fig.43 and Fig.44 As shown, the operation process of the third shift register unit of this exemplary embodiment includes the following stages.

[0224] In the first phase t31, the fifth clock signal line CK3 provides a high level signal, the sixth clock signal line CB3 provides a high level signal, and the third initial signal line STV3 provides a high level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-first transistor T31, and the thirty-third transistor T33 are turned off, the twenty-sixth transistor T26, the thirty-second transistor T32, and the thirty-fourth transistor T34 are turned on, and the sixth output terminal OUT6 outputs a low level signal.

[0225] In the second phase t32, the fifth clock signal line CK3 provides a low level signal, the sixth clock signal line CB3 provides a high level signal, and the third initial signal line STV3 provides a high level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-ninth transistor T29, and the thirtieth transistor T30 are turned on, the twenty-sixth transistor T26, the twenty-eighth transistor T28, the thirty-first transistor T31, the thirty-second transistor T32, the thirty-fourth transistor T34, and the thirty-third transistor T33 are turned off, and the sixth output terminal OUT6 outputs a low level signal.

[0226] In the third phase t33, the fifth clock signal line CK3 provides a high level signal, the sixth clock signal line CB3 provides a low level signal, and the third initial signal line STV3 provides a high level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-sixth transistor T26, the thirty-second transistor T32, and the thirty-fourth transistor T34 are turned off, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-first transistor T32, and the thirty-third transistor T33 are turned on, and the sixth output terminal OUT outputs a high level signal.

[0227] In the fourth stage t34, the fifth clock signal line CK3 provides a low level signal, the sixth clock signal line CB3 provides a high level signal, and the third initial signal line STV3 provides a high level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-ninth transistor T29, the thirtieth transistor T30, and the thirty-third transistor T33 are turned on, the twenty-sixth transistor T26, the twenty-eighth transistor T28, the thirty-first transistor T31, the thirty-second transistor T32, and the thirty-fourth transistor T34 are turned off, and the sixth output terminal OUT6 provides a high level signal.

[0228] In the fifth stage t35, the fifth clock signal line CK3 provides a high level signal, the sixth clock signal line CB3 provides a low level signal, and the third initial signal line STV3 provides a low level signal. The twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, the thirty-second transistor T32, and the thirty-fourth transistor T34 are turned off, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-first transistor T31, and the thirty-third transistor T33 are turned on, and the sixth output terminal OUT6 provides a high level signal.

[0229] In the sixth stage t36, the fifth clock signal line CK3 provides a low level signal, the sixth clock signal line CB3 provides a high level signal, and the third initial signal line STV3 provides a low level signal. The twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, the thirty-second transistor T32, and the thirty-fourth transistor T34 are turned on, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-first transistor T31, and the thirty-third transistor T33 are turned off, and the sixth output terminal OUT6 provides a low level signal.

[0230] In the seventh stage t37, the fifth clock signal line CK3 provides a high level signal, the sixth clock signal line CB3 provides a low level signal, and the third initial signal line STV3 provides a low level signal. The twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-ninth transistor T29, the thirtieth transistor T30 and the thirty-third transistor T33 are turned off, the twenty-sixth transistor T26, the thirty-first transistor T31, the thirty-second transistor T32 and the thirty-fourth transistor T34 are turned on, and the sixth output terminal OUT6 provides a low level signal.

[0231] After the seventh stage, the sixth stage and the seventh stage may be repeated until the third input terminal INPUT3 inputs a low level signal, and then restarts from the first stage.

[0232] The third shift register unit provided in the present exemplary embodiment provides a light emission control signal to the pixel circuit through the light emission control line.

[0233] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more of spraying and spin coating, and etching can be carried out by any one or more of dry etching and wet etching. "Thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0234] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0235] In some exemplary embodiments, the preparation process of the display substrate may include the following operations: Figures 20 to 27 as well as Figures 35 to 42 The preparation process of this exemplary embodiment is described by taking a sub-pixel in the display area and a first shift register unit in the peripheral area as an example, and the equivalent circuit diagram of the pixel circuit of the sub-pixel is shown in FIG. Fig.18 As shown, the equivalent circuit diagram of the first shift register unit is as follows Figure 7 shown.

[0236] (1) Prepare a flexible substrate on a glass carrier.

[0237] In some exemplary embodiments, the base substrate 30 includes a first flexible layer 30A, a first inorganic material layer 30B, a second flexible layer 30C, and a second inorganic material layer 30D stacked on a glass carrier. The materials of the first flexible layer 30A and the second flexible layer 30C can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer 30B and the second inorganic material layer 30D can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the base substrate. The first inorganic material layer 30B and the second inorganic material layer 30D are also called barrier layers.

[0238] In some exemplary embodiments, the preparation process of the base substrate may include: first coating a layer of polyimide on a glass carrier, and curing the layer to form a first flexible layer; then depositing a layer of barrier film on the first flexible layer to form a first barrier layer covering the first flexible layer; then coating the first barrier layer with another layer of polyimide, and curing the layer to form a second flexible layer; then depositing a layer of barrier film on the second flexible layer to form a second barrier layer covering the second flexible layer, thereby completing the preparation of the base substrate 30. After this process, the display area and the peripheral area both include the base substrate 30, such as Fig.21 and Fig.36 shown.

[0239] (2) Forming a first semiconductor layer pattern.

[0240] In some exemplary embodiments, a first insulating film and a first semiconductor film are sequentially deposited on the base substrate 30, and the first semiconductor film is patterned by a patterning process to form a first insulating layer 31 covering the entire base substrate 30, and a first semiconductor layer pattern is disposed on the first insulating layer 31, such as Fig. 22 and Fig.37 As shown. In some examples, the first semiconductor layer pattern includes at least: an active layer of multiple P-type transistors in the pixel circuit and the first shift register unit. The active layer may include a channel region, a source region, and a drain region. The channel region may not be doped with impurities and have semiconductor properties. The source region and the drain region may be on both sides of the channel region and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor film may be polysilicon.

[0241] (3) Forming a first conductive layer pattern.

[0242] In some exemplary embodiments, a second insulating film and a first metal film are sequentially deposited on the substrate substrate 30 on which the aforementioned pattern is formed, and the first metal film is patterned by a patterning process to form a second insulating layer 32 covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 32, such as Fig.23 and Fig.38 In some examples, the first conductive layer pattern includes at least: control electrodes of multiple P-type transistors in the pixel circuit and the first shift register unit, first electrodes of multiple capacitors in the pixel circuit and the first shift register unit, a light-emitting control line EM that provides a light-emitting control signal to the pixel circuit, a first scan line GT1 that provides a first scan signal to the pixel circuit, a second reset signal line RST2 that provides a second reset signal to the pixel circuit, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal OUT3 of the first shift register unit.

[0243] (4) Forming a second semiconductor layer pattern.

[0244] In some exemplary embodiments, on the substrate 30 formed with the aforementioned pattern, a third insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned by a patterning process to form a third insulating layer 33 covering the first conductive layer, and a second semiconductor layer pattern disposed on the third insulating layer 33, such as Fig.24 and Fig.39 In some examples, the second semiconductor layer pattern includes at least: the active layer of a plurality of N-type transistors in the pixel circuit and the first shift register unit. In some examples, the material of the second semiconductor film may be IGZO.

[0245] (5) Forming a second conductive layer pattern.

[0246] In some exemplary embodiments, on the substrate 30 having the aforementioned pattern, a fourth insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a fourth insulating layer 34 covering the second semiconductor layer, and a second conductive layer pattern disposed on the fourth insulating layer 34, such as Fig.25 and Fig.40 In some examples, the second conductive layer pattern includes at least: control electrodes of multiple N-type transistors in the pixel circuit and the first shift register unit, second electrodes of multiple capacitors in the pixel circuit and the first shift register unit, a first reset signal line RST1 for providing a first reset signal to the pixel circuit, a second scan line GT2 for providing a second scan signal to the pixel circuit, a reference voltage line REF for providing a reference voltage to the pixel circuit, and a control signal line CSL for providing a control signal to the first shift register unit.

[0247] (6) Forming a fifth insulating layer pattern.

[0248] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 30 having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer 35 pattern covering the second conductive layer, such as Fig.26 and Fig.41 As shown. In some examples, a plurality of vias are provided on the fifth insulating layer 35, and the plurality of vias include at least: first vias K1 to K26 exposing the first semiconductor layer, second vias D1 to D22 exposing the first conductive layer, third vias V1 to V8 exposing the second semiconductor layer, and fourth vias F1 to F15 exposing the second conductive layer. The fifth insulating layer 35, the fourth insulating layer 34, the third insulating layer 33, and the second insulating layer 32 in the first vias K1 to K26 are etched away, the fifth insulating layer 35, the fourth insulating layer 34, and the third insulating layer 33 in the second vias D1 to D22 are etched away, the fifth insulating layer 35 and the fourth insulating layer 34 in the third vias V1 to V8 are etched away, and the fifth insulating layer 35 in the fourth vias F1 to F15 is etched away.

[0249] (7) Forming a third conductive layer pattern.

[0250] In some exemplary embodiments, a third metal film is deposited on the substrate 30 on which the aforementioned pattern is formed, and the third metal film is patterned by a patterning process to form a third conductive layer pattern on the fifth insulating layer 35, such as Fig. 27 and Fig.42 In some examples, the third conductive layer pattern includes at least: first electrodes and second electrodes of multiple P-type transistors and multiple N-type transistors in the pixel circuit and the first shift register unit, an initial voltage line INT for providing an initial voltage to the pixel circuit, a data line DATA for providing a data signal to the pixel circuit, a third power line VDD for providing a power supply voltage to the pixel circuit, a first initial signal line STV1 connected to the first shift register unit, a first clock signal line CK1, a second clock signal line CK2, a first power line VGH and a second power line VGL, and multiple connection electrodes in the pixel circuit and the first shift register unit.

[0251] (8) Forming a planarization layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer and an encapsulation layer pattern in sequence.

[0252] In some exemplary embodiments, a flat film is coated on a substrate base having the aforementioned pattern formed thereon, and a flat layer pattern is formed by masking, exposing and developing the flat film. Subsequently, an anode film is deposited on the substrate base having the aforementioned pattern formed thereon, and the anode film is patterned by a patterning process to form an anode pattern on the flat layer. Then, a pixel definition film is coated on the substrate base having the aforementioned pattern formed thereon, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by masking, exposing and developing processes, and the pixel definition layer is formed in each sub-pixel in the display area, and the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode. Subsequently, an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode pattern, and the cathode is respectively connected to the organic light-emitting layer and the second power line. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material. In some possible implementations, the cathode may be connected to the second power line in a variety of ways, such as laser drilling, etc.

[0253] In some exemplary embodiments, the first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the fourth insulating layer 34 and the fifth insulating layer 35 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer 31 and the third insulating layer 33 are called buffer layers, and the first insulating layer 31 is configured to improve the water and oxygen resistance of the substrate; the second insulating layer 32 and the fourth insulating layer 34 are called gate insulating (GI) layers, and the fifth insulating layer 35 is called an interlayer insulating (ILD) layer. The planar layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The pixel definition layer may be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The anode may be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited to this. For example, the anode may be made of a reflective material such as a metal, and the cathode may be made of a transparent conductive material.

[0254] The structure and preparation process shown in this exemplary embodiment are merely exemplary. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, after forming the third conductive layer, the sixth insulating layer, the first flat layer, the fourth conductive layer, the second flat layer, the anode layer, the pixel definition layer, the organic light-emitting layer, the cathode layer and the encapsulation layer pattern can be formed in sequence. For another example, the first insulating layer, the first semiconductor layer, the second insulating layer, the first conductive layer, the third insulating layer, the second conductive layer, the fourth insulating layer, the second semiconductor layer, the fifth insulating layer and the third conductive layer can be formed in sequence on the substrate. For example, an N-type thin film transistor can adopt a bottom gate structure. However, this embodiment is not limited to this.

[0255] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0256] The display substrate provided by the exemplary embodiment provides a plurality of different gate drive signals to the pixel circuit through the gate drive circuit, which can improve the performance of the pixel circuit, so that the pixel circuit can meet both low-frequency (e.g., about 1 Hz) drive and high-frequency (e.g., about 140 Hz) drive. For example, when the electronic product is in standby or electronic reading, low-frequency drive is used to save power consumption, while high-frequency drive is used in the game state.

[0257] Fig.45 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.45 As shown, this embodiment provides a display device 91, including: a display substrate 910. The display substrate 910 is the display substrate provided in the above embodiment. Among them, the display substrate 910 can be an OLED display substrate. The display device 91 can be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and any other product or component with a display function. However, this embodiment is not limited to this.

[0258] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0259] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A shift register unit, comprising: An input circuit, a first control circuit, a second control circuit and an output circuit; The input circuit is connected to the first clock signal line, the second clock signal line, the first input terminal, the first power line, the first control node and the second control node, and is configured to provide the signal of the first input terminal to the second control node under the control of the first clock signal line, and to provide the signal of the first clock signal line or the first power line to the first control node under the control of the second clock signal line, the first input terminal and the second control node; The first control circuit is connected to the first control node, the second control node, the first power line, the second power line and the first output terminal, and is configured to provide a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node; The second control circuit is connected to the first power line, the second power line, the first output terminal and the second output terminal, and is configured to provide an effective level signal of the first power line or the second power line to the second output terminal under the control of the first output terminal; The output circuit is connected to the control signal line, the first power line, the second power line, the second output terminal and the third output terminal, and is configured to output the effective level signal of the first power line or the second power line to the third output terminal under the control of the control signal line and the second output terminal; within one frame time, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal; Wherein, the output circuit comprises: a first output subcircuit and a second output subcircuit; The first output subcircuit is connected to the control signal line, the first power line, the second output terminal and the third output terminal, and is configured to provide an effective level signal of the first power line to the third output terminal under the control of the control signal line and the second output terminal; The second output subcircuit is connected to the control signal line, the second power line, the second output terminal and the third output terminal, and is configured to provide an effective level signal of the second power line to the third output terminal under the control of the control signal line and the second output terminal; The first output subcircuit comprises: a first transistor and a second transistor; the control electrode of the first transistor is connected to the control signal line, the first electrode of the first transistor is connected to the first power line, and the second electrode of the first transistor is connected to the first electrode of the second transistor; the control electrode of the second transistor is connected to the second output terminal, and the second electrode of the second transistor is connected to the third output terminal; The second output subcircuit includes: a third transistor and a fourth transistor; the control electrode of the third transistor is connected to the second output terminal, the first electrode of the third transistor is connected to the second power line, and the second electrode of the third transistor is connected to the third output terminal; the control electrode of the fourth transistor is connected to the control signal line, the first electrode of the fourth transistor is connected to the second power line, and the second electrode of the fourth transistor is connected to the third output terminal.

2. The shift register unit according to claim 1, wherein: The output signal of the first output terminal is opposite in phase to the output signal of the second output terminal; the second output terminal and the third output terminal provide effective level signals with opposite polarities, and within one frame time, the third output terminal outputs the effective level signal of the first power line or the second power line at intervals.

3. The shift register unit according to claim 1, wherein: The effective level signal provided to the third output terminal within one frame time includes: a first time period and a second time period of interval; The first time period is configured to output a valid level signal of the second power line to the third output terminal under the control of the control signal line; The second time period is configured to output a valid level signal of the second power line to the third output terminal under the control of the second output terminal.

4. The shift register unit according to claim 1, wherein: The second control circuit includes: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first output terminal, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the second output terminal; The control electrode of the sixth transistor is connected to the first output terminal, the first electrode of the sixth transistor is connected to the second power line, and the second electrode of the sixth transistor is connected to the second output terminal.

5. The shift register unit according to claim 4, wherein: The input circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a first capacitor; The control electrode of the seventh transistor is connected to the second electrode of the eighth transistor and the second electrode of the ninth transistor, the first electrode of the seventh transistor is connected to the first clock signal line, and the second electrode of the seventh transistor is connected to the first control node; the control electrode of the eighth transistor is connected to the first input terminal, and the first electrode of the eighth transistor is connected to the first power line; the control electrode of the ninth transistor is connected to the second clock signal line, and the first electrode of the ninth transistor is connected to the first power line; the control electrode of the tenth transistor is connected to the first clock signal line, the first electrode of the tenth transistor is connected to the first input terminal, and the second electrode of the tenth transistor is connected to the second control node; the control electrode of the eleventh transistor is connected to the second control node, the first electrode of the eleventh transistor is connected to the first power line, and the second electrode of the eleventh transistor is connected to the first control node; the first electrode of the first capacitor is connected to the control electrode of the seventh transistor, and the second electrode of the first capacitor is connected to the first clock signal line.

6. The shift register unit according to claim 5, wherein: The first control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a second capacitor and a third capacitor; The control electrode of the twelfth transistor is connected to the second power line, the first electrode of the twelfth transistor is connected to the second control node, and the second electrode of the twelfth transistor is connected to the control electrode of the thirteenth transistor; the first electrode of the thirteenth transistor is connected to the second power line, and the second electrode of the thirteenth transistor is connected to the first output terminal; the control electrode of the fourteenth transistor is connected to the first control node, the first electrode of the fourteenth transistor is connected to the first power line, and the second electrode of the fourteenth transistor is connected to the first output terminal; The first electrode of the second capacitor is connected to the control electrode of the thirteenth transistor, and the second electrode of the second capacitor is connected to the first output end; the first electrode of the third capacitor is connected to the control electrode of the fourteenth transistor, and the second electrode of the third capacitor is connected to the first power line.

7. The shift register unit according to claim 6, wherein: The third transistor, the fourth transistor and the sixth transistor are first semiconductor type transistors, and the first transistor, the second transistor, the fifth transistor, the seventh transistor to the fourteenth transistor are second semiconductor type transistors; the doping types of the first semiconductor type and the second semiconductor type are opposite.

8. The shift register unit according to claim 7, wherein: The third transistor, the fourth transistor and the sixth transistor are oxide thin film transistors.

9. A driving method of a shift register unit, applied to the shift register unit according to any one of claims 1 to 8, the driving method comprising: The input circuit provides a signal of the first input terminal to the second control node under the control of the first clock signal line, and provides a signal of the first clock signal line or the first power line to the first control node under the control of the second clock signal line, the first input terminal and the second control node; The first control circuit provides a signal of the first power line or the second power line to the first output terminal under the control of the first control node and the second control node; The second control circuit provides an effective level signal of the first power line or the second power line to the second output terminal under the control of the first output terminal; Under the control of the control signal line and the second output terminal, the output circuit outputs the effective level signal of the first power line or the second power line to the third output terminal; within one frame time, the duration of the effective level signal provided by the third output terminal is greater than the duration of the effective level signal provided by the second output terminal.

10. The driving method according to claim 9, wherein: The output circuit outputs the effective level signal of the first power line or the second power line to the third output terminal under the control of the control signal line and the second output terminal, including: The output circuit outputs the effective level signal of the second power line to the third output terminal in a first time period within a frame time under the control of the control signal line; Under the control of the second output terminal, the output circuit outputs the effective level signal of the second power line to the third output terminal in a second time period spaced apart from the first time period within one frame time.

11. A gate drive circuit, comprising: A plurality of cascaded first shift register units, wherein the first shift register unit is a shift register unit according to any one of claims 1 to 8; Among them, the first input end of the first-stage first shift register unit is connected to the first initial signal line; the first input end of the n+1th-stage first shift register unit is connected to the first output end of the nth-stage first shift register unit, wherein n is an integer greater than 0.

12. The gate driving circuit according to claim 11, further comprising: a plurality of cascaded second shift register units; The second shift register unit comprises: a second input terminal, a fourth output terminal and a fifth output terminal; Among them, the second input end of the first-level second shift register unit is connected to the second initial signal line; the second input end of the n+1-level second shift register unit is connected to the fourth output end of the n-level second shift register unit; the fifth output end of the n-level second shift register unit is connected to the control signal line of the n-level first shift register unit, or the fourth output end of the n-level second shift register unit is connected to the control signal line of the n-level first shift register unit.

13. The gate driving circuit according to claim 12, wherein: The second shift register unit comprises: a fifteenth transistor to a twenty-fourth transistor, a fourth capacitor and a fifth capacitor; The control electrode of the fifteenth transistor is connected to the third clock signal line, the first electrode of the fifteenth transistor is connected to the second input terminal, and the second electrode of the fifteenth transistor is connected to the fourth control node; the control electrode of the sixteenth transistor is connected to the fourth control node, the first electrode of the sixteenth transistor is connected to the third clock signal line, and the second electrode of the sixteenth transistor is connected to the third control node; the control electrode of the seventeenth transistor is connected to the third clock signal line, the first electrode of the seventeenth transistor is connected to the second power supply line, and the second electrode of the seventeenth transistor is connected to the third control node; the control electrode of the eighteenth transistor is connected to the third control node, the first electrode of the eighteenth transistor is connected to the first power supply line, and the second electrode of the eighteenth transistor is connected to the fourth output terminal; the control electrode of the nineteenth transistor is connected to the second electrode of the twenty-second transistor, the first electrode of the nineteenth transistor is connected to the fourth clock signal line, and the second electrode of the nineteenth transistor is connected to the fourth output terminal; the control electrode of the twentieth transistor is connected to the third control node, and the first electrode of the twentieth transistor is connected to the first power supply line The second electrode of the 20th transistor is connected to the first electrode of the 21st transistor; the control electrode of the 21st transistor is connected to the fourth clock signal line, and the second electrode of the 21st transistor is connected to the fourth control node; the control electrode of the 22nd transistor is connected to the second power supply line, the first electrode of the 22nd transistor is connected to the fourth control node, and the second electrode of the 22nd transistor is connected to the control electrode of the 19th transistor; the control electrode of the 23rd transistor is connected to the fourth output terminal, the first electrode of the 23rd transistor is connected to the second power supply line, and the second electrode of the 23rd transistor is connected to the fifth output terminal; the control electrode of the 24th transistor is connected to the fourth output terminal, the first electrode of the 24th transistor is connected to the first power supply line, and the second electrode of the 24th transistor is connected to the fifth output terminal; the first electrode of the fourth capacitor is connected to the control electrode of the 18th transistor, and the second electrode of the fourth capacitor is connected to the first power supply line; the first electrode of the fifth capacitor is connected to the control electrode of the 19th transistor, and the second electrode of the fifth capacitor is connected to the fourth output terminal.

14. A display substrate, comprising: A display area and a peripheral area located around the display area; The display area is provided with a plurality of sub-pixels; The peripheral area is provided with a gate driving circuit; The gate driving circuit comprises: a plurality of cascaded first shift register units, wherein the first shift register unit is a shift register unit according to any one of claims 1 to 8; At least one sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; The n-th stage first shift register unit of the gate driving circuit is configured to provide a gate driving signal to the pixel circuits of the n-th row of sub-pixels, wherein n is an integer greater than 0.

15. The display substrate according to claim 14, wherein: The pixel circuit comprises: a data writing subcircuit, a driving subcircuit, a storage subcircuit, a compensation subcircuit, a level holding subcircuit, a light emitting control subcircuit, a first initialization subcircuit and a second initialization subcircuit; The data writing subcircuit is connected to the data line, the first scan line and the second node, and is configured to write the signal of the data line to the storage subcircuit under the control of the first scan line; the driving subcircuit is connected to the third power line, the first node and the third node, and is configured to output the driving current to the light emitting control subcircuit through the third node under the control of the first node; the storage subcircuit is connected to the first node and the second node; the level holding subcircuit is connected to the third power line and the second node, and is configured to hold the potential of the second node; the compensation subcircuit is connected to the second scan line, the first node and the third node, and is configured to output the driving current to the light emitting control subcircuit through the third node under the control of the first node; The threshold voltage of the driving subcircuit is compensated under the control of the first reset signal line; the first initialization subcircuit is connected to the first reset signal line, the initial voltage line and the first node, and is configured to initialize the first node under the control of the first reset signal line; the second initialization subcircuit is connected to the second reset signal line, the reference voltage line and the second node, and is configured to initialize the second node under the control of the second reset signal line; the light-emitting control subcircuit is connected to the light-emitting control line, the third node and the first electrode of the light-emitting element, and is configured to drive the light-emitting element to emit light according to the driving current under the control of the light-emitting control line; the second electrode of the light-emitting element is connected to the fourth power line; The writing time length of the data writing subcircuit writing the signal of the data line into the storage subcircuit is shorter than the threshold voltage compensation time length of the driving subcircuit by the compensation subcircuit; The third output end of the nth-stage first shift register unit of the gate driving circuit is connected to the second reset signal line of the pixel circuit driving the nth row of sub-pixels; the second output end of the nth-stage first shift register unit is connected to the second scan line of the pixel circuit driving the nth row of sub-pixels.

16. The display substrate according to claim 15, wherein: The pixel circuit also includes: a third initialization sub-circuit, connected to a third reset signal line, an initial voltage line and a first electrode of the light-emitting element, and configured to initialize the first electrode of the light-emitting element under the control of the third reset signal line; the third reset signal line connected to the pixel circuit of the nth row of sub-pixels is configured to be connected to the second reset signal line of the pixel circuit driving the n+1th row of sub-pixels.

17. The display substrate according to claim 16, wherein: The data writing sub-circuit comprises: a data writing transistor, wherein a control electrode of the data writing transistor is connected to a first scanning line, a first electrode of the data writing transistor is connected to a data line, and a second electrode of the data writing transistor is connected to a second node; The driving subcircuit comprises: a driving transistor, a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third power line, and a second electrode of the driving transistor is connected to the third node; The storage subcircuit comprises: a storage capacitor, a first electrode of the storage capacitor is connected to a first node, and a second electrode of the storage capacitor is connected to a second node; The level-maintaining subcircuit comprises: a voltage-stabilizing capacitor, a first electrode of the voltage-stabilizing capacitor is connected to the second node, and a first electrode of the voltage-stabilizing capacitor is connected to the third power line; The compensation subcircuit comprises: a compensation transistor, a control electrode of the compensation transistor is connected to the second scan line, a first electrode of the compensation transistor is connected to the first node, and a second electrode of the compensation transistor is connected to the third node; The light emitting control subcircuit comprises: a light emitting control transistor, a control electrode of the light emitting control transistor is connected to a light emitting control line, a first electrode of the light emitting control transistor is connected to a third node, and a second electrode of the light emitting control transistor is connected to a first electrode of a light emitting element; The first initialization subcircuit comprises: a first initialization transistor, wherein a control electrode of the first initialization transistor is connected to a first reset signal line, a first electrode of the first initialization transistor is connected to an initial voltage line, and a second electrode of the first initialization transistor is connected to a first node; The second initialization sub-circuit comprises: a second initialization transistor, a control electrode of the second initialization transistor is connected to a second reset signal line, a first electrode of the second initialization transistor is connected to a reference voltage line, and a second electrode of the second initialization transistor is connected to a second node; The third initialization subcircuit includes: a third initialization transistor, a control electrode of the third initialization transistor is connected to a third reset signal line, a first electrode of the third initialization transistor is connected to an initial voltage line, and a second electrode of the third initialization transistor is connected to a first electrode of the light-emitting element.

18. The display substrate according to claim 17, wherein: The compensation transistor and the first initialization transistor are first semiconductor type transistors, the driving transistor, the data writing transistor, the light emitting control transistor, the second initialization transistor and the third initialization transistor are second semiconductor type transistors; the first semiconductor type and the second semiconductor type have opposite doping types.

19. The display substrate according to any one of claims 14 to 18, wherein: The gate driving circuit further includes: a plurality of cascaded second shift register units; The second shift register unit comprises: a second input terminal, a fourth output terminal and a fifth output terminal; The second input terminal of the first-stage second shift register unit is connected to the second initial signal line; the second input terminal of the n+1-th-stage second shift register unit is connected to the fourth output terminal of the n-th-stage second shift register unit; The fourth output terminal of the second shift register unit of the nth stage is connected to the first scan line of the pixel circuit driving the sub-pixels of the n-2th row; The fifth output terminal of the n-th stage second shift register unit is connected to the first reset signal line of the pixel circuit driving the n-th row of sub-pixels.

20. A display device comprising the display substrate according to any one of claims 14 to 19.

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