Method and apparatus for programming and erasing dual ended memory devices

Abstract

A method of performing an erase or program operation on dual-ended storage devices includes initiating erase cycles or program cycles of dual-ended storage devices of a first batch of dual-ended storage devices substantially simultaneously, monitoring an erase detect or program detect condition of each dual-ended storage device, and prior to detecting the erase detect or program detect condition of all of the dual-ended storage devices, the method includes detecting the erase detect or program detect condition of a first dual-ended storage device of the first batch of dual-ended storage devices, and in response to detecting the erase detect or program detect condition of the first dual-ended storage device, initiating an erase cycle or program of a second dual-ended storage device of a second batch of dual-ended storage devices.

Description

Technical Field

[0001] Embodiments of this disclosure relate to dual-ended storage devices and methods. For example, embodiments relate to methods and apparatus for performing bulk programming or erasing operations on resistive random access memory in a dual-ended storage device. Background Technology

[0002] Resistor-switched memory (RSM) represents the latest innovation in the field of integrated circuit technology. Although most RSM technologies are still under development, the inventors have articulated various technical concepts for RSM, and these concepts are in one or more verification stages to prove or refute related theories or technologies. The inventors believe that RSM technology demonstrates compelling evidence of its substantial advantages over competing technologies in the semiconductor electronics industry.

[0003] The inventors believe that a resistance-switching memory cell can be configured to include multiple states with different measurable resistance values. For example, for a single bit cell, the resistance-switching memory cell can be configured to exist in a relatively low resistance state or a relatively high resistance state. A multi-bit cell can have other states with resistances different from each other and different from the relatively low resistance state and the relatively high resistance state. The different resistance states of the resistance-switching memory cell can be associated with logical information states to perform digital storage operations. Therefore, the inventors believe that an array of many such memory cells can provide digital memory storage of many bits.

[0004] The inventors have successfully made resistive-switched memories enter one resistive state or another in response to external conditions. Therefore, in transistor terms, applying or removing external conditions can be used to program or deprogram (e.g., erase) the memory. Furthermore, depending on the physical configuration and electrical arrangement, resistive-switched memory cells can typically remain in a programmed or deprogrammed state. Depending on the characteristics of the memory cell device, maintaining the state may require other conditions to be met (e.g., the presence of a minimum operating voltage, a minimum operating temperature, etc.), or the conditions may not be met.

[0005] The inventors have proposed several schemes for practically applying resistor-switching technology to memory applications in electronic devices. For example, resistor-switching elements are generally considered in theory to be a viable alternative, at least partially, to metal-oxide-semiconductor (MOS) type memory transistors used for electronic storage of digital information. Compared to non-volatile FLASH MOS type transistors, resistor-switched memory devices offer several potential technological advantages.

[0006] In view of the above, the rights holder of this disclosure is committed to the continuous development of the practical application of resistance switching technology. Summary of the Invention

[0007] The following is a simplified overview of this disclosure to provide a basic understanding of some aspects described herein. This overview is not a comprehensive summary of this disclosure. It is not intended to identify essential or key elements of this disclosure, nor to depict the scope of the invention. Its sole purpose is to present some concepts of this disclosure in a simplified form as a prelude to the more detailed description that follows.

[0008] Some embodiments relate to a filament-based resistive random access memory (ReRAM) device being developed by the patentee. Other embodiments may also be applied to other types of two-terminal devices, such as oxygen-vacancy memories, phase-change memories, magnetic memories, etc. In various embodiments, it is conventional to associate an erase state with a high-resistance state and a programming state with a low-resistance state, although other conventions are also within the scope of this disclosure. When a read voltage or current is applied to the ReRAM device, the erase state of the ReRAM device is determined by detecting a small current (e.g., relative to a preset threshold), and the programming state of the ReRAM is determined by detecting a large current (e.g., also relative to a threshold).

[0009] According to one aspect, a method for performing erase or programming operations on dual-ended memory devices is described. One technique includes initiating erase or programming cycles for a first batch of dual-ended memory devices approximately simultaneously, and monitoring erase detection or programming detection conditions for each dual-ended memory device. In various embodiments, the substantially simultaneous nature of the electronic storage operation can be defined, for example, simultaneous application of power signals, initiation of power signals within the same clock cycle of a control current or voltage circuit to perform a storage operation on the dual-ended memory device, or in adjacent clock cycles. A process includes, before detecting erase detection or programming detection conditions for all dual-ended memory devices: detecting erase detection or programming detection conditions for a first batch of dual-ended memory devices, and, in response to detecting erase detection or programming detection conditions for the first batch of dual-ended memory devices, initiating erase cycles or programming cycles for a second batch of dual-ended memory devices.

[0010] According to another aspect, a semiconductor device is described. An apparatus includes a first batch of dual-ended memory devices and a second batch of dual-ended memory devices. A system may include: a state adjustment initiation unit connected to the first batch of dual-ended memory devices and the second batch of dual-ended memory devices, wherein the state adjustment initiation unit is configured to substantially initiate each dual-ended memory device in the first batch of dual-ended memory devices into a predetermined state, wherein the predetermined state is selected from a group consisting of an erase state and a programming state; and a detection unit connected to the first batch of dual-ended memory devices and the state adjustment initiation unit, wherein the detection unit is configured to simultaneously detect whether each dual-ended memory device in the first batch of dual-ended memory devices has encountered an adjustment success condition. In various embodiments, the state adjustment initiation unit is further configured to, in response to detecting that a second dual-ended memory device in the first batch of dual-ended memory devices has encountered an adjustment success condition and before detecting adjustment success conditions for all dual-ended memory devices in the first batch of dual-ended memory devices, initiate the first dual-ended memory device in the second batch of dual-ended memory devices into a predetermined state.

[0011] The following description and accompanying drawings illustrate certain illustrative aspects of this specification. However, these aspects represent only a few of the various ways in which the principles of this specification may be employed. Other advantages and novel features of this specification will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Many aspects, embodiments, objects, and advantages of the present invention will become apparent upon consideration of the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals refer to the same parts throughout. Numerous specific details are set forth in this specification to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the present disclosure may be practiced without these specific details or using other methods, components, materials, etc. In other instances, well-known structures and apparatuses are shown in block diagram form to facilitate the description of the present disclosure;

[0013] Figure 1 An example circuit diagram of an array of dual-ended storage devices for implementing various aspects of this disclosure is shown in an embodiment;

[0014] Figure 2 An example block diagram of a memory operation circuit for operating a block of memory cells according to a further embodiment is depicted;

[0015] Figure 3 A block diagram illustrating the asynchronous operation of the storage operation driver relative to other drivers in an embodiment is shown.

[0016] Figure 4 A diagram depicts the possible programming cycles of an asynchronous driver operating on a double-ended memory cell block in a further embodiment;

[0017] Figure 5 A signal timing diagram of multiple dual-ended memory cells is shown that contributes to improved operating time in other embodiments;

[0018] Figure 6 A schematic diagram of an example multiplexer for connecting an operation driver to a different subset of a storage block is depicted in one or more embodiments;

[0019] Figure 7 A flowchart illustrating an example method for programming or erasing a block of memory cells according to a disclosed embodiment is shown;

[0020] Figure 8 A flowchart is shown for an example method for implementing storage operations on a dual-ended storage device according to a further embodiment;

[0021] Figure 9 A block diagram of an example electronic operating environment according to certain embodiments presented herein is shown;

[0022] Figure 10 A block diagram depicts an example computing environment for implementing one or more of the disclosed embodiments. Detailed Implementation

[0023] As the name suggests, a dual-ended memory device has two terminals or electrodes. Here, the terms "electrode" and "terminal" are used interchangeably. Typically, the first electrode of a dual-ended memory is called the "top electrode" (TE), and the second electrode is called the "bottom electrode" (BE), but it should be understood that the electrodes of a dual-ended memory device can be arranged in any suitable configuration, including horizontal arrangements where the components of the memory cell are (generally) side-by-side rather than overlapping each other. The layer between the TE and BE of a dual-ended memory device is typically an interface layer, sometimes also called a switching layer, resistance-switching medium (RSM), or resistance-switching layer (RSL). When an RSM is incorporated, the dual-ended memory device may be referred to as a (dual-ended) resistance-switching device. Various embodiments of this disclosure provide a dual-ended resistance-switching device that connects to multiple components at one of the two terminals, thereby forming a three-terminal non-volatile memory cell.

[0024] Generally, the composition of a memory cell can vary depending on the individual device selected to achieve desired characteristics (e.g., volatile / non-volatile, on / off current ratio, switching time, read time, memory durability, program / erase cycle time, etc.). An example of a filament-based device may include: a conductive layer, such as a metal, metal alloy, or metal nitride (e.g., including TiN, TaN, TiW, or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) support layer (e.g., p-type or n-type Si support layer, p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, etc.)); a resistive switching layer (RSL); and an active metal layer capable of being ionized. Under suitable conditions, the active metal layer can provide ions for filament formation to the RSL. In these embodiments, the conductive filament (e.g., formed by ions) can be made conductive by at least a subset of the RSL, and the resistance of the filament-based device can be determined, for example, by the tunneling resistance between the filament and the conductive layer. A storage cell with this characteristic can be described as a filament-based device.

[0025] RSL (which may also be referred to in the art as resistance switching medium (RSM)) may include, for example, an undoped amorphous Si layer, a semiconductor layer with intrinsic properties, or silicon nitride (e.g., SiN, Si3N4, SiN...). x Suboxides of Si (e.g., SiO2) x (where x is between 0.1 and 2), Si nitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si. x Ge y O z (where x, y, and z are appropriate positive numbers), silicon dioxide (e.g., SiO2). N (where N is a suitable positive number), silicon oxynitride, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is a suitable number), Al2O E (where E is a suitable positive number) etc., nitrides (e.g., AlN, SiN), or suitable combinations thereof.

[0026] In some embodiments, a RSL (non-volatile RSL) that is part of a non-volatile memory device can include a relatively large amount (e.g., compared to a volatile selector device) of material voids or defects to trap neutral metal particles within the RSL (at least at low voltages). The large amount of voids or defects can facilitate the formation of a thick, stable structure of neutral metal particles. In such a structure, these trapped particles can keep the non-volatile memory device in a low resistance state without an external stimulus (e.g., a power source), enabling non-volatile operation. In other embodiments, a RSL (volatile RSL) employed in a volatile selector device can have very few material voids or defects. Due to the few voids / defects for trapping particles, the conductive filaments formed in such a RSL are very thin and unstable without a suitably high external stimulus (e.g., an electric field, voltage, current, Joule heat, or a suitable combination thereof). Additionally, particles with a high surface energy and good diffusivity within the RSL can be selected. This results in conductive filaments that can form quickly in response to a suitable stimulus but are also easily deformed, e.g., in response to an external stimulus reduced below the deformation magnitude. Note that the volatile RSL and conductive filaments for a selector device can have different electrical characteristics from the conductive filaments and non-volatile RSL for a non-volatile memory device. For example, the selector device RSL can have a higher material resistance and can have a higher on / off current ratio, etc.

[0027] The active metal layer for a filament-based memory cell can include: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of the present disclosure, other suitable conductive materials and compounds, nitrides, oxides, alloys, or combinations of the foregoing or similar materials can be used for the active metal layer. Additionally, in at least one embodiment, the active metal layer can employ non-stoichiometric compounds, such as non-stoichiometric metal oxides or metal nitrides (e.g., AlO x , AlN x , CuO x , CuN x , AgO x , AgN x etc., where x is a suitable positive number 0 < x < 2 and can have different values for different non-stoichiometric compounds) or other suitable metal compounds.

[0028] In one or more embodiments, the disclosed filament resistive switching device can include an active metal layer that includes a material selected from the group consisting of TiN xTaN x AlN x CuN x WN x and AgN x The group consists of metal nitrides, where x is a positive number. In a further embodiment, the active metal layer may include TiO2 selected from TiO2. x TaO x AlO x CuO x WO x and AgO x The metal oxides comprising the group. In one or more embodiments, the active metal layer may include TiO2. a N b AlO a N b CuO a N b WO a N b and AgO a N b The group consists of metal oxynitrides, where a and b are positive numbers. The disclosed filament resistance switching device may further include a switching layer comprising a switching material selected from the group consisting of: SiO₂ y AlN y TiO y TaO y AlO y CuO y TiN x TiN y TaN x TaN y SiO x SiN y AlN x CuN x CuN y AgN x AgN y TiO x TaO x AlO x CuO x AgO x and AgO y , where x and y are positive numbers, and y is greater than x. Various combinations of the above are contemplated and considered within the scope of embodiments of the present invention.

[0029] In one example, the disclosed filament resistance switching device includes a particle donor layer comprising a metal compound (e.g., an active metal layer) and a resistance switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MN x For example, AgN x TiN x AlN x The resistive switching layer includes a metal nitride: MN y For example, AgO y TiO y AlO y And so on, where y and x are positive numbers, and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises a metal oxide: MO x For example, AgO x TiO x AlO x The resistance switching layer includes metal oxides: MO y For example, AgO y TiO y AlO y And so on, where y and x are positive numbers, and in some cases y is greater than x. In yet another alternative embodiment, the metal compound of the particle donor layer is MN. x (e.g. AgN) x TiN x AlN x (etc.), and the resistance switching layer is freely selectable by MO. y (For example, AgO) y TiO y AlO y (etc.) and SiO y The group consists of x and y, which are typically non-stoichiometric values, or in another embodiment, the opposite.

[0030] As used herein, variables x, a, b, etc., representing the value or ratio of one element relative to another (or other) element in a compound may have different values ​​applicable to each compound and are not intended to represent the same or similar values ​​or ratios between compounds. Some details relating to embodiments of this disclosure, similar to the examples above, can be found in the following U.S. patent applications licensed to the holder of this patent application: U.S. Patent Application No. 11 / 875,541, filed October 19, 2007, and U.S. Patent Application No. 12 / 575,921, filed October 8, 2009, and U.S. Patent Application No. 14 / 588,185, assigned to the holder of this patent application, filed December 31, 2014. Each of the foregoing patent applications is incorporated herein by reference, in its entirety and for all purposes.

[0031] It should be understood that the embodiments herein can utilize various memory cell technologies with different physical characteristics. For example, different resistor-switched memory cell technologies can have different discrete programmable resistors, different associated programming / erasing voltages, and other differentiated characteristics. For example, embodiments of this disclosure can employ bipolar switching devices that exhibit a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erase state) to an electrical signal of a second polarity. Bipolar switching devices, for example, contrast with unipolar devices, which exhibit both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity but different amplitudes.

[0032] In various embodiments, the filament-based resistance switching device can operate in a bipolar manner, exhibiting different behaviors in response to external stimuli of different polarities (or directions, energy flows, energy source orientations, etc.). As an illustrative example, for a volatile filament-based selector device, in response to a first polarity stimulus exceeding a first threshold voltage (or voltage group), the filament selector device can change from a first resistive state to a second resistive state. Furthermore, in response to a second polarity stimulus exceeding a second threshold voltage, the filament selector device can change from the first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurable intrinsic characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus amplitudes (although opposite in polarity or direction), etc. In other embodiments, the third state can differ from the second state in terms of measurable characteristics (e.g., conductivity values ​​in response to reverse polarity compared to positive polarity) or in terms of the threshold stimulus associated with switching out of the first state (e.g., the amplitude of the positive voltage required to switch to the second state compared to the amplitude of the negative voltage required to switch to the third state).

[0033] For bipolar operation of a non-volatile filament-based memory cell, a conductive path or filament is formed through the non-volatile RSL in response to a suitable programming voltage applied to the memory cell. Specifically, upon application of the programming voltage, metal ions are generated from the active metal layer and migrate into the non-volatile RSL layer. The metal ions can occupy voids or defect sites within the non-volatile RSL layer. In some embodiments, after the bias voltage is removed, the metal ions become neutral metal particles and remain trapped in the voids or defects of the non-volatile RSL layer. When a sufficient number of particles are trapped, a filament is formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance through the non-volatile RSL layer. In some resistance-switching devices, an erase process can be implemented to at least partially deform the conductive filament, thereby returning the memory cell from a low-resistance state to a high-resistance state. More specifically, when an erase bias voltage is applied, metal particles trapped in the gaps or defects of the non-volatile RSL become mobile ions and migrate back towards the active metal layer. In the context of memory, this state change can be associated with the individual states of binary bits. For an array of multiple memory cells, words, bytes, pages, blocks, etc., of the memory cells can be programmed or erased to represent zeros or ones of binary information, and the binary information is stored by actually retaining these states for a period of time. In various embodiments, multi-level information (e.g., multiple bits) can be stored in such memory cells.

[0034] It will be understood by those skilled in the art, or through the background provided herein, that when no specific memory cell technology or programming / erasing voltage is specified in the various aspects and embodiments herein, it is intended that these aspects and embodiments be incorporated into any suitable memory cell technology and operated by a programming / erasing voltage suitable for that memory cell technology. It should be further understood that embodiments including alternative memory cell technologies or signal level variations are considered within the scope of this disclosure when circuit modifications known to those skilled in the art or changes in operating signal levels known to those skilled in the art are required to replace different memory cell technologies.

[0035] As described above, applying a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a dual-terminal memory causes the formation of a conductive filament in the interface layer (e.g., RSL). Conventionally and as generally described herein, the TE receives the programming pulse and the BE is grounded (or maintained at a lower voltage or opposite polarity compared to the programming pulse), but this is not intended to limit all embodiments. Conversely, applying an "erase pulse" (typically a pulse with the opposite polarity to the programming pulse or a pulse applied to the opposite electrode) to one of the electrodes, for example by driving the metal particles or other material forming the filament back to the active metal source, disrupts the continuity of the filament. The characteristics of this conductive filament and its presence or absence affect the electrical characteristics of the dual-terminal memory cell; for example, the presence of a conductive filament reduces resistance and / or increases conductance between the terminals, while its absence has the opposite effect.

[0036] After a programming or erasing pulse, a read pulse can be determined. The amplitude of this read pulse is typically lower than that of the programming or erasing pulse and is generally insufficient to affect the conductive filament and / or change the state of the dual-ended memory cell. By applying a read pulse to one of the electrodes of the dual-ended memory, the current (e.g., Ion) measured compared to a predetermined threshold current can indicate the conductive state of the dual-ended memory cell. The threshold current can be preset based on the expected current value of the dual-ended memory device in different states (e.g., high-resistance state current; corresponding currents for one or more low-resistance states, etc.), applicable to a given dual-ended memory technology. For example, when a conductive filament has been formed (e.g., in response to the application of a programming pulse), the cell's conductance is greater than in other cases, and the current (e.g., Ion) reading measured in response to the read pulse will be larger. On the other hand, when the conductive filament is removed (e.g., in response to the application of an erasing pulse), the cell's resistance is higher due to the relatively high resistance of the interface layer, therefore the cell's conductance is lower, and the current (e.g., Ioff) reading measured in response to the read pulse will be lower. Conventionally, when a conductive filament is formed, a memory cell is referred to as being in a "conducting state" with high conductivity. When the conductive filament is absent, the memory cell is referred to as being in a "turn-off state." Memory cells in the conducting or turning-off states can be logically mapped to binary values, such as "1" and "0". It should be understood that the conventions associated with the states of cells or the associated logical binary mappings used herein are not intended to be limiting, and other conventions, including the opposite conventions, can be adopted in conjunction with this disclosure. The techniques detailed herein are described and illustrated in conjunction with single-level cell (SLC) memory, but it should be understood that the disclosed techniques can also be used in multi-level cell (MLC) memory, in which a single memory cell can hold a set of measurable different states representing multi-bit information.

[0037] Digital information can be stored in such devices by mapping it to the non-volatile resistive states of dual-ended memory cells. Electronic devices containing many such dual-ended memory cells can also store large amounts of data. High-density arrays are configured to contain as many memory cells as possible for a given chip space area, thereby maximizing the data storage capacity of the memory chip or system-on-a-chip device.

[0038] For dual-ended memories (e.g., crossover arrays) formed at the intersections of metal lines within a wafer, the inventors of this disclosure recognize two general conventions for arranging memory cells. The first convention is a 1T1R memory array, where each memory cell is isolated from the electrical effects (e.g., current, including leakage path current) of surrounding circuitry by an associated transistor. The second convention is a 1TnR memory array (where n is a positive number greater than 1), where a group of multiple memory cells is isolated from the electrical effects of surrounding circuitry by one (or more) transistors. In a 1T1R environment, individual memory cells can be configured to have high current suppression between memory cells, significantly reducing leakage path current in the 1T1R memory array.

[0039] An example mechanism for connecting a 1T1R memory array is provided. The first terminal of the two-terminal resistive memory device can be connected to the drain of a transistor. The second terminal of the two-terminal resistive memory device can be connected to the bit line of the 1T1R memory array. Depending on the erase / programming conditions of the memory array, the source of the transistor is grounded or used as the source of the erase or programmable signal.

[0040] Examples of improved memory architectures for programming or erasing dual-ended storage devices

[0041] Some embodiments of this disclosure include increasing read or erase bandwidth by performing asynchronous programming or erase operations on multiple double-ended (e.g., resistive random access) memory devices (ReRAM devices). In some embodiments, programming or erase operations are applied substantially simultaneously to ReRAM devices from a set of ReRAM devices; however, the inventors have recognized that in some cases these operations can actually be completed at different times. In one example, an erase operation is driven simultaneously by a single charge pump to multiple (e.g., 16) ReRAM devices, but some (e.g., 2) ReRAM devices can be programmed faster than the rest. Therefore, embodiments of this disclosure are provided to initiate programming or erase operations on other (e.g., another 2) ReRAM devices in another set of such devices, rather than waiting for the programming or erase operations on the remaining (e.g., 14) ReRAM devices to complete. As an example above, for the first ReRAM device and the second ReRAM device, the erase operation begins at approximately the same time (e.g., simultaneously, within a common clock cycle, within adjacent clock cycles, etc.); the erase operation for the first ReRAM device is completed; then, before the erase operation for the second ReRAM device is completed, the erase operation for the third ReRAM device begins; next, before the erase operation for the third ReRAM device is completed, the erase operation for the second ReRAM device is completed; subsequently, before the erase operation for the third ReRAM device is completed, the erase operation for the fourth ReRAM device begins; and so on. As can be seen from the above, because the programming or erasing operations for the ReRAM devices are completed at different times, the embodiment can begin performing additional programming or erasing operations without waiting for the slower programming or erasing operations to complete.

[0042] In other embodiments of this disclosure, erasure or programming operations can be performed on multiple ReRAM devices by reducing the verification cycle after erase or programming detection. More specifically, in the initial embodiments of this disclosure, during a normal erase cycle, the current amount is detected, and an erase flag is set when the current drops below a programmed or predetermined low level (e.g., 0.5 microamps (µA), 0.3µA, or 0.1µA, or any other suitable level for a high-resistance state suitable for a given dual-ended memory technology). If the erase flag is not detected, another erase pulse is provided (or, in some embodiments, the erase pulse is held or continued) while the current is monitored; if the erase flag is set, the ReRAM device is considered to have been erased, and the erase pulse terminates. In some embodiments, after the erase flag is detected, a verification process (read operation) is performed to verify that the ReRAM device has been erased, and if the verification process is successful, the ReRAM device is considered to have been erased (e.g., verified as erased).

[0043] In various embodiments related to programming ReRAM devices, during a normal programming cycle, the current magnitude is detected, and a programming flag is set when the current exceeds a programmed or predetermined high level (e.g., 1.0µA, 1.3µA, or 1.5µA, or any other suitable level for a low-resistance state (or one of a set of low-resistance states) applicable to a given dual-ended memory technology). If no programming current magnitude is detected, another programming pulse is provided (or the programming cycle is held or continued) while the current is monitored; if the programming flag is set, the ReRAM device is considered to have been programmed, and the programming pulse terminates. In some embodiments, after the programming flag is detected, a verification process (read operation) is performed to verify that the ReRAM device has been programmed, and if the verification process is successful, the ReRAM device is considered to have been programmed (e.g., verified as programmed).

[0044] In various embodiments, the verification process is considered to take a relatively long time (e.g., 1µs to 5µs), and in some cases, up to half the duration of an erase pulse (e.g., 2µs to 10µs) or a programming pulse (e.g., 2µs to 10µs). Therefore, some embodiments of this disclosure provide the aforementioned verification process to significantly reduce the time of the erase or programming process. This is particularly important when programming or erasing operations are performed on multiple ReRAM devices at once. In various embodiments, after an erase flag or programming flag is detected, the erase or programming pulse is terminated (e.g., the erase or programming is not verified by a read step), and then the ReRAM device is considered to have been erased or programmed.

[0045] Other embodiments of this disclosure include the ability to detect when a ReRAM device has been erased. As described above, in various embodiments, a verification operation (e.g., a read operation, a read voltage) is applied to the ReRAM device to detect whether it has been erased. If erased correctly, in various embodiments, the typical erase state current flowing through the ReRAM device is on the order of 50 nA to 200 nA. In some embodiments, reliable sensing of this small current can be achieved at least to some extent by separating it from background noise. The sensing time after the ReRAM device has actually been erased is relatively long because background noise from other parts of the chip often causes interference. In other words, noise forces the erase cycle to be longer than originally required.

[0046] In various embodiments, to reduce the impact of noise and the amount of time required for the erase cycle, this disclosure is provided to bias the current flowing through the ReRAM with a bias current (e.g., background current) and then compare the combined bias current with a threshold current. More specifically, in some embodiments, the current (e.g., about 50 nA for erasing cells to about 200 nA for programming cells) is biased (e.g., 1 uA to 3 uA) with a bias current (e.g., 1 uA), and the combined bias current (e.g., about 1.05 uA for erasing cells to about 1.20 uA for programming cells) is sensed and compared with a threshold current (e.g., about 1.12 uA). In this example, if the combined bias current is less than about 1.12 µA (e.g., about 1.05 µA for erasing a cell), the cell is considered to have been erased; and if the combined bias current is greater than 1.12 µA (e.g., about 1.20 µA for programming a cell), the cell is considered to have been programmed. With this embodiment, it is believed that it is possible to determine when a ReRAM device is erased more quickly than before. In other embodiments, other bias currents, threshold currents, etc., may also be used.

[0047] Embodiments of this disclosure may include using one, two, or all three of the above-described techniques, as well as other techniques, to erase and program multiple ReRAM devices.

[0048] Now refer to the attached diagram, Figure 1 A diagram illustrates an example array 100 for implementing one or more embodiments of the present disclosure of a dual-ended memory device. In an embodiment, array 100 may represent a single dual-ended memory block, wherein the dual-ended memory block is defined as having a first set of bit lines 102 intersecting a second set of word lines 104 and source lines 106, and memory cells 120 are located at the (illustrated) intersections of the bit lines 102 and source lines 106. The number of bit lines 102 in a block can be conventionally set, and the absolute minimum is not less than one bit line, but in practice each block will have multiple bit lines 102 (e.g., 8 bit lines, 32 bit lines, 128 bit lines, 256 bit lines, or any suitable number therein, or more). Rather, a block is merely a convenient descriptor for the default number of bit lines 102, word lines 104, and source lines 106, which may vary in their respective numbers according to one or more embodiments disclosed herein. For illustrative purposes, array 100 includes X bit lines (where X is a suitable integer greater than 1), wherein bit lines 102 are collectively referred to as bit lines BL0, BL1, BL2, BL3, BL4, BL5, ... BL X .

[0049] The double-ended storage cells 120 included in array 100 are arranged in row 110 connected to common word line 104 and source line 106. For example, row 110 is connected to WL0 and SL0, while another row (e.g., the Nth row, where N is a suitable integer greater than 1) is connected to WL0. N and SL N As shown in the figure.

[0050] Each dual-ended memory cell 120 includes a resistor switching device (represented by a resistor symbol) electrically connected in series with a transistor device (represented by a transistor symbol). The top electrode 122 of the memory cell 120 is connected to one of the bit lines 102 (e.g., BL). X The memory cell 120 shares a node with one of the source lines (e.g., WL0) in the source line 106. Furthermore, the first terminal of the resistor switching device is connected to the junction of TE 122 and BL. X The common node, while the second terminal of the resistor switching device is connected to the drain (or source, depending on convention) of the transistor device.

[0051] To apply a programming signal to memory cell 120 in a given row 110, an activation signal (e.g., a high voltage, such as 2.5 volts, or any other suitable voltage for activating a transistor device selected for the chosen transistor technology in memory cell 120) is applied to WL0. The transistor device with its gate node electrically connected to WL0 is activated, causing current to flow between the source and drain nodes of the transistor. Once the associated transistor device is activated, the second terminal of the resistor-switching device of memory cell 120 is electrically connected to SL0. This is achieved through BL... X By applying an operating voltage (or current, electric field, or other suitable excitation) to SL0, a corresponding storage operation can be performed on storage cell 120. Examples of operations include read, write, and erase operations, each with a suitable voltage or voltage range, pulse duration, peak current value, etc., to implement these storage operations. For some resistive random access memory devices, suitable voltage ranges for read, write, and erase operations may be, for example, 0.5V to 1.5V, 2V to 3V, and -2V to -3V, respectively, but those skilled in the art will understand that such voltage / ranges will vary depending on the two-terminal technology selected for storage cell 120.

[0052] In this embodiment, a high voltage is connected to BL when WL0 is activated. X Connecting a low voltage (e.g., zero volts, ground, or other suitable low voltage) to SL0 will program memory cell 120 into a low-resistance state. Conversely, connecting a low voltage (e.g., zero volts, ground, etc.) to BL when WL0 is activated... XConnecting a high voltage to SL0 will erase memory cell 120 to a high-resistance state. A medium read voltage (e.g., small enough not to program or erase memory cell 120) can be connected to BL. X To perform a read operation, connect the low voltage to SL0 and the activation voltage to WL0.

[0053] In some embodiments, the source driver may be used to provide a suitable storage operation voltage or current with a suitable pulse duration to achieve these storage operations (e.g., see below). Figure 2 and Figure 3 as well as Figure 6 Source drivers can utilize technologies known in the art or those skilled in the art, as provided in this document (e.g., see below). Figure 6 Any suitable known multiplexer is connected to each bit line of array 100. In some embodiments, sensing circuitry may be connected to the bit lines during memory operations. In the case of programming or erasing operations, the sensing circuitry may be configured to respond to detection via BL X The erase flag is set by a decrease in current and an erase operation applied to the memory cell 120, or in response to the detection of a BL signal. X The programming flag is set by the increase in current and the programming operation applied to the memory cell 120. In an embodiment, a single bit may represent both the erase flag and the programming flag, and if the bit is set (or reset, depending on convention) to be the erase bit, it is reset (or set, depending on convention) to be the programming bit. In other embodiments, separate bits may be provided for the erase flag and the programming flag.

[0054] In a further embodiment, the source driver may repeat the storage operation if the programming or erase bit is not set by the sensing circuit during a predetermined pulse time for the storage operation. As an illustrative example, if an erase operation is initiated and the sensing circuit does not set the erase flag before the predetermined pulse time ends, the source driver may repeat the erase operation on a given memory cell. As an alternative embodiment, the source driver may not have a predetermined pulse time and may be configured to maintain the erase operation until the sensing circuit sets the erase flag, and in response to this (e.g., in a subsequent clock cycle, or after receiving an erase flag setting signal, etc.), the source driver may terminate the erase operation. In yet another embodiment, the foregoing combination may be programmed into the source driver. For example, the source driver may perform an erase operation within a predetermined pulse time and terminate the erase operation in response to the setting of the erase flag (in one embodiment, before the end of the pulse time). Subsequent pulse-time erase operations may be performed until the erase flag is set.

[0055] In alternative or other embodiments of this disclosure, the source driver may be configured to verify a programming or erasing flag. When the programming or erasing flag is set, the source driver terminates the programming or erasing operation (if applicable). A read operation can then be initiated, and as described herein, a BL connected to memory cell 120 can be read. X The current is compared to the appropriate current magnitude used for programming or erasing operations. As an illustrative example, if BL is measured... X If the current on the memory cell is greater than approximately 1.0 μA (or another value applicable to a given two-ended technology, or greater than one of a set of values ​​for an MLC two-ended memory cell), then memory cell 120 is determined to be in a programmed state and the programming flag is verified. As another example, if the current measured ... X If the current on the memory cell 120 is less than about 0.5 μA (or another suitable value given the two-terminal technique), the memory cell 120 is determined to be in an erase state and the erase flag is verified. In at least some embodiments, in response to the setting of the programming flag or the erase flag, the source driver may abandon the verification of programming or erasure and continue reading subsequent bit lines (and memory cells).

[0056] Now for reference Figure 2 A block diagram of a storage device 200 that can operate by combining one or more of the disclosed embodiments is shown. The storage device 200 includes multiple blocks of dual-ended storage cells, including BLOCK1 202A, BLOCK2 202B, and BLOCK... Z 202C (collectively referred to as memory blocks 202A-202C). Memory blocks 202A-202C each include X bit lines. It should be understood that each block does not need to have the same number of X bit lines, and one or more blocks can have bit lines with different integers (e.g., Y, where Y is a suitable number of greater than zero). As shown in the figure, memory BLOCK1 202A includes the first group of X bit lines: BL1<0:X>208A. Similarly, BLOCK2 202B includes the second group of X bit lines: BL2<0:X>208B, and so on up to BLOCK... Z 202C includes the X bit lines in the Z group: BLZ<0:X>208C (collectively referred to as bit lines 208A-208C).

[0057] Each row of a storage cell is connected by an associated word line WL0, ... WL N Activation. Once activated, voltage or current can be applied to the memory cells of a given memory block 202A-202C. The memory device 200 includes source drivers: DRIVER1 240A, DRIVER2 240B, ... DRIVER ZSource drivers 240C (collectively referred to as source drivers 240A-240C) are used to apply signals to the bit lines of bit lines 208A-208C. Source drivers 240A-240C are connected to individual bit lines 208A via multiplexer 230. In one embodiment, multiplexer 230 is configured to connect only each source driver 240A-240C to the bit lines of the associated memory blocks 202A-202C. However, in some embodiments, multiplexer 230 may be configured to connect source drivers 240A (or 240B, or 240C) to any one of memory blocks 202A-202C.

[0058] A charge pump 250 is provided to power the source drivers 240A-240C. Furthermore, the charge pump 250 can provide power to selected word line / source line pairs via a decoder 220. The charge pump 250 applies a high signal 2200 to the selected word line (e.g., WL0) via the decoder 220, thereby activating the memory cell connected to the associated source line (e.g., SL0). Low signal 220 N Applied to unselected word lines (e.g., WL) N This will deactivate the memory cell connected to the deactivate word line.

[0059] Storage operations are implemented by storage device 200 by activating a selected word line (e.g., WL0, etc.) and applying signals to the selected bit line and the source line associated with the selected bit line (e.g., SLO, etc.). In various embodiments, source drivers 240A-240C can initiate storage operations on multiple memory cells in respective memory blocks 202A-202C substantially simultaneously (e.g., simultaneously, within a common clock cycle, within adjacent clock cycles, or other suitable conventions). As defined herein, the multiple memory cells are implemented by memory cells in the same bit line order in different memory blocks 202A-202C. In other words, the zero-level bit line (including: BL1) of each memory block... <0> 210A, BL2 <0> 210B, ...BLZ <0> The memory cells on 210C (collectively referred to as level zero bit lines 210A-210C) are included in the first batch of memory cells. For example... Figure 2 As shown, the first batch of storage cells includes storage cells 212A, 212B, ... 212C (collectively referred to as multiple storage cells 212A-212C). The second batch of storage cells includes a first-level bit line (BL1) in each storage block 202A-202C. <1> BL2 <1> BLZ <1> The third batch of storage cells includes the second-level bit lines (BL1) in each storage block 202A-202C.<2> BL2 <2> BLZ <2> Those storage units on ) and so on.

[0060] To improve the erase time of memory blocks, source drivers 240A-240C can be configured to simultaneously initiate memory operations on the first batch of memory blocks 212A-212C, but can independently perform memory operations on subsequent memory blocks 202A-202C. In other words, a given source driver 240A starts a batch erase (or program) operation on memory blocks 202A-202C simultaneously with source drivers 240B and 240C, but can continue operating on subsequent bit lines of BLOCK1202A independently of the progress of source drivers 240B and 240C, and vice versa. This improves batch operation time because the delay of one source driver (e.g., 240B) erasing or programming a given memory block does not delay the progress of subsequent memory blocks on subsequent bit lines of other source drivers (e.g., 240A, 240C). Conversely, once a completion event is detected (e.g., setting a programming flag or an erase flag, optionally in conjunction with a read verification operation), the source driver (e.g., 240A) can utilize multiplexer 230 to connect to subsequent bit lines (e.g., from BL1). <0> To BL1 <1> In at least one embodiment, the source driver completes all bit lines (e.g., BL1) in a given memory block (e.g., BLOCK1 202A). <0:X> This source driver can be connected to different memory blocks (e.g., BLOCK2 202B, BLOCK...). Z The bit lines in 202C) are used to further reduce the total time of batch erase (or program) operations.

[0061] Now for reference Figure 3 This illustrates a storage device 300 configured to perform storage operations on storage units in different batches of storage units as provided herein. In one or more embodiments, the storage device 300 may be related to the above-described storage device 300. Figure 2 The storage device 200 is generally similar. Therefore, as shown, the storage device 300 may include source drivers 240A-240C, a multiplexer 230, memory blocks 202A-202C, and bit lines 208A-208C as described above, as well as those not in... Figure 3 Other components of the storage device 200 are specifically depicted in the text.

[0062] This illustrates a bulk storage operation of storage device 300, specifically, the different source drives 240A-240C at a time t0 after the start time t0. aOperations are performed on different batches of memory cells, where a is an integer greater than 0. An activation signal is provided to WL0, activating all transistors connected to WL0. An appropriate signal is applied to the source line SL0 to program (e.g., low signal) or erase (e.g., high signal) the memory cells connected to SL0. The source driver 1240A still operates on the memory cells in the zeroth group of bit lines, specifically those connected to BL1. <0> Memory cell 312A of 210 is being operated. Simultaneously, source driver 2240B has been operating on memory cells in the second set of bit lines, specifically those connected to BL2. <2> The storage cell 312B of 210B is operated, and the source driver 240C has been connected to the storage cell in the first group, specifically to BLZ. <1> The storage cell 312Z of 210C is operated. As shown in storage device 200, the long operation time of storage cell 312A will not delay the operation of source driver 2240B on BLOCK 2202B, nor will it delay the operation of source driver 202C on BLOCK 2202B. Z Operation of 202C. The source drivers 240A-240C are configured independently of other source drivers 240A-240C to continue to feed subsequent bit line groups (e.g., from BLZ). <0> To Blizzard <1> Operations on bit lines in memory cells (such as batch erase or batch program) can minimize the impact of longer operation times on a given memory cell, thereby improving the overall speed of such operations.

[0063] Figure 4 An example pulse timing diagram 400 of a memory block according to other embodiments of the present disclosure is shown. The pulse timing diagram 400 plots current on the vertical axis and time on the horizontal axis. Furthermore, Figure 4 The corresponding pulse timing diagrams for each of blocks 202A-202C are provided.

[0064] Each pulse has a time allotted for a successful programming or erasing operation on a given memory cell within the relevant memory block. For BLOCK1 202A, multiple pulse times are shown based on the time taken for the memory cell to complete the programming or erasing operation (e.g., determined by setting an erase flag or programming flag, optionally in conjunction with a read / verify operation). The first memory cell (indicated by the first pulse of BLOCK1 202A, starting from the left side of the figure) is programmed in the first pulse time t0 422. In one embodiment, the pulse time t0 422 may be a default or minimum pulse time. In other embodiments, a default pulse time (e.g., 20 nanoseconds, or other suitable values ​​associated with the average, average, typical, etc., programming or erasing time of a given type of dual-ended memory technology employed by the memory cell) may be provided, which may be shortened upon detection of a programming or erasing event. In other words, in later embodiments, the initial time may be a default time, but there is no minimum pulse time.

[0065] If the storage operation is not completed on a given memory cell by the end of the pulse time, an additional pulse can be applied until the sensing circuit detects that the memory cell has completed the storage operation. In an alternative embodiment, the initial pulse time can be maintained until the storage operation is detected to be complete. The second memory cell of BLOCK1 (starting from the left side of the figure) requires a t2 pulse time of 424, which is longer than the t0 422 pulse time, to complete the storage operation. Other memory cells involve a t1 426 pulse time to complete the storage operation, where t2 > t1 > t0. In contrast, the pulse times of BLOCK2 202B are all the default t0 pulse time of 422, while BLOCK... Z The 202C has several t1 426 pulse times, but no t2 424 pulse times.

[0066] Because source drivers 240A-240C are configured to continue operating on subsequent bit lines (and memory cells) independently of other source drivers 240A-240C, each memory block 202A-240C can complete a different number of memory cells in a given time T1 450. For BLOCK1 202A, the fourteenth memory cell 412A (counting the number of completion pulses) is completed at time T1 250, while for BLOCK2 202B, the seventeenth memory cell 412B has been completed. And for BLOCK... Z 202C, the fifteenth storage unit 412Z was completed before time T1 250.

[0067] According to one or more embodiments, source drivers 240A-240C can be connected to different blocks when operations on all memory cells of a given block are completed. In some embodiments, source driver 240B can operate on memory block 202A that another source driver 240A is currently operating on, to complete memory block 202A more quickly. In other embodiments, source driver 240B can point to a memory block (not depicted) that is not currently assigned a source driver.

[0068] Figure 5 An example timing diagram 500 for storage operations on multiple storage devices is depicted in the disclosed embodiments. According to further embodiments of this disclosure, timing diagram 500 helps reduce the programming / erasing operation time for multiple storage devices. For example, where a precharge time 504 (an amplification signal, e.g., before a set of storage operations begins) and a rampdown time 508 (a decrementation signal, e.g., after a set of storage operations) have durations comparable to a state change time 506, applying a state change signal to multiple storage devices within state change time 506 can significantly reduce the programming / erasing duration for multiple storage devices.

[0069] As an illustrative example, consider a 1.6µs precharge time 504, a 1.6µs state transition time 506, and a 1.6µs ramp time 508. Given all these times, initiating and completing a memory operation on a single memory cell requires 3 × 1.6µs or 4.8µs. However, some dual-ended memory technologies can program or erase within a fraction of this time (e.g., an erase time of approximately 20ns, as an example of some resistive random access memories). However, for the fixed times 504, 506, 508, the operating speed of dual-ended memory is not achieved through the manipulation of circuitry. However, for batch operations involving programming or erasing multiple memory cells during state transition time 506, the average operating time per cell can be significantly reduced. During state transition time 506, an operation signal is applied to the first line / top electrode (BL / TE1) 520, then to the second BL / TE2 522, the third BL / TE3 524, and so on up to the Zth BL / TE. Z 526, as shown in the figure. For example, if the average operation time is 20 ns, the number of cells that can be completed is equal to 1.6 μs (1600 ns) / 20 ns, or 80 memory cells. Completing 80 memory cells in the same 4.6 μs significantly reduces the operation time per cell from 4.6 μs per cell to 57.5 ns per cell.

[0070] exist Figure 5In this embodiment, the pulse time is modular, having a default time t0 422 and multiples of the default time (e.g., twice), such as t1 426. Other embodiments within the scope of this disclosure will not have modular time, for example, when the pulse period is terminated in response to the detection of a memory operation (e.g., in the next clock cycle, such as 10ns for a 100MHz clock, 2ns for a 500MHz clock, or at a high-speed clock or faster). A new memory cell can be targeted after the pulse time terminates (e.g., in a subsequent suitable clock cycle).

[0071] Figure 6 An example schematic diagram of a multiplexer 600 according to one or more other embodiments of the present disclosure is shown. The multiplexer 600 can be configured to selectively connect source drivers (e.g., source drivers 240A-240C) to bit lines of a memory block. The multiplexer 600 depicts a first set of bit lines BL of a single memory block. <0> 602, BL <1> 604, BL <2> 606、...BL <z>< / z> 608, collectively referred to as bit lines 602-608. However, it should be understood that multiplexers can also incorporate bit lines from multiple memory blocks (e.g., bit lines BL2<0:X>208B, BLZ<0:X>208C, and other bit lines not described herein).

[0072] A driver switch 610 is provided to connect a source driver to the bit lines 602-608. In some embodiments, multiple source drivers may be connected to any bit lines 602-608 (e.g., via a driver multiplexer (not depicted)). However, in other embodiments, each source driver may be connected to the bit lines of only a single memory block.

[0073] In various embodiments, a sensing circuit 618 is provided for sensing the current on one or more bit lines 602-608 to determine when a storage operation is completed. For example, the sensing circuit 618 may compare the current flowing in the bit line to a current threshold and identify current changes that exceed the current threshold. For a programming operation, the sensing circuit 618 may detect that the current flowing through the bit line has increased above the current threshold and set a programming flag to notify the associated source driver of the detected programming event. For an erase operation, the sensing circuit 618 may detect that the current flowing through the bit line has decreased below the current threshold and set an erase flag to notify the associated source driver of the detected erase event. The sensing circuit 618 may be connected to the selected bit line via a sensing contact 614.

[0074] In alternative or other embodiments, multiplexer 600 may include a bias signal to provide bias to the current detected by sensing circuitry 618. Bias signal 616 may be configured to have an amplitude suitable for reducing the impact of noise on sensing circuitry 618 when current is detected in bit lines 602-608. In this case, sensing circuitry 618 compares the current to a threshold current that includes a constant bias current. As an illustrative example, the current may be biased from about 1 microamp (µA) to about 3 µA, or any other suitable value. In this example, using a 1 µA bias current, a constant 1 µA is added to the threshold current used by sensing circuitry 618. With an average / moderate / typical current flowing through cell erasure of about 50 nA and an average / moderate / typical current flowing through cell programming of about 200 nA, the baseline current threshold that can measurably distinguish cell erasure from cell programming may be, for example, 120 nA. When a 1µA bias current is added, the sensing circuit 618 will detect currents on bit lines 602-608 that are higher or lower than 1.12µA to distinguish between erasing and programming of the cell. This bias current helps to mitigate the effects of low-signal noise in electronic devices and improves the accuracy of the sensing circuit 618.

[0075] The diagrams included herein are described in relation to interactions between several memory cells, memory cell components, memory arrays, or memory architectures. It should be understood that such diagrams may include those memory cells, components, arrays, and architectures specified therein, a portion of a specified memory cell / component / array / architecture, or suitable alternatives or additional memory cells / components / arrays / architectures. Sub-components may also be implemented as electrically connected to other sub-components, rather than being contained within a parent architecture. Similarly, according to other embodiments, individual components may be implemented in a combined architecture. For example, in one embodiment, source drivers 240A-240C may be implemented as a sub-component of a single voltage / current driver. Furthermore, some disclosed embodiments may be implemented as part of other disclosed embodiments where appropriate.

[0076] Furthermore, one or more disclosed processes can be combined into a single process that provides aggregate functionality. For example, a programming or erasing process may include a read / verify process, and vice versa, to program / erase a semiconductor cell and verify the completion of the programming / erase via a single process. Additionally, it should be understood that individual rows of a multi-cell memory architecture can be erased in groups (e.g., multiple rows erased simultaneously) or individually. Furthermore, it should be understood that multiple memory cells on a particular row can be read or programmed in groups (e.g., multiple memory cells read / programmed simultaneously) or individually. Components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art or becoming apparent from the context provided herein.

[0077] Based on the example diagrams described in this article, please refer to... Figure 7 and Figure 8 The flowchart will help you better understand the processing method that can be implemented according to this disclosure. Although for ease of illustration, Figure 7 and Figure 8 The methods are illustrated and described as a series of boxes, but it should be understood and interpreted that the claimed technical solutions are not limited by the order of the boxes, as some boxes may appear in a different order or simultaneously with other boxes depicted and described herein. Furthermore, implementing the methods described herein may not require all the illustrated boxes, and in some embodiments, additional method steps not described but known to those skilled in the art or known from the context provided herein may be incorporated into the described methods. Moreover, it should be further understood that the methods disclosed in this specification can be stored on an article of writing to facilitate the transfer and assignment of such methods to electronic devices. As used, the term article of writing is intended to cover a computer program accessible from any computer-readable device, a device coupled with a carrier, or a storage medium.

[0078] Now for reference Figure 7 This document describes a flowchart of an example method 700 for performing erase or program operations on dual-end memory devices according to further embodiments of the present disclosure. Method 700 may include, at 702, initiating erase or program cycles for a first batch of dual-end memory devices substantially simultaneously. In embodiments, the first batch of dual-end memory devices may include memory cells on corresponding zero-bit lines in different blocks of the dual-end memory devices. Method 700 may include, at 704, monitoring erase detection or program detection conditions for each dual-end memory device in the first batch. Furthermore, method 700 may include, at 706, detecting erase detection or program detection conditions for a first dual-end memory device of the first batch of dual-end memory devices before detecting erase detection or program detection conditions for all dual-end memory devices of the first batch. Furthermore, method 700 may include, at 708, initiating erase or program cycles for a second batch of dual-end memory devices of a second batch before detecting erase detection or program detection conditions for all dual-end memory devices of the first batch. A subsequent erase or program cycle may be in response to the detection of an erase or program detection condition for the first dual-ended memory device. As described herein, a second batch of dual-ended memory devices may include memory devices on corresponding first-level bit lines of different blocks of the dual-ended memory devices.

[0079] In a further embodiment, before detecting erase detection or programming detection conditions for all dual-end memory devices, method 700 may further include detecting erase detection or programming detection conditions for a third dual-end memory device in the first batch of dual-end memory devices. Additionally, method 700 may include initiating an erase cycle or programming cycle for a fourth dual-end memory device in response to detecting an erase detection or programming detection condition for the third dual-end memory.

[0080] In a further embodiment, detecting the erase detection or programming detection condition of the first dual-end storage device in the first batch of dual-end storage devices may include performing a verification cycle on the first dual-end storage device to determine a success condition or to determine that a success condition is lacking. Furthermore, in other embodiments, in response to detecting the erase detection or programming detection condition of the first dual-end storage device and determining a success condition, initiating an erase cycle or programming cycle for the second batch of dual-end storage devices.

[0081] In alternatives or other embodiments of method 700, the erase cycle or programming cycle of the second batch of dual-ended storage devices is substantially not the same as the verification cycle of the first batch of dual-ended storage devices. According to such an embodiment, the verification cycle can be selected from the group consisting of erase verification cycles and programming verification cycles.

[0082] In a further embodiment, detecting an erase detection or programming detection condition for the first dual-ended memory device includes receiving a current associated with the first dual-ended memory device. In a later embodiment, method 700 may further include biasing a current by a current offset to form a bias current and comparing the bias current with a current threshold to detect an erase detection or programming detection condition. Furthermore, detecting an erase detection or programming detection condition in response to a sensed current may include detecting an erase detection condition when the sensed current is less than a current threshold. Alternatively, detecting an erase detection or programming detection condition in response to a sensed current may include detecting a programming detection condition when the sensed current is greater than a current threshold.

[0083] In yet another embodiment, the dual-ended memory device includes a resistive random access (ReRAM) device. In such an embodiment, monitoring the erase detection or programming detection conditions of each dual-ended memory device may include monitoring the erase detection or programming detection conditions of each ReRAM device.

[0084] In another embodiment, the dual-ended memory device is selected from the group consisting of phase-change memory, metal-oxide memory, silicon suboxide memory, chalcogenide memory, magnetic memory, carbon nanotube memory, and filament-based memory. In other embodiments, after detecting an erase detection or programming detection condition for the last dual-ended memory device of the first batch of dual-ended memory devices, method 700 may include initiating an erase cycle or programming cycle for a third dual-ended memory device of the second batch of dual-ended memory devices in response to detecting the erase detection or programming detection condition for the last dual-ended memory device of the first batch of dual-ended memory devices. In at least one disclosed embodiment, the number of dual-ended memory devices in the first batch of dual-ended memory devices is in the range of 8 to 32.

[0085] Figure 8 A flowchart is depicted for an example method 800 for implementing additional aspects of this disclosure. Method 800 may include, at 802, initiating a state change operation of a memory cell in a first set of bit lines connected to a corresponding memory block of a dual-ended memory. Method 800 may include, at step 804, initiating state change detection of the memory cells on the first set of bit lines. Furthermore, method 800 may include, at 806, detecting a state change of a memory cell in the first memory cell block, and method 800 may include, at 808, connecting power to a bit line of a second set of bit lines belonging to the corresponding memory block. Method 800 may include, at 810, detecting state changes of other memory cells in memory blocks associated with other memory cells. Method 800 may include, at 812, connecting power to a subsequent bit line in a subsequent set of bit lines within the associated memory block. At 814, determining whether all memory devices in the memory block have successfully changed state. If yes, method 800 may end at 816. Otherwise, method 800 returns to 810.

[0086] Example of operating environment

[0087] To provide background for the various aspects of this disclosure, Figure 9The following discussion is intended to provide a brief overview of suitable environments in which the various aspects of this disclosure can be implemented or processed. Although the technical solutions have been described above in the general context of semiconductor architecture and process methods for operating arrays of dual-ended memory devices, those skilled in the art will recognize that this disclosure can also be implemented in combination with other architectures or process methods. Furthermore, those skilled in the art will understand that the disclosed processes can be practiced alone or in conjunction with a host processing system or computer processor, which may include single-processor or multi-processor computer systems, small computing devices, mainframe computers and personal computers, handheld computing devices (e.g., PDAs, telephones, watches), microprocessor-based or programmable consumer or industrial electronics, etc. The aspects shown can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the claimed innovations can be implemented on separate electronic devices, such as memory cards, flash memory modules, removable storage devices (e.g., CF cards, USB memory sticks, SD cards, micro SD cards), etc. In a distributed computing environment, program modules can reside in local and remote memory storage modules or devices.

[0088] Figure 9 Examples of operation of a memory array 902 comprising a multi-cell array according to various aspects of this disclosure and a block diagram of a control environment 900 are shown. In at least one aspect of this disclosure, the memory array 902 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 902 may include a dual-ended memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable dual-ended memory technologies may include resistor-switched memory, conductive-bridged memory, phase-change memory, organic memory, magnetoresistive memory, etc., or suitable combinations thereof. In yet another embodiment, the memory array 902 may be configured to operate according to the batch programming or erasing operations provided herein.

[0089] Column controller 906 and sense amplifier 908 may be configured to be adjacent to memory array 902. Furthermore, column controller 906 may be configured to activate (or identify for activation) a subset of bit lines of memory array 902. Column controller 906 may utilize control signals provided by reference and control signal generator 918 to activate and operate corresponding bit lines in the subset of bit lines, applying appropriate programming, erasing, or read voltages to these bit lines. Inactive bit lines may be held at a disabled voltage (also applied by reference and control signal generator 918) to mitigate or avoid bit interference effects on these inactive bit lines.

[0090] Furthermore, the operating and control environment 900 may include a row controller 904. The row controller 904 may be configured to be adjacent to and electrically connected to the word lines (and source lines, in some embodiments) of the memory array 902. Furthermore, using control signals in the reference and control signal generator 918, the row controller 904 can select a specific row of memory cells using an appropriate selection voltage. Additionally, the row controller 904 can perform programming, erasing, or reading operations by applying appropriate voltages to the selected word lines (and source lines). Similar to the column controller 906, the row controller 904 can apply a disable voltage to inactive word lines (source lines) to mitigate or avoid bit-disturbance effects on the inactive word lines (source lines).

[0091] The sensing amplifier 908 can read data from or write data to the active memory cells of the memory array 902 selected by column control 906 and row control 904. Data read from the memory array 902 can be provided to the input / output buffer 912. Similarly, data to be written to the memory array 902 can be received from the input / output buffer 912 and written to the active memory cells of the memory array 902.

[0092] Clock source 910 can provide corresponding clock pulses to time the read, write, and programming operations of row controller 904 and column controller 906. Clock source 910 can further facilitate word line or bit line selection in response to external or internal commands received by operating and control environment 900. Input / output buffer 912 can include command and address inputs as well as bidirectional data inputs and outputs. Instructions are provided via command and address inputs, and data to be written to and read from memory array 902 is transmitted via bidirectional data inputs and outputs, facilitating connection to external host devices, such as computers or other processing devices (not shown, but see example...). Figure 10 Computer 1002, as described below).

[0093] The input / output buffer 912 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, and receive address data, command data, and address data for corresponding commands. Address data can be transferred to the row controller 904 and column controller 906 via the address register 914. Additionally, input data is transmitted to the memory array 902 via the signal input line between the sense amplifier 908 and the input / output buffer 912, and output data is received from the memory array 902 via the signal output line from the sense amplifier 908 to the input / output buffer 912. Input data can be received from the host device, and output data can be transmitted to the host device via the I / O bus.

[0094] Commands received from the host device can be provided to command interface 916. Command interface 916 can be configured to receive external control signals from the host device and determine whether the data input to input / output buffer 912 is write data, a command, or an address. Input commands can be transmitted to state machine 920.

[0095] State machine 920 can be configured to manage the programming and reprogramming of memory array 902 (and other memory groups of multiple memory arrays). Instructions provided to state machine 920 are implemented according to control logic configuration, enabling state machine 920 to manage read, write, erase, data input, data output, and other functions associated with memory cell array 902. In some aspects, state machine 920 can send and receive responses or negative responses regarding the successful receipt or execution of various commands. In further embodiments, state machine 920 can decode and execute state-related commands, decode and execute configuration commands, and so on.

[0096] To implement functions such as read, write, erase, input, and output, state machine 920 can control clock source 908 or reference and control signal generator 918. Control of clock source 908 can configure output pulses to facilitate specific functions performed by row controller 904 and column controller 906. Output pulses can be transmitted, for example, by column controller 906 to selected bit lines, or, for example, by row controller 904 to word lines.

[0097] refer to Figure 10 A suitable environment 1000 for implementing various aspects of the claimed technical solution includes a computer 1002. The computer 1002 includes a processing unit 1004, system memory 1010, a codec 1014, and a system bus 1008. The system bus 1008 connects system components (including but not limited to system memory 1010) to the processing unit 1004. The processing unit 1004 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 1004.

[0098] The system bus 1008 can be any of several types of bus architectures, including memory bus or memory controller, peripheral bus or external bus and / or local bus using any of the various available bus architectures (including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Plug-in Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), PCMCIA Bus, FireWire (IEEE 1394), and Small Computer System Interface (SCSI)).

[0099] System memory 1010 includes volatile memory 1010A and non-volatile memory 1010B. A basic input / output system (BIOS), including, for example, a basic program that transfers information between components within computer 1002 during startup, is stored in non-volatile memory 1010B. Furthermore, according to the invention, encoder / decoder 1014 may include at least one of an encoder or a decoder, wherein the encoder or decoder may include hardware, software, or a combination of hardware and software. Although encoder / decoder 1014 is depicted as a separate component, it may be included within non-volatile memory 1010B. By way of illustration and not limitation, non-volatile memory 1010B may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, dual-ended memory, etc. Volatile memory 1010A includes random access memory (RAM) used as external cache memory. According to this aspect, volatile memory may store write operation retry logic (…). Figure 10 (not shown in the image). As an illustration and not a limitation, RAM can take many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0100] Computer 1002 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 10As shown, for example, is disk storage 1006. Disk storage 1006 includes, but is not limited to, devices such as: disk drives, solid-state drives (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Furthermore, disk storage 1006 may comprise storage media alone or in combination with other storage media, including but not limited to optical disc drives such as high-density disk read-only memory (CD-ROM), CD-R drives, CD-RW drives, or digital versatile optical disc ROM drives (DVD-ROM). To facilitate connection of disk storage device 1006 to system bus 1008, a removable or non-removable interface, such as storage interface 1012, is typically used. It is understood that storage device 1006 can store user-related information. This information may be stored in or provided to a server or an application running on a user device. In one embodiment, the user may be informed (e.g., via output device 1032) of the type of information stored in disk storage 1006 or transferred to a server or application. Users may be given the opportunity to opt in or out (e.g., via input from input device 1042) to collect and / or share such information with a server or application.

[0101] It should be understood that Figure 10 Software is described that serves as an intermediary between a user and the basic computer resources described in the suitable operating environment 1000. This software includes an operating system 1006A. The operating system 1006A, which may be stored on disk storage 1006, is used to control and allocate resources of the computer system 1002. Application program 1006C utilizes the operating system 1006A to manage resources through program module 1006D, and program data 1006D stored in system memory 1010 or disk storage 1006, such as start / close transaction tables, etc. It should be understood that the claimed technical solution can be implemented using various operating systems or combinations of operating systems.

[0102] Users input commands or information into computer 1002 via input device 1042. Input device 1042 includes, but is not limited to, pointing devices such as mice, trackballs, styluses, touchpads, keyboards, microphones, joysticks, game controllers, satellite dishes, scanners, TV tuners, digital cameras, digital camcorders, webcams, etc. These and other input devices are connected to processing unit 1004 via input port 1040 through system bus 1008. Input port 1040 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1032 uses some of the same type of ports as input device 1042. Thus, for example, a USB port can be used to provide input to computer 1002 and output information from computer 1002 to output device 1032. Output adapter 1030 is provided to account for the presence of some output devices 1032 that require special adapters, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1030 includes a video card and a sound card that provide a connection between output device 1032 and system bus 1008. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1038.

[0103] Computer 1002 can operate in a networked environment using a logical connection to one or more remote computers (e.g., remote computer 1024). Remote computer 1024 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer-to-peer device, smartphone, tablet, or other network node, and typically includes many of the elements described relative to computer 1002. For simplicity, only storage device 1026 is illustrated for remote computer 1024. Remote computer 1024 is logically connected to computer 1002 via network 1022 and then connected via communication interface 1020. Network 1022 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs), as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and Digital Subscriber Line (DSL).

[0104] Communication interface 1020 refers to the hardware / software used to connect network 1022 to bus 1008. Although communication interface 1020 is shown inside computer 1002 for clarity, it may also be outside computer 1002. The hardware / software required to connect to network 1022 includes (for illustrative purposes only) internal and external technologies, such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

[0105] The aspects shown in this disclosure can also be implemented in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules or stored information, instructions, etc., can reside in local or remote storage devices.

[0106] Furthermore, it should be understood that the various components described herein may include circuits that may include suitable values ​​of components and circuit elements to implement embodiments of this disclosure. Additionally, it is understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a set of components may be implemented in a single IC chip. In other embodiments, one or more corresponding components are fabricated or implemented on separate IC chips.

[0107] Regarding the various functions performed by the aforementioned components, architectures, circuits, processes, etc., the terms used to describe these components (including references to "means") are intended to correspond to any component (e.g., an equivalent form of the function) used to perform a particular function of the described component, unless otherwise stated, even if they are not structurally equivalent to the disclosed structure (which performs the functions in the exemplary aspects of the embodiments shown herein). In this regard, it should also be recognized that the embodiments include systems as well as computer-readable media having computer-executable instructions for performing actions and / or events of the various processes.

[0108] Furthermore, although a particular feature may be disclosed with reference to only one of several embodiments, this feature may be combined with one or more other features of other embodiments in a manner desired and advantageous to any given or particular application. Moreover, with regard to the use of the terms "comprising" and "including" and variations thereof in the detailed description or claims, these terms are intended to be included in a manner similar to the term "comprising".

[0109] As used in this application, the term "or" is intended to mean an inclusive "or," not an exclusive "or." That is, unless otherwise stated or clearly understood from the context, "X adopts A or B" is intended to mean any natural inclusive arrangement. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" satisfies any of the foregoing conditions. Furthermore, unless otherwise stated or clearly understood from the context to refer to the singular form, the articles "a" and "an" as used in this application and the appended claims should generally be understood to mean "one or more."

[0110] Upon reading this disclosure, those skilled in the art can conceive of further embodiments. For example, in several embodiments, erase operations can be initiated simultaneously on multiple ReRAM devices (e.g., 16, 32, etc.).

[0111] In other embodiments, combinations or sub-combinations of the embodiments disclosed above can be advantageously performed. For ease of understanding, the block diagrams and flowcharts of the architecture have been grouped. However, it should be understood that combinations of blocks, additions of new blocks, rearrangements of blocks, etc., are contemplated in alternative embodiments of this disclosure.

[0112] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes made thereto will inspire those skilled in the art and be included within the spirit and scope of this application and the appended claims.

Claims

1. A method for performing an erase or program operation on a dual-ended storage device, comprising: Initiating the erase or programming cycle of the first batch of dual-ended storage devices includes applying a signal voltage to the first dual-ended storage device of the first batch of dual-ended storage devices and simultaneously applying the signal voltage to the second dual-ended storage device of the first batch of dual-ended storage devices; Monitor the erase detection condition or programming detection condition of each dual-end storage device in the first batch of dual-end storage devices. Detecting the erase detection condition indicates that the erase operation of the dual-end storage device has been completed, and detecting the programming detection condition indicates that the programming operation of the dual-end storage device has been completed. as well as Before detecting the erase or programming conditions of all dual-ended memory devices in the first batch of dual-ended memory devices, the method includes: Detect the erase detection conditions or programming detection conditions of the first dual-end storage device; as well as In response to the detection of an erase detection condition or a programming detection condition of the first dual-ended storage device, the erase cycle or programming cycle of the third dual-ended storage device of the second batch of dual-ended storage devices is initiated while the signal voltage is applied to the second dual-ended storage device, wherein the first batch of dual-ended storage devices does not include the second batch of dual-ended storage devices.

2. The method according to claim 1, wherein, Before detecting erase or programmable conditions on all dual-ended storage devices, the method includes: The erase detection condition or programming detection condition of the second dual-end storage device of the first batch of dual-end storage devices is detected; and In response to the detection of an erase detection condition or a programming detection condition of the second dual-end storage device, the erase cycle or programming cycle of the fourth dual-end storage device of the second batch of dual-end storage devices is initiated.

3. The method according to claim 1, wherein, After detecting the erase detection condition or programming detection condition of the first dual-end memory device in the first batch of dual-end memory devices, the method includes performing a verification cycle on the first dual-end memory device to determine a success condition or to determine the lack of a success condition, and Specifically, in response to detecting the erase detection condition or programming detection condition of the first dual-end storage device and determining the success condition, the erase cycle or programming cycle of the third dual-end storage device of the second batch of dual-end storage devices is initiated.

4. The method according to claim 1, wherein, The erase cycle or programming cycle of the third dual-end storage device that initiates the second batch of dual-end storage devices does not have the verification cycle of the first dual-end storage device of the first batch of dual-end storage devices.

5. The method according to claim 4, wherein, The verification cycle is selected from the group consisting of the erase verification cycle and the programming verification cycle.

6. The method according to claim 1, wherein, The erase detection conditions or programming detection conditions for the first batch of dual-ended storage devices include: Receive current associated with the first dual-ended storage device; The current is biased by current offset to form a bias current; and The bias current is compared with a current threshold to detect erase detection conditions or programming detection conditions.

7. The method according to claim 6, wherein, The response to the bias current detection erase detection condition or programming detection condition includes: When the bias current is less than the current threshold, the detection condition is set for erasure detection; or When the bias current is greater than the current threshold, the detection is a programmed detection condition.

8. The method according to claim 1, wherein, The dual-ended storage device includes a resistive random access device, i.e., a ReRAM device; and Monitoring the erase detection conditions or programming detection conditions of each dual-end memory device includes monitoring the erase detection conditions or programming detection conditions of each ReRAM device.

9. The method according to claim 1, wherein, The dual-end storage device is selected from the group consisting of phase change memory, metal oxide memory, silicon suboxide memory, chalcogenide memory, magnetic memory, carbon nanotube memory and filament-based memory.

10. The method according to claim 1, wherein, After detecting the erase detection condition or programming detection condition of the last dual-end memory device in the first batch of dual-end memory devices, the method includes: In response to detecting an erase detection condition or a programming detection condition of the last dual-end memory device in the first batch of dual-end memory devices, the erase cycle or programming cycle of the fourth dual-end memory device in the second batch of dual-end memory devices is initiated, and The number of dual-end storage devices in the first batch of dual-end storage devices ranges from 8 to 32.

11. A semiconductor device, comprising: The first batch of dual-ended storage devices includes a first dual-ended storage device and a second dual-ended storage device; The second batch of dual-end storage devices includes the third and fourth dual-end storage devices; A state adjustment activation unit is connected to the first batch of dual-end storage devices and the second batch of dual-end storage devices, wherein the state adjustment activation unit is configured to simultaneously apply a signal to the first batch of dual-end storage devices and the second batch of dual-end storage devices to activate each dual-end storage device in the first batch of dual-end storage devices to enter a predetermined state, wherein the predetermined state is selected from the group consisting of an erase state and a programming state. A detection unit is connected to the first batch of dual-end storage devices and the status adjustment activation unit, wherein the detection unit is configured to detect the adjustment success conditions of the dual-end storage devices of the first batch of dual-end storage devices; The state adjustment initiation unit is further configured to, in response to detecting the adjustment success condition of the second dual-end storage device and before detecting the adjustment success condition of the first dual-end storage device, initiate the third dual-end storage device of the second batch of dual-end storage devices to enter the predetermined state by at least partially simultaneously applying the signal to the first dual-end storage device when the signal is applied to the third dual-end storage device of the second batch of dual-end storage devices.

12. The semiconductor device according to claim 11, wherein, The state adjustment initiation unit is further configured to, in response to detecting the adjustment success condition of the first dual-end storage device of the first batch of dual-end storage devices and before detecting the adjustment success condition of the fifth dual-end storage device of the first batch of dual-end storage devices, initiate the fourth dual-end storage device of the second batch of dual-end storage devices to enter the predetermined state.

13. The semiconductor device according to claim 11, further comprising: A verification unit is connected to the first batch of dual-end storage devices, the second batch of dual-end storage devices, the state adjustment activation unit, and the detection unit, wherein the verification unit is configured to verify that the second dual-end storage device has reached the predetermined state. The state adjustment initiation unit is further configured to, in response to detecting the adjustment success condition of the second dual-end storage device and in response to the verification unit verifying that the second dual-end storage device has reached a predetermined state, initiate the third dual-end storage device to enter the predetermined state.

14. The semiconductor device according to claim 11, wherein, The state adjustment activation unit is configured to activate the third dual-end storage device to enter the predetermined state without verifying the predetermined state.

15. The semiconductor device according to claim 14, wherein, The verification cycle associated with the verification of the predetermined state is selected from the group consisting of the erase verification cycle and the programming verification cycle.

16. The semiconductor device according to claim 11, wherein, The detection unit includes: The first input is configured to receive current associated with the second dual-ended storage device; A bias circuit, connected to the first input and configured to bias the current by current offset to form a bias current; A comparator, connected to the bias circuit and configured to compare the bias current with a threshold current to determine the sensed current; and A detector circuit, connected to the comparator, is configured to determine an adjustment success condition in response to the sensed current.

17. The semiconductor device according to claim 16, wherein, The detector circuit is configured to determine that the adjustment is successful when the sensed current is less than a first threshold current, or The detector circuit is configured to determine that the adjustment is successful when the sensed current is greater than the second threshold current.

18. The semiconductor device according to claim 11, wherein, The first batch of dual-ended storage devices includes resistive random access devices, i.e., ReRAM devices.

19. The semiconductor device according to claim 11, wherein, The first batch of dual-end storage devices are selected from the group consisting of phase change memory, metal oxide memory, silicon suboxide memory, chalcogenide memory, magnetic memory, carbon nanotube memory and filament-based memory.

20. The semiconductor device according to claim 11, wherein, The number of dual-end storage devices in the first batch is in the range of 8 to 32.

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