camera device

Abstract

An imaging device includes a plurality of pixels. Each of the plurality of pixels includes a first electrode, a second electrode, a photoelectric conversion layer between the first electrode and the second electrode, a donor semiconductor material, an acceptor semiconductor material, a pair of an electron and a hole, a first charge-blocking layer between the first electrode and the photoelectric conversion layer, a second charge-blocking layer between the second electrode and the photoelectric conversion layer, and a charge accumulation region electrically connected to the second electrode and accumulating the hole. A difference between an electron affinity of the acceptor semiconductor material and an electron affinity of the first charge-blocking layer is larger than a difference between an ionization potential of the donor semiconductor material and an ionization potential of the second charge-blocking layer.

Description

Technical Field

[0001] This disclosure relates to a camera device using photoelectric conversion elements. Background Technology

[0002] Photoelectric conversion elements using thin films of semiconductor materials can be used as optical sensors by extracting the charge generated by light as an electrical signal. For example, Patent Document 1 discloses a method of providing an electron blocking layer or a hole blocking layer between the photoelectric conversion material and the electrodes to prevent backflow of charge from the electrodes. Furthermore, Patent Document 2 discloses a method of varying the bias voltage applied to the electrodes connected to both ends of the photoelectric conversion element.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 5969843

[0006] Patent Document 2: Japanese Patent Application Publication No. 2018-092990 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] To improve the signal-to-noise ratio (S / N) of a camera device, it is desirable to reduce parasitic sensitivity.

[0009] Therefore, the purpose of this disclosure is to provide a camera device that can reduce parasitic sensitivity.

[0010] Methods used to solve problems

[0011] An imaging device according to a technical solution of this disclosure includes multiple pixels. Each of the multiple pixels includes: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, containing a donor semiconductor material and an acceptor semiconductor material to generate electron-hole pairs; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; a second charge blocking layer located between the second electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the second electrode to accumulate holes as signal charges. The ionization potential of the second charge blocking layer is greater than the ionization potential of the donor semiconductor material. The electron affinity of the first charge blocking layer is less than the electron affinity of the acceptor semiconductor material. The difference between the electron affinity of the acceptor semiconductor material and the electron affinity of the first charge blocking layer is greater than the difference between the ionization potential of the donor semiconductor material and the ionization potential of the second charge blocking layer.

[0012] Furthermore, the imaging device of one technical solution of this disclosure includes multiple pixels. Each of the multiple pixels includes: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, containing a donor semiconductor material and an acceptor semiconductor material to generate electron-hole pairs; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; a second charge blocking layer located between the second electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the second electrode to accumulate electrons as signal charge. The electron affinity of the second charge blocking layer is less than the electron affinity of the acceptor semiconductor material. The ionization potential of the first charge blocking layer is greater than the ionization potential of the donor semiconductor material. The difference between the ionization potential of the donor semiconductor material and the ionization potential of the first charge blocking layer is greater than the difference between the electron affinity of the acceptor semiconductor material and the electron affinity of the second charge blocking layer.

[0013] Invention Effects

[0014] According to this disclosure, it is possible to provide a camera device that can reduce parasitic sensitivity. Attached Figure Description

[0015] Figure 1 This is a schematic cross-sectional view showing the configuration of the photoelectric conversion element according to the relevant implementation method.

[0016] Figure 2 This is an illustrative energy band diagram of a photoelectric conversion element according to an embodiment.

[0017] Figure 3A This is an illustrative energy band diagram of the photoelectric conversion element in the relevant embodiment when a reverse bias voltage is applied.

[0018] Figure 3B This is an illustrative energy band diagram of the photoelectric conversion element under a positive bias voltage applied according to an embodiment.

[0019] Figure 4 This is a diagram illustrating an example of the circuit configuration of a camera device according to an embodiment.

[0020] Figure 5 This is a schematic cross-sectional view showing the device structure of the pixels of the camera device according to the relevant implementation.

[0021] Figure 6 This is a diagram illustrating an example of the schematic current-voltage characteristics of the photoelectric conversion layer in a relevant implementation.

[0022] Figure 7 This is an energy band diagram illustrating another photoelectric conversion element in this embodiment.

[0023] Figure 8This is a diagram illustrating a portion of the circuit configuration of pixels in a relevant implementation method.

[0024] Figure 9 This is a timing diagram showing an example of the voltage supplied to the upper electrode of the photoelectric conversion unit and the timing of the operation of each row of the pixel array of the imaging device in the relevant embodiment.

[0025] Figure 10 This is a timeline illustrating an example of how the camera device in the relevant implementation adjusts the sensitivity of photoelectric conversion via pulse duty cycle control.

[0026] Figure 11 This is a diagram illustrating the schematic configuration of the photoelectric conversion element in an embodiment.

[0027] Figure 12 This is a diagram showing the schematic configuration of the photoelectric conversion element in the comparative example.

[0028] Figure 13 This is a graph showing the current density in bright and dark conditions when a bias voltage is applied to the photoelectric conversion element of the embodiment.

[0029] Figure 14 This is a graph showing the current density in bright and dark conditions when a bias voltage is applied to the photoelectric conversion element of the comparative example. Detailed Implementation

[0030] (Summary of this disclosure)

[0031] The summary of a technical solution disclosed herein is as follows.

[0032] An imaging device according to a technical solution of this disclosure includes multiple pixels. Each of the multiple pixels includes: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, containing a donor semiconductor material and an acceptor semiconductor material to generate electron-hole pairs; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; a second charge blocking layer located between the second electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the second electrode to accumulate holes as signal charges. The ionization potential of the second charge blocking layer is greater than the ionization potential of the donor semiconductor material. The electron affinity of the first charge blocking layer is less than the electron affinity of the acceptor semiconductor material. The difference between the electron affinity of the acceptor semiconductor material and the electron affinity of the first charge blocking layer is greater than the difference between the ionization potential of the donor semiconductor material and the ionization potential of the second charge blocking layer.

[0033] Due to the relationship between electron affinity and ionization potential, the energy barrier for electrons generated by the photoconversion layer to move towards the first electrode is greater than the energy barrier for holes generated by the photoconversion layer to move towards the second electrode. Therefore, electrons are more likely to remain in the photoconversion layer than holes. Consequently, when reading out holes accumulated in the charge accumulation region as signal charges, at the desired timing to stop the movement of holes towards the charge accumulation region, electrons remaining in the photoconversion layer readily recombine with holes remaining in the photoconversion layer, thus sufficiently promoting hole recombination. Therefore, the movement of holes towards the charge accumulation region is suppressed regardless of the amount of light irradiated onto the photoconversion layer. Thus, the parasitic sensitivity of the imaging device can be reduced.

[0034] Alternatively, for example, the difference between the electron affinity of the acceptor semiconductor material and the electron affinity of the first charge barrier layer may be greater than the difference between the ionization potential of the donor semiconductor material and the ionization potential of the second charge barrier layer by more than 0.1 eV.

[0035] Therefore, the energy barrier for electrons generated by the photoelectric conversion layer to move towards the first electrode is sufficiently large compared to the energy barrier for holes generated by the photoelectric conversion layer to move towards the second electrode. This allows for a further reduction in the parasitic sensitivity of the imaging device.

[0036] Alternatively, for example, the first charge-blocking layer may contain the aforementioned donor semiconductor material.

[0037] Therefore, since it is composed of donor organic semiconductor materials contained in the photoelectric conversion layer 4, it is possible to realize an imaging device with reduced parasitic sensitivity using fewer types of materials.

[0038] Furthermore, the imaging device of one technical solution of this disclosure includes multiple pixels. Each of the multiple pixels includes: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, containing a donor semiconductor material and an acceptor semiconductor material to generate electron-hole pairs; a first charge blocking layer located between the first electrode and the photoelectric conversion layer; a second charge blocking layer located between the second electrode and the photoelectric conversion layer; and a charge accumulation region electrically connected to the second electrode to accumulate electrons as signal charge. The electron affinity of the second charge blocking layer is less than the electron affinity of the acceptor semiconductor material. The ionization potential of the first charge blocking layer is greater than the ionization potential of the donor semiconductor material. The difference between the ionization potential of the donor semiconductor material and the ionization potential of the first charge blocking layer is greater than the difference between the electron affinity of the acceptor semiconductor material and the electron affinity of the second charge blocking layer.

[0039] Due to the relationship between electron affinity and ionization potential, the energy barrier for holes generated in the photoconversion layer to move towards the first electrode is greater than the energy barrier for electrons generated in the photoconversion layer to move towards the second electrode. Therefore, holes are more likely to remain in the photoconversion layer than electrons. Consequently, when reading out electrons accumulated in the charge accumulation region as signal charges, at the desired timing to stop the movement of electrons towards the charge accumulation region, holes remaining in the photoconversion layer readily recombine with electrons remaining in the photoconversion layer, causing the electrons to easily disappear. Thus, the movement of electrons towards the charge accumulation region is suppressed regardless of the amount of light irradiated onto the photoconversion layer. Therefore, the parasitic sensitivity of the imaging device can be reduced.

[0040] Alternatively, the camera device may also include a voltage supply circuit electrically connected to the first electrode, which imparts a potential difference between the first electrode and the second electrode. The voltage supply circuit supplies a first voltage to the first electrode during a first period and a second voltage different from the first voltage during a second period.

[0041] Therefore, by setting the first voltage and the second voltage according to the characteristics of the photoelectric conversion layer, the timing of photoelectric conversion and the timing of readout can be separated, which can further reduce parasitic sensitivity.

[0042] Alternatively, for example, the photoelectric conversion efficiency of the plurality of pixels in the first period may be different from that of the plurality of pixels in the second period.

[0043] Therefore, during the first and second periods, a first voltage and a second voltage that cause different changes in current density depending on the amount of light incident on the photoconversion layer are selected. For example, during the period when the change in current density depending on the amount of light is small, holes and electrons in the photoconversion layer are recombined, thereby reducing parasitic sensitivity.

[0044] Furthermore, for example, the aforementioned camera device may also operate in a global shutter mode where the timing of the exposure between the aforementioned multiple pixels is unified, or the aforementioned signal charge may be accumulated in the aforementioned charge accumulation area during the aforementioned exposure period.

[0045] In this way, exposure can be performed at the same time across all pixels, thus enabling a camera device that can suppress phenomena such as image distortion inherent in rolling shutters while reducing parasitic sensitivity.

[0046] Alternatively, for example, the first period mentioned above could be the exposure period mentioned above, and the second period mentioned above could be a non-exposure period that is different from the exposure period mentioned above.

[0047] In this way, by setting the second period as a non-exposure period for signal readout, it is possible to achieve a global shutter mode while reducing parasitic sensitivity during the second period.

[0048] Alternatively, for example, the electrons and holes in the photoelectric conversion layer can recombine by supplying the second voltage to the first electrode through the voltage supply circuit.

[0049] Thus, since a second voltage is supplied during the second period to allow electrons and holes to recombine, by setting this second period, which is the non-exposure period, as the signal readout period, the current density generated from the photoconversion layer during the non-exposure period is less affected by the amount of light incident on the photoconversion layer. Therefore, parasitic sensitivity can be reduced during the second period.

[0050] Alternatively, for example, the sensitivity of photoelectric conversion can be generated in the photoelectric conversion layer by supplying the first voltage to the first electrode by the voltage supply circuit described above.

[0051] In this way, during the first period of exposure, a voltage is supplied to the first electrode to generate sensitivity in the photoelectric conversion layer, thus enabling an imaging device that can reduce parasitic sensitivity while improving the S / N ratio.

[0052] Alternatively, for example, the first period and the second period may be included in one of more exposure periods within the same frame, during which the signal charge is accumulated in the charge accumulation region.

[0053] Therefore, one of the more than one exposure periods within the same frame includes a first period and a second period where different voltages are supplied to the first electrode. Thus, the imaging device can adjust the magnitude of the first and second voltages, or the length of the first and second periods, to adjust the sensitivity of the photoelectric conversion. Therefore, in such an imaging device with electronic ND (Neutral Density) functionality, parasitic sensitivity can be reduced.

[0054] Alternatively, for example, the aforementioned donor semiconductor material may be a donor organic semiconductor material, and the aforementioned acceptor semiconductor material may be an acceptor organic semiconductor material.

[0055] Therefore, thin films that serve as photoelectric conversion layers can be easily formed.

[0056] Alternatively, for example, the thickness of the first charge-blocking layer could be 5 nm or more.

[0057] Therefore, it is easy to ensure the function of the first charge-blocking layer, which can further reduce parasitic sensitivity.

[0058] Alternatively, for example, the thickness of the second charge-blocking layer could be 5 nm or more.

[0059] Therefore, it is easy to ensure the function of the second charge-blocking layer, which can further reduce parasitic sensitivity.

[0060] Hereinafter, this embodiment will be described with reference to the accompanying drawings.

[0061] Furthermore, the embodiments described below are inclusive or specific examples. The numerical values, shapes, constituent elements, arrangements and connections of constituent elements, steps, and sequences of steps shown in the following embodiments are examples and are not intended to limit this disclosure. Additionally, constituent elements in the following embodiments that are not described in the independent claims representing the highest-level concept are described as arbitrary constituent elements. Furthermore, the figures are not necessarily strictly illustrated. In the figures, substantially identical components are given the same reference numerals, and repeated descriptions may be omitted or simplified.

[0062] (Implementation Method)

[0063] [Photoelectric conversion element]

[0064] First, use Figure 1 The photoelectric conversion element included in the imaging device of this embodiment will be described. The photoelectric conversion element in this embodiment is a charge readout type photoelectric conversion element. Figure 1 This is a schematic cross-sectional view showing the configuration of the photoelectric conversion element 10 in this embodiment.

[0065] like Figure 1 As shown, the photoelectric conversion element 10 is supported by a support substrate 1 and includes an upper electrode 6 and a lower electrode 2 as a pair of electrodes, a photoelectric conversion layer 4 located between the upper electrode 6 and the lower electrode 2, a hole blocking layer 5 located between the upper electrode 6 and the photoelectric conversion layer 4, and an electron blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the upper electrode 6 is an example of a first electrode, and the lower electrode 2 is an example of a second electrode. Furthermore, the hole blocking layer 5 is an example of a first charge blocking layer, and the electron blocking layer 3 is an example of a second charge blocking layer.

[0066] Hereinafter, the constituent elements of the photoelectric conversion element 10 of this embodiment will be described.

[0067] The support substrate 1 can be any substrate used in the support of a typical photoelectric conversion element, such as a glass substrate, quartz substrate, semiconductor substrate or plastic substrate.

[0068] The lower electrode 2 is formed of a metal, a metal nitride, a metal oxide, or polycrystalline silicon that has been given conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. Examples of methods for giving polycrystalline silicon conductivity include doping with impurities.

[0069] The upper electrode 6 is, for example, a transparent electrode formed of a transparent conductive material. Examples of materials that can be used for the upper electrode 6 include transparent conductive oxide (TCO), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), SnO2, and TiO2. Furthermore, depending on the desired transmittance, the upper electrode 6 can also be made by individually or in combination of multiple TCO, aluminum (Al), and gold (Au) materials.

[0070] Furthermore, the materials used for the lower electrode 2 and the upper electrode 6 are not limited to the conductive materials described above; other materials can also be used. For example, the lower electrode 2 can also be a transparent electrode.

[0071] In the fabrication of the lower electrode 2 and the upper electrode 6, various methods are used depending on the materials used. For example, when using ITO, methods such as electron beam deposition, sputtering, resistance heating vapor deposition, chemical reaction methods such as sol-gel deposition, and coating of indium tin oxide dispersions can also be used. In this case, in the fabrication of the lower electrode 2 and the upper electrode 6, UV-ozone treatment, plasma treatment, etc., can also be performed after the ITO film is formed.

[0072] The photoconversion layer 4 comprises a donor semiconductor material and a acceptor semiconductor material. The photoconversion layer 4 is fabricated, for example, using an organic semiconductor material. The fabrication method of the photoconversion layer 4 can be a wet method such as spin coating, or a dry method such as vacuum evaporation. Vacuum evaporation is a method that vaporizes the material of the layer by heating under vacuum and deposits it onto a substrate. Furthermore, the photoconversion layer 4 is, for example, a hybrid film with a bulk-heterojunction structure comprising both donor and acceptor organic semiconductor materials. By comprising donor and acceptor organic semiconductor materials, the photoconversion layer 4 can be easily formed into a thin film. Hereinafter, specific examples of donor and acceptor organic semiconductor materials will be given.

[0073] Examples of donor organic semiconductor materials include metal complexes with triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, cyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyaryl compounds, condensed aromatic carbocyclic compounds (such as naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetraphenylene derivatives, pyrene derivatives, dinaphthalene-containing benzene derivatives, and fluoranthene derivatives), and nitrogen-containing heterocyclic compounds as ligands.

[0074] Examples of acceptor organic semiconductor materials include fullerenes (e.g., C60 fullerenes and C70 fullerenes) and fullerene derivatives (e.g., PCBM (phenyl C60 fullerenes)). 61 Methyl butyrate and ICBA (indole C) 60 Biadditions, etc.), condensed aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetraphenylene derivatives, pyrene derivatives, dinaphthalene-benzene derivatives, fluoranthene derivatives, etc.), and five-membered to seven-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, zoline, isoquinoline, pteridine, acridine, phenazine, phenanthrene, tetrazolium). Compounds containing nitrogen-containing heterocyclic compounds as ligands include cyclohexane, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolidinedion, triazolidinedion, tetrazaindene, oxadiazole, imidazolepyridine, pyrrolidine, pyrrolopyridine, thiadiazopyridine, dibenzozazonol, tribenzozazonol, etc.), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and metal complexes with nitrogen-containing heterocyclic compounds as ligands.

[0075] Furthermore, the donor organic semiconductor materials and acceptor organic semiconductor materials are not limited to the examples mentioned above. Any organic compound that can be formed into a photoelectric conversion layer by either dry or wet methods can be used as the donor organic semiconductor material and acceptor organic semiconductor material constituting the photoelectric conversion layer 4.

[0076] Furthermore, the photoelectric conversion layer 4 may also contain semiconductor materials other than those mentioned above as both donor and acceptor semiconductor materials. For example, the photoelectric conversion layer 4 may also contain silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, or any mixture of two or more of them as semiconductor materials.

[0077] The photoelectric conversion element 10 of this embodiment includes an electron blocking layer 3 disposed between the lower electrode 2 and the photoelectric conversion layer 4, and a hole blocking layer 5 disposed between the upper electrode 6 and the photoelectric conversion layer 4. By providing the electron blocking layer 3 and the hole blocking layer 5, charge injection from the electrodes can be suppressed, and noise signals that adversely affect the S / N ratio can be reduced.

[0078] The thickness of the electron blocking layer 3 is, for example, 5 nm or more. This makes it easy to ensure the function of the electron blocking layer 3. Furthermore, from the viewpoint of suppressing the decrease in the photoelectric conversion efficiency of the photoelectric conversion element 10, the thickness of the electron blocking layer 3 can also be 100 nm or less.

[0079] The thickness of the hole blocking layer 5 is, for example, 5 nm or more. This easily ensures the function of the hole blocking layer 5. Furthermore, from the viewpoint of suppressing the decrease in the photoelectric conversion efficiency of the photoelectric conversion element 10, the thickness of the hole blocking layer 5 can also be 100 nm or less.

[0080] The materials used in the electron blocking layer 3 and the hole blocking layer 5 are semiconductor materials with energy bands, as described later. The electron blocking layer 3 and the hole blocking layer 5 are formed, for example, of organic semiconductor materials. The materials forming the electron blocking layer 3 and the hole blocking layer 5 are not limited to organic semiconductor materials; they may also be oxide semiconductors or nitride semiconductors, or composite materials thereof.

[0081] Furthermore, the hole blocking layer 5 may also contain the donor organic semiconductor material contained in the photoelectric conversion layer 4 as the main material. The hole blocking layer 5 is, for example, composed of the donor organic semiconductor material contained in the photoelectric conversion layer 4. By including the donor organic semiconductor material contained in the photoelectric conversion layer 4 in the hole blocking layer 5, the photoelectric conversion element 10 can be implemented with fewer types of materials. Furthermore, when the photoelectric conversion layer 4 and the hole blocking layer 5 are connected as shown in the figure, by including the same donor organic semiconductor material as the photoelectric conversion layer 4 in the hole blocking layer 5, the adhesion of the interface between the photoelectric conversion layer 4 and the hole blocking layer 5 is improved.

[0082] Figure 2 yes Figure 1 An illustrative energy band diagram of the photoelectric conversion element 10 is shown. Figure 2 The energy bands of each layer are represented by rectangles.

[0083] When photoconversion layer 4 is irradiated with light, electron-hole pairs are generated internally. These generated electron-hole pairs are separated into electrons and holes by an electric field acting on photoconversion layer 4. The electrons and holes move towards the lower electrode 2 or the upper electrode 6, respectively, according to the electric field. Here, the semiconductor material that provides electrons from the electron-hole pairs generated by absorbing light to the other material is a donor semiconductor material, and the semiconductor material that accepts electrons is a acceptor semiconductor material. A donor organic semiconductor material is one example, and an acceptor organic semiconductor material is another example. If photoconversion layer 4 is irradiated with light, for example, the donor semiconductor material generates electron-hole pairs and provides electrons to the acceptor semiconductor material. When using two different organic semiconductor materials, the relative positions of the HOMO (Highest Occupied Molecular Orbital) and LUMO (Lowest Unoccupied Molecular Orbital) energy levels at the contact interface typically determine which material is the donor and which is the acceptor. Figure 2 In the rectangle representing the energy bands, the upper end is the LUMO level and the lower end is the HOMO level.

[0084] like Figure 2 As shown, among the two organic semiconductor materials, the one with a smaller energy difference (i.e., electron affinity) between the vacuum level and the LUMO level is the donor organic semiconductor material 4A, and the one with a larger energy difference is the acceptor organic semiconductor material 4B.

[0085] In addition, such as Figure 2 As shown, in the photoelectric conversion element 10 of this embodiment, the energy difference, i.e., the ionization potential, between the vacuum level and the HOMO level of the electron blocking layer 3 is greater than or equal to the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. Furthermore, the electron affinity of the electron blocking layer 3 is, for example, less than or equal to the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0086] Furthermore, the electron affinity of the hole blocking layer 5 is weaker than that of the acceptor organic semiconductor material 4B of the photoconversion layer 4. Additionally, the ionization potential of the hole blocking layer 5 is, for example, greater than the ionization potential of the donor organic semiconductor material 4A of the photoconversion layer 4.

[0087] also, Figure 2 The difference in electron affinity between the hole-blocking layer 5 (represented by ΔE2) and the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4 is greater than that between the hole-blocking layer 5 and the photoelectric conversion layer 4. Figure 2The difference in ionization potential between the electron blocking layer 3 (represented by ΔE1) and the donor organic semiconductor material 4A of the photoelectric conversion layer 4 is large.

[0088] The materials used as electron blocking layer 3 and hole blocking layer 5 are, for example, materials having the above-described energy magnitude relationship among the donor organic semiconductor materials and acceptor organic semiconductor materials illustrated above.

[0089] In addition, such as Figure 2 As shown, the lower electrode 2 is electrically connected to the charge accumulation node 34, which will be described later. The charge accumulation node 34, as an example of a charge accumulation region, accumulates holes generated by the photoelectric conversion layer 4.

[0090] Figure 3A This is an exemplary energy band diagram of the photoelectric conversion element 10 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 6. Furthermore, Figure 3B This is an exemplary energy band diagram of the photoelectric conversion element 10 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 6. In this specification, it is assumed that when a higher voltage is applied to the upper electrode 6 than to the lower electrode 2, the voltage is reverse biased, also known as the reverse bias voltage, and when a lower voltage is applied to the upper electrode 6 than to the lower electrode 2, the voltage is forward biased, also known as the forward bias voltage, for the following explanation.

[0091] For example, as a photoelectric conversion mode in Figure 3A In the state shown, electron-hole pairs are generated in the photoelectric conversion layer 4. Then, the holes move to the lower electrode 2, and the electrons move to the upper electrode 6, as a readout mode. Figure 3B In the state shown, the signal of the hole stored in the charge storage node 34 is read out via the lower electrode 2.

[0092] In this case, in photoelectric conversion mode, the energy barrier for holes moving from photoelectric conversion layer 4 to the lower electrode 2 is ΔE1, and the energy barrier for electrons moving from photoelectric conversion layer 4 to the upper electrode 6 is ΔE2. Since ΔE2, the energy barrier for electron movement, is greater than ΔE1, the energy barrier for hole movement, electrons are more difficult to move than holes. As a result, in photoelectric conversion mode, electrons are more likely to remain in photoelectric conversion layer 4 than holes. Therefore, during the transition to readout mode, when residual electrons and holes recombine, the presence of easily retained electrons sufficiently promotes hole recombination, thus suppressing the movement of residual holes to the lower electrode 2.

[0093] As described above, the photoelectric conversion element 10 of the camera device 100 of this embodiment can effectively reduce parasitic sensitivity in the manner of reading out holes from the lower electrode 2 by using the electron blocking layer 3 and the hole blocking layer 5 having the above-described energy band.

[0094] [Camera device]

[0095] The following uses Figure 4 and Figure 5 The camera device described in this embodiment will be explained. Figure 4 Is it installed and used? Figure 1 This diagram illustrates an example of the circuit configuration of the camera device 100 within the photoelectric conversion unit 10A of the photoelectric conversion element 10. Furthermore, Figure 5 This is a schematic cross-sectional view showing an example of the device structure of the pixel 24 of the camera device 100 in this embodiment.

[0096] like Figure 4 and Figure 5 As shown, the imaging device 100 of this embodiment includes a semiconductor substrate 40 and a plurality of pixels 24. Each of the plurality of pixels 24 includes a charge detection circuit 35 disposed on the semiconductor substrate 40, a photoelectric conversion unit 10A disposed on the semiconductor substrate 40, and a charge accumulation node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 includes the aforementioned photoelectric conversion element 10. That is, each of the plurality of pixels 24 includes an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4, a hole blocking layer 5, an electron blocking layer 3, and a charge accumulation node 34. In this embodiment, the charge accumulation node 34 is an example of a charge accumulation region.

[0097] The charge accumulation node 34 accumulates the charge obtained by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the charge accumulated in the charge accumulation node 34. In addition, the charge detection circuit 35 provided on the semiconductor substrate 40 can be provided on the semiconductor substrate 40 or in the semiconductor substrate 40.

[0098] like Figure 4 As shown, the imaging device 100 includes multiple pixels 24 and peripheral circuitry. The imaging device 100 is an organic image sensor implemented using a single-chip integrated circuit, having a pixel array PA comprising multiple pixels 24 arranged in a two-dimensional manner. The imaging device 100 is, for example, an imaging device that operates in a global shutter mode where the exposure time is uniform across the multiple pixels 24. That is, the imaging device 100 has a global shutter function. Details regarding the exposure time will be described later.

[0099] Multiple pixels 24 are arranged two-dimensionally on the semiconductor substrate 40, both in the row and column directions, to form a photosensitive area that serves as a pixel region. Figure 4 The image shows an example of 24 pixels arranged in a 2x2 matrix. Additionally, in... Figure 4 For ease of illustration, the diagram of the circuit (e.g., pixel electrode control circuit) used to individually set the sensitivity of pixel 24 is omitted. Furthermore, the imaging device 100 can also be a line sensor. In this case, the multiple pixels 24 can also be arranged in one dimension. Additionally, in this specification, row direction and column direction refer to the directions in which rows and columns extend, respectively. That is, in Figure 4 In Chinese, the vertical axis of the paper represents the column direction, and the horizontal axis represents the row direction.

[0100] like Figure 4 and Figure 5 As shown, each pixel 24 includes a photoelectric conversion unit 10A and a charge accumulation node 34 electrically connected to a charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0101] The photoelectric conversion unit 10A includes a lower electrode 2, which is provided as a pixel electrode, and an upper electrode 6, which is provided as a counter electrode. The photoelectric conversion unit 10A includes the photoelectric conversion element 10 described above. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 6 via the counter electrode signal line 26.

[0102] The lower electrode 2 is connected to the gate electrode 21G of the amplifying transistor 21. The signal charge collected by the lower electrode 2 is stored in the charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplifying transistor 21. In this embodiment, the signal charge is a hole. That is, the charge storage node 34 is electrically connected to the lower electrode 2 and stores the holes generated by the photoelectric conversion layer 4.

[0103] The signal charge stored in charge accumulation node 34 is applied as a voltage corresponding to the amount of signal charge to the gate electrode 21G of amplifying transistor 21. Amplifying transistor 21 amplifies this voltage, which is selectively read out as a signal voltage by address transistor 23. Reset transistor 22, with its source / drain electrodes connected to lower electrode 2, resets the signal charge stored in charge accumulation node 34. In other words, reset transistor 22 resets the potential of the gate electrode 21G and lower electrode 2 of amplifying transistor 21.

[0104] To selectively perform the aforementioned actions on multiple pixels 24, the imaging device 100 includes a power supply line 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, which are connected to each pixel 24 respectively. Specifically, the power supply line 31 is connected to the source / drain electrodes of the amplifying transistor 21, and the vertical signal line 27 is connected to the source / drain electrodes of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. Furthermore, the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0105] The peripheral circuitry includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, multiple column signal processing circuits 29, multiple load circuits 28, and multiple differential amplifiers 32.

[0106] The voltage supply circuit 19 is electrically connected to the upper electrode 6 via the counter electrode signal line 26. By supplying voltage to the upper electrode 6, the voltage supply circuit 19 establishes a potential difference between the upper electrode 6 and the lower electrode 2. For example, the voltage supply circuit 19 supplies a first voltage during a first period, such as the exposure period described later, and supplies a second voltage different from the first voltage during a second period, such as the non-exposure period.

[0107] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, selecting multiple pixels 24 arranged in each row by row, reading out the signal voltage, and resetting the potential of the lower electrode 2. The power supply wiring 31, serving as the source follower power supply, supplies a predetermined power voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplifying transistor 21 form a source follower circuit.

[0108] Multiple differential amplifiers 32 are provided corresponding to each column. The input terminal on the negative side of the differential amplifier 32 is connected to the corresponding vertical signal line 27. In addition, the output terminal of the differential amplifier 32 is connected to the pixel 24 via the feedback line 33 corresponding to each column.

[0109] The vertical scan circuit 25 applies a row selection signal to the gate electrode 23G of the address transistor 23 via the address signal line 36, controlling the on / off state of the address transistor 23. This scans and selects the row to be read. The signal voltage from the pixel 24 of the selected row is read out to the vertical signal line 27. Furthermore, the vertical scan circuit 25 applies a reset signal to the gate electrode 22G of the reset transistor 22 via the reset signal line 37, controlling the on / off state of the reset transistor 22. This selects the row of pixels 24 to be reset. The signal voltage read from the pixel 24 selected by the vertical scan circuit 25 is transmitted to the column signal processing circuit 29 via the vertical signal line 27.

[0110] The signal processing circuit 29 performs noise suppression signal processing, represented by correlated double sampling, and analog-to-digital conversion (AD conversion).

[0111] The horizontal signal readout circuit 20 reads signals sequentially from multiple column signal processing circuits 29 onto the horizontal common signal line (not shown).

[0112] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its negative terminal. The differential amplifier 32 performs feedback operation to make the gate potential of the amplifying transistor 21 a predetermined feedback voltage. At this time, the output voltage of the differential amplifier 32 is 0V or a positive voltage near 0V. The feedback voltage refers to the output voltage of the differential amplifier 32.

[0113] like Figure 5 As shown, pixel 24 includes a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge accumulation node 34 (see reference). Figure 4 ).

[0114] The semiconductor substrate 40 may also be an insulating substrate, such as a p-type silicon substrate, on the surface where a semiconductor layer is formed on the side where the photosensitive area is formed. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S and a component separation region 41 for electrical separation between pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the component separation region 41 is provided between impurity regions 21D and 22D. This suppresses leakage of signal charge accumulated by the charge accumulation node 34. Furthermore, the component separation region 41 is formed, for example, by ion implantation of a acceptor under specified implantation conditions.

[0115] Impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed within the semiconductor substrate 40. Figure 5As shown, the amplifying transistor 21 includes impurity regions 21S and 21D, and a gate electrode 21G. Impurity regions 21S and 21D function as, for example, the source and drain regions of the amplifying transistor 21, respectively. A channel region of the amplifying transistor 21 is formed between the impurity regions 21S and 21D.

[0116] Similarly, address transistor 23 includes sludge regions 23S and sludge regions 21S, and a gate electrode 23G connected to address signal line 36. In this example, amplification transistor 21 and address transistor 23 are electrically connected to each other by sharing sludge region 21S. Sludge region 23S functions as, for example, the source region of address transistor 23. Sludge region 23S has a similarity to... Figure 4 The connection of the vertical signal line 27 is shown.

[0117] The reset transistor 22 includes impurity regions 22D and 22S, and a gate electrode 22G connected to the reset signal line 37. The impurity region 22S functions as, for example, the source region of the reset transistor 22. The impurity region 22S has a similar characteristic to... Figure 4 The connection of the reset signal line 37 is shown.

[0118] An interlayer insulating layer 50 is stacked on the semiconductor substrate 40 in such a way that it covers the amplification transistor 21, the address transistor 23 and the reset transistor 22.

[0119] Furthermore, a wiring layer (not shown) may be disposed in the interlayer insulating layer 50. The wiring layer may be formed of a metal such as copper, and may include wiring such as the vertical signal line 27 described above in a portion thereof. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer disposed in the interlayer insulating layer 50 may be arbitrarily set.

[0120] In the interlayer insulating layer 50, a contact plug 53 electrically connected to the gate electrode 21G of the amplifying transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and wiring 52 connecting the contact plugs 51, 54, and 53 are disposed. Thus, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplifying transistor 21. Figure 5 In the illustrated configuration, the contact plugs 51, 53 and 54, the wiring 52, the gate electrode 21G of the amplifying transistor 21 and the impurity region 22D of the reset transistor 22 constitute at least a portion of the charge accumulation node 34.

[0121] The charge detection circuit 35 detects the signal charge captured by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplifying transistor 21, a reset transistor 22, and an address transistor 23, and is formed on the semiconductor substrate 40.

[0122] The amplifying transistor 21 includes an impurity region 21D and an impurity region 21S formed in the semiconductor substrate 40 and functioning as a drain electrode and a source electrode, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0123] The reset transistor 22 includes an impurity region 22D and an impurity region 22S formed in the semiconductor substrate 40 and functioning as a drain electrode and a source electrode, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0124] Address transistor 23 includes impurity regions 21S and 23S formed in semiconductor substrate 40 and functioning as drain and source electrodes, respectively, a gate insulating layer 23X formed on semiconductor substrate 40, and a gate electrode 23G formed on gate insulating layer 23X. Impurity region 21S is connected in series with amplification transistor 21 and address transistor 23.

[0125] The photoelectric conversion unit 10A described above is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. Furthermore, the plurality of pixels 24 arranged two-dimensionally on the semiconductor substrate 40 form a photosensitive area. The distance between two adjacent pixels 24 (i.e., pixel pitch) may, for example, be about 2 μm.

[0126] The photoelectric conversion unit 10A has the structure of the photoelectric conversion element 10 described above.

[0127] A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above it. The color filter 60 is, for example, formed as a pattern-based on-chip color filter, using a photosensitive resin in which dyes or pigments are dispersed. The microlens 61 is, for example, formed as an on-chip microlens, using an ultraviolet photosensitive material.

[0128] In the manufacture of the camera device 100, conventional semiconductor manufacturing processes can be used. In particular, when a silicon substrate is used as the semiconductor substrate 40, various silicon semiconductor processes can be used.

[0129] Figure 6 This is a diagram illustrating an example of the schematic current-voltage (I-V) characteristics of the photoelectric conversion layer 4. Figure 6 In the diagram, the thick solid curve represents an exemplary I-V characteristic of the photoelectric conversion layer 4 when a voltage is applied between the lower electrode 2 and the upper electrode 6 under illumination. Furthermore, in... Figure 6In the figure, a thick dashed line is used to show an example of the I-V characteristics of the photoelectric conversion layer 4 when a voltage is applied between the lower electrode 2 and the upper electrode 6 in the absence of illumination.

[0130] like Figure 6 As shown, the photocurrent characteristics of the photoconversion layer 4 in this embodiment are generally characterized by a first voltage range, a second voltage range, and a third voltage range. In the first voltage range, the current variation of the photoconversion layer 4 is less dependent on the bias voltage applied between the lower electrode 2 and the upper electrode 6 and the amount of incident light onto the photoconversion layer 4. That is, in the first voltage range, the difference between the current flowing through the photoconversion layer 4 when light is incident and the current flowing through the photoconversion layer 4 when no light is incident is small. In the first voltage range, even if hole-electron pairs are generated by the incident light onto the photoconversion layer 4, since the absolute value of the voltage applied between the lower electrode 2 and the upper electrode 6 is small, their recombination occurs before the holes and electrons separate.

[0131] also, Figure 6 The second voltage range is the reverse bias voltage range, and it is the region where the absolute value of the output current density increases as the reverse bias voltage increases. That is, the second voltage range is the region where the current value increases as the amount of incident light to the photoelectric conversion layer 4 and the bias voltage applied between the lower electrode 2 and the upper electrode 6 increases.

[0132] Furthermore, the third voltage range is the positive bias voltage range, and it is the region where the output current density increases with the increase of the positive bias voltage. That is, the third voltage range is the region where the current increases with the increase of the bias voltage applied between the lower electrode 2 and the upper electrode 6, even when no light is incident on the photoelectric conversion layer 4.

[0133] The above Figure 3A This is an illustrative energy band diagram corresponding to the case where a bias voltage of the second voltage range is applied to the photoelectric conversion element 10. Furthermore, Figure 3B An illustrative band diagram equivalent to the case where a bias voltage of the first voltage range is applied to the photoelectric conversion element 10.

[0134] The photoelectric conversion unit 10A, which is composed of the photoelectric conversion element 10 of the camera device 100 of this embodiment, has a first voltage range in which the difference between the current value flowing under light incidence and the current value flowing under no light incidence is small by having a photoelectric conversion layer 4 with such a directional photoelectric conversion layer 4. The camera device 100 can realize the global shutter function while reducing parasitic sensitivity.

[0135] When the signal charge to be detected is a hole, such as Figure 2 , Figure 3A and Figure 3B As shown, the greater the difference in electron affinity ΔE2 between the acceptor organic semiconductor material 4B and the hole blocking layer 5 compared to the difference in ionization potential ΔE1 between the donor organic semiconductor material 4A and the electron blocking layer 3, the more easily electrons remain in the photoelectric conversion layer 4 compared to holes. Therefore, when the bias voltage applied between the lower electrode 2 and the upper electrode 6 is within the first voltage range, by improving the effect of promoting the recombination of electrons and holes, holes are less likely to move to the lower electrode 2, thus reducing parasitic sensitivity. For example, from the viewpoint of improving the effect of reducing parasitic sensitivity, the difference in electron affinity ΔE2 between the acceptor organic semiconductor material 4B and the hole blocking layer 5 can also be 0.1 eV or more greater than the difference in ionization potential ΔE1 between the donor organic semiconductor material 4A and the electron blocking layer 3. From the perspective of further improving the effect of reducing parasitic sensitivity, the difference in electron affinity ΔE2 between the acceptor organic semiconductor material 4B and the hole blocking layer 5 can be more than 0.3 eV greater than the difference in ionization potential ΔE1 between the donor organic semiconductor material 4A and the electron blocking layer 3.

[0136] Alternatively, when the signal charge to be detected is an electron, it can be configured such that a hole blocking layer is provided between the lower electrode 2 and the photoelectric conversion layer 4 as a second charge blocking layer, and an electron blocking layer is provided between the upper electrode 6 and the photoelectric conversion layer 4 as a first charge blocking layer, with the lower electrode 2 electrically connected to the charge accumulation node 34. That is, the imaging device according to this embodiment may also include an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 6 and the lower electrode 2, a hole blocking layer located between the lower electrode 2 and the photoelectric conversion layer 4, an electron blocking layer located between the upper electrode 6 and the photoelectric conversion layer 4, and a charge accumulation node 34 electrically connected to the lower electrode 2 and accumulating electrons. Figure 7 This is an illustrative energy band diagram relating to other photoelectric conversion elements of this embodiment. Figure 7In this embodiment, as another example of a photoelectric conversion element for an imaging device, an energy band structure is shown that includes an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 6 and the lower electrode 2, a hole blocking layer 5A located between the lower electrode 2 and the photoelectric conversion layer 4, and an electron blocking layer 3A located between the upper electrode 6 and the photoelectric conversion layer 4. In this case, the electron affinity of the hole blocking layer 5A is less than that of the acceptor semiconductor material 4B, and the ionization potential of the electron blocking layer 3A is greater than that of the donor semiconductor material 4A. Furthermore, the ionization potential difference ΔE4 between the donor organic semiconductor material 4A and the electron blocking layer 3A in the photoelectric conversion layer 4 is made greater than the electron affinity difference ΔE3 between the acceptor organic semiconductor material 4B and the hole blocking layer 5A in the photoelectric conversion layer 4. Even with a camera device that reads out electrons by accumulating them in charge accumulation nodes 34, holes are more likely to remain in the photoelectric conversion layer 4 than electrons, thanks to the same mechanism as the camera device 100 that reads out holes by accumulating them in charge accumulation nodes 34. This results in a reduction in parasitic sensitivity.

[0137] [The action of the camera device]

[0138] Next, refer to Figure 8 and Figure 9 The operation of the camera device 100 is explained. Here, holes are used as signal charges as described above.

[0139] Figure 8 This diagram illustrates a portion of the circuitry for pixel 24. For simplicity, it shows the case where one end of the charge accumulation node 34 is grounded and its potential is zero. This state is, for example, equivalent to... Figure 4 The feedback line 33 shown is set to 0V. In this state, if the voltage of the charge accumulation node 34 is set to Vc, then Vc is zero.

[0140] Figure 4 The voltage supply circuit 19 shown supplies different voltages to the upper electrode 6 via the counter electrode signal line 26 between the exposure period (an example of the first period) and the non-exposure period (an example of the second period). In this specification, "exposure period" refers to the period during which one of the electrons and holes generated by photoelectric conversion is accumulated as a signal charge in the charge accumulation node 34. That is, "exposure period" can also be called "charge accumulation period." Furthermore, in this specification, the period during which the imaging device operates, but other than the exposure period, is called "non-exposure period." "Non-exposure period" can be either a period during which the incident light to the photoelectric conversion unit 10A is blocked, or a period during which light is irradiated onto the photoelectric conversion unit 10A, but no charge is substantially accumulated in the charge accumulation node 34.

[0141] In the initial state, the potential difference between the lower electrode 2 and the upper electrode 6 of the photoelectric conversion unit 10A, i.e., the bias voltage applied to the photoelectric conversion layer 4, the electron blocking layer 3, and the hole blocking layer 5, is set to a value within a first voltage range. For example, the voltage supply circuit 19 supplies a voltage to the upper electrode 6 equal to the voltage of the lower electrode 2 using the counter electrode signal line 26. Here, let the voltage supplied to the upper electrode 6 be V2, and assume that V2 is a reference voltage Vref. In this case, if the bias voltage applied to the photoelectric conversion unit 10A is Vo, then Vo = V2 - Vc, Vo = 0.

[0142] Next, the operation during exposure will be explained. At the start of exposure, the voltage supply circuit 19 supplies voltage V2 to the upper electrode 6 using the counter electrode signal line 26, so that a voltage within the second voltage range, i.e., a reverse bias voltage, is applied to the photoelectric conversion unit 10A. That is, during exposure, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage V2 that generates the sensitivity of photoelectric conversion in the photoelectric conversion layer 4. For example, if the photoelectric conversion layer 4 is made of an organic semiconductor material, V2 is a voltage of a few V to about 10 V. As a result, holes corresponding to the amount of incident light to the photoelectric conversion layer 4 are accumulated as signal charges in the charge accumulation nodes 34 of each pixel 24.

[0143] Next, the operation during the non-exposure period will be explained. After the exposure period ends, the voltage supply circuit 19 supplies voltage V2 to the upper electrode 6 using the counter electrode signal line 26, so that a voltage within the first voltage range is applied to the photoelectric conversion unit 10A. That is, during the non-exposure period, the voltage supply circuit 19 supplies voltage V2 to the upper electrode 6 to recombine electrons and holes in the photoelectric conversion layer 4. For example, the voltage V2 supplied to the upper electrode 6 is set as the reference voltage Vref. In the charge accumulation node 34 of each pixel 24, holes corresponding to the amount of light incident on the photoelectric conversion layer 4 during the exposure period are accumulated, and the value of Vc varies depending on the pixel 24. Since Vo = V2 - Vc, Vo is also zero in pixels 24 where Vc does not change and no exposure has occurred. However, Vo is not zero in pixels 24 where Vc has changed. By ensuring the amplitude of the first voltage range with a sufficiently wide voltage range, even if the value of Vc differs in each pixel 24, a voltage V2 can be set in pixel 24 such that the voltage Vo applied to the photoelectric conversion unit 10A falls within the first voltage range. The deviation of the voltage Vc value falling within the first voltage range corresponds to the size of the dynamic range. For example, if the amplitude of the first voltage range is 0.5V or more, then at a conversion gain of 50μV / e... － The camera device can ensure a dynamic range of more than 80dB, equivalent to that of the human eye.

[0144] When a voltage V2 is supplied to the upper electrode 6 so that the voltage Vo is within the first voltage range, even if light is incident on the pixel 24, holes are unlikely to move to the charge accumulation node 34. That is, the voltage supply circuit 19 supplies voltage to the upper electrode 6 so that the photoelectric conversion efficiency of the multiple pixels 24, specifically the photoelectric conversion unit 10A, differs during exposure and non-exposure periods. Furthermore, holes accumulated in the charge accumulation node 34 are difficult to discharge to the lower electrode 2, or the charge supplied from the voltage supply circuit 19 via the lower electrode 2 is difficult to flow into the charge accumulation node 34.

[0145] Therefore, the holes accumulated in the charge accumulation nodes 34 of each pixel 24 are maintained at an amount corresponding to the amount of incident light onto the photoelectric conversion layer 4. That is, even if light is incident again into the photoelectric conversion layer 4, the holes accumulated in the charge accumulation nodes 34 of each pixel 24 can be maintained as long as the holes in the charge accumulation nodes 34 are not reset. Therefore, during non-exposure periods, even when readout operations are performed sequentially row by row, it is not easy for new holes to accumulate between readout operations. Therefore, for example, rolling distortion will not occur as with a rolling shutter. Therefore, for example, a global shutter function can be implemented with a simple pixel circuit like that of pixel 24 without the need for transmission transistors and additional accumulation capacitors. Since the pixel circuit is simple, pixel miniaturization of pixel 24 can be advantageously achieved in the imaging device 100.

[0146] Figure 9 This is a timing diagram showing an example of the timing of the voltage V2 supplied to the upper electrode 6 of the photoelectric conversion unit 10A and the operation of each row of the pixel array PA of the imaging device 100. Figure 9 For ease of understanding, only the change in voltage V2 and the timing of exposure and signal readout for each row in the pixel array PA, represented by R0 to R7, are shown. In the imaging device 100, during the non-exposure period N, the voltage supply circuit 19 supplies voltage Vb to the upper electrode 6, which is voltage V2 when voltage Vo falls within the first voltage range. During the exposure period E, voltage Va is supplied, which is voltage V2 when voltage Vo falls within the second voltage range. Figure 9 As shown, during the non-exposure period N, the signals of pixels 24 in each row R0 to R7 are read out sequentially. Furthermore, the timing of the start and end of the exposure period E is consistent across all rows of pixels 24 from R0 to R7. That is, the imaging device 100 reads out the signals of each row of pixels 24 sequentially and achieves a global shutter function that exposes all rows of the pixel array PA together.

[0147] As described above, in the imaging device 100 of this embodiment, the ionization potential of the electron blocking layer 3 is greater than or equal to the ionization potential of the donor organic semiconductor material 4A, and the electron affinity of the hole blocking layer 5 is less than that of the acceptor organic semiconductor material 4B. Furthermore, the difference in electron affinity ΔE2 between the acceptor organic semiconductor material 4B and the hole blocking layer 5 is greater than the difference in ionization potential ΔE1 between the donor organic semiconductor material 4A and the electron blocking layer 3.

[0148] Therefore, since the energy barrier ΔE2 for electrons generated by the photoelectric conversion layer 4 to move towards the upper electrode 6 is greater than the energy barrier ΔE1 for holes to move towards the lower electrode 2 in the photoelectric conversion layer 4, electrons tend to remain in the photoelectric conversion layer 4. Consequently, when holes are read from the charge accumulation node 34 connected to the lower electrode 2, the recombination of holes and electrons is promoted, making it difficult for holes to move towards the charge accumulation node 34. Thus, regardless of the amount of light irradiating the photoelectric conversion layer 4, the movement of holes towards the charge accumulation node 34 is suppressed. Therefore, an imaging device 100 capable of reducing parasitic sensitivity is realized.

[0149] Furthermore, the operation of the camera device 100 is not limited to the examples described above; for example, it can also perform the operation of an electronic ND function to adjust the sensitivity of photoelectric conversion.

[0150] For example, in Figure 9 During the exposure period E, the voltage supply circuit 19, instead of voltage Va, supplies voltage V2 to the upper electrode 6 based on the relationship between the bias voltage and the current value at that voltage (i.e., the amount of holes and electrons extracted), thereby enabling the electronic ND function of the imaging device 100.

[0151] also, Figure 10 This is a timeline illustrating an example of how the camera device 100 adjusts the sensitivity of the photoelectric conversion via pulse duty cycle control. For example... Figure 10 As shown, the voltage supply circuit 19 supplies, for example, pulsed voltages of voltages Va and Vb that are repeatedly applied during the exposure period E. Thus, the first period of supplying voltage Va (an example of a first voltage) and the second period of supplying voltage Vb (an example of a second voltage) can be included within the same exposure period E. In this case, the duty cycle of the pulsed voltages of Va and Vb is set to a duty cycle corresponding to a preset ND value, and the voltage supply circuit 19 supplies voltage to the upper electrode 6. This also enables the electronic ND function of the imaging device 100.

[0152] Thus, even when the camera device 100 has an electronic ND function, the parasitic sensitivity of the camera device 100 is reduced as described above, so the camera device 100 can achieve low-noise imaging.

[0153] Example

[0154] The following describes in detail, with examples, the photoelectric conversion element included in the imaging device of the present disclosure, but the present disclosure is not entirely limited to the following examples. In detail, the photoelectric conversion element included in the imaging device of the embodiments of the present disclosure and the photoelectric conversion element for characteristic comparison are manufactured, the current in bright and dark conditions is measured, and the parasitic sensitivity is evaluated.

[0155] (Fabrication of photoelectric conversion elements)

[0156] Photoelectric conversion elements of the embodiments and comparative examples were fabricated.

[0157] [Example]

[0158] The substrate after TiN film formation is used as the support substrate. TiN with a work function of 4.7 eV is used as the lower electrode 2. On the lower electrode 2, 9,9′-[1,1′-biphenyl]-4,4′-dimethylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole is deposited as the material for the electron blocking layer 3 by vacuum evaporation, thereby forming the electron blocking layer 3. The thickness of the electron blocking layer 3 is 50 nm.

[0159] Next, on the electron blocking layer 3, a subphthalocyanine, serving as the donor organic semiconductor, and a C60 fullerene, serving as the acceptor organic semiconductor, are co-deposited at a weight ratio of 1:9 using a vacuum evaporation method to form the photoconversion layer 4. The resulting photoconversion layer 4 has a film thickness of approximately 500 nm. Furthermore, the subphthalocyanine used is one with boron (B) as the central metal and chloride ions coordinated on B.

[0160] Next, on the photoelectric conversion layer 4, subphthalocyanine is deposited as the material of the hole blocking layer 5 through a metal shadow mask by vacuum evaporation to make it a film thickness of 10nm, thereby forming the hole blocking layer 5.

[0161] Next, an ITO film with a thickness of 30 nm is formed on the hole blocking layer 5 as the upper electrode 6 by sputtering. Then, an Al2O3 film is formed on the upper electrode 6 as a sealing film by atomic layer deposition, thereby obtaining the photoelectric conversion element. Figure 11 The diagram shows a schematic configuration of the photoelectric conversion element in an embodiment. Figure 11In this context, material A is 9,9′-[1,1′-biphenyl]-4,4′-dimethylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole, material B is C60 fullerene, and material C is phthalocyanine. Furthermore, these will be discussed later... Figure 12 The same applies to China.

[0162] [Comparative Example]

[0163] Except for using C60 fullerene instead of phthalocyanine as the material for hole blocking layer 5, the same process as in the embodiment was performed to obtain the photoelectric conversion element. Figure 12 The diagram shows a schematic configuration of the photoelectric conversion element in the comparative example.

[0164] (Measurement of ionization potential and electron affinity of materials)

[0165] For each material used in the examples and comparative examples, ionization potential and electron affinity were measured.

[0166] In the measurement of ionization potential, firstly, samples of the materials used in the examples and the materials used in the comparative examples were prepared, with ITO film deposited on a glass substrate. Next, for the prepared samples, an atmospheric photoelectron spectrometer (AC-3, manufactured by Riken Keiki Co., Ltd.) was used to measure the number of photoelectrons when the energy of ultraviolet irradiation changed, and the energy position at which photoelectrons began to be detected was set as the ionization potential.

[0167] In the measurement of electron affinity, firstly, samples of the materials used in the examples and the materials used in the comparative examples were prepared and deposited on a quartz substrate. Next, for the prepared samples, the absorption spectrum was measured using a spectrophotometer (U4100, manufactured by Hitachi High Technology Co., Ltd.), and the optical band gap was calculated based on the absorption end of the obtained absorption spectrum. Electron affinity was estimated by subtracting the ionization potential obtained from the above ionization potential measurement from the calculated optical band gap.

[0168] The ionization potentials and electron affinities of the materials used in the examples are shown in Table 1. Furthermore, the ionization potentials and electron affinities of the materials used in the comparative examples are shown in Table 2.

[0169] [Table 1]

[0170]

[0171] [Table 2]

[0172]

[0173] As shown in Table 1, in the photoelectric conversion element of the embodiment, the ionization potential of material A constituting electron blocking layer 3 is 5.8 eV, and the ionization potential of material C, which serves as a donor organic semiconductor material in photoelectric conversion layer 4, is 5.5 eV. That is, in the photoelectric conversion element of the embodiment, the ionization potential of electron blocking layer 3 is greater than the ionization potential of the donor organic semiconductor material in photoelectric conversion layer 4.

[0174] Furthermore, in the photoelectric conversion element of the embodiment, the electron affinity of material C constituting hole blocking layer 5 is 3.4 eV, while the electron affinity of material B, which is an acceptor organic semiconductor material included in photoelectric conversion layer 4, is 4.2 eV. That is, in the photoelectric conversion element of the embodiment, the electron affinity of hole blocking layer 5 is smaller than the electron affinity of the acceptor organic semiconductor material included in photoelectric conversion layer 4.

[0175] Furthermore, in the photoelectric conversion element of this embodiment, the difference in electron affinity between the acceptor organic semiconductor material included in the photoelectric conversion layer 4 and the hole blocking layer 5 is 0.8 eV, and the difference in ionization potential between the donor organic semiconductor material included in the photoelectric conversion layer 4 and the electron blocking layer 3 is 0.3 eV. That is, in the photoelectric conversion element of this embodiment, the difference in electron affinity between the acceptor organic semiconductor material included in the photoelectric conversion layer 4 and the hole blocking layer 5 is greater than the difference in ionization potential between the donor organic semiconductor material included in the photoelectric conversion layer 4 and the electron blocking layer 3.

[0176] In addition, in the photoelectric conversion element of the embodiment, the material of the hole blocking layer 5 is the same as the donor organic semiconductor material contained in the photoelectric conversion layer 4, but it can be different as long as the material is in the above-mentioned energy relationship.

[0177] Furthermore, as shown in Table 2, in the comparative example photoelectric conversion element, the electron affinity of material B constituting hole blocking layer 5 is 4.2 eV, and the ionization potential is 6.2 eV. Moreover, in the comparative example photoelectric conversion element, the difference in electron affinity between the acceptor organic semiconductor material included in photoelectric conversion layer 4 and hole blocking layer 5 is 0.0 eV, and the difference in ionization potential between the donor organic semiconductor material included in photoelectric conversion layer 4 and electron blocking layer 3 is 0.3 eV. That is, in the comparative example photoelectric conversion element, the difference in electron affinity between the acceptor organic semiconductor material included in photoelectric conversion layer 4 and hole blocking layer 5 is smaller than the difference in ionization potential between the donor organic semiconductor material included in photoelectric conversion layer 4 and electron blocking layer 3.

[0178] (Evaluation of parasitic sensitivity)

[0179] For the photoelectric conversion elements of the embodiments and comparative examples, the current density was measured in bright and dark conditions to evaluate parasitic sensitivity. In the current density measurement, a semiconductor device parameter analyzer (B1500A, manufactured by Keysight Technologies) was used. Specifically, the current-voltage characteristics in bright and dark conditions were measured by varying the bias applied between a pair of electrodes of the photoelectric conversion element, namely the upper electrode 6 and the lower electrode 2.

[0180] In addition, regarding the reverse bias and forward bias, applying a negative voltage to the lower electrode 2 or a positive voltage to the upper electrode 6 is defined as reverse bias, and applying a positive voltage to the lower electrode 2 or a negative voltage to the upper electrode 6 is defined as forward bias.

[0181] exist Figure 13 The text indicates the current density in bright and dark conditions when a bias voltage is applied to the photoelectric conversion element of the embodiment. On the other hand, in... Figure 14 The values ​​represent the current densities in bright and dark conditions when a bias voltage is applied to the photoelectric conversion element of the comparative example. Figure 13 and Figure 14 In the graph, the solid curve represents the IV characteristic of the state after illumination. Furthermore, in... Figure 13 and Figure 14 In the diagram, the dashed curve represents the IV characteristics in the state without illumination. Furthermore, in... Figure 13 and Figure 14 In the diagram, the vertical axis represents the current density in both logarithmic and absolute values, and the horizontal axis represents the voltage on the usual axis.

[0182] like Figure 14 As shown, in the comparative photoelectric conversion element, due to the difference in current density between dark and bright conditions, except for a very small bias voltage near 0V, the parasitic sensitivity increases regardless of the voltage set during the non-exposure period, making it almost impossible to find a suitable voltage for the non-exposure period. In contrast, as... Figure 13 As shown, in the photoelectric conversion element of the embodiment, there is almost no difference in current density between bright and dark times in a wide bias range below 0V. By setting the voltage during non-exposure periods to make the bias voltage fall within this range, parasitic sensitivity can be reduced.

[0183] As described above, it has been confirmed that in the photoelectric conversion element of the imaging device of this disclosure, such as the photoelectric conversion element of the embodiment, the difference in electron affinity between the acceptor organic semiconductor material contained in the photoelectric conversion layer 4 and the hole blocking layer 5 is greater than the difference in ionization potential between the donor organic semiconductor material contained in the photoelectric conversion layer 4 and the electron blocking layer 3, thereby suppressing the difference in current density between bright and dark conditions and achieving the effect of reducing parasitic sensitivity.

[0184] The imaging device of this disclosure has been described above based on the embodiments and examples, but this disclosure is not limited to these embodiments and examples. Various modifications to the embodiments and examples that can be conceived by those skilled in the art, as well as other forms constructed by combining some of the constituent elements of the embodiments and examples, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0185] Industrial availability

[0186] The camera device disclosed herein can be applied to a wide variety of camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, rangefinder cameras, microscope cameras, drone cameras, and robot cameras.

[0187] Label Explanation

[0188] 1 Support base plate

[0189] 2 Lower electrode

[0190] 3 Electron blocking layer

[0191] 4. Photoelectric conversion layer

[0192] 4A Donor Organic Semiconductor Materials

[0193] 4B Acceptor-based organic semiconductor materials

[0194] 5. Cavity blocking layer

[0195] 6. Upper electrode

[0196] 10 Photoelectric conversion element

[0197] 10A Photoelectric Conversion Unit

[0198] 19. Voltage supply circuit

[0199] 20 Horizontal Signal Readout Circuit

[0200] 21 Amplifying Transistors

[0201] 22 Reset transistor

[0202] 23 Address Transistors

[0203] Impurity regions 21D, 21S, 22D, 22S, 23S

[0204] 21G, 22G, 23G gate electrodes

[0205] 21X, 22X, 23X gate insulating layers

[0206] 24 pixels

[0207] 25 Vertical Scanning Circuit

[0208] 26 Opposite electrode signal lines

[0209] 27 Vertical signal lines

[0210] 28 Load Circuit

[0211] 29-column signal processing circuits

[0212] 31 Power Wiring

[0213] 32 Differential Amplifier

[0214] 33 Feedback Line

[0215] 34 Charge accumulation nodes

[0216] 35 Charge Detection Circuit

[0217] 36 address signal lines

[0218] 37 Reset signal line

[0219] 40 Semiconductor substrate

[0220] 41 Component Separation Area

[0221] 50 interlayer insulation layers

[0222] 51, 53, 54 Contact plugs

[0223] 52 Wiring

[0224] 60 color filter

[0225] 61 Microlenses

[0226] 100 camera devices

Claims

1. A camera device, wherein, It has multiple pixels, The aforementioned pixels include: Electrode 1; Second electrode; The photoelectric conversion layer, located between the first electrode and the second electrode, contains donor semiconductor material and acceptor semiconductor material to generate electron-hole pairs; The first charge blocking layer is located between the first electrode and the photoelectric conversion layer. A second charge-blocking layer is located between the second electrode and the photoelectric conversion layer; and The charge accumulation region is electrically connected to the second electrode mentioned above, and accumulates the electrons as signal charge. The absolute value of the electron affinity of the second charge-blocking layer is less than the absolute value of the electron affinity of the acceptor semiconductor material. The absolute value of the ionization potential of the first charge-blocking layer is greater than the absolute value of the ionization potential of the donor semiconductor material. The difference between the absolute value of the ionization potential of the donor semiconductor material and the absolute value of the ionization potential of the first charge barrier layer is greater than the difference between the absolute value of the electron affinity of the acceptor semiconductor material and the absolute value of the electron affinity of the second charge barrier layer.

2. The camera device as claimed in claim 1, wherein, It also includes a voltage supply circuit, which is electrically connected to the first electrode to impart a potential difference between the first electrode and the second electrode. The voltage supply circuit described above supplies a first voltage to the first electrode during the first period and a second voltage different from the first voltage during the second period.

3. The camera device as described in claim 2, wherein, The photoelectric conversion efficiency of the aforementioned plurality of pixels in the first period is different from that of the aforementioned plurality of pixels in the second period.

4. The camera device as described in claim 2, wherein, The aforementioned camera device operates using a global shutter mode that unifies the timing of exposures between the aforementioned multiple pixels. During the aforementioned exposure period, the aforementioned signal charge is accumulated in the aforementioned charge accumulation region.

5. The camera device as claimed in claim 4, wherein, The first period mentioned above refers to the aforementioned exposure period. The second period mentioned above is a non-exposure period, which is different from the exposure period mentioned above.

6. The camera device as claimed in claim 5, wherein, By supplying the second voltage to the first electrode through the voltage supply circuit, the electrons and holes recombine in the photoelectric conversion layer.

7. The camera device as claimed in claim 5, wherein, By supplying the first voltage to the first electrode through the voltage supply circuit, the sensitivity of photoelectric conversion is generated in the photoelectric conversion layer.

8. The camera device as claimed in claim 3, wherein, The first period and the second period mentioned above are included in one of more than one exposure periods within the same frame. During one or more exposures, the signal charge is accumulated in the charge accumulation region.

9. The camera device as claimed in claim 1, wherein, The aforementioned donor semiconductor materials are donor organic semiconductor materials. The aforementioned receptor semiconductor material is a receptor organic semiconductor material.

10. The camera device as claimed in claim 1, wherein, The thickness of the first charge-blocking layer mentioned above is 5 nm or more.

11. The camera device as claimed in claim 1, wherein, The thickness of the second charge-blocking layer mentioned above is 5 nm or more.

12. The camera device as claimed in claim 1, wherein, The first electrode mentioned above is a transparent electrode.

13. The camera device as claimed in claim 1, wherein, The work function of the first electrode is greater than or equal to the work function of the second electrode.

Images