Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate and a light-shielding layer. The base substrate includes a display area, which includes multiple repeating units. Each of the multiple repeating units includes a transparent area and a pixel area. The pixel area includes multiple sub-pixels. Each of the multiple sub-pixels includes a sub-pixel driving circuit and a light-emitting element. The light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first and second electrodes. The light-shielding layer is disposed on the base substrate and is located on a side of the sub-pixel driving circuit that is close to the base substrate. At least a portion of the orthographic projection of the light-shielding layer on the base substrate overlaps with the orthographic projection of the sub-pixel driving circuit on the base substrate. The light-shielding layer is connected to the second electrode to serve as an auxiliary electrode for the second electrode. This display substrate can reduce wiring space and improve display transmittance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] In the display field, the market demand for large-size, high-PPI (Pixels Per Inch) transparent display devices is increasing. Transparent display devices can be used in applications such as vehicles, smart homes, and store windows. At the same time, the development of transparent display technology can effectively expand the application areas of OLED (Organic Light-Emitting Diode). Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, comprising a base substrate and a light-shielding layer. The base substrate comprises a display area, wherein the display area comprises a plurality of repeating units arranged in an array, each of the plurality of repeating units comprising a transparent area and a pixel area arranged along a first direction, the pixel area comprising a plurality of sub-pixels, each of the plurality of sub-pixels comprising a sub-pixel driving circuit and a light-emitting element, the light-emitting element being located on a side of the sub-pixel driving circuit away from the base substrate, the sub-pixel driving circuit being configured to drive the light-emitting element to emit light, the light-emitting element comprising a first electrode, a second electrode, and a light-emitting layer located between the first and second electrodes. The light-shielding layer is disposed on the base substrate and located on a side of the sub-pixel driving circuit close to the base substrate, at least a portion of the orthographic projection of the light-shielding layer on the base substrate overlaps with the orthographic projection of the sub-pixel driving circuit on the base substrate, wherein the light-shielding layer is connected to the second electrode to serve as an auxiliary electrode for the second electrode.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel area includes an electrode overlapping area, the electrode overlapping area is located on the side of the pixel area close to the transparent area, the orthographic projection of the electrode overlapping area on the board surface of the base substrate and the orthographic projection of the light-shielding layer on the board surface of the base substrate at least partially overlap, the electrode overlapping area includes a first composite hole structure and a first composite overlapping electrode, and the light-shielding layer is connected to the second electrode through the first composite overlapping electrode and the first composite hole structure.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first composite overlapping electrode includes a first overlapping electrode and a second overlapping electrode, the first composite hole structure includes a first overlapping hole and a second overlapping hole, the first overlapping electrode is connected to the light-shielding layer through the first overlapping hole, the second overlapping electrode is connected to the first overlapping electrode through the second overlapping hole, and the second overlapping electrode is also connected to the second electrode.

[0006] For example, the display substrate provided by at least one embodiment of the present disclosure further includes: a first insulating layer, a second insulating layer, a first conductive layer, a third insulating layer and a first electrode layer, wherein the first insulating layer is located on a side of the light-shielding layer away from the base substrate, the second insulating layer is located on a side of the first insulating layer away from the base substrate, the first conductive layer is located on a side of the second insulating layer away from the base substrate, the third insulating layer is located on a side of the first conductive layer away from the base substrate, the first electrode layer is located on a side of the third insulating layer away from the base substrate, the first overlapping hole includes a first overlapping sub-hole passing through the first insulating layer and a second overlapping sub-hole passing through the second insulating layer, the second overlapping sub-hole is sleeved in the first overlapping sub-hole, the first overlapping sub-hole and the second overlapping sub-hole are configured to expose the light-shielding layer, the second overlapping hole passes through the third insulating layer to expose the first overlapping electrode, the first conductive layer includes the first overlapping electrode, the first electrode layer includes the second overlapping electrode and the first electrode of the light-emitting element, the first electrode and the second overlapping electrode are in the same layer and are configured with the same material, and the first electrode and the second overlapping electrode are spaced apart from each other.

[0007] For example, the display substrate provided in at least one embodiment of the present disclosure also includes a buffer layer, wherein the buffer layer is located between the first insulating layer and the second insulating layer, and the first overlapping hole also includes a third overlapping sub-hole, and the third overlapping sub-hole is arranged between the first overlapping sub-hole and the second overlapping sub-hole, and the third overlapping sub-hole passes through the buffer layer and is configured to expose the light-shielding layer.

[0008] For example, the display substrate provided in at least one embodiment of the present disclosure further includes a passivation layer, wherein the passivation layer is located between the third insulating layer and the first conductive layer, and the second overlapping hole also penetrates the passivation layer.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second overlapping electrode includes a first sub-electrode layer, a second sub-electrode layer and a third sub-electrode layer stacked on each other, the first sub-electrode layer is located on the side of the third sub-electrode layer close to the base substrate, the second sub-electrode layer is located between the first sub-electrode layer and the third sub-electrode layer, and in the direction parallel to the board surface of the base substrate, the orthographic projection of the second sub-electrode layer on the board surface of the base substrate is located in the orthographic projection of the first sub-electrode layer on the board surface of the base substrate, the orthographic projection of the third sub-electrode layer on the board surface of the base substrate is located in the orthographic projection of the first sub-electrode layer on the board surface of the base substrate, and the area of the orthographic projection of the first sub-electrode layer on the board surface of the base substrate is larger than the area of the orthographic projection of the third sub-electrode layer on the board surface of the base substrate.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the projection area of the second sub-electrode layer on the board surface of the base substrate is respectively smaller than the projection areas of the first sub-electrode layer and the third sub-electrode layer on the board surface of the base substrate, the cross-sections of the first sub-electrode layer, the second sub-electrode layer and the third sub-electrode layer are I-shaped, and the first sub-electrode layer is connected to the first overlapping electrode through the second overlapping hole.

[0011] For example, the display substrate provided in at least one embodiment of the present disclosure further includes a pixel defining layer, wherein the pixel defining layer is located on a side of the first electrode away from the base substrate, and in the electrode overlapping area, the pixel defining layer at least partially covers an area of the first sub-electrode layer protruding from the second sub-electrode layer.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting layer of the light-emitting element is stacked on the side of the pixel defining layer away from the base substrate, and the light-emitting layer includes a first part and a second part located in the electrode overlapping area, the first part covers at least a part of the area of the first sub-electrode layer protruding from the second sub-electrode layer, and the second part is located on the side of the third sub-electrode layer away from the base substrate.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second electrode of the light-emitting element includes a first electrode portion and a second electrode portion located in the electrode overlapping area, the first electrode portion is located in an area of the first sub-electrode layer protruding from the second sub-electrode layer, and the first electrode portion is in contact with the first sub-electrode layer and the second sub-electrode layer, the second electrode portion is located on a side of the second portion of the light-emitting layer away from the base substrate, and the orthographic projection of the first portion of the light-emitting layer on the surface of the base substrate at least partially overlaps with the orthographic projection of the first electrode portion on the surface of the base substrate.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate further comprising a filter layer and a black matrix, wherein the filter layer and the black matrix are located on a side of the light-emitting element away from the base substrate. In each pixel region, the black matrix comprises a plurality of light-shielding lines extending along the first direction. The filter layer comprises a first sub-pixel filter region, a second sub-pixel rate filter region, and a third sub-pixel filter region. The first sub-pixel filter region, the second sub-pixel rate filter region, and the third sub-pixel filter region are arranged spaced apart from each other along a second direction different from the first direction. At least a portion of the orthographic projections of the plurality of light-shielding lines on the surface of the base substrate overlaps with the first sub-pixel filter region, the second sub-pixel rate filter region, and the third sub-pixel filter region in the second direction. In addition to the plurality of light-shielding lines, the black matrix does not include any other light-shielding lines extending along the first direction on a side of the filter layer adjacent to the light-transmitting region.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the first direction, on the side of the pixel area close to the light-transmitting area, the orthographic projections of the first sub-pixel filter area, the second sub-pixel filter area, and the third sub-pixel filter area on the surface of the base substrate partially overlap with the orthographic projection of the pixel defining layer on the surface of the base substrate.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first sub-pixel filter area, the second sub-pixel rate filter area, and the third sub-pixel filter area overlap with the pixel defining layer in a direction perpendicular to the base substrate, and the size range along the first direction is 5 microns to 7 microns.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first sub-pixel filter region, the second sub-pixel filter region, and the third sub-pixel filter region are respectively a red light region, a green light region, and a blue light region.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, in each of the pixel areas, the light-shielding layer includes a light-shielding electrode, the light-shielding electrode extends along the second direction, at least part of the orthographic projection of the light-shielding electrode on the board surface of the base substrate overlaps with the orthographic projections of the multiple sub-pixel driving circuits of each of the pixel areas on the board surface of the base substrate, and the light-shielding electrode includes a first end, a middle recess, and a second end in the second direction, the middle recess is located between the first end and the second end, and the widths of the first end and the second end in the first direction are greater than the width of the middle recess in the first direction.

[0019] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a peripheral area, a gate driving circuit and a plurality of gate lines extending along a first direction, wherein the peripheral area at least partially surrounds the display area, the gate driving circuit is located in the peripheral area, the plurality of gate lines are connected to the gate driving circuit and are connected to the sub-pixel driving circuits of the pixel areas of each row of the repeating units extending along the first direction respectively, the gate driving circuit is configured to output gate scanning signals one by one to drive the plurality of sub-pixels of the pixel areas of each row of the repeating units extending along the first direction respectively, the plurality of the repeating units are arranged into N rows extending along the first direction respectively, the gate driving circuit includes N cascaded shift register units, the nth stage shift register unit is connected to the sub-pixel driving circuit of the pixel area of the nth row of repeating units, wherein 1≤n≤N, and N is an integer greater than or equal to 2.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, a plurality of sub-pixel driving circuits in each pixel area are arranged along the first direction, and each sub-pixel driving circuit includes a data writing circuit, a driving circuit, a charge storage circuit, and a sensing circuit. The driving circuit is connected to a first node, a second node, and a third node, and the third node is also connected to a first power supply voltage terminal. The driving circuit is configured to receive the first power supply voltage through the third node, and control the driving current flowing through the light-emitting element under the control of the level of the first node; the data writing circuit is connected to the first node and is configured to receive the gate scanning signal as a scanning driving circuit. signal, and writes a data signal to a first node in response to the scan drive signal; the charge storage circuit is connected to the first node and the second node, and is configured to store the written data signal and the reference voltage signal; the sensing circuit is connected to the second node, configured to receive the gate scan signal as a sensing drive signal, and write the reference voltage signal to the drive circuit or read the sensing voltage signal from the drive circuit in response to the sensing drive signal; the light-emitting element is connected to the second node and a second power supply voltage terminal, and is configured to receive a second power supply voltage through the second power supply voltage terminal, and emit light under the drive of the driving current.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the active layers of the data writing transistor and the driving transistor on the surface of the base substrate overlap with the orthographic projections of the second end portion of the light-shielding electrode on the surface of the base substrate, and the orthographic projections of the active layer of the sensing transistor on the surface of the base substrate overlap with the orthographic projections of the first end portion of the light-shielding electrode on the surface of the base substrate.

[0022] At least one embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1 A schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of a planar layout of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2The schematic cross-sectional view of a partial structure of a display substrate is shown;

[0027] Figure 4 for Figure 3 Schematic diagram of the planar layout of the middle electrode overlap area;

[0028] Figure 5 A schematic diagram of an optical simulation of a display substrate provided by at least one embodiment of the present disclosure;

[0029] Figure 6 A schematic diagram of the layout of a sub-pixel driving circuit and a light-emitting element of a display substrate provided by at least one embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of the layout of a black matrix and a filter layer of a display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 8A A circuit diagram of a sub-pixel driving circuit provided in at least one embodiment of the present disclosure;

[0032] Figure 8B A schematic diagram illustrating the connection between a sub-pixel driving circuit and a register unit circuit of a sub-pixel unit circuit provided by at least one embodiment of the present disclosure;

[0033] Figure 9A A plan view of a light shielding layer provided for at least one embodiment of the present disclosure;

[0034] Figure 9B A plan view of a first insulating layer provided for at least one embodiment of the present disclosure;

[0035] Figure 9C A plan view of a buffer layer provided for at least one embodiment of the present disclosure;

[0036] Figure 9D A plan view of a semiconductor layer provided for at least one embodiment of the present disclosure;

[0037] Figure 9E A layout diagram of a second conductive layer provided in at least one embodiment of the present disclosure;

[0038] Figure 9F A plan view of an interlayer insulating layer provided for at least one embodiment of the present disclosure;

[0039] Figure 9G A plan view of a first conductive layer provided for at least one embodiment of the present disclosure;

[0040] Figure 10 for Figures 9A to 9B Layout diagram after stacking;

[0041] Figure 11A for Figure 10Enlarged view of the middle A1 region;

[0042] Figure 11B for Figure 11A Schematic diagram of the cross section along line B1-B2;

[0043] Figure 11C for Figure 10 Enlarged view of the middle A2 area;

[0044] Figure 12A A plan view of a passivation layer provided for at least one embodiment of the present disclosure;

[0045] Figure 12B A plan view of a third insulating layer provided for at least one embodiment of the present disclosure;

[0046] Figure 12C A plan view of a first sublayer of a first electrode layer provided in at least one embodiment of the present disclosure;

[0047] Figure 12D A plan view of the third sublayer of the first electrode layer provided in at least one embodiment of the present disclosure;

[0048] Figure 12E A plan view of a pixel defining layer provided in at least one embodiment of the present disclosure;

[0049] Figure 13 A schematic diagram of a display device provided in at least one embodiment of the present disclosure; and

[0050] Figures 14A-14F A schematic diagram of a manufacturing process of a display device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which the invention belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present invention clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present invention appears in more than one figure, the component is represented by the same reference numeral in each figure.

[0054] The resolution of large-scale transparent displays commonly found on the market today is around 40 PPI, with relatively few high-PPI products. A bottleneck in today's large-scale, high-PPI transparent display devices is that as the PPI increases, the smaller the pixel size, the greater the metal wiring density, and the wiring density cannot be made too high. Furthermore, since top-emitting white light OLEDs use transparent cathodes with relatively high resistance, auxiliary cathodes must be added to reduce the wiring resistance drop (IR Drop), so conventional auxiliary cathodes also occupy the transparent area of the transparent display device. All of the above reasons result in a smaller transparent area, which affects transmittance and makes the pinhole diffraction effect more likely to occur. This is reflected in the actual experience that objects viewed through the transparent display device have a ghosting phenomenon, which seriously affects the user experience. How to maximize the transparent area while maintaining a high PPI is the key to current transparent display device design.

[0055] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and a light-shielding layer. The base substrate includes a display area, the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along a first direction, the pixel area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the base substrate, the sub-pixel driving circuit is configured to drive the light-emitting element to emit light, the light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The light-shielding layer is provided on the base substrate and is located on a side of the sub-pixel driving circuit close to the base substrate, at least a portion of the orthographic projection of the light-shielding layer on the board surface of the base substrate overlaps with the orthographic projection of the sub-pixel driving circuit on the board surface of the base substrate, and the light-shielding layer is connected to the second electrode to be reused as an auxiliary electrode for the second electrode.

[0056] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate.

[0057] The display substrate provided by the above-mentioned embodiment of the present disclosure uses the shading layer for shading the sub-pixel driving circuit while also connecting it to the second electrode to reuse it as an auxiliary electrode of the second electrode, thereby increasing the space of the transparent area of the display substrate and improving the transmittance of the display substrate. At the same time, since the resistance of the auxiliary electrode reused by the shading layer is smaller, the effect of increasing the resistance of the second electrode is more obvious (that is, the effect of reducing the resistance drop is more obvious).

[0058] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0059] Figure 1 A schematic diagram of a display substrate provided according to at least one embodiment of the present disclosure. Figure 2 A schematic diagram of a planar layout of a display substrate provided in at least one embodiment of the present disclosure. Figure 3 for Figure 2 The figure shows a schematic cross-sectional view of a partial structure of a display substrate.

[0060] For example, Figure 1 As shown, the display substrate 1 includes a base substrate 10. The base substrate 10 includes a display area 101. The display area 101 includes a plurality of repeating units C1 arranged in an array. The plurality of repeating units C1 are arranged in multiple rows along a first direction X and a second direction Y, for example, rows 1 to N extending along the first direction X, and rows 1 and F extending along the second direction Y. Each of the plurality of repeating units C1 includes a transparent region TM10 and a pixel region P10 arranged along the first direction X. The pixel region P10 includes a plurality of sub-pixels. For example, in the embodiment of the present disclosure, the pixel region P10 is taken as including three sub-pixels.

[0061] For example, the base substrate 10 may be a flexible substrate or a rigid substrate. The base substrate 10 may be made of, for example, glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0062] For example, Figure 1 As shown, the display substrate 1 includes a plurality of power lines VDD10 and a plurality of sensing lines SES10. The plurality of power lines VDD10 and the plurality of sensing lines SES10 are disposed on the base substrate 10 and extend along the second direction Y. The plurality of power lines VDD10 and the plurality of sensing lines SES10 are respectively connected to a plurality of sub-pixels and extend to the bonding area 103 of the display substrate 1. The power lines VDD10 are connected to a corresponding column of sub-pixels extending in the second direction Y and provide a second power supply voltage signal. The sensing lines SES10 are connected to a corresponding column of sub-pixels extending in the second direction Y and provide a reference voltage signal. The display substrate also includes a gate drive circuit 13 located in the peripheral area 102 and a plurality of gate lines G10 extending along the first direction X. The gate drive circuit 13 is configured to output gate scan signals row by row to drive the plurality of sub-pixel unit circuits 16. The gate lines G10 are connected to the gate drive circuit 13 and a corresponding row of sub-pixels extending in the first direction X, and provide gate scan signals to activate the sub-pixels.

[0063] For example, Figure 2 and Figure 3 As shown, each of the plurality of sub-pixels includes a sub-pixel driving circuit 1601 (e.g., a first sub-pixel driving circuit P161, a second sub-pixel driving circuit P162, and a third sub-pixel driving circuit P163) and a light-emitting element 160. The light-emitting element 160 is located on a side of the sub-pixel driving circuit 1601 that is away from the substrate 10. The sub-pixel driving circuit 1601 is configured to drive the light-emitting element 160 to emit light. The light-emitting element 160 includes a first electrode 161, a second electrode 162, and a light-emitting layer 163 located between the first electrode 161 and the second electrode 162.

[0064] For example, in some embodiments, each sub-pixel driving circuit 1601 may include a pixel circuit having a circuit structure such as 7T1C, 8T2C, 4T1C or 3T1C in the art. The embodiments of the present disclosure are introduced using a pixel circuit including a 3T1C circuit structure as an example, and the embodiments of the present disclosure are not limited to this.

[0065] For example, Figure 2 and Figure 3As shown, a light shielding layer 131 is disposed on the base substrate 10 and is located on a side of the sub-pixel driving circuit 1601 close to the base substrate 10 to block external light. At least a portion of the orthographic projection of the light shielding layer 131 on the surface of the base substrate 10 (e.g., the upper surface of the base substrate 10) overlaps with the orthographic projection of the sub-pixel driving circuit 1601 on the surface of the base substrate 10. The light shielding layer 131 is connected to the second electrode 162 to serve as an auxiliary electrode for the second electrode 162. The orthographic projection of the light-shielding layer 131 on the surface of the base substrate 10 overlaps with the pixel area P10 of the repeating unit C1, but does not overlap with the transparent area TM10 of the repeating unit C1. The light-shielding layer 131 shields the pixel area P10 and is reused as an auxiliary electrode of the second electrode 162, thereby increasing the space of the transparent area TM10 of the display substrate 1 and improving the transmittance of the display substrate 1. At the same time, since the resistance of the auxiliary electrode reused by the light-shielding layer 131 is smaller, the effect of increasing the resistance of the second electrode 162 is more obvious (that is, the effect of reducing the resistance drop is more obvious).

[0066] For example, the light shielding layer 131 may be made of a metal material, such as silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, molybdenum-neodymium alloy, or any combination thereof.

[0067] For example, Figure 2 and Figure 3 As shown, the pixel area P10 includes an electrode overlapping area 12, which is located on a side of the pixel area P10 close to the transparent area TM10. That is, in a repeating unit C1, the electrode overlapping area 12 is located between the pixel area P10 and the transparent area TM10. The orthographic projection of the electrode overlapping area 12 on the plate surface of the base substrate 10 and the orthographic projection of the light shielding layer 131 on the plate surface of the base substrate 10 at least partially overlap, for example, partially overlap. The electrode overlapping area 12 includes a first composite hole structure and a first composite overlapping electrode. The first composite hole structure is configured to expose the light shielding layer 131. For example, the first composite hole structure includes a first overlapping hole F11 and a second overlapping hole F12. The first composite overlapping electrode is configured to connect the second electrode 162 and the light shielding layer 131. For example, the first composite overlapping electrode includes a first overlapping electrode FD11 and a second overlapping electrode FD12. The light shielding layer 131 is connected to the second electrode 162 through the first composite bonding electrode and the first composite hole structure, so as to be reused as an auxiliary electrode of the second electrode 162 .

[0068] Figure 4 for Figure 3 Schematic diagram of the planar layout of the middle electrode overlapping area.

[0069] For example, Figure 3 and Figure 4As shown, the first composite strapping electrode includes a first strapping electrode FD11 and a second strapping electrode FD12. The first strapping electrode FD11 is located on the side of the second strapping electrode FD11 that is closer to the base substrate 11. The first composite hole structure includes a first strapping hole FK11 and a second strapping hole FK12. The first strapping hole FK11 is located on the side of the second strapping hole FK12 that is closer to the base substrate 10. The first strapping electrode FD11 is connected to the light shielding layer 131 through the first strapping hole FK11, and the second strapping electrode FD12 is connected to the first strapping electrode FD11 through the second strapping hole FK12. The second strapping electrode FK12 is also connected to the second electrode 162. For example, the second strapping electrode FK12 can be indirectly connected to the second electrode 162. The second strapping electrode FK12 is also separated from the second electrode 162 by a light-emitting layer 163, that is, the second strapping electrode FK12 (for example, partially) is connected to the second electrode 162 through the light-emitting layer 163.

[0070] For example, in other embodiments, the second bonding electrode FK12 may be directly connected to the second electrode 162 .

[0071] Figure 8A A circuit diagram of a sub-pixel driving circuit provided in at least one embodiment of the present disclosure.

[0072] For example, Figure 8A As shown, the sub-pixel driving circuit 1601 may adopt a pixel circuit with a 3T1C circuit structure in the art. For example, the sub-pixel driving circuit 1601 includes a data writing transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor CST.

[0073] For example, in some embodiments, Figure 3 As shown, the display substrate further includes a first insulating layer 132 (e.g., a barrier layer), a second insulating layer 134 (e.g., an interlayer insulating layer), a first conductive layer SD, a third insulating layer 136 (e.g., a planarization layer), and a first electrode layer AN. The first insulating layer 132 provides a flat surface for forming the sub-pixel driving circuit 1601 and prevents impurities that may be present in the base substrate 10 from diffusing into the sub-pixel driving circuit or the gate driving circuit 13 and adversely affecting the performance of the display substrate. The thickness of the first insulating layer 132 also prevents parasitic capacitance from being generated between the light shielding layer 131 and other film layers.

[0074] For example, the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0075] For example, the first insulating layer 132 is located on a side of the light-shielding layer 131 away from the base substrate 10. The second insulating layer 134 is located on a side of the first insulating layer 132 away from the base substrate 10. The first conductive layer SD is located on a side of the second insulating layer 134 away from the base substrate 10. The third insulating layer 136 is located on a side of the first conductive layer SD away from the base substrate 10. The first electrode layer AN is located on a side of the third insulating layer 136 away from the base substrate 10. For example, the first electrode layer AN is the film layer where the first electrode 162 of the light-emitting element 160 is located, and the first conductive layer SD is the film layer where the first electrode TSD22 (e.g., source) and the second electrode TSD21 (e.g., drain) of the driving transistor T2 are located.

[0076] For example, the materials of the first insulating layer 132 and the second insulating layer 134 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0077] For example, the material of the first conductive layer SD may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed of molybdenum, aluminum, and titanium. For example, the multilayer structure is a multi-metal stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of the functional layers.

[0078] For example, the material of the third insulating layer 136 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, and the embodiments of the present disclosure are not limited to this.

[0079] For example, in some embodiments, Figure 3 and Figure 4As shown, the first strapping hole FK11 includes a first strapping sub-hole FK111 that penetrates the first insulating layer 132 and a second strapping sub-hole FK112 that penetrates the second insulating layer 134. The second strapping sub-hole FK112 is nested within the first strapping sub-hole FK111, i.e., the orthographic projection of the second strapping sub-hole FK112 on the surface of the base substrate 10 is located at the orthographic projection of the first strapping sub-hole FK111 on the surface of the base substrate 10. The first strapping sub-hole FK111 and the second strapping sub-hole FK112 are configured to expose the light shielding layer 131. The first strapping electrode FD11 is located on the side of the second insulating layer 134 away from the base substrate 10. The second strapping hole FK12 penetrates the third insulating layer 136 to expose the first strapping electrode FD11. The first conductive layer SD includes the first strapping electrode FD11. The first electrode layer AN includes the second strapping electrode FD12 and the first electrode 161 of the light-emitting element 160. The first electrode 161 and the second strapping electrode FD12 are formed in the same layer and made of the same material, and are spaced apart from each other. That is, although the first electrode 161 and the second strapping electrode FD12 are formed in the same layer and made of the same material, for example, produced through the same process, they are disconnected or otherwise disconnected from each other. The second strapping electrode FD12 is configured to connect to the second electrode 162 of the light-emitting element and the first strapping electrode FD11. Fabricating the first electrode 161 and the second strapping electrode FD12 in the same film layer can reduce the patterning process and the thickness of the display substrate.

[0080] For example, in some embodiments, Figure 3 and Figure 4 As shown, the display substrate further includes a buffer layer 133. The buffer layer 133 is located between the first insulating layer 132 and the second insulating layer 134. The first overlapping hole FK11 further includes a third overlapping sub-hole FK113. The third overlapping sub-hole FK113 is nested between the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112. The third overlapping sub-hole FK113 penetrates the buffer layer 133 and is configured to expose the light shielding layer 131. The orthographic projection of the third overlapping sub-hole FK113 on the surface of the base substrate 10 is located within the orthographic projection of the first overlapping sub-hole FK111 on the surface of the base substrate 10. The first overlapping hole FK11 is a nested hole formed by the third overlapping sub-hole FK113, the first overlapping sub-hole FK111, and the second overlapping sub-hole FK112.

[0081] For example, the material of the buffer layer may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0082] For example, in other embodiments, after forming the second insulating layer 134 on the display substrate, the second overlapping sub-hole FK112 may be etched first, and then the third overlapping sub-hole FK113 may be etched. In this case, the second overlapping sub-hole FK112 and the third overlapping sub-hole FK113 have substantially the same size. The second insulating layer 134 will not contact the third overlapping sub-hole FK113.

[0083] For example, Figure 3 and Figure 4 As shown, the display substrate further includes a passivation layer 135. The passivation layer 135 is located between the third insulating layer 136 and the first conductive layer SD (first bonding electrode FD11). The second bonding hole FK12 also penetrates the passivation layer 135. The passivation layer 135 can protect the first conductive layer SD from corrosion by water vapor.

[0084] For example, the material of the passivation layer 135 may include an organic insulating material or an inorganic insulating material, such as silicon nitride material, which has a high dielectric constant and good hydrophobicity and can well protect the sub-pixel driving circuit from being corroded by water vapor.

[0085] For example, in some embodiments, Figure 4 As shown, the width of the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 in the first direction X can be approximately 3.5-4.5 microns, for example, approximately 4 microns. For example, the width of the third overlapping sub-hole FK113 in the first direction X can be approximately 7.5-8.5 microns, for example, approximately 8 microns. For example, the width of the second overlapping hole FK12 in the first direction X can be approximately 6.5-7.5 microns, for example, approximately 7 microns. For example, the sizes of the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 can be equal or unequal. The sizes of the first overlapping sub-hole FK111, the second overlapping sub-hole FK112, the third overlapping sub-hole FK113 and the second overlapping hole FK12 are selected by the display substrate during the manufacturing process, and the embodiments of the present disclosure are not limited thereto.

[0086] It should be noted that, in the embodiments of the present disclosure, “about” means that the value may fluctuate within a range of, for example, ±15% or ±5%.

[0087] For example, in some embodiments, Figure 3As shown, the first electrode layer AN includes a first layer AN1, a second layer AN2, and a third layer AN3. The first layer AN1 is located on the side of the third insulating layer 136 away from the substrate 10, the third layer AN3 is located on the side of the first layer AN1 away from the substrate 10, and the second layer AN2 is located between the first layer AN1 and the third layer AN3. The first electrode 161 of the light-emitting element 160 has a three-layer structure, disposed on the same layer as the first layer AN1, the second layer AN2, and the third layer AN3. The cross-section of the first electrode 161 is an I-shaped structure. The second electrode 162 can be provided in part or all of the display area 101, allowing it to be formed across the entire surface during the manufacturing process.

[0088] For example, the first electrode 161 of the light-emitting element may include a reflective layer, and the second electrode 162 of the light-emitting element may include a transparent layer or a semi-transparent layer. Thus, the first electrode 161 can reflect light emitted from the light-emitting layer 163, and some of this light is emitted into the external environment through the second electrode 162, thereby improving light extraction efficiency. When the second electrode 162 includes a semi-transmissive layer, some of the light reflected by the first electrode 161 is reflected again by the second electrode 162, so that the first electrode 161 and the second electrode 162 form a resonant structure, thereby improving light extraction efficiency.

[0089] For example, the materials of the first layer AN1 and the second layer AN2 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. For example, the material of the third layer 163 may include an alloy material, such as AlNd, etc.

[0090] For example, the light-emitting layer 163 may include small molecule organic materials or polymer molecule organic materials, and may be fluorescent or phosphorescent, emitting red, green, blue, or white light. Furthermore, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, as needed. For QLEDs, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, with a particle size of 2-20 nm. In the disclosed embodiments, the light-emitting layer 163 emitting white light is used as an example.

[0091] For example, the second electrode 162 may include various conductive materials. For example, the second electrode 162 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag). For example, the second electrode 162 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0092] For example, in some embodiments, Figure 3As shown, the second bonding electrode FD12 includes a first sub-electrode layer FD121, a second sub-electrode layer FD122, and a third sub-electrode layer FD123, which are stacked one on top of the other. The first sub-electrode layer FD121 is located on the side of the third sub-electrode layer FD123 that is closest to the base substrate 10, while the second sub-electrode layer FD122 is located between the first and third sub-electrode layers FD121 and FD123. The first sub-electrode layer FD121 is formed from the same layer and material as the first layer AN1 of the first electrode layer AN. The second sub-electrode layer FD122 is formed from the same layer and material as the second layer AN2 of the first electrode layer AN. The third sub-electrode layer FD123 is formed from the same layer and material as the third layer AN3 of the first electrode layer AN. In a direction parallel to the surface of the base substrate 10, at least one side of the first sub-electrode layer FD121 protrudes circumferentially beyond the second sub-electrode layer FD122. For example, as shown in the figure, the first sub-electrode layer FD121 protrudes circumferentially beyond the second sub-electrode layer FD122. The orthographic projection of the second sub-electrode layer FD122 on the surface of the base substrate 10 lies within the orthographic projection of the first sub-electrode layer FD121 on the surface of the base substrate 10. The orthographic projection of the third sub-electrode layer FD123 on the surface of the base substrate 10 lies within the orthographic projection of the first sub-electrode layer FD121 on the surface of the base substrate 10. The projected area of the first sub-electrode layer FD121 on the surface of the base substrate 10 is larger than the projected area of the third sub-electrode layer FD123 on the surface of the base substrate 10. In other words, the orthographic projection of the first sub-electrode layer FD121 on the surface of the base substrate 10 has the largest projected area, the orthographic projection of the third sub-electrode layer FD123 on the surface of the base substrate 10 has the second largest projected area, and the orthographic projection of the second sub-electrode layer FD122 on the surface of the base substrate 10 has the smallest projected area. Therefore, the portion of the first sub-electrode layer FD121 that protrudes beyond the second sub-electrode layer FD122 can be used for connection to the second electrode 162.

[0093] For example, in some embodiments, Figure 3 As shown, the projected area of the second sub-electrode layer FD122 on the surface of the base substrate 10 is smaller than the projected areas of the first sub-electrode layer FD121 and the third sub-electrode layer FD123 on the surface of the base substrate 10. The first sub-electrode layer FD121, the second sub-electrode layer FD122, and the third sub-electrode layer FD123 have an I-shaped cross-section, and the first sub-electrode layer FD121 is connected to the first bonding electrode FD11 via the second bonding hole FK12.

[0094] For example, in some embodiments, Figure 4As shown, the width D3 of the first sub-electrode layer FD121 in the first direction X can be approximately 28-30 microns, for example, approximately 29 microns. The length D4 of the first sub-electrode layer FD121 in the second direction Y can be approximately 30-31 microns, for example, approximately 31.5 microns. The distance D1 between the third sub-electrode layer FD123 (or the second sub-electrode layer FD122) and the edge of the first sub-electrode layer FD121 in the first direction X can be, for example, approximately 5.5-6.5 microns, for example, approximately 6 microns.

[0095] For example, in some embodiments, the display substrate 10 further includes a pixel-defining layer 138. The pixel-defining layer 138 is located on the side of the first electrode 161 away from the base substrate 10. The pixel-defining layer 138 includes multiple openings, some of which define sub-pixels and correspond to the light-emitting areas of the light-emitting element 160. For example, the light-emitting layer 163 is also entirely disposed on the side of the second electrode 162 that is closer to the base substrate 10. In the electrode overlap region 12, the pixel-defining layer 138 further includes an opening, and the pixel-defining layer 138 partially covers the area of the first sub-electrode layer FD121 that protrudes from the second sub-electrode layer FD122. For example, the pixel-defining layer 138 extends to the area of the first sub-electrode layer FD121 that protrudes from the second sub-electrode layer FD122 and covers the edge of the first sub-electrode layer FD121. Thus, the pixel-defining layer 138 can prevent discharge in the light-emitting layer 163 due to burrs on the corners of the first sub-electrode layer FD121, resulting in process defects.

[0096] For example, in some embodiments, Figure 4 As shown, a distance D2 between an edge of the pixel defining layer 138 and an edge of the first sub-electrode layer FD121 in the second direction Y may be, for example, approximately 2.5-3.5 micrometers, for example, approximately 3 micrometers.

[0097] For example, in some embodiments, Figure 3 As shown, the light-emitting layer 163 of the light-emitting element 160 is stacked on the side of the pixel-defining layer 138 away from the base substrate 10. The light-emitting layer 163 includes a first portion 1631 and a second portion 1632 located in the electrode-bonding region 12. The first portion 1631 covers at least a portion of the first sub-electrode layer FD121 that protrudes from the second sub-electrode layer FD122, and the first portion 1631 is in contact with the first sub-electrode layer FD121. The second portion 1632 is located on the side of the third sub-electrode layer FD123 away from the base substrate 10.

[0098] For example, in some embodiments, Figure 3As shown, the second electrode 162 of the light-emitting element 160 includes a first electrode portion 1621 and a second electrode portion 1622 located in the electrode overlapping region 12. The first electrode portion 1621 is located in a region of the first sub-electrode layer FD121 that protrudes beyond the second sub-electrode layer FD122, and contacts the first and second sub-electrode layers FD121 and FD122. The second electrode portion FD122 is located on a side of the second portion 1632 of the light-emitting layer 163 that is away from the base substrate 10. The orthographic projection of the first portion 1631 of the light-emitting layer 163 on the surface of the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode portion 1621 on the surface of the base substrate 10. That is, in the area of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122, the first electrode portion 1621 is in contact with the first portion 1631 of the light-emitting layer 163, the upper surface of the first sub-electrode layer FD121 (parallel to the plate surface of the base substrate 10), and the side surface of the second sub-electrode layer FD122 (perpendicular to the plate surface of the base substrate 10).

[0099] For example, in some embodiments, the display substrate 10 further includes a semiconductor layer ACT, a fourth insulating layer 137 (e.g., a gate insulating layer), and a second conductive layer GATE. The semiconductor layer ACT is located on the side of the buffer layer 133 away from the base substrate 10. The fourth insulating layer 137 is located on the side of the semiconductor layer ACT away from the base substrate 10. The second conductive layer GATE is located between the second insulating layer 134 and the fourth insulating layer 137. The semiconductor layer ACT includes an active layer TA2 of the drive transistor T2. The second conductive layer GATE includes a gate electrode TG2 of the drive transistor T2. The first conductive layer SD includes a first electrode TSD21 and a second electrode TSD22 of the drive transistor T2. The second conductive layer TA2 includes a source region corresponding to the first electrode TSD21 and a drain region corresponding to the second electrode TSD22. The semiconductor layer ACT also includes a first plate CST1 of the storage capacitor CST. The first conductive layer SD also includes a second plate CST2 of the storage capacitor CST. The second insulating layer 134 is interposed between the first plate CST1 and the second plate CST2. For example, the second electrode plate CST2 is connected to the first electrode TSD21 of the driving transistor T2. For example, the first electrode 161 of the light-emitting element 160 is connected to the first conductive layer via a via hole that penetrates the passivation layer 135 and the third insulating layer 136. For example, the portion of the first electrode 161 of the light-emitting element 160 that is in the same layer as the first sublayer AN1 of the first electrode layer AN is connected to the first electrode TSD21 of the driving transistor T2 via a via hole that penetrates the passivation layer 135 and the third insulating layer 136. For example, the portion of the first electrode 161 of the light-emitting element 160 that is in the same layer as the first sublayer AN1 of the first electrode layer AN is connected to the second electrode plate CST2, thereby connecting to the first electrode TSD21 of the driving transistor T2.

[0100] For example, in other embodiments, a portion of the first electrode 161 of the light-emitting element 160 that is in the same layer as the first sublayer AN1 of the first electrode layer AN is directly connected to the first electrode TSD21 of the driving transistor T2. That is, in a cross-sectional view perpendicular to the surface of the base substrate 10, the first electrode TSD21 of the driving transistor T2 is spaced apart from the first electrode plate 1 of the storage capacitor CST.

[0101] It should be noted that the cross-sectional structures of other transistors of the sub-pixel driving circuit 160 , such as the data writing transistor T1 and the driving transistor T2 , may be the same as the cross-sectional structure of the sensing transistor T3 , and are not described in detail here.

[0102] It should be noted that, in the embodiment of the present disclosure, the first electrode represents the source of the transistor, and the second electrode represents the drain of the transistor. The above can also be interchanged, and the embodiment of the present disclosure is not limited to this.

[0103] For example, the material of the semiconductor layer ACT may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0104] For example, the material of the fourth insulating layer 137 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0105] For example, the material of the second conductive layer GATE may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium. For example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti)).

[0106] For example, in some embodiments, the display substrate 10 further includes an encapsulation layer 139. The encapsulation layer 139 is disposed on a side of the light-emitting element 160 away from the base substrate 10. The encapsulation layer 139 seals the light-emitting element 160, thereby reducing or preventing degradation of the light-emitting element 160 caused by moisture and / or oxygen in the environment. The encapsulation layer 139 may be a single-layer structure or a composite layer structure including a stacked structure of an inorganic layer and an organic layer. The encapsulation layer 139 includes at least one encapsulation sublayer. For example, the encapsulation layer 139 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially disposed.

[0107] For example, the material of the encapsulation layer 139 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, to planarize the surface of the display substrate and relieve stress on the first and second inorganic encapsulation layers. A water-absorbing material such as a desiccant may also be included to absorb intrusive water, oxygen, and the like.

[0108] For example, in some embodiments, Figure 3 As shown, the display substrate 1 further includes a filter layer LG and a black matrix BM. The filter layer LG and the black matrix BM are located on the side of the light-emitting element 160 away from the base substrate 10, that is, on the encapsulation layer 139. The filter layer LG and the black matrix BM can be partially stacked. In the stacked portion of the filter layer LG and the black matrix BM, the black matrix BM is located on the side of the filter layer LG closer to the base substrate 10.

[0109] Figure 6 A schematic diagram of the layout of a sub-pixel driving circuit and a light-emitting element of a display substrate provided in at least one embodiment of the present disclosure. Figure 7 A schematic diagram of the layout of a black matrix and a filter layer of a display substrate provided in at least one embodiment of the present disclosure.

[0110] For example, in some embodiments, in combination Figure 6 and Figure 7 As shown, in each pixel area P10, the black matrix BM includes a plurality of light shielding lines extending along the first direction X (eg Figure 7BM1 / BM2 are shown. The filter layer LG includes a first sub-pixel filter region LG1, a second sub-pixel rate filter region LG2, and a third sub-pixel filter region LG3. The first sub-pixel filter region LG1, the second sub-pixel rate filter region LG2, and the third sub-pixel filter region LG3 are spaced apart from each other along the second direction Y. At least a portion of the orthographic projection of the plurality of light-shielding lines onto the surface of the base substrate 10 overlaps with the spacing between the first sub-pixel filter region LG1, the second sub-pixel rate filter region LG2, and the third sub-pixel filter region LG3 in the second direction Y. For example, at least a portion of the orthographic projection of the plurality of light-shielding lines BM1 onto the surface of the base substrate 10 overlaps with the spacing between the first sub-pixel filter region LG1 and the second sub-pixel rate filter region LG2 in the second direction Y. For example, at least a portion of the orthographic projection of the plurality of light-shielding lines BM2 onto the surface of the base substrate 10 overlaps with the spacing between the second sub-pixel rate filter region LG2 and the third sub-pixel filter region LG3 in the second direction Y. For example, the first sub-pixel light filtering region LG1, the second sub-pixel light filtering region LG2, and the third sub-pixel light filtering region LG3 correspond to the light-emitting elements of the sub-pixels of the pixel region P10, respectively. In addition to the plurality of light-shielding lines, on the side of the filter layer LG near the light-transmitting region TM10, the black matrix BM does not include other light-shielding lines that do not extend along the first direction X. In other words, the black matrix BM does not include light-shielding lines that extend in other directions between the light-transmitting region TM10 and the pixel region P10, and only includes Figure 7 As shown in FIG, the light shielding lines extending along the first direction are arranged in the spacing area between the first sub-pixel light filtering area LG1, the second sub-pixel light filtering area LG2, and the third sub-pixel light filtering area LG3 in the second direction Y. Thus, the area of the light transmission area TM10 can be increased to increase the transmittance of the display substrate.

[0111] For example, the angle between the first direction X and the second direction Y referred to in the present disclosure is between 70° and 90°, inclusive. For example, the angle between the first direction X and the second direction Y is 70°, 90°, or 80°, etc., which can be set according to actual circumstances and is not limited in the embodiments of the present disclosure. For example, the angle between the first direction X and the second direction Y can also be 75°, 85°, etc.

[0112] For example, the material of the filter layer may include a resin material doped with a colorant, such as a dye or pigment, so that the resin material, such as a polymer resin material, has color. For example, the material of the black matrix BM may include an opaque black resin material.

[0113] For example, in some embodiments, the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, and the third sub-pixel filter region LG3 are respectively a red light region, a green light region, and a blue light region, that is, they transmit red light, green light, and blue light, respectively. The order of the colors of the light transmitted by the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, and the third sub-pixel filter region LG3 can be interchanged, but the embodiments of the present disclosure are not limited thereto.

[0114] For example, in some embodiments, Figure 2 As shown, in the first direction X, on the side of the pixel area P10 close to the light-transmitting area TM10, the orthographic projections of the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 on the surface of the base substrate 10 partially overlap with the orthographic projections of the pixel defining layer 138 on the surface of the base substrate 10. That is, in a direction perpendicular to the surface of the base substrate 10, on the side close to the light-transmitting area TM10, the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 extend beyond the edge of the pixel defining layer 138 and above the pixel defining layer 138. Figure 3 As shown, the orthographic projection of the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, or the third sub-pixel filter region LG3 on the surface of the base substrate 10 overlaps with the pixel defining layer 138 on the surface of the base substrate 10 by a length D5. Thus, without guaranteeing the occupation of the transparent area, light leakage from the light-emitting area of the light-emitting element can be reduced at different angles, thereby reducing color attenuation of the display substrate.

[0115] Figure 5 A schematic diagram of an optical simulation of a display substrate provided by at least one embodiment of the present disclosure.

[0116] For example, in some embodiments, the portions of the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, and the third sub-pixel filter region LG3 that overlap with the pixel defining layer 138 in a direction perpendicular to the base substrate 10 have a size range along the first direction X of, for example, approximately 5 microns to 7 microns, for example, approximately 6 microns, thereby achieving a better display effect.

[0117] For example, Figure 5 As shown, taking the case where the filter area exceeds the pixel defining layer 138 in the first direction X as an example, optical simulation is performed in the second direction Y to select a suitable value range for the filter area to exceed the pixel defining layer 138 . Figure 5 The length D5 of the middle filter layer extending beyond the pixel defining layer 138 in the first direction X (also as shown in FIG. Figure 3The size range of the length D5 is, for example, about 5 microns to 7 microns, for example, about 6 microns. At this time, the effect of preventing light leakage is better and the display effect requirements can be met. When the value of the length D5 is larger, the effect of preventing light leakage is better. If the design size allows, a larger length D5 can also be selected. It should be noted that Figure 5 The pixel defining layer 138 in FIG. 1 shows an opening area (ie, the pixel defining layer 138 is shown in reverse, and the marked area is the dug-out area).

[0118] For example, in some embodiments, Figure 3 As shown, the display substrate further includes a light-transmitting layer 1310 and a protective layer 1311. The light-transmitting layer 1310 is disposed on the side of the filter layer LG away from the base substrate 10. The protective layer 1311 is disposed on the side of the light-transmitting layer 1310 away from the base substrate 10. For example, the protective layer 1311 can serve as a cover plate. The material of the protective layer 1311 can include a flexible material, such as transparent polyimide (CPI), polyethylene terephthalate (PET), or cycloolefin polymer (COP). For example, the light-transmitting layer 1310 can be an optical adhesive layer, which can both transmit light and act as an adhesive. For example, the material of the light-transmitting layer 1310 can include a transparent insulating material, such as polyimide, resin, or a transparent organic material such as a special double-sided adhesive (OCA) with an optically transparent substrate.

[0119] For example, in some embodiments, Figure 1 As shown, the gate drive circuit 13 is configured to output gate scanning signals through the gate lines G10 to drive the operation of the plurality of sub-pixels of the pixel area P10 of each row of repeating units C1 extending along the first direction X. The plurality of repeating units C1 are arranged in N rows extending along the first direction, and the gate drive circuit 13 includes N cascaded shift register units 170 (e.g., Figure 8B As shown), the n-th stage shift register unit 170 is connected to the sub-pixel driving circuit 1601 of the pixel area P10 of the n-th row of repeating unit C1, wherein 1≤n≤N, and N is an integer greater than or equal to 2.

[0120] For example, Figure 2 As shown, the multiple sub-pixel driving circuits of the pixel area P10 of each repeating unit C1 are arranged along the first direction X. The multiple sub-pixel driving circuits are respectively connected to different light-emitting elements.

[0121] As shown in FIG8A , the sub-pixel driving circuit 1601 of each of the plurality of sub-pixels includes a data write circuit 1603, a drive circuit 1604, a charge storage circuit 1606, and a sensing circuit 1605. The drive circuit 1604 is connected to a first node G, a second node S, and a third node D. The third node D is also connected to a first power supply voltage terminal ELVDD. For example, the first power supply voltage terminal ELVDD is connected to a power line VDD10 that provides a first power supply voltage. The drive circuit 1604 is configured to control the drive current flowing through the light-emitting element 160 under the control of the voltage level of the first node G. The data write circuit 1603 is connected to the first node G and is configured to receive a gate scan signal (for example, provided by the gate drive circuit via the gate line G10) as a scan drive signal, and writes a data signal to the first node G in response to the scan drive signal. The charge storage circuit 1606 is connected to the first node G and the second node S and is configured to store the written data signal and a reference voltage signal. The sensing circuit 1605 is connected to the second node S and is configured to receive the gate scan signal as a sensing drive signal, and in response to the sensing drive signal, write a reference voltage signal to the driving circuit 1604 or read a sensing voltage signal from the driving circuit 1604. The light-emitting element 160 (e.g., the first electrode 161 of the light-emitting element 160) is connected to the second node S and the second power supply voltage terminal ELVSS, and is configured to receive the second power supply voltage through the second power supply voltage terminal ELVSS and emit light under the drive current. For example, the second power supply voltage terminal ELVSS is connected to a power line ELVSS (not shown in the figure), and the power line ELVSS is configured to provide the second power supply voltage.

[0122] For example, in the embodiment of the present disclosure, the power line ELVSS is configured to be routed around the display area 101 , and the second electrode 1602 of the light emitting element 160 is disposed on the entire surface and connected to the power line ELVSS to receive the second power voltage.

[0123] For example, Figure 8A As shown, the data writing circuit 1603 is implemented as a data writing transistor T1 , the driving circuit 1604 is implemented as a driving transistor T2 , the charge storage circuit 1606 is implemented as a storage capacitor CST, and the sensing circuit 1605 is implemented as a sensing transistor T3 . Figure 1 The plurality of gate lines G10 include a first gate line G1 and a second gate line G2.

[0124] A first electrode of the data write transistor T1 is connected to one of the plurality of data lines DATA so as to receive a data signal, and a second electrode of the data write transistor T1 is connected to a first node G (i.e., connected to a gate electrode TG2 of the drive transistor T2). A gate electrode TG1 of the data write transistor T1 is connected to a first gate line G1 of the plurality of gate lines (i.e., a gate line connected to an output terminal of the shift register unit) so as to receive a scan drive signal.

[0125] A first electrode of the driving transistor T2 is connected to a second power voltage terminal ELVDD and is configured to receive a first power voltage. A second electrode of the driving transistor T2 is connected to a second node S (ie, connected to a first electrode of the sensing transistor T3 ).

[0126] The gate G221 of the sensing transistor T22 is configured to receive a sensing drive signal. For example, the gate G221 of the sensing transistor T22 is connected to a second gate line G2 among the plurality of gate lines (i.e., a gate line connected to the output terminal of the shift register unit in a different row from the sensing transistor T22) so as to receive the sensing drive signal. The first electrode of the sensing transistor T2 is connected to the second node S, and the second electrode of the sensing transistor T2 is connected to a sensing signal line SENSE ( Figure 1 The sensor is connected to one of the plurality of sensing signal lines SES10 in the sensor, and is configured to receive a reference voltage signal or output a sensing voltage signal.

[0127] The first electrode (e.g., the first electrode 161) of the light-emitting element 160 is connected to the second node S, that is, connected to the second electrode (e.g., the second electrode 162) of the driving transistor T2 and the first electrode of the sensing transistor T3, so that it can receive the driving current of the driving transistor T2; the second electrode of the light-emitting element 160 is configured to be connected to the second power supply voltage terminal ELVSS to receive the second power supply voltage. For example, in some embodiments, the second electrode of the light-emitting element 160 is configured to be grounded, and the second driving voltage is 0V. For example, the first power supply voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the second power supply voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages). When the driving transistor T2 is turned on (or partially turned on), the first power supply voltage and the second power supply voltage can be regarded as a power supply, which is used to generate the driving current for driving the light-emitting element 160.

[0128] It should be noted that the light emitting element 160 may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0129] For example, the above transistors are all described using N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (on level), and is turned off when the gate is connected to a low level (off level). It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the shift register unit provided in the embodiments of the present disclosure may also be P-type transistors. In this case, the first electrode may be a source electrode, and the second electrode may be a drain electrode. It is only necessary to connect the polarities of the electrodes of the selected type of transistors according to the polarities of the electrodes of the corresponding transistors in the embodiments of the present disclosure.

[0130] For example, Figure 8B This is a schematic diagram of the connection between the sub-pixel driving circuit and the register unit circuit of the sub-pixel unit circuit provided in at least one embodiment of the present disclosure. Figure 8B As shown, the first gate line G1 is connected to the data writing circuit 1603 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-th row of repeating units C1 extending along the first direction X, the sensing circuit 1605 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-1-th row of repeating units C1 extending along the first direction X, and the output end of the M-th row shift register unit 170, so as to output the gate scanning signal output from the output end of the M-th row shift register unit 170 to the data writing circuit 1603 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-th row of repeating units C1 as a scanning driving signal, and to the sensing circuit 1605 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-1-th row of repeating units C1 as a sensing driving signal. The second gate line G2 is connected to the sensing circuits 1605 of the multiple sub-pixel driving circuits 1601 in the pixel region P10 of the Mth row of repeating unit C1, the data writing circuits 1603 of the multiple sub-pixel driving circuits 1601 in the pixel region P10 of the M+1th row of repeating unit C1 extending along the first direction X, and the output terminal of the M+1th row of shift register unit 170. This allows the gate scanning signal output from the output terminal of the M+1th row of shift register unit 170 to be output to the data writing circuits 1603 of the multiple sub-pixel driving circuits 1601 in the pixel region P10 of the M+1th row of repeating unit C1 as a scanning driving signal, and to the sensing circuits 1605 of the multiple sub-pixel driving circuits 1601 in the pixel region P10 of the Mth row of repeating unit C1 as a sensing driving signal. 1<M<N, where M is an odd number greater than 1.

[0131] It should be noted that, in the embodiment of the present disclosure, the M-th row extending along the first direction X represents the M-th row in the horizontal direction, and the M-th row extending along the second direction Y represents the M-th column in the vertical direction.

[0132] Figure 9A A plan view of a light-shielding layer provided in at least one embodiment of the present disclosure.

[0133] For example, in some embodiments, in combination Figure 9A as well as Figure 6 In each pixel area P10, the light-shielding layer 131 includes a light-shielding electrode 111, which extends along the second direction Y (for example, the length of the light-shielding electrode 111 in the second direction Y is larger), and at least a portion of the positive projection of the light-shielding electrode 111 on the board surface of the base substrate 10, for example, partially overlaps with the positive projection of multiple sub-pixel driving circuits 1601 (for example, the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 or the third sub-pixel driving circuit P163) of each pixel area P10 on the board surface of the base substrate 10, thereby blocking external light from irradiating the sub-pixel driving circuit, especially the active layer of the transistor, to avoid the generation of dark current.

[0134] For example, Figure 9A As shown, the light shielding electrode 131 includes a first end 1111, a middle recess 1113, and a second end 1112 in the second direction Y. The middle recess 1113 is located between the first end 1111 and the second end 1112. The widths of the first end 1111 and the second end 1112 in the first direction X are greater than the width of the middle recess 1113 in the first direction. Figure 6 The orthographic projections of the first end 1111 and the second end 1112 on the substrate 10 overlap with the orthographic projections of the active layers of the data write transistor T1, the drive transistor T2, and the sense transistor T3 of the sub-pixel drive circuit 1601 on the substrate 10. The electrode overlap region 12 is located between the middle recess 1113 and the light-transmitting region TM10. The light-shielding electrode 131 is configured with a narrow center and two ends, which reduces the space occupied by the light-shielding electrode 131 and increases the area of the light-transmitting region.

[0135] For example, Figure 6 As shown, in the second direction Y, the sensing transistor T3 is located above (for example, above the storage capacitor CST), and the driving transistor T2 and the data writing transistor T1 are located on the side of the storage capacitor CST away from the sensing transistor T3. The orthographic projections of the active layers of the data writing transistor T1 and the driving transistor T2 on the surface of the substrate 10 overlap with the orthographic projections of the second end 1112 of the light shielding electrode 131 on the surface of the substrate 10. The orthographic projections of the active layer of the sensing transistor T3 on the surface of the substrate 10 overlap with the orthographic projections of the first end 1111 of the light shielding electrode 131 on the surface of the substrate 10. Thus, the light shielding layer can block external light from reaching the active layers of the data writing transistor T1, the driving transistor T2, and the sensing transistor T3, thereby preventing the generation of dark current.

[0136] For example, in some embodiments, Figure 6and Figure 7 As shown, the first plate CST1 and second plate CST2 of the storage capacitor CST of the sub-pixel driver circuit 1601 (e.g., the first sub-pixel driver circuit P161, the second sub-pixel driver circuit P162, and the third sub-pixel driver circuit P163) in the pixel region P10 comprise strips extending along the second direction Y. In each repeating unit C1, the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, and the third sub-pixel filter region LG3 are sequentially arranged along the second direction Y, with the second sub-pixel filter region LG2 located between the first sub-pixel filter region LG1 and the third sub-pixel filter region LG3. The first sub-pixel filter region LG1 overlaps with at least a portion (e.g., the portion near the storage capacitor CST) of the sub-pixel driver circuits of the multiple sub-pixels in the pixel region P10, as well as the portion of the storage capacitor CST near the sensing transistor T3 (e.g., the portion located above the storage capacitor CST if the strip-shaped storage capacitor CST is divided into three parts in the first direction Y) of the orthographic projection on the substrate 10. The third sub-pixel filter region LG3 overlaps with the orthographic projections of at least a portion of the data write transistors and drive transistors (e.g., the portion near the storage capacitor CST) of the sub-pixel drive circuits of the multiple sub-pixels in the pixel region P10, as well as the portion of the storage capacitor CST near the drive transistor T2 (e.g., the portion located below the storage capacitor CST) on the substrate 10. The second sub-pixel filter region LG2 overlaps with the orthographic projections of the storage capacitor CST of the sub-pixel drive circuits of the multiple sub-pixels in the pixel region P10 near the center thereof in the first direction (e.g., the portion located in the middle of the storage capacitor CST) on the substrate 10. The design of the strip-shaped storage capacitor CST and the square-shaped filter region can increase the transparent area of the display substrate, thereby improving display quality.

[0137] For example, in other embodiments, the first sub-pixel light filtering region LG1 , the second sub-pixel light filtering region LG2 , and the third sub-pixel light filtering region LG3 may also be designed as strips extending along the second direction Y, but the present disclosure is not limited thereto.

[0138] For example, at least one embodiment of the present disclosure further provides a display substrate comprising a base substrate and a plurality of sensing lines. The plurality of sensing signal lines are disposed on the base substrate and extend along a second direction different from the first direction. Two rows of repeating units are disposed between two adjacent sensing signal lines, respectively extending along the second direction. Each of the plurality of sensing signal lines is simultaneously connected to sub-pixel drive circuits of a plurality of sub-pixels in the two adjacent rows of repeating units, respectively extending along the second direction, and is configured to provide a reference voltage signal. This reduces the space occupied by the signal lines, increases the area of the transparent region, and improves light transmittance.

[0139] For example, in some embodiments, Figure 1 As shown, multiple sensing signal lines SES10 are disposed on a substrate 10 and extend along a second direction Y. The multiple sensing signal lines SES10 extend to a bonding region 13 and, for example, are connected to contact pads (not shown) in the bonding region 13 to receive electrical signals from an external driver circuit (e.g., a chip). Two rows of repeating units C1, respectively, along the second direction Y, are disposed between adjacent two sensing signal lines SES10. Each of the multiple sensing signal lines SES10 is simultaneously connected to the subpixel driver circuits of multiple subpixels in the two adjacent rows of repeating units C10, respectively, along the second direction Y, and is configured to provide reference voltage signals. That is, two adjacent sensing signal lines in each of the multiple sensing signal lines SES10 are separated by two repeating units C1 in the same row. Each of the multiple sensing signal lines SES10 is connected to the pixel regions P10 of the two repeating units C1 on either side of it along the first direction X. Thus, the sub-pixel driving circuits of the multiple sub-pixels in the pixel area P10 of the two repeating units C1 share one sensing signal line SES10, thereby reducing the number of sensing signal lines and the occupied wiring space, thereby increasing the area of the transparent region.

[0140] For example, in some embodiments, Figure 1 As shown, multiple power lines VDD10 are disposed on a base substrate 10 and extend along a second direction Y. In a first direction X, the multiple power lines VDD10 and multiple sensing signal lines SES10 are alternately arranged. A row of repeating units C1 extending along the second direction Y is provided between each of the multiple sensing signal lines SES10 and its adjacent power line VDD10. That is, the multiple power lines VDD10 and the multiple sensing signal lines SES10 define a space between each row of repeating units C1 extending along the second direction Y. A row of repeating units C1 extending along the second direction Y is provided between each of the multiple power lines VDD10 and its adjacent sensing signal line SES10. Two rows of repeating units C1, each extending along the second direction Y, are provided between two adjacent pairs of the multiple power lines VDD10. Each of the multiple power lines VDD10 is simultaneously connected to the sub-pixel driving circuits of multiple sub-pixels in the two adjacent rows of repeating units C1 extending along the second direction Y, and is configured to provide a first power supply voltage. That is, two adjacent power lines VDD10 are spaced apart in the same row by two repeating units C1. Each of the power lines VDD10 is connected to the pixel areas P10 of two repeating units C1 on either side thereof along the first direction X. Thus, the sub-pixel driving circuits for the multiple sub-pixels in the pixel areas P10 of the two repeating units C1 share a single power line VDD10, thereby reducing the number of power lines and the occupied wiring space, thereby increasing the area of the transparent region.

[0141] Figure 9B A plan view of a first insulating layer provided in at least one embodiment of the present disclosure. Figure 9C A plan view of a buffer layer provided in at least one embodiment of the present disclosure. Figure 9D A plan view of a semiconductor layer provided for at least one embodiment of the present disclosure. Figure 9E A layout diagram of the second conductive layer provided in at least one embodiment of the present disclosure. Figure 9F A plan view of an interlayer insulating layer provided in at least one embodiment of the present disclosure. Figure 9G A plan view of a first conductive layer provided for at least one embodiment of the present disclosure. Figure 10 for Figures 9A to 9B The layout diagram after stacking. Figures 9B-9G as well as Figure 10 The structure of the sub-pixel unit driving circuit 1601 of the plurality of sub-pixels in the pixel area is introduced in detail. Figures 9B-9G as well as Figure 10 The structure of one sub-pixel unit driving circuit 1601 is taken as an example for description, and the structures of other sub-pixel unit driving circuits are the same and will not be repeated herein.

[0142] For example, in some embodiments, Figure 2 and Figure 6 As shown, the display area 101 includes a first repeating unit C11 and a second repeating unit C12 adjacently arranged along a first direction. A sensing signal line SES11 is provided between the pixel region of the first repeating unit C11 and the transparent region TM10 of the second repeating unit C12. The sensing signal line SES11 is connected to multiple sub-pixel driving circuits in the pixel region P10 of the first repeating unit C11 and the second repeating unit C12. That is, the multiple sub-pixel driving circuits in the pixel region P10 of the first repeating unit C11 and the second repeating unit C12 share a single sensing signal line. A power line VDD11 is provided on a side of the pixel area P10 of the second repeating unit C12 away from the transparent area TM10 of the second repeating unit C12, and the power line VDD11 is connected to multiple sub-pixel driving circuits of the pixel area P10 of the second repeating unit C12. Another power line VDD12 is provided on a side of the transparent area TM10 of the first repeating unit C11 away from the pixel area P10 of the first repeating unit C11, and the other power line VDD12 is connected to multiple sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11. Figure 2 and Figure 6 In the repeating unit shown, if another repeating unit is drawn on the left side of the first repeating unit C11, that is, on the side where the other power line VDD12 is away from the first repeating unit C11, the sub-pixels in the pixel area of the other repeating unit are also connected to the other power line VDD12. Figure 2 and Figure 6In the repeating unit shown, if another repeating unit is drawn on the right side of the second repeating unit C12, that is, on the side where the power line VDD11 is away from the second repeating unit C12, the sub-pixels in the pixel area of the other repeating unit are also connected to the power line VDD11. In other words, each power line is connected to the pixel areas of two repeating units. Figure 2 and Figure 6 The structure shown in the figure is introduced here, and other parts with similar structures will not be shown and introduced in detail.

[0143] For example, in some embodiments, Figure 2 and Figure 6 As shown, the multiple sub-pixel driving circuits of the pixel region P10 of the first repeating unit C11 and the multiple sub-pixel driving circuits of the pixel region P10 of the second repeating unit layer 2 respectively include a first sub-pixel driving circuit P161, a second sub-pixel driving circuit P162, and a third sub-pixel driving circuit P163 arranged in the first direction X. The second sub-pixel driving circuit P162 is located between the first sub-pixel driving circuit P161 and the third sub-pixel driving circuit P163. The orthographic projections of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 on the surface of the base substrate 10 all extend along the second direction Y. The first sub-pixel driving circuit P161 is mirror-symmetrical to the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163.

[0144] It should be noted that in the embodiment of the present disclosure, the structurally identical parts of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 are introduced taking one sub-pixel driving circuit as an example, and the other sub-pixel driving circuits will not be described in detail.

[0145] For example, Figure 9B As shown, the first insulating layer 132 is provided with a first overlapping sub-hole FK111 located in the electrode overlapping region 12 to expose the Figure 9A The light shielding layer 131 shown, for example, the middle concave portion 1113 of the light shielding layer 131 .

[0146] For example, Figure 9C As shown, the buffer layer 133 is provided with a third overlapping sub-hole FK113 located in the electrode overlapping region 12 to expose the Figure 9A The light shielding layer 131 shown, for example, the middle recess 1113 of the light shielding layer 131. The third overlapping sub-hole FK113 is sleeved in the first overlapping sub-hole FK111.

[0147] For example, in some embodiments, Figure 6 and Figure 9DAs shown, the orthographic projections of the data writing transistor T1, the driving transistor T2 and the sensing transistor T3 of the sub-pixel driving circuit on the base substrate 10 all extend along the second direction Y. Figure 6 In the embodiment, the semiconductor layer ACT includes the active layer TA1 of the data write transistor T1 of the sub-pixel drive circuit, the active layer TA2 of the drive transistor T2, and the active layer TA3 of the sensing transistor T3. The active layer TA1 of the data write transistor T1 of the sub-pixel drive circuit, the active layer TA2 of the drive transistor T2, and the active layer TA3 of the sensing transistor T3 all extend along the second direction Y. For example, the base substrate 10 can be a flexible substrate. Thus, when the display substrate is bent, the electrical performance of each transistor in the sub-pixel drive circuit is not affected, ensuring the stability of the display substrate.

[0148] For example, the active layer TA1 of the data writing transistor T1, the active layer TA2 of the driving transistor T2, and the active layer TA3 of the sensing transistor T3 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0149] For example, Figure 9D As shown, taking the first sub-pixel driving circuit P161 as an example, the structure of the active layer and storage capacitor of each transistor in the sub-pixel driving circuit is described in detail. For example, the semiconductor layer ACT also includes the first plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161. The active layer TA3 of the sensing transistor T3 is located on the upper side of the first plate CST1 of the storage capacitor. The active layer TA2 of the driving transistor T2 and the active layer TA1 of the data writing transistor T1 are located on the side of the first plate CST1 of the storage capacitor away from the sensing transistor T3. The active layer TA2 of the driving transistor T2 is located between the sensing transistor T3 and the data writing transistor T1. The first plate CST1 of the storage capacitor CST is connected to the active layer TA2 of the driving transistor T2 and is integrally arranged. The first plate CST1 of the storage capacitor is strip-shaped and extends along the second direction Y. The first electrode plate CST1 of the storage capacitor is provided with a protrusion CST11 protruding from the side away from the transparent area TM10 at a position corresponding to the electrode overlapping area 12, and the protrusion has a recess CST12. The recess CST12 surrounds the electrode overlapping area 12 to leave space for the electrode overlapping area 12. That is, the electrode overlapping area 12 occupies part of the space of the first electrode plate CST1, thereby reducing the space occupied by the electrode overlapping area 12 in the transparent area TM10 and increasing the area of the transparent area. For example, Figure 9DAs shown, the shape of the first plate CST1 of the storage capacitor of the second sub-pixel driver circuit P162 is slightly different from that of the first plate CST1 of the storage capacitor of the first sub-pixel driver circuit P161. The portion of the first plate CST1 of the storage capacitor of the second sub-pixel driver circuit P162 corresponding to the protrusion CST11 is bent to provide routing space between the first sub-pixel driver circuit P161 and the second sub-pixel driver circuit P162. The shape of the first plate CST1 of the storage capacitor of the third sub-pixel driver circuit P163 is slightly different from that of the first plate CST1 of the storage capacitor of the first sub-pixel driver circuit P161 and the second sub-pixel driver circuit P162. The portion of the first plate CST1 of the storage capacitor of the third sub-pixel driver circuit P163 corresponding to the protrusion CST11 is recessed to the right (away from the second sub-pixel driver circuit P162) at the edge of the first plate CST1 of the storage capacitor of the third sub-pixel driver circuit P163 corresponding to the protrusion CST11, to provide routing space between the second sub-pixel driver circuit P162 and the third sub-pixel driver circuit P163. That is, a structure similar to the recess CST12 surrounding the electrode overlapping region 12 may also be correspondingly provided in the first electrode plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 .

[0150] For example, Figure 9D As shown, the active layer TA3 of the sensing transistor T3 includes a source region TS3, a channel region TP3, and a drain region TD3. For example, the active layer TA2 of the driving transistor T2 includes a source region TS2, a channel region TP2, and a drain region TD2. For example, the active layer TA1 of the data writing transistor T1 includes a source region TS1, a channel region TP1, and a drain region TD1.

[0151] For example, Figure 9E As shown, the second conductive layer GATE includes the gate TG1 of the data write transistor T1, the gate TG2 of the drive transistor T2, and the gate TG3 of the sense transistor T3. The orthographic projection of the channel region TP3 on the substrate partially overlaps with the orthographic projection of the gate TG3 on the substrate. The orthographic projection of the channel region TP1 on the substrate partially overlaps with the orthographic projection of the gate TG1 on the substrate. The orthographic projection of the channel region TP2 on the substrate partially overlaps with the orthographic projection of the gate TG2 on the substrate.

[0152] For example, Figure 9G As shown, the first conductive layer SD includes the first electrode TSD11 and the second electrode TSD12 of the data writing transistor T1, the first electrode TSD21 and the second electrode TSD22 of the driving transistor T2, the first electrode TSD31 and the second electrode TSD32 of the gate of the sensing transistor T3, and the second electrode CST2 of the storage capacitor CST. Figure 9DAs shown, the first electrode TSD11 and the second electrode TSD12 of the data writing transistor T1 overlap with the orthographic projections of the source region TS1 and the drain region TSD1 of the data writing transistor T1 on the substrate 10, respectively. The first electrode TSD21 and the second electrode TSD22 of the driving transistor T2 overlap with the orthographic projections of the source region TS2 and the drain region TD2 of the driving transistor T2 on the substrate 10, respectively. The first electrode TSD31 and the second electrode TSD32 of the sensing transistor T3 overlap with the orthographic projections of the source region TS3 and the drain region TD3 of the sensing transistor T3 on the substrate 10, respectively. A second insulating layer 134 is separated between the second plate CST2 of the storage capacitor CST and the first plate CST1 of the storage capacitor to form a capacitor function. Combined Figure 9F As shown, the first electrode TSD31 of the sensing transistor T3 is connected to the source region TS3 via a third via GK3, and the second electrode TSD32 of the sensing transistor T3 is connected to the drain region TD3 via a first source-drain via SDG1 (e.g., passing through the second insulating layer 134). The first electrode TSD21 of the driving transistor T2 is connected to the source region TS2 via a second source-drain via SDG2 (e.g., passing through the second insulating layer 134), and the second electrode TSD22 of the driving transistor T2 is connected to the drain region TD2 via a fourth via GK3. The first electrode TD11 of the data write transistor T1 is connected to the source region TS1 via a third source-drain via SDG3 (e.g., passing through the second insulating layer 134), and the second electrode TD12 of the data write transistor T1 is connected to the drain region TD1 via a fourth source-drain via SDG4 (e.g., passing through the second insulating layer 134). The structures of the third and fourth vias GK3 will be described in detail later.

[0153] It should be noted that the first source-drain via hole SDG1 , the second source-drain via hole SDG2 , the third source-drain via hole SDG3 , and the fourth source-drain via hole SDG4 may be disposed to pass through the second insulating layer 134 and the fourth insulating layer 137 .

[0154] For example, the size of the first source-drain via SDG1, the second source-drain via SDG2, the third source-drain via SDG3, and the fourth source-drain via SDG4 can be in the range of approximately 2-4 microns, for example, approximately 3 microns. The sizes of the first source-drain via SDG1, the second source-drain via SDG2, the third source-drain via SDG3, and the fourth source-drain via SDG4 are selected during the display substrate manufacturing process.

[0155] It should be noted that a second insulating layer 134 and a fourth insulating layer 137 may be further interposed between the second plate CST2 and the first plate CST1 of the storage capacitor CST, but the embodiment of the present disclosure is not limited thereto.

[0156] For example, Figure 9FAs shown, the second insulating layer 134 further includes a second overlapping sub-hole FK112 located in the electrode overlapping region 12 .

[0157] For example, Figure 9G As shown, the first conductive layer SD further includes a first strapping electrode FD11 located in the electrode strapping region 12 .

[0158] For example, in some embodiments, Figure 9G As shown, an end of the second plate CST2 of the storage capacitor CST, which is close to the second electrode TSD32 of the sensing transistor T3, is connected to the second electrode TSD2 of the sensing transistor T3, and the second plate CST2 and the second electrode TSD32 of the sensing transistor T3 are integrally provided. A first electrode TSD21 of the driving transistor T2 is connected to an end of the second plate CST2 of the storage capacitor CST, which is away from the sensing transistor T3, and the first electrode TSD21 and the second plate CST2 of the driving transistor T2 are integrally provided to reduce occupied space.

[0159] For example, Figure 9E 、 Figure 9G and Figure 10 As shown, each of the multiple power lines, such as power line VDD11 or power line VDD12, includes a first sub-line VDD111 located in the second conductive layer GATE and a second sub-line VDD121 located in the first conductive layer SD. The first sub-line VDD111 includes multiple first routing segments VDD112 extending along the second direction Y. These multiple first routing segments VDD112 are respectively located in different repeating units C1. The second sub-line VDD121 passes through the display area 101 along the second direction Y. In other words, the power lines are double-layered, located in the first conductive layer SD and the second conductive layer GATE. Each first routing segment VDD112 of each first sub-line VDD111 in the second conductive layer GATE is located in a repeating unit C1. The second sub-line VDD121 in the first conductive layer SD extends along the second direction Y and passes through a row of repeating units C1 in the second direction Y. In other words, the second sub-line VDD121 is arranged entirely in the second direction Y. The second sub-line VDD121 is stacked on the side of the first sub-line VDD111 away from the base substrate 10 and is connected to the second sub-line VDD121 through at least one first via hole GK1 (eg, Figure 9F As shown) is connected to the first sub-line VDD111. Figure 9F As shown, a plurality of first vias GK1 are arranged along the second direction Y for connecting the second sub-line VDD121 and the first sub-line VDD111. Thus, the wiring resistance of the power line can be reduced.

[0160] For example, Figure 9E 、 Figure 9G and Figure 10As shown, each of the multiple sensing signal lines, for example, sensing line SES11, includes a third sub-line SES111 located in the second conductive layer GATE and a fourth sub-line SES121 located in the first conductive layer SD. The third sub-line SES111 includes multiple second routing segments SES112 extending along the second direction Y. The multiple second routing segments SES112 are distributed in different repeating units. The fourth sub-line SES121 passes through the display area 101 along the second direction Y. That is, the sensing line is a double-layer routing line, located in the first conductive layer SD and the second conductive layer GATE. Each second routing segment SES112 of the third sub-line SES111 in the second conductive layer GATE is located in a repeating unit C1, while the fourth sub-line SES121 in the first conductive layer SD extends along the second direction Y and passes through a row of repeating units C1 in the second direction Y. That is, the fourth sub-line SES121 is arranged entirely in the second direction Y. The fourth sub-line SES121 is stacked on the side of the second sub-line SES111 away from the base substrate 10 and is connected to the second sub-line SES121 through at least one second via hole GK2 (eg, Figure 9F As shown) is connected to the third sub-line SES111. Figure 9F As shown, a plurality of second vias GK2 are arranged along the second direction Y for connecting the fourth sub-line SES121 and the third sub-line SES111. Thus, the wiring resistance of the power line can be reduced.

[0161] For example, in some embodiments, Figure 9G and Figure 10 As shown, the first conductive layer SD includes a first transfer electrode ZL1 extending along the first direction X. A first end ZL11 of the first transfer electrode ZL1 is connected to the first electrode TSD31 of the sensing transistor T3 of the third sub-pixel driving circuit P163 of the first repeating unit C11. A second end ZL12 of the first transfer electrode ZL1 is connected to the first electrode TSD31 of the sensing transistor T3 of the first sub-pixel driving circuit P161 of the second repeating unit C12. The first transfer electrode ZL1 is cross-connected to the second sub-line SES121 of the sensing signal line SES11. In other words, the sensing signal line SES11 provides reference voltage signals to both the first and second repeating units C11 and C12 through the first transfer electrode ZL1.

[0162] Figure 11A for Figure 10 Magnified view of the A1 region in the middle.

[0163] For example, in some embodiments, Figure 9E and Figure 11AAs shown, the second conductive layer GATE includes a first connecting line LL1 extending along a first direction X. The first connecting line LL1 connects to the first electrode TSD31 of the sensing transistor T3 in the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12 through at least a portion (e.g., a portion) of the third via GK3. Specifically, a first connecting line LL1 is provided in the pixel region of each repeating unit so that the first electrodes TSD31 of the sensing transistors T3 in the multiple sub-pixel driving circuits receive the reference voltage signal provided by the sensing signal line SES11. At least a portion (e.g., a portion) of the orthographic projection of the first electrodes TSD31 of the sensing transistors T3 in the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 on the surface of the base substrate 10 overlaps with the orthographic projection of the first connecting line LL1 on the surface of the base substrate 10.

[0164] For example, the first connection line LL1 may not be parallel to the first direction X, for example, it may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0165] Figure 11B for Figure 11A Schematic diagram of the cross section along line B1-B2.

[0166] like Figure 11B As shown, the orthographic projection of the first electrode TSD31 on the substrate 10 overlaps with the orthographic projection of the first connection trace LL1 on the substrate 10. The first electrode TSD31 of the sensing transistor T3 includes a first sub-portion TSD311 and a second sub-portion TSD312 connected along the second direction Y. The projection of the third via GK3 on the substrate 10 overlaps with the projections of the first sub-portion TSD311 and the second sub-portion TSD312 of the first electrode TSD31 on the substrate 10. A portion of the third via GK3, such as the portion overlapping with the projection of the first sub-portion TSD311 on the substrate 10, is configured to penetrate the second insulating layer 134 and the fourth insulating layer 137 to expose the active layer TA3 (e.g., the source region TS3) of the sensing transistor T3. Another portion of the third via GK3, such as the portion overlapping with the projection of the second sub-portion TSD312 on the substrate 10, is configured to penetrate the second insulating layer 134 to expose the first connection trace LL1. The first sub-portion TSD311 contacts and is connected to the active layer TA3 of the sensing transistor T3, and the second sub-portion TSD312 contacts and is connected to the first connection line LL1. The cross-sectional structure of the third via GK3 can also be called a semi-buried via, which can reduce the wiring space to leave space for the transparent area.

[0167] For example, Figure 11A As shown, the width of the third via hole GK3 in the first direction X is, for example, approximately 2-4 microns, such as approximately 3 microns. The length of the third via hole GK3 in the second direction Y is, for example, approximately 5-7 microns, such as approximately 6 microns.

[0168] For example, in some embodiments, Figure 9G and Figure 10 As shown, the first conductive layer SD further includes a second transfer electrode ZL2 and a third transfer electrode ZL3, and the second transfer electrode ZL2 and the third transfer electrode ZL3 respectively include the third node D (as shown in FIG. Figure 8A As shown in FIG. A second electrode TSD22 of the driving transistor T2 is located on a side of the driving transistor T2 away from the storage capacitor CST. One end of the second switching electrode ZL2 is connected to the second electrode TSD22 of the driving transistor T2 of the third sub-pixel driving circuit P163 of the second repeating unit C12, and the other end of the second switching electrode ZL2 is connected to the power line VDD11 of the third sub-pixel driving circuit P163 near the second repeating unit C12 to provide a first power supply voltage. The second switching electrode ZL2 extends along the first direction X. One end of the third switching electrode ZL3 is connected to the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161 of the first repeating unit C11, and the other end of the third switching electrode ZL3 is connected to the power line VDD12 of the transparent area TM10 near the first repeating unit C11 to provide a first power supply voltage. The third transfer electrode ZL3 is routed below the light-transmitting region TM10 (near the data write transistor T1) and bends between the transparent region TM10 and the pixel region P10 toward the drive transistor T2 to reduce wiring space. In other words, either the power line VDD11 or the power line VDD12 is connected to a second transfer electrode ZL2 and a third transfer electrode ZL3 to connect to the sub-pixel drive circuits on either side. The structures on the other side of the power lines VDD11 and VDD12 will not be further described here.

[0169] Figure 11C for Figure 10 Magnified view of area A2 in the middle.

[0170] For example, in some embodiments, Figure 9G and Figure 11CAs shown, the second conductive layer includes a second connecting trace LL2 extending along the first direction X. The second connecting trace LL2 is connected to the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12 through at least a portion (e.g., a portion) of the fourth via GK4. In other words, the multiple sub-pixel driving circuits in the pixel area are connected to the power line via the second connecting trace LL2. The orthographic projection of the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 on the surface of the base substrate 10 overlaps with the orthographic projection of the second connecting trace LL2 on the surface of the base substrate 10. The cross-sectional structure of the fourth via GK4 is similar to that of the third via GK3 and will not be described in detail here.

[0171] For example, the second connection line LL2 may not be parallel to the first direction X, for example, it may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0172] For example, in some embodiments, Figure 9G and Figure 10 As shown, the display substrate 1 further includes a plurality of data lines extending along the second direction Y. The plurality of data lines include a first data line DR, a second data line DG, and a third data line DB located in each repeating unit. The first data line DR and the second data line DB are located between the first sub-pixel driving circuit P161 and the second sub-pixel driving circuit P162, while the third data line DB is located between the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163. The first data line DR, the second data line DG, and the third data line DB are bent at locations corresponding to the electrode overlapping area 12. The first data line DR, the second data line DG, and the third data line DB are electrically connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163, respectively, to provide data signals. The first conductive layer further includes a fourth transfer electrode ZL4, a fifth transfer electrode ZL5, and a sixth transfer electrode ZL6 along the first direction X. The fourth transfer electrode ZL4 is connected to the first data line DR and the second electrode TSD12 of the data write transistor T1 of the first sub-pixel driving circuit P161, the fifth transfer electrode ZL5 is connected to the second data line DG and the second electrode TSD12 of the data write transistor T1 of the second sub-pixel driving circuit P162, and the sixth transfer electrode ZL6 is connected to the third data line DB and the second electrode TSD12 of the data write transistor T1 of the third sub-pixel driving circuit P163.

[0173] For example, the fourth transition electrode ZL4 , the fifth transition electrode ZL5 , and the sixth transition electrode ZL6 may not be parallel to the first direction X, for example, they may intersect with the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0174] For example, Figure 9G and Figure 10 As shown, the second electrode TSD12 and the fourth switching electrode ZL4 of the data writing transistor T1 of the first sub-pixel driving circuit P161 are mirror-symmetrical with the second electrode TSD12 and the fifth switching electrode ZL5 of the data writing transistor T1 of the second sub-pixel driving circuit P162.

[0175] For example, in some embodiments, Figure 9E and Figure 11A As shown, the first gate line G1 and the second gate line G2 are located in the second conductive layer GATE. The first gate line G1 is close to the sensing transistor T3 of the first repeating unit C11 and the second repeating unit C12, and the second gate line G2 is close to the data writing transistor T1 of the first repeating unit C11 and the second repeating unit C12. The first gate line G1 includes a fold line portion, which includes a first fold line portion G111 along the first direction X, a second fold line portion G112 along the second direction Y connected to both ends of the first fold line portion G111, and a third fold line portion G113. The first fold line portion G111, the second fold line portion G111, and the third fold line portion G113 bypass the first connecting line ZL1. The orthographic projection of the first fold line portion G111 on the board surface of the base substrate 10 overlaps with the orthographic projection of the active layer TA3 of the sensing transistor T3 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 of the first repeating unit C10 on the board surface of the base substrate 10, and the overlapping part forms the gate TG3 of the sensing transistor T3.

[0176] For example, Figure 9G and Figure 10As shown, the second conductive layer GATE also includes a third connecting line LL3, a fourth connecting line LL4 and a fifth connecting line LL5. The third connecting line LL3, the fourth connecting line LL4 and the fifth connecting line LL5 are roughly "L"-shaped broken lines, and the bending directions of the fourth connecting line LL4 and the fifth connecting line LL5 are the same (for example, toward the first sub-pixel driving circuit P161), and the bending direction of the third connecting line LL3 (for example, toward the second sub-pixel driving circuit P162) is opposite to the bending direction of the fourth connecting line LL4 and the fifth connecting line LL5. The third connecting line LL3 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the first sub-pixel driving circuit P161. The fourth connecting line LL4 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the second sub-pixel driving circuit P162. The fifth connecting line LL5 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the third sub-pixel driving circuit P163.

[0177] For example, in some embodiments, Figure 9G and Figure 10 As shown, the first conductive layer SD further includes a seventh transfer electrode ZL7, an eighth transfer electrode ZL8, and a ninth transfer electrode ZL9 along the second direction Y. The orthographic projections of the seventh transfer electrode ZL7, the eighth transfer electrode ZL8, and the ninth transfer electrode ZL9 on the surface of the base substrate 10 overlap with the orthographic projection of the second connection trace ZL2 on the surface of the base substrate 10. A first end (the upper end) of the seventh transfer electrode ZL7 is connected to the gate electrode TG2 of the drive transistor T2 of the first sub-pixel drive circuit P161 through at least a portion (e.g., a portion) of an eighth via GK8 that penetrates the second insulating layer 134. A second end (the lower end) of the seventh transfer electrode ZL7 is connected to the first electrode TSD11 of the data write transistor T1 of the first sub-pixel drive circuit P161. The first end (the upper end) of the eighth transfer electrode ZL8 is connected to the gate electrode TG2 of the driving transistor T2 of the second sub-pixel driving circuit P162 via at least a portion (e.g., a portion) of a ninth via hole GK9 penetrating the second insulating layer 134. The second end (the lower end) of the eighth transfer electrode ZL8 is connected to the first electrode TSD11 of the data write transistor T1 of the second sub-pixel driving circuit P162. The first end (the upper end) of the ninth transfer electrode ZL9 is connected to the gate electrode TG3 of the driving transistor T3 of the third sub-pixel driving circuit P163 via at least a portion (e.g., a portion) of a tenth via hole GK10 penetrating the second insulating layer 134. The second end (the lower end) of the ninth transfer electrode ZL9 is connected to the first electrode TSD11 of the data write transistor T1 of the third sub-pixel driving circuit P163.

[0178] For example, the seventh switching electrode ZL7 , the eighth switching electrode ZL8 , and the ninth switching electrode ZL9 may not be parallel to the first direction X, for example, they may intersect with the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0179] For example, the structures of the eighth via hole GK8 , the ninth via hole GK9 , and the tenth via hole GK10 may be similar to the structure of the third via hole GK3 , and are not further described here.

[0180] For example, in some embodiments, Figure 10 As shown, in the second direction Y, the portion of the first gate line G1 and the first connecting line ZL1 that runs parallel is located on one side of the first connecting line ZL1 near the transparent region TM10 of the second repeating unit C12. In the second direction Y, the first connecting line ZL1 is spaced apart from the first fold line G111 of the first gate line G1, and the second connecting line ZL2 is spaced apart from the second gate line G2 to reduce interference between the line signals.

[0181] Figure 12A A plan view of a passivation layer provided in accordance with at least one embodiment of the present disclosure. Figure 12B A plan view of a third insulating layer provided in at least one embodiment of the present disclosure. Figure 12C A plan view of a first sublayer of a first electrode layer provided in at least one embodiment of the present disclosure. Figure 12D A plan view of the third sublayer of the first electrode layer provided in at least one embodiment of the present disclosure. Figure 12E A plan view of a pixel defining layer provided in at least one embodiment of the present disclosure. 12A to 12E The structure of the display substrate is introduced in detail.

[0182] For example, in some embodiments, Figure 6 、 Figure 7 as well as Figure 12CAs shown, the multiple light-emitting elements 160 in each repeating unit C1 include a first light-emitting element 164, a second light-emitting element 165, and a third light-emitting element 166. The first light-emitting element 164, the second light-emitting element 165, and the third light-emitting element 166 are respectively arranged corresponding to the first sub-pixel filter region LG1, the second sub-pixel filter region LG2, and the third sub-pixel filter region LG3. The display substrate 1 also includes a fifth via hole GK5, a sixth via hole GK6, and a seventh via hole GK7 that penetrate at least the third insulating layer 136 (and may also penetrate the passivation layer 135). The fifth via hole GK5, the sixth via hole GK6, and the seventh via hole GK7 are configured to expose the first sub-pixel driver circuit P161, the second sub-pixel driver circuit P162, and the third sub-pixel driver circuit P163, respectively. The first electrode 161 of the first light-emitting element 164 is connected to the first sub-pixel driver circuit P161 through the fifth via hole GK5. The first electrode 161 of the second light emitting element 165 is connected to the second sub-pixel driving circuit P162 through the sixth via GK6. The first electrode 161 of the third light emitting element 166 is connected to the third sub-pixel driving circuit P163 through the seventh via GK7.

[0183] For example, Figure 12A and Figure 12B As shown, the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively penetrate the third insulating layer 136 and the passivation layer 135 to connect the first light-emitting element 164 to the first sub-pixel driving circuit P161, the second light-emitting element 165 to the second sub-pixel driving circuit P162, and the third light-emitting element 166 to the third sub-pixel driving circuit P163.

[0184] It should be noted that Figure 12A and Figure 12B The third insulating layer 136 and the through passivation layer 135 are shown to have an inverse structure, that is, the filled portion is the dug-out (non-existent) portion.

[0185] For example, Figure 6 As shown, the orthographic projection of the fifth via hole GK5 on the surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of the first light-emitting element 164 on the surface of the base substrate 10, thereby improving the flatness of the light-emitting area of the first light-emitting element 164. The orthographic projection of the sixth via hole GK6 on the surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of the second light-emitting element 165 on the surface of the base substrate 10, thereby improving the flatness of the light-emitting area of the second light-emitting element 165. The orthographic projection of the seventh via hole GK7 on the surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of the third light-emitting element 166 on the surface of the base substrate 10, thereby improving the flatness of the light-emitting area of the third light-emitting element 166.

[0186] For example, the size of the fifth via hole GK5, the sixth via hole GK6, and the seventh via hole GK7 can be in the range of approximately 9-12 microns. For example, the size of the fifth via hole GK5, the sixth via hole GK6, and the seventh via hole GK7 is selected to be approximately 10 or 11 microns. The size of the fifth via hole GK5, the sixth via hole GK6, and the seventh via hole GK7 is selected during the display substrate manufacturing process.

[0187] For example, in some embodiments, Figure 2 、 Figure 6 as well as Figure 7 As shown, the orthographic projections of the fifth and sixth via holes GK5 and GK6 on the substrate 10 are close to the orthographic projection of the light-shielding line BM1 between the first and second sub-pixel filter areas LG1 and LG2, and are located on both sides of the orthographic projection of the light-shielding line BM1 between the first and second sub-pixel filter areas LG1 and LG2. In other words, the fifth via hole GK5 is below the light-emitting area of the first light-emitting element 164 and above the light-shielding line BM1, while the sixth via hole GK6 is above the light-emitting area of the second light-emitting element 165. This increases the area of the light-emitting areas of the first and second light-emitting elements 164 and 165. The orthographic projection of the seventh via hole GK7 on the substrate 10 is close to the orthographic projection of the light-shielding line BM2 between the second and third sub-pixel filter areas LG2 and LG3, and overlaps with the third sub-pixel filter area LG3. That is, the seventh through hole GK7 is located on the upper side of the light emitting area of the third light emitting element 166 to increase the area of the light emitting area of the third light emitting element 166. It should be noted that in this embodiment, the position of the fifth through hole GK5 is the same as that of the first through hole GK5. Figure 6 The position of the fifth via hole GK5 shown in FIG. 5 is different.

[0188] For example, in other embodiments, Figure 2 、 Figure 6 as well as Figure 7As shown, the orthographic projection of the fifth via GK5 on the substrate 10 overlaps with the orthographic projection of the end of the first plate CST1 of the storage capacitor CST of the first sub-pixel driver circuit P161, which is connected to the second electrode TSD31 of the sensing transistor T3, on the substrate 10. That is, the fifth via GK5 is located above the light-emitting area of the first light-emitting element 164 to reduce the impact on the light-emitting area of the first light-emitting element 164. The orthographic projection of the sixth via GK6 on the substrate 10 is close to the orthographic projection of the light-shielding line BM1 between the first sub-pixel filter area LG1 and the second sub-pixel filter area LG2, and overlaps with the second sub-pixel filter area LG2. That is, the sixth via GK6 is located above the light-emitting area of the second light-emitting element 165 to increase the area of the light-emitting area of the first light-emitting element 164. The orthographic projection of the seventh via hole GK7 on the substrate 10 is close to the orthographic projection of the light-shielding line BM2 between the second sub-pixel filter area LG2 and the third sub-pixel filter area LG3 on the substrate 10, and overlaps with the third sub-pixel filter area LG3. In other words, the seventh via hole GK7 is located above the light-emitting area of the third light-emitting element 166 to increase the area of the light-emitting area of the third light-emitting element 166.

[0189] For example, Figure 12C As shown, the first layer AN1 of the first electrode layer AN includes a first sub-electrode layer FD121 and a layer of the first electrodes of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163 close to the base substrate 10. The first light-emitting element 164, the second light-emitting element 165 and the first electrodes of the third light-emitting element 163 close to the base substrate 10 are connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 through the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively. The first sub-electrode layer FD121 is connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 through the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively. Figure 12A and Figure 12B The second strap hole FD12 penetrating the passivation layer 135 and the third insulating layer 136 is connected to the first strap electrode FD11 .

[0190] For example, Figure 12D As shown, the third layer AN3 of the first electrode layer AN includes the second electrode layer FD122 and the first electrodes of the first light emitting element 164 , the second light emitting element 165 and the third light emitting element 163 , which is a layer away from the base substrate 10 .

[0191] For example, Figure 12EAs shown, the pixel defining layer 138 has a plurality of openings defining the light-transmitting region TM10, the light-emitting regions of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, and the electrode bonding region 12. It should be noted that the pixel defining layer 138 has a plurality of openings defining the light-transmitting region TM10, the light-emitting regions of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, and the electrode bonding region 12. Figure 12E The middle one is an inverted structure, that is, the filled part in the figure represents the dug-out part.

[0192] For example, the first conductive layer SD ( Figure 9G The width of each trace covering the via hole is 4 to 5 microns. Figure 9E For example, the first electrode or the second electrode of the data writing transistor T1 and the driving transistor T2 may extend above and below the via hole by 1 micron, for example, 4.0 to 4.5 microns.

[0193] For example, in some examples, the thickness of the second conductive layer GATE is 2000-300 angstroms and the thickness of the first conductive layer SD is 5000-8000 angstroms, which is not limited in the embodiments of the present disclosure.

[0194] At least one embodiment of the present disclosure further provides a display device. Figure 13 Schematic diagram of a display device provided by at least one embodiment of the present disclosure. Figure 13 As shown, the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, Figure 2 The display substrate 1 shown in FIG.

[0195] It should be noted that the display device 2 may be a product or component with a transparent display function. The display device 2 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0196] It should be noted that for the sake of clarity and brevity, the embodiments of this disclosure do not provide all components of the display device. To implement the substrate function of the display device, those skilled in the art may provide and configure other structures not shown according to specific needs, and the embodiments of this disclosure do not limit this.

[0197] Regarding the technical effects of the display device 2 provided in the above embodiment, reference may be made to the technical effects of the display substrate 1 provided in the embodiments of the present disclosure, which will not be repeated here.

[0198] Figures 14A-14F A schematic diagram of a manufacturing process of a display device provided in at least one embodiment of the present disclosure.

[0199] For example, Figure 14AAs shown, a base substrate 10 is provided, and a metal material is deposited on the base substrate to form a light-shielding layer 131 through a patterning process. For example, the metal material includes silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, molybdenum-neodymium alloy or any combination thereof. An insulating material is deposited on the light-shielding layer 131 to form a first insulating layer 132 through a patterning process. The first insulating layer 132 includes a first overlapping sub-hole FK111. For example, the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. An insulating material is deposited on the first insulating layer 132 to form a buffer layer 133 through a patterning process. The buffer layer 133 includes a third overlapping sub-hole FK113. A semiconductor material is deposited on the buffer layer 133 to form the active layer TA2 of the driving circuit T2 of the sub-pixel driving circuit and the first plate CST1 of the storage capacitor CST through a patterning process, that is, to form Figure 9D The semiconductor layer ACT shown in FIG.

[0200] For example, Figure 14A As shown, an insulating material is deposited on the semiconductor layer ACT and a fourth insulating layer 137 is formed by patterning. A metal material is deposited on the fourth insulating layer 137 to form the gate TG2 of the driving circuit T2 of the sub-pixel driving circuit, that is, to form a gate TG2 of the sub-pixel driving circuit T2. Figure 9E The second conductive layer GATE is shown. The material of the gate electrode TG2 of the driving circuit T2 includes, for example, a metal material or an alloy material, such as a metal single layer or multilayer structure formed of molybdenum, aluminum, and titanium. For example, the multilayer structure is a multi-metal stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). An insulating material is deposited on the second conductive layer GATE and a second insulating layer 134 is formed by a patterning process. The second insulating layer 134 includes a second bonding sub-hole FK112. A metal material is deposited on the second insulating layer 134 and a patterning process is formed to form the first electrode TSD21 and the second electrode TSD22 of the driving circuit T2 and the first bonding electrode FD11, that is, the first conductive layer SD. For example, the material of the first electrode TSD21 and the second electrode TSD22 of the driving circuit T2 and the first bonding electrode FD11 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed of molybdenum, aluminum, and titanium. For example, the multilayer structure is a multi-metal stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). A passivation layer 135 and a third insulating layer 136 are sequentially formed on the first conductive layer SD. The passivation layer 135 and the third insulating layer 136 include a second landing hole FK12 and a via hole exposing the sub-pixel driving circuit.

[0201] For example, Figure 14AAs shown, a metal material is deposited on the third insulating layer 136 and a patterning process is used to form the first layer AN1 of the first electrode layer AN. The first layer AN1 of the first electrode layer AN includes two parts spaced apart from each other, namely the first sub-electrode layer FD121 of the second strapping electrode FD12 and a layer of the first electrode 161 of the light-emitting element 160 close to the base substrate. The first sub-electrode layer FD121 of the second strapping electrode FD12 is connected to the first strapping electrode through the second strapping hole FK12. The layer of the first electrode 161 of the light-emitting element 160 close to the base substrate is connected to the sub-pixel driving circuit through vias in the metal layer 135 and the third insulating layer 136. For example, the material of the first layer AN1 of the first electrode layer AN includes at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0202] For example, Figure 14B As shown, a material layer M2 is formed on the first layer AN1 of the first electrode layer AN, for example, by evaporation, and the material layer M2 is used to form the second layer AN2 of the first electrode 161. For example, the material layer M2 may include an alloy material, such as AlNd.

[0203] For example, Figure 14C As shown, a material layer M3 is formed on the material layer M2, for example, by magnetron sputtering, and the material layer M3 is used to form the third layer AN3 of the first electrode 161. For example, the material layer M3 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0204] For example, Figure 14D As shown, the material layer M3 is patterned to form a third sub-electrode layer FD123 of the second strapping electrode FD12 and a layer of the first electrode 161 of the light-emitting element 160 away from the substrate, that is, a third layer AN3.

[0205] For example, Figure 14E As shown, the material layer M2 is patterned to form the second sub-electrode layer FD122 of the second bonding electrode FD12 and the intermediate layer between the first electrode 161 of the light-emitting element 160 , that is, the second layer AN2 .

[0206] pass Figures 14A to 14E The preparation process of the first electrode layer AN where the first electrode 161 of the first light-emitting element is located can make the cross-section of the first electrode 161 of the light-emitting element 160 be I-shaped and the cross-sections of the first sub-electrode layer FD121, the second sub-electrode layer FD122 and the third sub-electrode layer FD123 be I-shaped.

[0207] For example, Figure 14FAs shown, a pixel defining layer 138, a light-emitting layer 163 of the light-emitting element 160, a second electrode 162 of the light-emitting element 160, an encapsulation layer 139, a black matrix BM, a filter layer LG, a light-transmitting layer 1310, and a protective layer 1311 are formed one by one on the first electrode layer AN. The detailed preparation process of the above-mentioned film layers is not repeated here.

[0208] It should be noted that the structure of each film layer formed during the preparation of the display substrate 2 can refer to the Figure 3 The introduction will not be described in detail here.

[0209] There are a few points to note:

[0210] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0211] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0212] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A base substrate includes a display area, wherein the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along a first direction, the pixel area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the base substrate, the sub-pixel driving circuit is configured to drive the light-emitting element to emit light, the light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode, a light shielding layer, disposed on the base substrate and located on a side of the sub-pixel driving circuit close to the base substrate, wherein at least a portion of an orthographic projection of the light shielding layer on the base substrate overlaps with an orthographic projection of the sub-pixel driving circuit on the base substrate. The light shielding layer is connected to the second electrode to serve as an auxiliary electrode of the second electrode. The pixel area includes an electrode overlapping area, the electrode overlapping area is located on a side of the pixel area close to the transparent area, and the orthographic projection of the electrode overlapping area on the plate surface of the base substrate at least partially overlaps with the orthographic projection of the light shielding layer on the plate surface of the base substrate. The electrode overlapping region includes a first composite hole structure and a first composite overlapping electrode, and the light shielding layer is connected to the second electrode through the first composite overlapping electrode and the first composite hole structure.

2. The display substrate according to claim 1, wherein The first composite bonding electrode includes a first bonding electrode and a second bonding electrode, and the first composite hole structure includes a first bonding hole and a second bonding hole. The first bonding electrode is connected to the light shielding layer through the first bonding hole, the second bonding electrode is connected to the first bonding electrode through the second bonding hole, and the second bonding electrode is also connected to the second electrode.

3. The display substrate according to claim 2, further comprising: a first insulating layer, a second insulating layer, a first conductive layer, a third insulating layer, and a first electrode layer, The first insulating layer is located on a side of the light-shielding layer away from the base substrate, the second insulating layer is located on a side of the first insulating layer away from the base substrate, the first conductive layer is located on a side of the second insulating layer away from the base substrate, the third insulating layer is located on a side of the first conductive layer away from the base substrate, and the first electrode layer is located on a side of the third insulating layer away from the base substrate. The first overlapping hole includes a first overlapping sub-hole penetrating the first insulating layer and a second overlapping sub-hole penetrating the second insulating layer, the second overlapping sub-hole is sleeved in the first overlapping sub-hole, the first overlapping sub-hole and the second overlapping sub-hole are configured to expose the light shielding layer, and the second overlapping hole penetrates the third insulating layer to expose the first overlapping electrode. The first conductive layer includes the first bonding electrode, The first electrode layer includes the second bonding electrode and the first electrode of the light-emitting element, The first electrode and the second bonding electrode are provided in the same layer and with the same material, and the first electrode and the second bonding electrode are spaced apart from each other.

4. The display substrate according to claim 3, further comprising a buffer layer, in, The buffer layer is located between the first insulating layer and the second insulating layer. The first overlapping hole further includes a third overlapping sub-hole, and the third overlapping sub-hole is sleeved between the first overlapping sub-hole and the second overlapping sub-hole. The third overlapping sub-hole passes through the buffer layer and is configured to expose the light shielding layer.

5. The display substrate according to claim 3, further comprising a passivation layer, in, The passivation layer is located between the third insulating layer and the first conductive layer, The second overlapping hole also penetrates the passivation layer.

6. The display substrate according to claim 3, wherein: The second strapping electrode includes a first sub-electrode layer, a second sub-electrode layer, and a third sub-electrode layer stacked on top of each other, the first sub-electrode layer is located on a side of the third sub-electrode layer close to the base substrate, and the second sub-electrode layer is located between the first sub-electrode layer and the third sub-electrode layer. In a direction parallel to the plate surface of the base substrate, the orthographic projection of the second sub-electrode layer on the plate surface of the base substrate is located in the orthographic projection of the first sub-electrode layer on the plate surface of the base substrate, The orthographic projection of the third sub-electrode layer on the board surface of the base substrate is located in the orthographic projection of the first sub-electrode layer on the board surface of the base substrate, and the area of the orthographic projection of the first sub-electrode layer on the board surface of the base substrate is larger than the area of the orthographic projection of the third sub-electrode layer on the board surface of the base substrate.

7. The display substrate according to claim 6, wherein: The projected area of the second sub-electrode layer on the plate surface of the base substrate is smaller than the projected areas of the first sub-electrode layer and the third sub-electrode layer on the plate surface of the base substrate. The cross sections of the first sub-electrode layer, the second sub-electrode layer, and the third sub-electrode layer are in an I-shape, and the first sub-electrode layer is connected to the first bonding electrode through the second bonding hole.

8. The display substrate according to claim 6, further comprising a pixel defining layer, in, The pixel defining layer is located on a side of the first electrode away from the base substrate. In the electrode overlapping region, at least a portion of the pixel defining layer covers a region of the first sub-electrode layer that protrudes from the second sub-electrode layer.

9. The display substrate according to claim 8, wherein: The light-emitting layer of the light-emitting element is stacked on a side of the pixel defining layer away from the base substrate. The light-emitting layer includes a first part and a second part located in the electrode overlapping area, the first part covers at least part of the area of the first sub-electrode layer protruding from the second sub-electrode layer, and the second part is located on the side of the third sub-electrode layer away from the base substrate.

10. The display substrate according to claim 8, wherein The second electrode of the light emitting element includes a first electrode portion and a second electrode portion located in the electrode overlapping region. The first electrode portion is located in a region of the first sub-electrode layer protruding from the second sub-electrode layer, and the first electrode portion is in contact with the first sub-electrode layer and the second sub-electrode layer, and the second electrode portion is located on a side of the second portion of the light-emitting layer away from the base substrate. The orthographic projection of the first portion of the light-emitting layer on the plate surface of the base substrate at least partially overlaps with the orthographic projection of the first electrode portion on the plate surface of the base substrate.

11. The display substrate according to claim 8, further comprising a filter layer and a black matrix, wherein: The filter layer and the black matrix are located on a side of the light emitting element away from the base substrate. In each pixel area, the black matrix includes a plurality of light shielding lines extending along the first direction. The filter layer includes a first sub-pixel filter region, a second sub-pixel rate filter region, and a third sub-pixel filter region, wherein the first sub-pixel filter region, the second sub-pixel rate filter region, and the third sub-pixel filter region are arranged in a second direction different from the first direction. At least a portion of the orthographic projection of the plurality of light-shielding lines on the surface of the base substrate overlaps with the first sub-pixel filter region, the second sub-pixel filter region, and the third sub-pixel filter region at an interval in the second direction. In addition to the plurality of light-shielding lines, on a side of the filter layer close to the transparent area, the black matrix does not include other light-shielding lines extending along the first direction.

12. The display substrate according to claim 11, wherein: In the first direction, on the side of the pixel area close to the transparent area, the orthographic projections of the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area on the surface of the base substrate partially overlap with the orthographic projection of the pixel defining layer on the surface of the base substrate.

13. The display substrate according to claim 12, wherein: The portions of the first sub-pixel filter region, the second sub-pixel rate filter region, and the third sub-pixel filter region that overlap with the pixel defining layer in a direction perpendicular to the base substrate have a size range of 5 microns to 7 microns along the first direction.

14. The display substrate according to claim 12, wherein: The first sub-pixel filter region, the second sub-pixel filter region, and the third sub-pixel filter region are a red light region, a green light region, and a blue light region, respectively.

15. The display substrate according to any one of claims 11 to 14, wherein: In each of the pixel regions, the light shielding layer includes a light shielding electrode, the light shielding electrode extends along the second direction, and at least a portion of an orthographic projection of the light shielding electrode on the surface of the base substrate overlaps with an orthographic projection of a plurality of sub-pixel driving circuits in each of the pixel regions on the surface of the base substrate. The light-shielding electrode includes a first end, a middle recess and a second end in the second direction. The middle recess is located between the first end and the second end. The widths of the first end and the second end in the first direction are greater than the width of the middle recess in the first direction.

16. The display substrate according to claim 15 , further comprising a peripheral area, a gate driving circuit, and a plurality of gate lines extending along a first direction, wherein the peripheral area at least partially surrounds the display area, the gate driving circuit is located in the peripheral area, and the plurality of gate lines are connected to the gate driving circuit and to the sub-pixel driving circuits of the pixel areas of each row of the repeating units extending along the first direction. The gate driving circuit is configured to output gate scanning signals one by one to drive the plurality of sub-pixels of the pixel area of each row of the repeating unit extending along the first direction. The plurality of repeating units are arranged in N rows extending along the first direction respectively, the gate driving circuit includes N cascaded shift register units, the n-th stage shift register unit is connected to the sub-pixel driving circuit of the pixel area of the n-th row of repeating units, wherein, 1≤n≤N, where N is an integer greater than or equal to 2.

17. The display substrate according to claim 16, wherein: A plurality of sub-pixel driving circuits in each pixel area are arranged along the first direction, and each sub-pixel driving circuit includes a data writing circuit, a driving circuit, a charge storage circuit, and a sensing circuit. The driving circuit is connected to a first node, a second node, and a third node, wherein the third node is further connected to a first power supply voltage terminal, and the driving circuit is configured to receive the first power supply voltage through the third node and control a driving current flowing through the light-emitting element under control of a level of the first node; The data writing circuit is connected to the first node and is configured to receive the gate scanning signal as a scanning driving signal and write a data signal into the first node in response to the scanning driving signal; The charge storage circuit is connected to the first node and the second node, and is configured to store the written data signal and the reference voltage signal; The sensing circuit is connected to the second node and configured to receive the gate scanning signal as a sensing driving signal, and write the reference voltage signal into the driving circuit or read the sensing voltage signal from the driving circuit in response to the sensing driving signal; The light emitting element is connected to the second node and a second power supply voltage terminal, and is configured to receive a second power supply voltage through the second power supply voltage terminal and emit light under the driving of the driving current.

18. The display substrate according to claim 17, wherein: The data writing circuit is implemented as a data writing transistor, the driving circuit is implemented as a driving transistor, and the sensing circuit is implemented as a sensing transistor. The orthographic projections of the active layers of the data writing transistor and the driving transistor on the plate surface of the base substrate overlap with the orthographic projection of the second end portion of the light shielding electrode on the plate surface of the base substrate. The orthographic projection of the active layer of the sensing transistor on the surface of the base substrate overlaps with the orthographic projection of the first end portion of the light-shielding electrode on the surface of the base substrate.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

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