Solid-state image pickup device

Abstract

The present invention improves image quality in a solid-state imaging device in which all pixels are exposed at the same time. An upstream circuit generates a predetermined reset level and a signal level corresponding to an exposure amount in sequence, and causes each of first and second capacitive elements to hold the reset level and the signal level. A selection circuit performs control for connecting one of the first and second capacitive elements to a predetermined downstream node, control for disconnecting both of the first and second capacitive elements from the downstream node, and control for connecting the other of the first and second capacitive elements to the downstream node in sequence. When both of the first and second capacitive elements are disconnected from the downstream node, a downstream reset transistor initializes the level of the downstream node. A downstream circuit reads out the reset level and the signal level from the first and second capacitive elements in sequence via the downstream node, and outputs the read-out reset level and signal level.

Description

Technical Field

[0001] This technology relates to solid-state imaging elements. Specifically, this technology relates to a control method for solid-state imaging elements that perform analog-to-digital (AD) conversion for each column. Background Technology

[0002] Typically, to achieve pixel miniaturization, solid-state imaging devices have used column analog-to-digital converter (ADC) systems where an ADC is positioned outside the pixel array for each column, and pixel signals are read out row by row. In such a column ADC system, rolling shutter distortion may occur when exposure is performed using a rolling shutter method that starts exposure row by row. Therefore, a solid-state imaging device has been proposed (see, for example, Non-Patent Document 1) in which, to achieve a global shutter method where exposure starts simultaneously in all pixels, a pair of capacitors is provided for each pixel to hold the reset level and signal level. This pair of capacitors is connected in series with a source follower circuit via a node, and the reset level and signal level are read out sequentially using this source follower circuit.

[0003] List of cited references

[0004] Non-patent literature

[0005] Non-patent document 1: Jae-kyu Lee, et al., A 2.1e-Temporal Noise and-105dBParasitic Light Sensitivity Backside-Illuminated 2.3μm-Pixel Voltage-DomainGlobal Shutter CMOS Image Sensor Using High-Capacity DRAM CapacitorTechnology, ISSCC 2020. Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] In the aforementioned conventional techniques, the global shutter mode in a column ADC system is achieved by maintaining the reset level and signal level in a pair of capacitors for each pixel. However, when the transistor in the source-coupled follower circuit initializes the node connected to the capacitor, there is a possibility that kTC noise (in other words, reset noise) corresponding to the capacitor level will be generated, thus degrading the image quality of the image data due to noise.

[0008] The present technology was achieved in view of the above-described circumstances, and aims to improve the image quality of a solid-state imaging device in which all pixels are exposed at the same time.

[0009] Technical solution to the problem

[0010] The present technology was achieved in view of the above-described circumstances, and aims to improve the image quality of a solid-state imaging device in which all pixels are exposed at the same time.

[0011] Further, in the first aspect, there can be further provided: an upstream selection transistor for opening and closing a path between the upstream circuit and a predetermined upstream node; and an upstream reset transistor for initializing a level of the upstream node. Further, the first and second capacitive elements each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit. This brings an effect of blocking noise from the upstream circuit.

[0012] Further, in the first aspect, during a period in which the upstream circuit causes the first and second capacitive elements each to hold the reset level and the signal level, the upstream selection transistor can be transitioned to a closed state, and during a period in which the downstream circuit sequentially reads out the reset level and the signal level from the first and second capacitive elements, the upstream reset transistor can initialize a level of the upstream node. This brings an effect of fixing a potential of the upstream node at the time of reading out.

[0013] Further, in the first aspect, the upstream circuit can include a photoelectric conversion element, an upstream transfer transistor that transfers a charge from the photoelectric conversion element to a floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, and an upstream amplification transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node. Further, the first and second capacitor elements can each have a first terminal commonly connected to the upstream node and each have a second terminal connected to the selection circuit. This brings an effect of providing a signal corresponding to a potential of the floating diffusion layer to the upstream node.

[0014] Further, in the first aspect, a switching section for adjusting a source voltage to be supplied to a source of the upstream amplification transistor can be provided. The upstream circuit can further include a current source transistor connected to a drain of the upstream amplification transistor. Further, after an end of an exposure period, the current source transistor can transition from an ON state to an OFF state. This brings an effect of letting the source follower of the upstream be in the OFF state at the time of readout.

[0015] Further, in the first aspect, during the exposure period, the switching section can supply a predetermined power supply voltage as the source voltage, and after the end of the exposure period, the switching section can supply a generated voltage different from the power supply voltage as the source voltage. This brings an effect of adjusting the source voltage of the source follower of the upstream.

[0016] Further, in the first aspect, a difference between the power supply voltage and the generated voltage can be substantially in accordance with a sum of a variation amount caused by reset feedthrough of the first reset transistor and a gate-source voltage of the upstream amplification transistor. This brings an effect of equalizing the potential of the upstream node at the time of exposure and at the time of readout.

[0017] Further, in the first aspect, at a predetermined exposure start timing, the upstream transfer transistor can transfer the charge to the floating diffusion layer, and the first reset transistor can initialize the photoelectric conversion element together with the floating diffusion layer. Further, at a predetermined exposure end timing, the upstream transfer transistor can transfer the charge to the floating diffusion layer. This brings an effect of generating a pixel signal corresponding to an exposure amount.

[0018] Further, in the first aspect, the upstream circuit can further include a drain transistor for draining the charge from the photoelectric conversion element. This brings an effect of initializing the photoelectric conversion element.

[0019] Further, in the first aspect, the first reset transistor can initialize the floating diffusion layer before a predetermined exposure start timing, and the drain transistor can drain the electric charge from the photoelectric conversion element. Further, at a predetermined exposure end timing, the upstream transfer transistor can transfer the electric charge to the floating diffusion layer. This brings an effect of realizing a very short exposure time.

[0020] Further, in the first aspect, a control circuit for controlling a reset power supply voltage of the upstream circuit is further provided. The first reset transistor can initialize the voltage of the floating diffusion layer to the reset power supply voltage. Further, the control circuit can set the reset power supply voltage to a voltage different from that during exposure within a readout period for reading out the reset level and the signal level. This brings an effect of improving light sensitivity unevenness.

[0021] Further, in the first aspect, a difference between the reset power supply voltage within the readout period and the reset power supply voltage within the exposure period can be substantially the same as an amount of variation caused by reset feedthrough of the first reset transistor. This brings an effect of improving light sensitivity unevenness.

[0022] Further, in the first aspect, a first reset signal can be input to a gate of the first reset transistor, and an amplitude of the first reset signal can be a value obtained by adding a predetermined margin to a value corresponding to a dynamic range. This brings an effect of suppressing a black spot phenomenon.

[0023] Further, in the first aspect, a digital signal processing section for adding a pair of consecutive frames can be further provided. The upstream circuit can cause one of the first and second capacitive elements to hold the reset level during exposure of one of the pair of frames, and then cause the other of the first and second capacitive elements to hold the signal level. Further, the upstream circuit can cause the other of the first and second capacitive elements to hold the reset level during exposure of the other of the pair of frames, and then cause the one of the first and second capacitive elements to hold the signal level. This brings an effect of improving light sensitivity unevenness.

[0024] Further, in the first aspect, an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals can be further provided. This brings an effect of generating digital image data.

[0025] Further, in the first aspect, the analog-digital converter can include a comparator that compares a level of a vertical signal line for transmitting the reset level and the signal level with a predetermined ramp signal and outputs a comparison result, and a counter that counts a count value during a period until the comparison result is inverted and outputs the digital signal representing the count value. This brings an effect of realizing analog-digital conversion by a simple structure.

[0026] Further, in the first aspect, the comparator can include a comparison section that compares levels of a pair of input terminals and outputs a comparison result, and an input-side selector that selects either of the vertical signal line and a node having a predetermined reference voltage and connects the selected vertical signal line or node to one of the pair of input terminals. Further, the ramp signal can be input to one of the pair of input terminals. This brings an effect of suppressing a black spot phenomenon.

[0027] Further, in the first aspect, there can be further provided a control section that determines whether or not illuminance is higher than a predetermined value based on the comparison result and outputs a determination result, a correlated double sampling (CDS) processing section that performs a CDS process on the digital signal, and an output-side selector that outputs the digital signal on which the CDS process is performed or a digital signal having a predetermined value based on the determination result. This brings an effect of suppressing a black spot phenomenon.

[0028] Further, in the first aspect, there can be further provided a vertical scanning circuit that performs control for controlling a plurality of lines each of which is arranged with a predetermined number of pixels to start exposure at the same time. Further, the first capacitor element, the second capacitor element, the upstream circuit, the selection circuit, the downstream reset transistor, and the downstream circuit can be arranged in each of the pixels. This brings an effect of making it easy to miniaturize pixels.

[0029] Further, in the first aspect, the vertical scanning circuit can further perform control for controlling the plurality of lines to start exposure in sequence. This brings an effect of making it easy to miniaturize pixels.

[0030] Further, in the first aspect, the upstream circuit can be provided on a first chip, and the first capacitor element, the second capacitor element, the selection circuit, the downstream reset transistor, and the downstream circuit can be provided on a second chip. This brings an effect of making it easy to miniaturize pixels.

[0031] Further, in the first aspect, an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals can be provided, and the analog-digital converter can be provided on the second chip. This brings an effect that makes it easy to miniaturize pixels.

[0032] Further, in the first aspect, an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals can be provided, and the analog-digital converter can be provided on the third chip. This brings an effect that makes it easy to miniaturize pixels.

[0033] Further, a second aspect of the present technology relates to a solid-state imaging device including: a photoelectric conversion section that converts incident light into an electric charge; a first amplification transistor that converts the electric charge into a voltage; a signal line that outputs a pixel signal; a first capacitor element whose first end is connected to a first node that is a destination of an output of the first amplification transistor; a second capacitor element that is provided in parallel with the first capacitor element between the first amplification transistor and the signal line, a first end of the second capacitor element being connected to the first node; a first selection transistor that is connected to the first capacitor element at a second end of the first capacitor element; a second selection transistor that is connected to the second capacitor element at a second end of the second capacitor element; a reset transistor whose source or drain is connected to a second node at which the first selection transistor and the second selection transistor are connected; and a second amplification transistor whose gate is connected to the second node, the second amplification transistor outputting the pixel signal. This brings an effect of generating image data with reduced kTC noise. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a block diagram illustrating a configuration example of an imaging device in the first embodiment of the present technology.

[0035] Figure 2 is a block diagram illustrating a configuration example of a solid-state imaging device in the first embodiment of the present technology.

[0036] Figure 3 is a circuit diagram illustrating a configuration example of a pixel in the first embodiment of the present technology.

[0037] Figure 4 is a block diagram illustrating a configuration example of a column signal processing circuit and a load MOS circuit block in the first embodiment of the present technology.

[0038] Figure 5 is a timing chart illustrating an example of a global shutter operation in the first embodiment of the present technology.

[0039] Figure 6is a timing chart showing an example of a read operation in the first embodiment of the present technology.

[0040] Figure 7 is a timing chart showing another example of a read operation in the first embodiment of the present technology.

[0041] Figure 8 is a circuit diagram showing a configuration example of a pixel in a comparative example.

[0042] Figure 9 is a graph showing an example of a state of a pixel in the first embodiment of the present technology at the time of reading out a reset level and at the time of initializing a downstream node.

[0043] Figure 10 is a graph showing an example of a state of a pixel in the first embodiment of the present technology at the time of reading out a signal level.

[0044] Figure 11 is a flowchart showing an example of an operation of a solid-state imaging device in the first embodiment of the present technology.

[0045] Figure 12 is a circuit diagram showing a configuration example of a pixel in the first modified example of the first embodiment of the present technology.

[0046] Figure 13 is a timing chart showing an example of a global shutter operation in the first modified example of the first embodiment of the present technology.

[0047] Figure 14 is a timing chart showing an example of a read operation in the first modified example of the first embodiment of the present technology.

[0048] Figure 15 is a graph showing an example of a stacked structure of a solid-state imaging device in the second modified example of the first embodiment of the present technology.

[0049] Figure 16 is a circuit diagram showing a configuration example of a pixel in the second modified example of the first embodiment of the present technology.

[0050] Figure 17 is a graph showing an example of a stacked structure of a solid-state imaging device in the third modified example of the first embodiment of the present technology.

[0051] Figure 18 is a circuit diagram showing a configuration example of a pixel in the second embodiment of the present technology.

[0052] Figure 19 is a timing chart showing an example of a global shutter operation in the second embodiment of the present technology.

[0053] Figure 20is a circuit diagram showing a configuration example of a pixel in the third embodiment of the present technology.

[0054] Figure 21 is a diagram for explaining reset feedthrough in the third embodiment of the present technology.

[0055] Figure 22 is a diagram for explaining a level change caused by reset feedthrough in the third embodiment of the present technology.

[0056] Figure 23 is a timing chart showing an example of voltage control in the third embodiment of the present technology.

[0057] Figure 24 is a timing chart showing an example of global shutter operation of an odd frame in the fourth embodiment of the present technology.

[0058] Figure 25 is a timing chart showing an example of readout operation of an odd frame in the fourth embodiment of the present technology.

[0059] Figure 26 is a timing chart showing an example of global shutter operation of an even frame in the fourth embodiment of the present technology.

[0060] Figure 27 is a timing chart showing an example of readout operation of an even frame in the fourth embodiment of the present technology.

[0061] Figure 28 is a circuit diagram showing a configuration example of a column signal processing circuit in the fifth embodiment of the present technology.

[0062] Figure 29 is a timing chart showing an example of global shutter operation in the fifth embodiment of the present technology.

[0063] Figure 30 is a timing chart showing an example of readout operation in the fifth embodiment of the present technology.

[0064] Figure 31 is a timing chart showing an example of rolling shutter operation in the sixth embodiment of the present technology.

[0065] Figure 32 is a block diagram showing a configuration example of a solid-state imaging device in the seventh embodiment of the present technology.

[0066] Figure 33 is a circuit diagram showing a configuration example of a dummy pixel, a regulator, and a switching section in the seventh embodiment of the present technology.

[0067] Figure 34 is a timing chart showing an example of operation of a dummy pixel and a regulator in the seventh embodiment of the present technology.

[0068] Figure 35 is a circuit diagram showing a configuration example of an effective pixel in the seventh embodiment of the present technology.

[0069] Figure 36 is a timing chart showing an example of a global shutter operation in the seventh embodiment of the present technology.

[0070] Figure 37 is a timing chart showing an example of a read operation in the seventh embodiment of the present technology.

[0071] Figure 38 is a graph for explaining an effect in the seventh embodiment of the present technology.

[0072] Figure 39 is a block diagram showing a schematic configuration example of a vehicle control system.

[0073] Figure 40 is an explanatory diagram showing an example of a setting position of an imaging section. DETAILED DESCRIPTION

[0074] Hereinafter, a scheme for implementing the present technology (hereinafter, referred to as an embodiment) will be explained. The explanation will be given in the following order.

[0075] 1. First embodiment (example in which a pixel signal is held in first and second capacitive elements)

[0076] 2. Second embodiment (example in which a drain transistor is added, and a pixel signal is held in first and second capacitive elements)

[0077] 3. Third embodiment (example in which a pixel signal is held in first and second capacitive elements, and a control reset power voltage is suppressed)

[0078] 4. Fourth embodiment (example in which a pixel signal is held in first and second capacitive elements, and a level to be held is switched for each frame)

[0079] 5. Fifth embodiment (example in which a pixel signal is held in first and second capacitive elements, and a black spot phenomenon is suppressed)

[0080] 6. Sixth embodiment (example in which a pixel signal is held in first and second capacitive elements, and a rolling shutter operation is performed)

[0081] 7. Application example of mobile body

[0082] <1. First embodiment>

[0083] [Configuration example of imaging device]

[0084] Figure 1 is a block diagram showing a configuration example of an imaging device 100 in the first embodiment of the present technology. The imaging device 100 is a device that images image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording section 120, and an imaging control section 130. As the imaging device 100, a digital camera or an electronic device (a smartphone, a personal computer, or the like) having an imaging function is assumed.

[0085] The solid-state imaging element 200 images image data under the control of the imaging control section 130. The solid-state imaging element 200 supplies the image data to the recording section 120 via a signal line 209.

[0086] The imaging lens 110 converges light and guides the light to the solid-state imaging element 200. The imaging control section 130 controls the solid-state imaging element 200 to image image data. The imaging control section 130 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200, for example, via a signal line 139. The recording section 120 records the image data.

[0087] Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and a periodic signal of a constant frequency (such as 60 Hz or the like) is used as the vertical synchronization signal VSYNC.

[0088] Incidentally, the imaging device 100 records image data, which can be transferred to the outside of the imaging device 100. In this case, an external interface configured to transfer the image data is also provided. Alternatively, the imaging device 100 can also display the image data. In this case, a display section is also provided.

[0089] [Configuration Example of Solid-State Imaging Element]

[0090] Figure 2 is a block diagram showing a configuration example of the solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 220, a plurality of pixels 300 are arranged in a two-dimensional lattice pattern. Furthermore, each circuit in the solid-state imaging element 200 is provided on, for example, a single semiconductor chip.

[0091] Hereinafter, a set of the pixels 300 arranged in a horizontal direction is referred to as a "row", and a set of the pixels 300 arranged in a direction perpendicular to the row is referred to as a "column".

[0092] The timing control circuit 212 controls the operation timing of each of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130.

[0093] The DAC 213 generates a ramp signal in a sawtooth waveform shape through digital-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0094] The vertical scanning circuit 211 selects and drives the rows one by one and outputs an analog pixel signal. The pixel 300 photoelectrically converts incident light to generate the analog pixel signal. The pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0095] In the load MOS circuit block 250, a MOS transistor that supplies a constant current is provided for each column.

[0096] The column signal processing circuit 260 performs signal processing such as AD conversion processing and CDS processing on the pixel signal of each column. The column signal processing circuit 260 supplies image data including the processed signal to the recording section 120. Incidentally, the column signal processing circuit 260 is an example of the signal processing circuit recited in the claims.

[0097] [Example of Configuration of Pixel]

[0098] Figure 3 is a circuit diagram showing an example of the configuration of the pixel 300 in the first embodiment of the present technology. The pixel 300 includes an upstream circuit 310, capacitive elements 321 and 322, a selection circuit 330, a downstream reset transistor 341, and a downstream circuit 350.

[0099] The upstream circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, an FD reset transistor 313, an FD (floating diffusion) 314, an upstream amplification transistor 315, and a current source transistor 316.

[0100] The photoelectric conversion element 311 generates a charge through photoelectric conversion. The transfer transistor 312 transfers the charge from the photoelectric conversion element 311 to the FD 314 according to a transfer signal trg from the vertical scanning circuit 211.

[0101] The FD reset transistor 313 extracts the electric charge from the FD 314 and performs initialization according to an FD reset signal rst from the vertical scanning circuit 211. The FD 314 accumulates the electric charge and generates a voltage corresponding to the amount of the electric charge. The upstream amplification transistor 315 amplifies the voltage level of the FD 314 and outputs the amplified voltage to the upstream node 320. Incidentally, the FD reset transistor 313 is an example of the first reset transistor recited in the claims. Further, the upstream amplification transistor 315 is an example of the first amplification transistor recited in the claims.

[0102] Further, the source of the FD reset transistor 313 and the source of the upstream amplification transistor 315 are connected to a power supply voltage VDD. The current source transistor 316 is connected to the drain of the upstream amplification transistor 315. The current source transistor 316 supplies a current idl under the control of the vertical scanning circuit 211.

[0103] One end of each of the capacitive elements 321 and 322 is commonly connected to the upstream node 320, and the other end of each of them is connected to the selection circuit 330. Incidentally, the capacitive elements 321 and 322 are examples of the first and second capacitive elements recited in the claims.

[0104] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens and closes a path between the capacitive element 321 and the downstream node 340 according to a selection signal Φr from the vertical scanning circuit 211. The selection transistor 332 opens and closes a path between the capacitive element 322 and the downstream node 340 according to a selection signal Φs from the vertical scanning circuit 211.

[0105] The downstream reset transistor 341 initializes the level of the downstream node 340 to a predetermined potential Vreg according to a downstream reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply potential VDD (for example, a potential lower than VDD) is set as the potential Vreg.

[0106] The downstream circuit 350 includes a downstream amplification transistor 351 and a downstream selection transistor 352. The downstream amplification transistor 351 amplifies the level of the downstream node 340. The downstream selection transistor 352 outputs a signal of the level amplified by the downstream amplification transistor 351 as a pixel signal to the vertical signal line 309 according to a downstream selection signal selb from the vertical scanning circuit 211. Incidentally, the downstream amplification transistor is an example of the second amplification transistor recited in the claims.

[0107] Incidentally, as the various transistors (transfer transistor 312 and the like) in the pixel 300, for example, an n-channel metal oxide semiconductor (nMOS) transistor is used.

[0108] At the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a transfer signal trg to all the pixels. Thus, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset".

[0109] Then, just before the end of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst for all the pixels while setting the downstream reset signal rstb and the selection signal Φr to high levels for a pulse period. Thus, the FD 314 is initialized, and a level corresponding to the level of the FD 314 at this time is held in the capacitance element 321. This control is hereinafter referred to as "FD reset".

[0110] The level of the FD 314 at the time of the FD reset and the level corresponding to the level (the level held in the capacitance element 321 and the level of the vertical signal line 309) are hereinafter collectively referred to as "P-phase" or "reset level".

[0111] When the exposure ends, the vertical scanning circuit 211 supplies a high-level transfer signal trg for all the pixels while setting the downstream reset signal rstb and the selection signal Φs to high levels for a pulse period. Thus, the signal charge corresponding to the exposure amount is transferred to the FD 314, and a level corresponding to the level of the FD 314 at this time is held in the capacitance element 322.

[0112] The level of the FD 314 at the time of the transfer of the signal charge and the level corresponding to the level (the level held in the capacitance element 322 and the level of the vertical signal line 309) are hereinafter collectively referred to as "D-phase" or "signal level".

[0113] This exposure control that starts and ends exposure for all the pixels at the same time is referred to as a global shutter method. With this exposure control, the upstream circuit 310 of all the pixels generates a reset level and a signal level in turn. The reset level is held in the capacitance element 321, and the signal level is held in the capacitance element 322.

[0114] After the exposure ends, the vertical scanning circuit 211 selects the rows one by one and outputs the reset level and the signal level of the row one by one. When the reset level is to be output, the vertical scanning circuit 211 provides the high-level selection signal Φr for a predetermined period while setting the FD reset signal rst and the downstream selection signal selb of the selected row to the high level. Thus, the capacitor element 321 is connected to the downstream node 340, and the reset level is read out.

[0115] After the reset level is read out, the vertical scanning circuit 211 provides the high-level downstream reset signal rstb for a pulse period while maintaining the FD reset signal rst and the downstream selection signal selb of the selected row at the high level. Thus, the level of the downstream node 340 is initialized. At this time, both the selection transistor 331 and the selection transistor 332 are in the open state, and the capacitor elements 321 and 322 are disconnected from the downstream node 340.

[0116] After the downstream node 340 is initialized, the vertical scanning circuit 211 provides the high-level selection signal Φs for a predetermined period while maintaining the FD reset signal rst and the downstream selection signal selb of the selected row at the high level. Thus, the capacitor element 322 is connected to the downstream node 340, and the signal level is read out.

[0117] Through the above-described readout control, the selection circuit 330 of the selected row performs the control of connecting the capacitor element 321 to the downstream node 340, the control of disconnecting the capacitor elements 321 and 322 from the downstream node 340, and the control of connecting the capacitor element 322 to the downstream node 340 one by one. Further, when the capacitor elements 321 and 322 are disconnected from the downstream node 340, the downstream reset transistor 341 of the selected row initializes the level of the downstream node 340. Further, the downstream circuit 350 of the selected row reads out the reset level and the signal level from the capacitor elements 321 and 322 via the downstream node 340 one by one and outputs the readout reset level and signal level to the vertical signal line 309.

[0118] [Configuration Example of Column Signal Processing Circuit]

[0119] Figure 4 is a block diagram illustrating a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 in the first embodiment of the present technology.

[0120] In the load MOS circuit block 250, the vertical signal line 309 is configured for each column. When the number of columns is I (I is an integer), I vertical signal lines 309 are configured. Further, the load MOS transistor 251 for providing a constant current id2 is connected to each vertical signal line 309.

[0121] In the column signal processing circuit 260, a plurality of ADCs 261 are arranged and a digital signal processing section 262 is arranged. The ADC 261 is arranged for each column. When the number of columns is I, I ADCs 261 are arranged.

[0122] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. For example, a single slope ADC including a comparator and a counter is arranged as the ADC 261.

[0123] The digital signal processing section 262 performs predetermined signal processing such as CDS processing on the digital signal for each column, respectively. The digital signal processing section 262 supplies image data including the processed digital signal to the recording section 120.

[0124] [Operation example of solid-state imaging device]

[0125] Figure 5 is a timing chart showing an example of a global shutter operation in the first embodiment of the present technology. The vertical scanning circuit 211 supplies the high-level FD reset signal rst and the transfer signal trg to all rows (in other words, all pixels) from the time T0 just before the exposure starts to the time T1 after the pulse period elapses. Accordingly, all pixels undergo the PD reset, and the exposure starts at the same time in all rows.

[0126] Here, rst_[n] and trg_[n] in the drawing represent signals with respect to the nth row of pixels of the Nth row. N is an integer representing the total number of rows, and n is an integer from 1 to N.

[0127] Then, at the time T2 just before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst within the pulse period while setting the downstream reset signal rstb and the selection signal Φr to the high level with respect to all pixels. Accordingly, all pixels undergo the FD reset, and the reset level is sampled and held. Here, rstb_[n] and Φr_[n] in the drawing represent signals with respect to the nth row of pixels.

[0128] At the time T3 after the time T2, the vertical scanning circuit 211 returns the selection signal Φr to the low level.

[0129] At the exposure end time T4, the vertical scanning circuit 211 provides a high-level transfer signal trg for the pulse period while setting the downstream reset signal rstb and the selection signal Φs to high levels in all pixels. Therefore, the signal level is sampled and held. Further, the level of the upstream node 320 is decreased from the reset level (VDD-Vsig) to the signal level (VDD-Vgs-Vsig). Here, VDD denotes a power supply voltage, and Vsig denotes a net signal level obtained by CDS processing. Vgs denotes a gate-source voltage of the upstream amplification transistor 315. Further, Φs_[n] in the figure denotes a signal with respect to the nth row of pixels.

[0130] At the time T5 after the time T4, the vertical scanning circuit 211 returns the selection signal Φs to a low level.

[0131] Further, the vertical scanning circuit 211 controls the current source transistor 316 of all rows (all pixels) to provide a current id1. Here, id1_[n] in the figure denotes a current of the nth row of pixels. When the current id is large, the IR drop becomes large, and therefore, the current id1 needs to be on the order of several nanoamperes (nA) to several tens of nanoamperes (nA). On the other hand, the load MOS transistor 251 of all columns is in an off state, and the current id2 is not provided to the vertical signal line 309.

[0132] Figure 6 is a timing chart illustrating an example of a read operation in the first embodiment of the present technology. During the read of the nth row from the time T10 to the time T17, the vertical scanning circuit 211 sets the FD reset signal rst and the downstream selection signal selb of the nth row to high levels. Further, during the read, the downstream reset signal rstb of all rows is controlled to a low level. Here, selb_[n] in the figure denotes a signal with respect to the nth row of pixels.

[0133] During a period from the time T11 to the time T13 immediately after the time T10, the vertical scanning circuit 211 provides a high-level selection signal Φr to the nth row. The potential of the downstream node 340 becomes the reset level Vrst.

[0134] During a period from the time T12 to the time T13 after the time T11, the DAC 213 gradually increases the ramp signal Rmp. The ADC 261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309, and counts a count value until the comparison result is inverted. Therefore, the P-phase level (reset level) is read out.

[0135] In the pulse period from time T14 immediately after time T13, the vertical scanning circuit 211 supplies the downstream reset signal rstb at a high level to the nth row. Therefore, when there is a parasitic capacitance in the downstream node 340, it is possible to erase the history of the last signal held in the parasitic capacitance.

[0136] In the period from time T15 to time T17 immediately after the initialization of the downstream node 340, the vertical scanning circuit 211 supplies the selection signal Φs at a high level to the nth row. The potential of the downstream node 340 becomes the signal level Vsig. Although the signal level is lower than the reset level at the time of exposure, it is higher than the reset level at the time of readout because the downstream node 340 is used as a reference. The difference between the reset level Vrst and the signal level Vsig corresponds to the net signal level from which the reset noise and the offset noise of the FD have been removed.

[0137] In the period from time T16 to time T17 after time T15, the DAC 213 gradually increases the ramp signal Rmp. The ADC 261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309 and counts the count value until the comparison result is inverted. Therefore, the D-phase level (signal level) is read out.

[0138] Further, the vertical scanning circuit 211 controls the current source transistor 316 of the nth row to be read out in the period from time T10 to time T17 to supply the current idl. Further, the timing control circuit 212 controls the load MOS transistor 251 of all columns during the readout period of all rows to supply the current id2.

[0139] Incidentally, the solid-state imaging device 200 reads out the signal level after the reset level, but is not limited to this order. As shown in Figure 7 The solid-state imaging device 200 can also read out the reset level after the signal level. In this case, as shown in the figure, the vertical scanning circuit 211 supplies the selection signal Φr at a high level after the selection signal Φs at a high level. Further, in this case, it is necessary to reverse the slope of the ramp signal.

[0140] Figure 8 is a circuit diagram showing a configuration example of a pixel in a comparative example. In the comparative example, the selection circuit 330 is not provided, and a transfer transistor is inserted between the upstream node 320 and the upstream circuit. Further, capacitors Cl and C2 are inserted in place of the capacitive elements 321 and 322. The capacitor Cl is inserted between the upstream node 320 and a ground terminal, and the capacitor C2 is inserted between the upstream node 320 and the downstream node 340.

[0141] For example, in the non-patent literature 1 of Figure 5Section 5.2 describes the pixel exposure control and readout control in this comparative example. In this comparative example, assuming the capacitance of capacitors C1 and C2 is C, the level Vn of kTC noise during exposure and readout is expressed by the following formula.

[0142] Vn=(3*kT / C) 1 / 2 ...Formula 1

[0143] In the above formula, k is the Boltzmann constant, and its unit is, for example, joules per kelvin (J / K). T is the absolute temperature, and its unit is, for example, kelvin (K). Furthermore, the unit of Vn is, for example, volts (V), and the unit of C is, for example, farads (F).

[0144] Figure 9 This is a diagram illustrating an example of the state of a pixel when reading out the reset level and when initializing the downstream node, according to a first embodiment of the present technology. Figure 9 In this context, 'a' indicates the state of pixel 300 when the reset level is read. Figure 9 In the figure, 'b' represents the state of pixel 300 when the downstream node 340 is initialized. Furthermore, for ease of explanation, in this figure, selection transistor 331, selection transistor 332, and downstream reset transistor 341 are represented by switch graphic symbols.

[0145] like Figure 9 As shown in diagram a, the vertical scan circuit 211 sets select transistor 331 to a closed state and select transistor 332 and downstream reset transistor 341 to an open state. Therefore, the reset level is read out via downstream circuit 350.

[0146] like Figure 9 As shown in b, after reading the reset level, the vertical scan circuit 211 sets select transistors 331 and 332 to the open-circuit state and sets the downstream reset transistor 341 to the closed-circuit state. Therefore, capacitors 321 and 322 are both disconnected from the downstream node 340, and the level of the downstream node 340 is initialized.

[0147] In this way, the parasitic capacitance Cp of the downstream node 340, which is disconnected from capacitor elements 321 and 322, is set to be very small compared to the capacitance values ​​of capacitor elements 321 and 322. For example, assuming the parasitic capacitance Cp is a few femtofarads (fF), then capacitor elements 321 and 322 are on the order of tens of femtofarads.

[0148] Figure 10 This is a diagram illustrating an example of the state of pixel 300 when the readout signal level is in the first embodiment of this technology.

[0149] After the initialization of the downstream node 340, the vertical scanning circuit 211 sets the selection transistor 332 to the closed state and sets the selection transistor 331 and the downstream reset transistor 341 to the open state. Thus, the signal level is read out via the downstream circuit 350.

[0150] Here, the kTC noise at the time of exposure of the pixel 300 is considered. At the time of exposure, the kTC noise occurs in each of the sampling of the reset level immediately before the end of exposure and the sampling of the signal level. Assuming that the capacitance value of each of the capacitance elements 321 and 322 is C, the level Vn of the kTC noise at the time of exposure is represented by the following equation.

[0151] Vn = (2 * kT / C) 1 / 2 ... Equation 2

[0152] Further, as shown in Figure 9 and Figure 10 indicated, the kTC noise occurs at this time because the downstream reset transistor 341 is driven at the time of readout. However, the capacitance elements 321 and 322 are disconnected at the time of driving the downstream reset transistor 341, and the parasitic capacitance Cp at this time is small. Thus, the kTC noise at the time of readout can be negligible compared to the kTC noise at the time of exposure. Thus, the kTC noise at the time of exposure and readout is represented by Equation 2.

[0153] According to Equations 1 and 2, the kTC noise in the pixel 300 in which the capacitor is disconnected at the time of readout is smaller than the kTC noise in the comparative example in which the capacitor is not disconnected at the time of readout. Thus, it is possible to improve the image quality of the image data.

[0154] Figure 11 is a flowchart showing an operation example of the solid-state imaging device 200 in the first embodiment of the present technology. This operation is started, for example, when a predetermined application for image data imaging is executed.

[0155] The vertical scanning circuit 211 performs exposure for all pixels (step S901). Then, the vertical scanning circuit 211 selects a row to be read out (step S902). The column signal processing circuit 260 reads out the reset level of the row (step S903), and then reads out the signal level (step S904).

[0156] The solid-state imaging device 200 determines whether the readout of all the rows has been completed (step S905). In a case where the readout of all the rows has not been completed (NO in step S905), the solid-state imaging device 200 repeats step S902 and the subsequent steps. On the other hand, in a case where the readout of all the rows has been completed (YES in step S905), the solid-state imaging device 200 performs a CDS process and the like, and ends the operation for imaging. In a case where a plurality of pieces of image data are continuously imaged, steps S901 to S905 are repeatedly performed in synchronization with a vertical synchronization signal.

[0157] In this way, in the first embodiment of the present technology, when the selection circuit 330 disconnects the capacitive elements 321 and 322 from the downstream node 340, the downstream reset transistor 341 initializes the downstream node 340. Since the capacitive elements 321 and 322 are disconnected, the level of the reset noise caused by driving thereof becomes a level corresponding to a parasitic capacitance smaller than the capacitance thereof. By the reduction of this noise, it is possible to improve the image quality of the image data.

[0158] [First Modification]

[0159] Although in the above-described first embodiment, the upstream circuit 310 reads out the signal in a state connected to the upstream node 320, in this configuration, it is difficult to block the noise from the upstream node 320 at the time of readout. The pixel 300 of the first modification of the first embodiment is different from the pixel of the first embodiment in that a transistor is inserted between the upstream circuit 310 and the upstream node 320.

[0160] Figure 12 is a circuit diagram showing a configuration example of the pixel 300 in the first modification of the first embodiment of the present technology. The pixel 300 of the first modification of the first embodiment is different from the pixel of the first embodiment in that the upstream reset transistor 323 and the upstream selection transistor 324 are further included. Further, the power supply voltage of the upstream circuit 310 and the downstream circuit 350 of the first modification of the first embodiment is set to VDD1.

[0161] The upstream reset transistor 323 initializes the level of the upstream node 320 at the power supply voltage VDD2. The power supply voltage VDD2 is preferably set to a value satisfying the following equation.

[0162] VDD2 = VDD1 - Vgs... Equation 3

[0163] In the above equation, Vgs represents the gate-source voltage of the upstream amplification transistor 315.

[0164] By setting the value to satisfy Formula 3, the potential variation between the upstream node 320 and the downstream node 340 at the time of darkness can be reduced. Thus, photo response non-uniformity (PRNU) can be improved.

[0165] The upstream selection transistor 324 opens and closes the path between the upstream circuit 310 and the upstream node 320 in accordance with the upstream selection signal sel from the vertical scanning circuit 211.

[0166] Figure 13 is a timing chart showing an example of a global shutter operation in the first modification of the first embodiment of the present technology. The timing chart of the first modification of the first embodiment differs from the timing chart of the first embodiment in that the vertical scanning circuit 211 also supplies the upstream reset signal rsta and the upstream selection signal sel. In this chart, rsta_[n] and sel_[n] represent signals with respect to the nth row of pixels.

[0167] The vertical scanning circuit 211 supplies the upstream selection signal sel at a high level to all the pixels from the time T2, which is just before the end of exposure, to the time T5. The upstream reset signal rsta is controlled to be at a low level.

[0168] Figure 14 is a timing chart showing an example of a read operation in the first modification of the first embodiment of the present technology. The upstream selection signal sel is controlled to be at a low level at the time of reading out each row. This control causes the upstream selection transistor 324 to turn into an open state, and the upstream node 320 to be disconnected from the upstream circuit 310. Thus, noise from the upstream node 320 can be blocked at the time of readout.

[0169] Further, during the readout of the nth row from the time T10 to the time T17, the vertical scanning circuit 211 supplies the upstream reset signal rsta at a high level to the nth row.

[0170] Further, at the time of readout, the vertical scanning circuit 211 controls the current source transistor 316 of all the pixels to stop supplying the current idl. The current id2 is supplied similarly to the first embodiment. In this way, compared with the first embodiment, the control of the current idl is simplified.

[0171] In this way, in the first modification of the first embodiment according to the present technology, the upstream selection transistor 324 turns into an open state at the time of readout, and the upstream circuit 310 is disconnected from the upstream node 320, so that noise from the upstream circuit 310 can be blocked.

[0172] [Second Modification]

[0173] Although in the above-described first embodiment, the circuits in the solid-state imaging device 200 are provided on a single semiconductor chip, in this configuration, when the pixels 300 are miniaturized, there is a possibility that the semiconductor chip cannot accommodate the elements. The solid-state imaging device 200 in the second modification example of the first embodiment differs from the solid-state imaging device of the first embodiment in that the circuits in the solid-state imaging device 200 are dispersedly arranged on two semiconductor chips.

[0174] Figure 15 is a diagram illustrating an example of a stacked structure of the solid-state imaging device 200 in the second modification example of the first embodiment of the present technology. The solid-state imaging device 200 in the second modification example of the first embodiment includes a lower-side pixel chip 202 and an upper-side pixel chip 201 stacked on the lower-side pixel chip 202. These two chips are electrically connected by, for example, Cu-Cu bonding. Incidentally, instead of using Cu-Cu bonding, connection can be made via a vertical interconnection via or a bump.

[0175] The upper-side pixel array section 221 is arranged on the upper-side pixel chip 201. The lower-side pixel array section 222 and the column signal processing circuit 260 are arranged on the lower-side pixel chip 202. As for each pixel in the pixel array section 220, a part thereof is arranged in the upper-side pixel array section 221, and the remaining part is arranged in the lower-side pixel array section 222.

[0176] Further, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are also arranged on the lower-side pixel chip 202. These circuits are not shown in this diagram.

[0177] Further, the upper-side pixel chip 201 is manufactured by, for example, a pixel-specific process, and the lower-side pixel chip 202 is manufactured by, for example, a complementary MOS (CMOS) process. Incidentally, the upper-side pixel chip 201 is an example of the first chip recited in the claims, and the lower-side pixel chip 202 is an example of the second chip recited in the claims.

[0178] Figure 16 is a circuit diagram illustrating a configuration example of the pixel 300 in the second modification example of the first embodiment of the present technology. In the pixel 300, the upstream circuit 310 is arranged on the upper-side pixel chip 201, and the other circuits and elements such as the capacitive elements 321 and 322, and the like are arranged on the lower-side pixel chip 202. Incidentally, the current source transistor 316 can be further arranged on the lower-side pixel chip 202. As shown in this diagram, since the elements in the pixel 300 are dispersedly arranged on the upper-side pixel chip 201 and the lower-side pixel chip 202 stacked, the area of the pixel can be reduced, and miniaturization of the pixel can be made easy.

[0179] In this way, since the circuits and elements in the pixel 300 are dispersedly arranged on the two semiconductor chips in the second modification of the first embodiment of the present technology, it is possible to make the miniaturization of the pixel easy.

[0180] [Third Modification]

[0181] In the second modification of the first embodiment described above, a part of the pixel 300 and the peripheral circuit such as the column signal processing circuit 260 and the like are arranged on the lower side pixel chip 202 on the lower side. However, in this configuration, the arrangement area of the circuits and elements on the lower side pixel chip 202 side is larger than that of the upper side pixel chip 201 due to the area occupied by the peripheral circuit, and a useless space not containing circuits or elements can be generated in the upper side pixel chip 201. The solid-state imaging device 200 of the third modification of the first embodiment is different from the solid-state imaging device of the second modification of the first embodiment in that the circuits in the solid-state imaging device 200 are dispersedly arranged on three semiconductor chips.

[0182] Figure 17 is a drawing illustrating an example of the stacked structure of the solid-state imaging device 200 in the third modification of the first embodiment of the present technology. The solid-state imaging device 200 of the third modification of the first embodiment includes an upper side pixel chip 203, a lower side pixel chip 204, and a circuit chip 202. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Incidentally, in addition to the Cu-Cu bonding, connection can be made by a vertical interconnection path or a bump.

[0183] The upper side pixel array section 221 is arranged on the upper side pixel chip 203. The lower side pixel array section 222 is arranged on the lower side pixel chip 204. As for each pixel in the pixel array section 220, a part thereof is arranged in the upper side pixel array section 221, and the remaining part is arranged in the lower side pixel array section 222.

[0184] Further, the column signal processing circuit 260, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are arranged on the circuit chip 202. The circuits other than the column signal processing circuit 260 are not shown in this drawing.

[0185] Incidentally, the upper side pixel chip 203 is an example of the first chip recited in the claims, and the lower side pixel chip 204 is an example of the second chip recited in the claims. The circuit chip 202 is an example of the third chip recited in the claims.

[0186] As illustrated in the drawing, since a three-layer configuration is employed, compared with a two-layer configuration, it is possible to reduce the useless space and further miniaturize the pixel. Further, the lower side pixel chip 204 in the second layer can be manufactured by a dedicated process of a capacitor or a switch.

[0187] In this way, since the circuit in the solid-state imaging device 200 is dispersedly arranged on three semiconductor chips in the third modification of the first embodiment of the present technology, compared with a case where the circuit is dispersedly arranged on two semiconductor chips, the pixel can be further miniaturized.

[0188] <2. Second Embodiment>

[0189] Although in the above-described first embodiment, the reset level is sample-held during the exposure period, in this configuration, it is difficult to set the exposure period to be shorter than the sample-holding period of the reset level. The solid-state imaging device 200 of the second embodiment is different from the solid-state imaging device of the first embodiment in that the exposure period is further shortened by adding a transistor for discharging a charge from a photoelectric conversion element.

[0190] Figure 18 is a circuit diagram illustrating a configuration example of a pixel 300 in the second embodiment of the present technology. The pixel 300 of the second embodiment is different from the pixel of the first embodiment in that a discharge transistor 317 is further provided in the upstream circuit 310.

[0191] The discharge transistor 317 functions as an overflow drain that discharges a charge from the photoelectric conversion element 311 according to a discharge signal ofg from the vertical scanning circuit 211. For example, an nMOS transistor is used as the discharge transistor 317.

[0192] In a configuration where the discharge transistor 317 is not provided as in the first embodiment, when a charge is transferred from the photoelectric conversion element 311 to the FD 314 for all pixels, blooming can occur. Then, at the time of FD reset, the potential of the FD 314 and the upstream node 320 drops. With this potential drop, the current that charges and discharges the capacitive elements 321 and 322 continues, and the IR drop of the power supply or the ground changes from a constant state where there is no blooming.

[0193] On the other hand, when the signal levels of all pixels are sample-held, after the signal charge is transferred, the photoelectric conversion element 311 becomes a state where there is no charge, and thus blooming does not occur, and the IR drop of the power supply or the ground becomes a constant state where there is no blooming. Since the IR drop at the time of sample-holding the reset level and the IR drop at the time of sample-holding the signal level are different, streaking noise occurs.

[0194] In contrast, in the second embodiment in which the drain transistor 317 is provided, the charges of the photoelectric conversion element 311 are drained to the overflow drain side. Therefore, approximately the same IR drop occurs at the time of sampling and holding the reset level and at the time of sampling and holding the signal level, and the band noise can be suppressed.

[0195] Figure 19 is a timing chart showing an example of a global shutter operation in the second embodiment of the present technology. At a time To before an exposure start time, the vertical scanning circuit 211 provides a high-level FD reset signal rst to all the pixels during a pulse period while setting the drain signal ofg of all the pixels to a high level. Therefore, the PD reset and the FD reset are performed on all the pixels. Further, the reset level is sampled and held. Here, ofg_[n] in the drawing indicates a signal with respect to the nth row of pixels among N rows.

[0196] Then, at the exposure start time Tl, the vertical scanning circuit 211 returns the drain signal ofg of all the pixels to a low level. Then, during a period from a time T2 just before the end of exposure to an exposure end time T3, the vertical scanning circuit 211 provides a high-level transfer signal trg to all the pixels. Therefore, the signal level is sampled and held.

[0197] In the configuration in which the drain transistor 317 is not provided as in the first embodiment, both the transfer transistor 312 and the FD reset transistor 313 have to be turned on at the start of exposure, that is, at the time of PD reset. In this control, the FD 314 also has to be reset at the same time as the PD reset. Therefore, it is necessary to perform the FD reset again during the exposure period and to sample and hold the reset level, and it is difficult to set the exposure period to be shorter than the sampling and holding period of the reset level. When the reset level of all the pixels is sampled and held, a certain wait time is required until the voltage or current reaches a stable state, and for example, a sampling and holding period of several microseconds (μβ) to several tens of microseconds (μβ) is required.

[0198] On the other hand, in the second embodiment in which the drain transistor 317 is provided, the PD reset and the FD reset can be performed separately. Therefore, as shown in the drawing, the reset level can be sampled and held by performing the FD reset before the release of the PD reset (the start of exposure). Therefore, the exposure period can be set to be shorter than the sampling and holding period of the reset level.

[0199] Incidentally, the first to third modified examples of the first embodiment can also be applied to the second embodiment.

[0200] In this way, since the drain transistor 317 for draining the electric charge from the photoelectric conversion element 311 is provided according to the second embodiment of the present technology, the sample-and-hold reset level can be held by performing the FD reset before the start of exposure. Therefore, the exposure period during exposure can be set to be shorter than the sample-and-hold period of the reset level.

[0201] <3. Third Embodiment>

[0202] Although the FD 314 is initialized with the power supply voltage VDD in the above-described first embodiment, in this configuration, there is a possibility that photoresponsivity nonuniformity (PRNU) is degraded due to a difference or a parasitic capacitance of the capacitive elements 321 and 322. The solid-state imaging device 200 of the third embodiment differs from the solid-state imaging device of the first embodiment in that the PRNU is improved by lowering the power supply voltage of the FD reset transistor 313 at the time of readout.

[0203] Figure 20 is a circuit diagram showing a configuration example of the pixel 300 in the third embodiment of the present technology. The pixel 300 of the third embodiment differs from the pixel of the first embodiment in that the source of the FD reset transistor 313 is disconnected from the power supply voltage VDD of the pixel 300.

[0204] The drain of the FD reset transistor 313 of the third embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit 212. Incidentally, the timing control circuit 212 is an example of the control circuit recited in the claims.

[0205] Here, the degradation of the PRNU in the pixel 300 of the first embodiment will be considered with reference to Figure 21 and Figure 22 In the first embodiment, as shown in Figure 21 , the potential of the FD 314 is lowered due to the reset feedthrough of the FD reset transistor 313 at the time T0 just before the start of exposure. This amount of variation is Vft.

[0206] In the first embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 is varied from VDD to VDD-Vft at the time T0. Further, the potential of the upstream node 320 at the time of exposure is VDD-Vft-Vsig.

[0207] Further, in the first embodiment, as shown in Figure 22As shown, at the time of readout, the FD reset transistor 313 turns on, and the FD 314 is fixed to the power supply voltage VDD. The amount of fluctuation Vft of the FD 314 causes the potential of the upstream node 320 and the downstream node 340 to be offset by approximately Vft at the time of readout. However, the amount of voltage to be offset differs among the respective pixels due to the difference in the capacitance values of the capacitance elements 321 and 322 or due to parasitic capacitance, which causes degradation of the PRNU.

[0208] In the case where the downstream node 340 is offset by Vft, the amount of offset of the upstream node 320 is represented by, for example, the following equation.

[0209] {(Cs+δCs) / (Cs+δCs+Cp)}*Vft... Equation 4

[0210] In the above equation, Cs is the capacitance value of the capacitance element 322 on the signal level side, and δCs is the difference in Cs. Cp is the capacitance value of the parasitic capacitance of the downstream node 340.

[0211] Equation 4 can be approximated by the following equation.

[0212] {1-(δCs / Cs)*(Cp / Cs)}*Vft... Equation 5

[0213] According to Equation 5, the amount of fluctuation in the downstream node 340 can be represented by the following equation.

[0214] {(δCs / Cs)*(Cp / Cs)}*Vft... Equation 6

[0215] Assuming that (δCs / Cs) is 10 -2 , (Cp / Cs) is 10 -1 , and Vft is 400 millivolts (mV), then according to Equation 6, the PRNU is 400 μVrms, which is a relatively large value.

[0216] In particular, if it is desired to reduce the kTC noise when a capacitance that undergoes input scaling is sampled and held, it is necessary to increase the charge-voltage conversion efficiency of the FD 314. Although it is necessary to reduce the capacitance of the FD 314 in order to increase the charge-voltage conversion efficiency, as the capacitance of the FD 314 decreases, the amount of fluctuation Vft increases and can become several hundred millivolts (mV). In this case, according to Equation 6, the influence of the PRNU can be at a non-negligible level.

[0217] Figure 23 is a timing chart that shows an example of voltage control in the third embodiment of the present technology.

[0218] The timing control circuit 212 controls the reset power supply voltage VRST to a value different from that during the exposure period during the period in which the readout is performed row by row after the time T9.

[0219] For example, the timing control circuit 212 sets the reset power supply voltage VRST to the same value as the power supply voltage VDD during the exposure period. On the other hand, the timing control circuit 212 lowers the reset power supply voltage VRST to VDD-Vft during the readout period. That is, the timing control circuit 212 lowers the reset power supply voltage VRST by an amount substantially identical to the amount of variation Vft caused by the reset feedthrough during the readout period. This control enables the reset level of the FD 314 to be equal at the time of exposure and at the time of readout.

[0220] As shown in the figure, the control of the reset power supply voltage VRST enables the amount of variation in voltage between the FD 314 and the upstream node 320 to be reduced. Thus, degradation of the PRNU due to differences in the capacitive elements 321 and 322 or due to parasitic capacitance can be suppressed.

[0221] Incidentally, the first to third modifications of the first embodiment and the second embodiment can also be applied to the third embodiment.

[0222] In this way, according to the third embodiment of the present technology, since the timing control circuit 212 lowers the reset power supply voltage VRST by the amount of variation Vft caused by the reset feedthrough at the time of readout, the reset level can be made equal at the time of exposure and at the time of readout. Thus, degradation of the photo-sensitivity unevenness (PRNU) can be suppressed.

[0223] <4. Fourth Embodiment>

[0224] In the first embodiment described above, the signal level is read out after the reset level for each frame, but in this configuration, there is a possibility that the photo-sensitivity unevenness (PRNU) degrades due to differences in the capacitive elements 321 and 322 or due to parasitic capacitance. The solid-state imaging device 200 of the fourth embodiment differs from the solid-state imaging device of the first embodiment in that the level held in the capacitive element 321 and the level held in the capacitive element 322 are switched for each frame, thereby improving the PRNU.

[0225] The solid-state imaging device 200 of the fourth embodiment continuously images a plurality of frames in synchronization with a vertical synchronization signal. The odd-numbered frames are referred to as “odd-numbered frames”, and the even-numbered frames are referred to as “even-numbered frames”. Incidentally, the odd-numbered frames and the even-numbered frames are examples of the pair of frames recited in the claims.

[0226] Figure 24is a timing chart showing an example of a global shutter operation of an odd frame in the fourth embodiment. During exposure of the odd frame, the upstream circuit 310 in the solid-state imaging device 200 sets the selection signal Φs to a high level after the selection signal Φr, thereby causing the capacitor element 321 to hold a reset level and then causing the capacitor element 322 to hold a signal level.

[0227] Figure 25 is a timing chart showing an example of a readout operation of an odd frame in the fourth embodiment of the present technology. During readout of the odd frame, the downstream circuit 350 in the solid-state imaging device 200 sets the selection signal Φs to a high level after the selection signal Φr to read out a signal level after a reset level.

[0228] Figure 26 is a timing chart showing an example of a global shutter operation of an even frame in the fourth embodiment. During exposure of the even frame, the upstream circuit 310 in the solid-state imaging device 200 sets the selection signal Φr to a high level after the selection signal Φs, thereby causing the capacitor element 322 to hold a reset level and then causing the capacitor element 321 to hold a signal level.

[0229] Figure 27 is a timing chart showing an example of a readout operation of an even frame in the fourth embodiment of the present technology. During readout of the even frame, the downstream circuit 350 in the solid-state imaging device 200 sets the selection signal Φr to a high level after the selection signal Φs to read out a signal level after a reset level.

[0230] As shown in Figure 24 and Figure 26 , the levels to be held in the capacitor elements 321 and 322 are reversed in the even frame and the odd frame. Therefore, the polarity of the PRNU is also reversed in the even frame and the odd frame. The downstream column signal processing circuit 260 averages the odd frame and the even frame by adding them. Thus, PRNUs having opposite polarities cancel each other out.

[0231] This control is an effective control that is implemented by imaging a moving image and adding frames. Furthermore, no elements need to be added to the pixel 300, and the control can be realized only by a change in the driving method.

[0232] Incidentally, the first to third modifications of the first embodiment and the second and third embodiments can also be applied to the fourth embodiment.

[0233] In this way, in the fourth embodiment of the present technology, since the level held in the capacitance element 321 and the level held in the capacitance element 322 are reversed in the odd-numbered frame and the even-numbered frame, the polarity of the PRNU can be reversed in the odd-numbered frame and the even-numbered frame. Since the column signal processing circuit 260 adds the odd-numbered frame and the even-numbered frame, deterioration of the PRNU can be suppressed.

[0234] <5. Fifth Embodiment>

[0235] In the above-described first embodiment, the column signal processing circuit 260 calculates the difference between the reset level and the signal level for each column. However, in this configuration, when light having a very high illuminance is incident on the pixel, there is a possibility that a black point phenomenon in which the luminance decreases and becomes black due to overflow of charge from the photoelectric conversion element 311 occurs. The solid-state imaging device 200 of the fifth embodiment is different from the solid-state imaging device of the first embodiment in that it determines whether or not the black point phenomenon has occurred for each pixel.

[0236] Figure 28 is a circuit diagram showing a configuration example of the column signal processing circuit 260 in the fifth embodiment of the present technology. In the column signal processing circuit 260 of the fifth embodiment, a plurality of ADCs 270 and a digital signal processing section 290 are provided. Further, a plurality of CDS processing sections 291 and a plurality of selectors 292 are provided in the digital signal processing section 290. The ADC 270, the CDS processing section 291, and the selector 292 are provided for each column.

[0237] Further, the ADC 270 includes a comparator 280 and a counter 271. The comparator 280 compares the level of the vertical signal line 309 with the ramp signal Rmp from the DAC 213 and outputs a comparison result VCO. The comparison result VCO is supplied to the counter 271 and the timing control circuit 212. The comparator 280 includes a selector 281, capacitance elements 282 and 283, auto-zero switches 284 and 286, and a comparison section 285.

[0238] The selector 281 connects either the vertical signal line 309 of the corresponding column or a node having a predetermined reference voltage VREF to the non-inverting input terminal (+) of the comparison section 285 via the capacitance element 282 in accordance with an input-side selection signal selin. The input-side selection signal selin is supplied from the timing control circuit 212. Incidentally, the selector 281 is an example of the input-side selector recited in the claims.

[0239] The comparison section 285 compares the levels of the non-inverting input terminal (+) and the inverting input terminal (-) respectively, and outputs the comparison result VCO to the counter 271. The ramp signal Rmp is input to the inverting input terminal (-) via the capacitive element 283.

[0240] The auto-zero switch 284 shorts the non-inverting input terminal (+) of the comparison result VCO to the output terminal in accordance with the auto-zero signal Az from the timing control circuit 212. The auto-zero switch 286 shorts the inverting input terminal (-) of the comparison result VCO to the output terminal in accordance with the auto-zero signal Az.

[0241] The counter 271 counts the count value during the period until the comparison result VCO is inverted, and outputs a digital signal CNT_out representing the count value to the CDS processing section 291.

[0242] The CDS processing section 291 performs CDS processing on the digital signal CNT_out. The CDS processing section 291 calculates the difference between the digital signal CNT_out corresponding to the reset level and the digital signal CNT_out corresponding to the signal level, and outputs the difference as CDS_out to the selector 292.

[0243] The selector 292 outputs the digital signal CDS_out after CDS processing or the full code digital signal FULL as the pixel data of the corresponding column in accordance with the output side selection signal selout from the timing control circuit 212. Incidentally, the selector 292 is an example of the output side selector recited in the claims.

[0244] Figure 29 is a timing chart showing an example of the global shutter operation in the fifth embodiment of the present technology. The control method of the transistor at the time of the global shutter operation of the fifth embodiment is similar to the control method of the first embodiment.

[0245] Here, it is assumed that light having a very high illuminance is incident on the pixel 300. In this case, the charge of the photoelectric conversion element 311 becomes full, the charge overflows from the photoelectric conversion element 311 to the FD 314, and the potential of the FD 314 after the FD reset decreases. The dotted line in the figure indicates the potential variation of the FD 314 when weak sunlight that would cause a relatively small amount of overflow charge is incident. The dashed line in the figure indicates the potential variation of the FD 314 when strong sunlight that would cause a relatively large amount of overflow charge is incident.

[0246] When weak sunlight is incident, the reset level decreases at the timing T3 at which the FD reset is completed, but the level does not completely decrease at this time.

[0247] On the other hand, when strong sunlight is incident, the reset level is completely lowered at time T3. In this case, the signal level becomes the same as the reset level, and the potential difference between them is "0", so that the digital signal after the CDS processing becomes black as in the case of the dark state. In this way, a phenomenon in which the pixel becomes black even if light having a very high illuminance such as sunlight is incident is called a black point phenomenon or a flare.

[0248] Further, when the level of the FD 314 of the pixel in which the black point phenomenon has occurred is too low, it is difficult to secure the operating point of the upstream circuit 310, and the current idl of the current source transistor 316 varies. Since the current source transistor 316 of each pixel is connected to a common power supply or ground, when the current in a certain pixel varies, the variation in the IR drop of that pixel affects the sampling level of other pixels. The pixel in which the black point phenomenon has occurred becomes a source of disturbance, and the pixel in which the sampling level has varied due to that pixel becomes a victim. Thus, banding noise occurs.

[0249] Incidentally, in the case where the drain transistor 317 is provided as in the second embodiment, in the pixel having a black point (flare), the overflow charge is discarded to the drain transistor 317 side, so that it is less likely that the black point phenomenon occurs. However, even if the drain transistor 317 is provided, a part of the charge can flow to the FD 314, and there is a possibility that the black point phenomenon is not completely solved. Further, since the drain transistor 317 is added, there is a disadvantage that the ratio of the effective area / charge amount per pixel decreases. Therefore, it is desired to suppress the black point phenomenon without using the drain transistor 317.

[0250] As a method of suppressing the black point phenomenon without using the drain transistor 317, two methods can be conceived. The first method is to adjust the clip level of the FD 314. The second method is to determine whether the black point phenomenon occurs at the time of readout and replace the output with a full code when the black point phenomenon occurs.

[0251] In the first method, the high level of the FD reset signal rst in the figure (in other words, the gate of the FD reset transistor 313) corresponds to the power supply voltage VDD, and its low level corresponds to the clip level of the FD 314. In the first embodiment, the difference (that is, the amplitude) between the high level and the low level is set to a value corresponding to the dynamic range. In contrast to this, in the fifth embodiment, it is adjusted to a value obtained by further adding a margin to this value. Here, the value corresponding to the dynamic range corresponds to the difference between the power supply voltage VDD and the potential of the FD 314 when the digital signal becomes a full code.

[0252] By lowering the gate voltage of the FD reset transistor 313 in the off state (low level of the FD reset signal rst), it is possible to prevent the FD 314 from excessively lowering due to blooming and damaging the operating point of the upstream amplification transistor 315.

[0253] Incidentally, the dynamic range changes depending on the analog gain of the ADC. When the analog gain is low, a large dynamic range is required, and when the analog gain is high, a small dynamic range is sufficient. Therefore, the gate voltage of the FD reset transistor 313 in the off state can also be changed depending on the analog gain.

[0254] Figure 30 is a timing chart showing an example of a read operation in the fifth embodiment of the present technology. When the selection signal Φr becomes high at a time T11 immediately after a read start time T10, the potential of the vertical signal line 309 changes in a pixel in which sunlight is incident. The dotted line in the drawing indicates a change in the potential of the vertical signal line 309 when weak sunlight is incident. The dashed line in the drawing indicates a change in the potential of the vertical signal line 309 when strong sunlight is incident.

[0255] During the auto-zero period from the time T10 to the time T12, the timing control circuit 212 supplies the input-side selection signal selin with, for example, "0", and connects the comparison section 285 to the vertical signal line 309. During this auto-zero period, the timing control circuit 212 performs auto-zero by the auto-zero signal Az.

[0256] For the second method, during the determination period from the time T12 to the time T13, the timing control circuit 212 supplies the input-side selection signal selin with, for example, "1". According to the input-side selection signal selin, the comparison section 285 is disconnected from the vertical signal line 309 and connected to a node having the reference voltage VREF. The reference voltage VREF is set to a desired value of the level of the vertical signal line 309 when no blooming occurs. For example, when the gate-source voltage of the downstream amplification transistor 351 is Vgs2, Vrst corresponds to Vreg-Vgs2. Further, the DAC 213 lowers the level of the ramp signal Rmp from Vrmp_az to Vrmp_sun during the determination period.

[0257] Further, during the determination period, the reset level Vrst of the vertical signal line 309 is substantially the same as the reference voltage VREF in the case where no blooming occurs, and the potential of the inverting input terminal (+) of the comparison section 285 does not change much from that at the time of auto-zero. On the other hand, since the non-inverting input terminal (-) has been lowered from Vrmp_az to Vrmp_sun, and therefore, the comparison result VCO becomes high.

[0258] On the other hand, in the case where a flare occurs, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and the comparison result VCO becomes a low level when the following formula is satisfied.

[0259] Vrst-VREF>Vrmp_az-Vrmp_sun... Formula 7

[0260] That is, the timing control circuit 212 can determine whether a flare occurs or not depending on whether the comparison result VCO becomes a low level during the determination period.

[0261] Incidentally, in order not to cause erroneous determination due to a difference in threshold voltage of the downstream amplification transistor 351, an IR drop difference in Vregs in the plane, and the like, it is necessary to ensure a larger margin for the sun determination (right side of Formula 7) to some extent.

[0262] After the timing T13 after the determination period, the timing control circuit 212 connects the comparison section 285 to the vertical signal line 309. Further, when the P-phase stable period from the timing T13 to the timing T14 elapses, the P-phase is read out during the period from the timing T14 to the timing T15. When the D-phase stable period from the timing T15 to the timing T19 elapses, the D-phase is read out during the period from the timing T19 to the timing T20.

[0263] In the case where it is determined that no flare occurs during the determination period, the timing control circuit 212 controls the selector 292 by the output side selection signal selout, and directly outputs the CDS-processed digital signal CDS_out as it is.

[0264] On the other hand, in the case where it is determined that a flare occurs during the determination period, the timing control circuit 212 controls the selector 292 by the output side selection signal selout, and outputs the full code FULL instead of the CDS-processed digital signal CDS_out. Thus, the black spot phenomenon can be suppressed.

[0265] Incidentally, the first to third modified examples of the first embodiment and the second to fourth embodiments can also be applied to the fifth embodiment.

[0266] In this way, according to the fifth embodiment of the present technology, since the timing control circuit 212 determines whether the black spot phenomenon has occurred based on the comparison result VCO, and outputs the full code when the black spot phenomenon occurs, the black spot phenomenon can be suppressed.

[0267] <6. Sixth Embodiment>

[0268] In the above-described first embodiment, the vertical scanning circuit 211 performs control for exposing all rows (all pixels) at the same time (i.e., a global shutter operation). However, in a case where simultaneity of exposure is not required and low noise is required when testing is performed, when analysis is performed, and the like, it is desirable to perform a rolling shutter operation. The solid-state imaging device 200 of the sixth embodiment differs from the solid-state imaging device of the first embodiment in that a rolling shutter operation is performed when testing is performed and the like.

[0269] Figure 31 is a timing chart illustrating an example of a rolling shutter operation in the sixth embodiment of the present technology. The vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure. This chart illustrates exposure control of the nth row.

[0270] During a period from time T0 to time T2, the vertical scanning circuit 211 supplies the nth row with the downstream selection signal selb, the selection signal Φr, and the selection signal Φs at a high level. Further, at the exposure start time T0, the vertical scanning circuit 211 supplies the nth row with the FD reset signal rst and the downstream reset signal rstb at a high level during a pulse period. At the exposure end time T1, the vertical scanning circuit 211 supplies the nth row with the transfer signal trg. With the rolling shutter operation in this chart, the solid-state imaging device 200 is able to generate image data with low noise.

[0271] Incidentally, during ordinary imaging, the solid-state imaging device 200 of the sixth embodiment performs a global shutter operation similarly to the first embodiment.

[0272] Further, the first to third modified examples of the first embodiment and the second to fifth embodiments can also be applied to the sixth embodiment.

[0273] In this way, according to the sixth embodiment of the present technology, since the vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure (i.e., a rolling shutter operation), it is possible to generate image data with low noise.

[0274] <7. Seventh Embodiment>

[0275] In the above-described first embodiment, the source of the upstream source follower (the upstream amplification transistor 315 and the current source transistor 316) is connected to the power supply voltage VDD, and readout is performed row by row in a state where the source follower is turned on. However, in this driving method, there is a possibility that circuit noise of the upstream source follower propagates to the downstream when readout is performed row by row, thereby increasing random noise. The solid-state imaging device 200 of the seventh embodiment differs from the solid-state imaging device of the first embodiment in that noise is reduced by turning off the upstream source follower when readout is performed.

[0276] Figure 32 This is a block diagram illustrating a configuration example of the solid-state imaging element 200 according to the seventh embodiment of the present technology. The solid-state imaging element 200 of the seventh embodiment differs from that of the solid-state imaging element of the first embodiment in that it further includes an adjuster 420 and a switching unit 440. Furthermore, a plurality of effective pixels 301 and a predetermined number of pseudo pixels 430 are arranged in the pixel array unit 220 of the seventh embodiment. The pseudo pixels 430 are arranged around the area where the effective pixels 301 are arranged.

[0277] Furthermore, a power supply voltage VDD is provided to each pseudo-pixel 430, and both the power supply voltage VDD and the source voltage Vs are provided to each effective pixel 301. The signal lines used to provide the power supply voltage VDD to the effective pixels 301 are omitted in this figure. Additionally, the power supply voltage VDD is provided by pads 410 external to the solid-state imaging element 200.

[0278] The regulator 420 generates a constant generation voltage V based on the input potential Vi from the pseudo-pixel 430. gen The generated voltage is then supplied to the switching unit 440. The switching unit 440 selects either the power supply voltage VDD from the pad 410 or the generated voltage V from the regulator 420. gen The selected voltage is provided as the source voltage Vs to each column of the effective pixels 301.

[0279] Figure 33 This is a circuit diagram illustrating an example of the configuration of the pseudo-pixel 430, the regulator 420, and the switching unit 440 in the seventh embodiment of this technology. Figure 33 In the diagram, 'a' represents the circuit diagram of pseudo-pixel 430 and regulator 420, and... Figure 33 In the diagram, 'b' represents the circuit diagram of the switching unit 440.

[0280] like Figure 33 As shown in Figure a, pseudo-pixel 430 includes a reset transistor 431, an FD 432, an amplifying transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifying transistor 433 amplifies the voltage level of the FD 432 and provides the amplified voltage as the input voltage Vi to the regulator 420.

[0281] Furthermore, the sources of reset transistor 431 and amplification transistor 433 are connected to the power supply voltage VDD. Current source transistor 434 is connected to the drain of amplification transistor 433. Current source transistor 434 provides current id1 under the control of vertical scanning circuit 211.

[0282] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor element 423. The low-pass filter 421 allows components of the input voltage Vi signal in the low-frequency band below a predetermined frequency to pass as the output voltage Vj.

[0283] The output voltage Vj is input to the non-inverting input terminal (+) of buffer amplifier 422. The inverting input terminal (-) of buffer amplifier 422 is connected to its output terminal. Capacitor element 423 maintains the voltage at the output terminal of buffer amplifier 422 at Vj. gen The V gen It is provided to the switching unit 440.

[0284] like Figure 33 As shown in Figure a, the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442. The switching circuits 442 are configured for each column of effective pixels 301.

[0285] Inverter 441 inverts the switching signal SW from timing control circuit 212. Inverter 441 provides the inverted signal to each of switching circuits 442.

[0286] Switching circuit 442 selects the power supply voltage VDD and the generated voltage V. gen One of them, and provides the selected voltage as the source voltage Vs to the corresponding column in the pixel array section 220. The switching circuit 442 includes switches 443 and 444. Switch 443 opens and closes the path between the node with the power supply voltage VDD and the corresponding column according to the switching signal SW. Switch 444 opens and closes the path with the generated voltage VDD according to the inverted signal of the switching signal SW. gen The path between the node and the corresponding column.

[0287] Figure 34 This is a timing diagram illustrating an operational example of the pseudo-pixel 430 and regulator 420 in the seventh embodiment of this technology. At a time T10, just before a line is about to be read out, the vertical scan circuit 211 provides a high-level (here, power supply voltage VDD) reset signal RST to each pseudo-pixel 430. The potential Vfd of FD 432 in the pseudo-pixel 430 is initialized to the power supply voltage VDD. Then, when the reset signal RST goes low, the reset feedthrough causes a change in VDD-Vft.

[0288] Furthermore, the input voltage Vi decreases to VDD-Vgs-Vsig after reset. After passing through the low-pass filter 421, Vj and V gen It becomes a roughly constant voltage.

[0289] After time T20, just before the next line is read, similar control is performed for each line, and a constant generation voltage V is provided. gen.

[0290] Figure 35 is a circuit diagram showing a configuration example of the effective pixel 301 in the seventh embodiment of the present technology. The circuit configuration of the effective pixel 301 is similar to that of the pixel 300 of the first embodiment except that the source voltage Vs from the switching section 440 is supplied to the source of the upstream amplification transistor 315.

[0291] Figure 36 is a timing chart showing an example of the global shutter operation in the seventh embodiment of the present technology. In the seventh embodiment, when exposure is performed simultaneously in all pixels, the switching section 440 selects the power supply voltage VDD and supplies the same as the source voltage Vs. Further, the voltage of the upstream node decreases from VDD-Vgs-Vth to VDD-Vgs-Vsig at time T4. Here, Vth is the threshold voltage of the transfer transistor 312.

[0292] Figure 37 is a timing chart showing an example of the readout operation in the seventh embodiment of the present technology. In the seventh embodiment, at the time of readout, the switching section 440 selects the generation voltage V gen and supplies the same as the source voltage Vs. The generation voltage V gen is adjusted to VDD-Vgs-Vft. Further, in the seventh embodiment, the vertical scanning circuit 211 controls the current source transistor 316 of all rows (all pixels) to stop supplying the current id1.

[0293] Figure 38 is a graph for explaining the effect in the seventh embodiment of the present technology. In the first embodiment, when readout is performed row by row, the source follower (the upstream amplification transistor 315 and the current source transistor 316) of the pixel 300 to be read out is turned on. However, in this driving method, there is a possibility that the circuit noise of the upstream source follower propagates to the downstream (the capacitive element, the downstream source follower, or the ADC) to increase the readout noise.

[0294] For example, in the first embodiment, as shown in the graph, the kTC noise generated in the pixel during the global shutter operation is 450 μVrms. Further, the noise generated in the source follower of the upstream (the upstream amplification transistor 315 and the current source transistor 316) at the time of readout for each row is 380 μVrms. The noise generated thereafter by the source follower of the downstream is 160 μVrms. Thus, the total noise is 610 μVrms. In this way, in the first embodiment, the proportion of the noise of the source follower of the upstream in the total value of the noise becomes relatively large.

[0295] To reduce the noise of the upstream source follower, as described above, in the seventh embodiment, a voltage (Vs) that can be adjusted is supplied to the source of the upstream source follower. During a global shutter (exposure) operation, the switching section 440 selects the power supply voltage VDD and supplies the power supply voltage as the source voltage Vs. Then, after the end of the exposure, the switching section 440 switches the source voltage Vs to VDD-Vgs-Vft. Further, during the global shutter (exposure) operation, the timing control circuit 212 turns on the upstream current source transistor 316, and turns off the current source transistor 316 after the end of the exposure.

[0296] As Figure 36 and Figure 37 indicated above, the above control can make the potential of the upstream node equal when the global shutter operation is performed and when readout is performed for each row, and can improve the PRNU. Further, since the upstream source follower is in an off state when readout is performed for each row, as Figure 38 indicated above, the circuit noise of the source follower does not occur and becomes zero (μVrms). Incidentally, the upstream amplification transistor 315 in the upstream source follower is in an on state.

[0297] In this way, since the upstream source follower is in an off state at the time of readout according to the seventh embodiment of the present technology, the noise generated in the source follower can be reduced.

[0298] <8. Application example of mobile body>

[0299] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, and a robot.

[0300] Figure 39 is a block diagram that shows an illustrative configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0301] The vehicle control system 12000 includes a plurality of electronic control units that are connected to each other via a communication network 12001. In Figure 39 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F: interface) 12053 are shown.

[0302] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as a drive force generation device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating the braking force of the vehicle.

[0303] The body system control unit 12020 controls the operation of various devices mounted in the vehicle body in accordance with various programs. For example, the body system control unit 12020 functions as a control device for various devices such as a keyless entry system, an intelligent key system, a power window device, or various lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal lamp, a fog lamp, and the like. In this case, the body system control unit 12020 can be inputted with radio waves emitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives these inputted radio waves or signals, and controls the door lock device, the power window device, the lamps, and the like of the vehicle.

[0304] The outside information detecting unit 12030 detects information related to the outside of the vehicle on which the vehicle control system 12000 is mounted. For example, the outside information detecting unit 12030 is connected with an imaging section 12031. The outside information detecting unit 12030 causes the imaging section 12031 to take an image of the outside of the vehicle, and receives the taken image. Based on the received image, the outside information detecting unit 12030 can perform a detection process of an object such as a person, a vehicle, an obstacle, a sign, a character on a road surface, or a detection process of a distance thereto.

[0305] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can output the electrical signal as an image, or can output the electrical signal as ranging-related information. In addition, the light received by the imaging section 12031 can be visible light or can be non-visible light such as infrared rays.

[0306] The inside information detecting unit 12040 detects information related to the inside of the vehicle. For example, the inside information detecting unit 12040 is connected with a driver state detecting section 12041 that detects the state of the driver. For example, the driver state detecting section 12041 includes a camera that images the driver. Based on the detection information inputted from the driver state detecting section 12041, the inside information detecting unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, and can determine whether the driver is dozing off.

[0307] Based on information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate control target values of the driving force generation device, the steering mechanism, or the braking device, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation of the vehicle, follow-up running based on an inter-vehicle distance, vehicle constant speed running, warning of a vehicle collision, warning of vehicle lane departure, and the like.

[0308] In addition, based on information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at realizing autonomous driving of the vehicle without the operation of the driver, or the like, by controlling the driving force generation device, the steering mechanism, the braking device, and the like.

[0309] Further, based on information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control aimed at preventing glare, such as switching a headlamp from high beam to low beam, or the like.

[0310] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or aurally notifying information to the occupant of the vehicle or the outside of the vehicle. In Figure 39 In an example, as the output device, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are shown. The display section 12062 can include at least one of an on-board display and a head-up display, for example.

[0311] Figure 40 FIG. 12 is a view showing an example of a setting position of the imaging section 12031.

[0312] In Figure 40 The imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, 12105.

[0313] The imaging sections 12101, 12102, 12103, 12104, and 12105 are arranged, for example, at positions of a front nose, side mirrors, a rear bumper, and a trunk door of the vehicle 12100, and at a position of an upper portion of a windshield inside the cabin. The imaging section 12101 provided at the front nose and the imaging section 12105 at the upper portion of the windshield inside the cabin mainly acquire images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging section 12104 provided at the rear bumper or the trunk door mainly acquires images of the rear of the vehicle 12100. The imaging section 12105 provided at the upper portion of the windshield inside the cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal lamp, a traffic sign, a lane, and the like.

[0314] Incidentally, Figure 40 Examples of imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 represents an imaging range of the imaging section 12101 provided at the front nose. The imaging ranges 12112 and 12113 represent imaging ranges of the imaging sections 12102 and 12103 provided at the side mirrors, respectively. The imaging range 12114 represents an imaging range of the imaging section 12104 provided at the rear bumper or the trunk door. For example, an overhead view image of the vehicle 12100 viewed from above is obtained by superimposing image data taken by the imaging sections 12101 to 12104.

[0315] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging devices, or can be an imaging device having phase difference detection pixels.

[0316] For example, based on distance information obtained from the imaging sections 12101 to 12104, the microcomputer 12051 can calculate distances to each of the three-dimensional objects within the imaging ranges 12111 to 12114 and changes in the distances over time (relative speeds with respect to the vehicle 12100), and thereby extract, as a preceding vehicle, a three-dimensional object that is closest among the three-dimensional objects present on a travel path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). Further, the microcomputer 12051 can set a vehicle-to-vehicle distance that should be ensured in advance with respect to the front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, it is possible to perform coordinated control aimed at realizing automatic driving in which the vehicle can autonomously travel without the operation of the driver or the like.

[0317] For example, based on distance information obtained from the imaging sections 12101 to 12104, the microcomputer 12051 can classify stereoscopic object data related to a stereoscopic object into stereoscopic object data of a two-wheeled vehicle, a normal automobile, a large vehicle, a pedestrian, a utility pole, or another stereoscopic object, extract the classified stereoscopic object data, and use the extracted result to automatically avoid an obstacle. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into an obstacle that can be visually recognized by a driver of the vehicle 12100 and an obstacle that is difficult to be visually recognized by the driver of the vehicle 12100. Then, the microcomputer 12051 judges a degree of danger indicating a risk of collision with each obstacle. In a case where the risk of collision is equal to or greater than a set value and thus a collision is likely to occur, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the drive system control unit 12010. The microcomputer 12051 can thereby provide assisted driving for avoiding a collision.

[0318] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in an image captured by the imaging sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a process of extracting feature points from an image captured by the imaging sections 12101 to 12104 as infrared cameras and a process of determining whether an object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging sections 12101 to 12104 and thereby recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 to display a square outline for emphasis in superimposition on the recognized pedestrian. The sound / image output section 12052 can also control the display section 12062 to display an icon or the like representing the pedestrian at a desired position.

[0319] Examples in which the vehicle control system according to the technology of the present disclosure can be applied have been described above. The technology according to the present disclosure can be applied to the imaging section 12031 in the above-described configuration. Specifically, for example, Figure 1 The imaging device 100 in the above-described configuration can be applied to the imaging section 12031. When the technology according to the present disclosure is applied to the imaging section 12031, kTC noise can be reduced, and a captured image that is easier to view can be obtained, so that fatigue of a driver can be reduced.

[0320] Incidentally, the above embodiments illustrate examples for embodying the present technology, and the matters in the embodiments correspond to the matters specified in the claims. Similarly, the matters specified in the claims correspond to the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be implemented by making various modifications to the embodiments without departing from its spirit.

[0321] Incidentally, the effects described in this specification are illustrative and not limiting, and additional effects may exist.

[0322] Incidentally, this technology may also have the following configuration.

[0323] (1) Solid-state camera element, including:

[0324] First capacitor element and second capacitor element;

[0325] The upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to the exposure amount, and causes the first capacitor element and the second capacitor element to maintain the reset level and the signal level respectively;

[0326] The selection circuit sequentially executes control to connect one of the first capacitor element and the second capacitor element to a predetermined downstream node, control to disconnect both the first capacitor element and the second capacitor element from the downstream node, and control to connect the other of the first capacitor element and the second capacitor element to the downstream node.

[0327] A downstream reset transistor initializes the level of the downstream node when both the first and second capacitor elements are disconnected from the downstream node; and

[0328] The downstream circuit reads the reset level and the signal level sequentially from the first capacitor element and the second capacitor element via the downstream node, and outputs the read reset level and the signal level.

[0329] (2) The solid-state camera element according to (1) above further includes:

[0330] An upstream selection transistor that turns on and off the path between the upstream circuit and a predetermined upstream node; and

[0331] An upstream reset transistor initializes the voltage level of the upstream node.

[0332] wherein the first and second capacitive elements each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit.

[0333] (3) The solid-state imaging device according to the above (2), wherein

[0334] the upstream selection transistor transitions to a closed state during a period in which the upstream circuit causes the first and second capacitive elements each to hold the reset level and the signal level, and

[0335] the upstream reset transistor initializes the level of the upstream node during a period in which the downstream circuit sequentially reads out the reset level and the signal level from the first and second capacitive elements.

[0336] (4) The solid-state imaging device according to any one of the above (1) to (3), wherein

[0337] the upstream circuit includes:

[0338] a photoelectric conversion element;

[0339] an upstream transfer transistor that transfers charge from the photoelectric conversion element to a floating diffusion layer;

[0340] a first reset transistor that initializes the floating diffusion layer; and

[0341] an upstream amplification transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node, and

[0342] the first and second capacitive elements each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit.

[0343] (5) The solid-state imaging device according to the above (4), further comprising:

[0344] a switching section that adjusts a source voltage to be supplied to a source of the upstream amplification transistor,

[0345] wherein the upstream circuit further includes a current source transistor connected to a drain of the upstream amplification transistor, and

[0346] the current source transistor transitions from an on state to an off state after an end of an exposure period.

[0347] (6) The solid-state imaging device according to the above (5), wherein

[0348] The switching section supplies a predetermined power supply voltage as the source voltage during an exposure period, and

[0349] The switching section supplies a generated voltage different from the power supply voltage as the source voltage after an end of the exposure period.

[0350] (7) The solid-state imaging device according to (6) above, wherein

[0351] A difference between the power supply voltage and the generated voltage is substantially in accordance with a sum of a variation amount caused by a reset feedthrough of the first reset transistor and a gate-source voltage of the upstream amplification transistor.

[0352] (8) The solid-state imaging device according to any one of (4) to (7) above, wherein

[0353] The upstream transfer transistor transfers the charge to the floating diffusion layer at a predetermined exposure start timing, and the first reset transistor initializes the photoelectric conversion element together with the floating diffusion layer, and

[0354] The upstream transfer transistor transfers the charge to the floating diffusion layer at a predetermined exposure end timing.

[0355] (9) The solid-state imaging device according to any one of (4) to (7) above, wherein

[0356] The upstream circuit further includes a drain transistor for draining the charge from the photoelectric conversion element.

[0357] (10) The solid-state imaging device according to (9) above, wherein

[0358] The first reset transistor initializes the floating diffusion layer before a predetermined exposure start timing, and the drain transistor drains the charge from the photoelectric conversion element, and

[0359] The upstream transfer transistor transfers the charge to the floating diffusion layer at a predetermined exposure end timing.

[0360] (11) The solid-state imaging device according to any one of (4) to (10) above, further comprising:

[0361] a control circuit that controls a reset power supply voltage of the upstream circuit,

[0362] wherein the first reset transistor initializes a voltage of the floating diffusion layer to the reset power supply voltage, and

[0363] The control circuit sets the reset power supply voltage to a voltage different from that during the exposure period, during a readout period for reading out the reset level and the signal level.

[0364] (12) The solid-state imaging device according to (11) above, wherein

[0365] The difference between the reset power supply voltage during the readout period and the reset power supply voltage during the exposure period is substantially the same as an amount of variation caused by reset feedthrough of the first reset transistor.

[0366] (13) The solid-state imaging device according to any one of (4) to (12) above, wherein

[0367] A first reset signal is input to a gate of the first reset transistor, and

[0368] An amplitude of the first reset signal is a value obtained by adding a predetermined margin to a value corresponding to a dynamic range.

[0369] (14) The solid-state imaging device according to any one of (1) to (13) above, further comprising:

[0370] a digital signal processing section that adds a pair of consecutive frames in succession,

[0371] wherein the upstream circuit causes one of the first and second capacitive elements to hold the reset level during an exposure period of one of the pair of frames, and then causes the other of the first and second capacitive elements to hold the signal level, and

[0372] the upstream circuit causes the other of the first and second capacitive elements to hold the reset level during an exposure period of the other of the pair of frames, and then causes the one of the first and second capacitive elements to hold the signal level.

[0373] (15) The solid-state imaging device according to any one of (1) to (14) above, further comprising:

[0374] an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals.

[0375] (16) The solid-state imaging device according to (15) above, wherein

[0376] the analog-digital converter includes:

[0377] a comparator that compares a level of a vertical signal line for transmitting the reset level and the signal level with a predetermined ramp signal and outputs a comparison result; and

[0378] a counter that counts a count value during a period until the comparison result is inverted and outputs the digital signal representing the count value.

[0379] (17) The solid-state imaging device according to the above (16), wherein

[0380] the comparator includes:

[0381] a comparison section that compares levels of the pair of input terminals and outputs a comparison result;

[0382] and

[0383] an input-side selector that selects either of the vertical signal line and a node having a predetermined reference voltage and connects the selected vertical signal line or node to one of the pair of input terminals, and

[0384] the ramp signal is input to one of the pair of input terminals.

[0385] (18) The solid-state imaging device according to the above (17), further comprising:

[0386] a control section that determines whether or not an illuminance is higher than a predetermined value based on the comparison result and outputs a determination result;

[0387] a correlated double sampling (CDS) processing section that performs a CDS process on the digital signal; and

[0388] an output-side selector that outputs the digital signal on which the CDS process is performed or a digital signal having a predetermined value based on the determination result.

[0389] (19) The solid-state imaging device according to any one of the above (1) to (18), further comprising:

[0390] a vertical scanning circuit that performs control for controlling a plurality of lines each of which has a predetermined number of pixels arranged therein to start exposure at the same time,

[0391] wherein the first capacitance element, the second capacitance element, the upstream circuit, the selection circuit, the downstream reset transistor, and the downstream circuit are arranged in each of the pixels.

[0392] (20) The solid-state imaging device according to the above (19), wherein

[0393] The vertical scanning circuit also performs control for controlling the plurality of rows to start exposure in turn.

[0394] (21) The solid-state imaging device according to any one of (1) to (20) above, wherein

[0395] The upstream circuit is provided on a first chip, and

[0396] The first capacitance element, the second capacitance element, the selection circuit, the downstream reset transistor, and the downstream circuit are provided on a second chip.

[0397] (22) The solid-state imaging device according to (21) above, further comprising:

[0398] an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals,

[0399] wherein the analog-digital converter is provided on the second chip.

[0400] (23) The solid-state imaging device according to (21) above, further comprising:

[0401] an analog-digital converter that sequentially converts the output reset level and the output signal level into digital signals,

[0402] wherein the analog-digital converter is provided on a third chip.

[0403] (24) A solid-state imaging device comprising:

[0404] a photoelectric conversion section that converts incident light into electric charges;

[0405] a first amplification transistor that converts the electric charges into a voltage;

[0406] a signal line that outputs a pixel signal;

[0407] a first capacitance element whose first end is connected to a first node that is a destination of output of the first amplification transistor;

[0408] a second capacitance element that is provided in parallel with the first capacitance element between the first amplification transistor and the signal line, a first end of the second capacitance element being connected to the first node;

[0409] a first selection transistor that is connected to the first capacitance element at a second end of the first capacitance element;

[0410] a second selection transistor that is connected to the second capacitance element at a second end of the second capacitance element;

[0411] a reset transistor whose source or drain is connected to a second node at which the first selection transistor and the second selection transistor are connected; and

[0412] a second amplification transistor whose gate is connected to the second node, and which outputs the pixel signal.

[0413] [LIST OF REFERENCE NUMERALS]

[0414] 100: imaging device

[0415] 110: imaging lens

[0416] 120: recording section

[0417] 130: imaging control section

[0418] 200: solid-state imaging element

[0419] 201: upper pixel chip

[0420] 202: lower pixel chip

[0421] 203: circuit chip

[0422] 211: vertical scanning circuit

[0423] 212: timing control circuit

[0424] 213: DAC

[0425] 220: pixel array section

[0426] 221: upper pixel array section

[0427] 222: lower pixel array section

[0428] 250: load MOS circuit block

[0429] 251: load MOS transistor

[0430] 260: column signal processing circuit

[0431] 261, 270: ADC

[0432] 262, 290: digital signal processing section

[0433] 271: counter

[0434] 280: comparator

[0435] 281, 292: selector

[0436] 282, 283, 321, 322: capacitive element

[0437] 284, 286: auto-zeroing switch

[0438] 285: comparison section

[0439] 291: CDS processing section

[0440] 300: pixel

[0441] 301: effective pixel

[0442] 310: upstream circuit

[0443] 311: photoelectric conversion element

[0444] 312: transfer transistor

[0445] 313: FD reset transistor

[0446] 314: FD

[0447] 315: upstream amplification transistor

[0448] 316: current source transistor

[0449] 317: drain transistor

[0450] 323: upstream reset transistor

[0451] 324: upstream selection transistor

[0452] 330: selection circuit

[0453] 331, 332: selection transistor

[0454] 341: downstream reset transistor

[0455] 350: downstream circuit

[0456] 351: downstream amplification transistor

[0457] 352: downstream selection transistor

[0458] 420: regulator

[0459] 421: low-pass filter

[0460] 422: buffer amplifier

[0461] 423: capacitive element

[0462] 430: dummy pixel

[0463] 431: reset transistor

[0464] 432: FD

[0465] 433: Amplifying Transistor

[0466] 434: Current source transistor

[0467] 440: Switching Unit

[0468] 441: Inverter

[0469] 442: Switching Circuit

[0470] 443, 444: Switches

[0471] 12031: Camera Department

Claims

1. Solid-state camera element, including: First capacitor element and second capacitor element; The upstream circuit generates a predetermined reset level and a signal level corresponding to the exposure amount sequentially through exposure control, wherein the first capacitor element holds the reset level and the second capacitor element holds the signal level; The selection circuit sequentially executes control to connect one of the first capacitor element and the second capacitor element to a predetermined downstream node, control to disconnect both the first capacitor element and the second capacitor element from the downstream node, and control to connect the other of the first capacitor element and the second capacitor element to the downstream node. A downstream reset transistor initializes the level of the downstream node when both the first capacitor element and the second capacitor element are disconnected from the downstream node. The downstream circuit sequentially reads the reset level and the signal level from the first capacitor element and the second capacitor element via the downstream node, and outputs the read reset level and the signal level; and An upstream selection transistor is used to turn the path between the upstream circuit and a predetermined upstream node on and off. The first capacitor element and the second capacitor element each have a first end that is connected to the upstream node and a second end that is connected to the selection circuit.

2. The solid-state camera element according to claim 1, further comprising: An upstream reset transistor is used to initialize the level of the upstream node.

3. The solid-state imaging element according to claim 2, wherein, During the period when the upstream circuit causes the first capacitor element and the second capacitor element to maintain the reset level and the signal level respectively, the upstream selection transistor switches to a closed state, and During the period when the downstream circuit sequentially reads the reset level and the signal level from the first capacitor element and the second capacitor element, the upstream reset transistor initializes the level of the upstream node.

4. The solid-state imaging element according to claim 1, wherein, The upstream circuit includes: Photoelectric conversion element; An upstream transport transistor transfers charge from the photoelectric conversion element to the floating diffusion layer; A first reset transistor initializes the floating diffusion layer; and An upstream amplifying transistor amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node. The first capacitor element and the second capacitor element each have a first end that is commonly connected to the upstream node and a second end that is connected to the selection circuit.

5. The solid-state imaging element according to claim 4, further comprising: The switching unit adjusts the source voltage to be supplied to the source of the upstream amplifying transistor. The upstream circuit further includes a current source transistor connected to the drain of the upstream amplifying transistor, and After the exposure period ends, the current source transistor changes from the on state to the off state.

6. The solid-state imaging element according to claim 5, wherein, During the exposure period, the switching unit provides a predetermined power supply voltage as the source voltage, and After the exposure period ends, the switching unit provides a generated voltage different from the power supply voltage as the source voltage.

7. The solid-state imaging element according to claim 6, wherein, The difference between the power supply voltage and the generated voltage is substantially consistent with the sum of the following two: one is the variation caused by the reset feedthrough of the first reset transistor, and the other is the gate-source voltage of the upstream amplifying transistor.

8. The solid-state imaging element according to claim 4, wherein, At the predetermined exposure start time, the upstream transport transistor transfers the charge to the floating diffusion layer, and the first reset transistor initializes the photoelectric conversion element together with the floating diffusion layer. At the predetermined end of the exposure, the upstream transport transistor transfers the charge to the floating diffusion layer.

9. The solid-state imaging element according to claim 4, wherein, The upstream circuit also includes an exhaust transistor for discharging the charge from the photoelectric conversion element.

10. The solid-state imaging element according to claim 9, wherein, Before the predetermined exposure start time, the first reset transistor initializes the floating diffusion layer, and the discharge transistor discharges the charge from the photoelectric conversion element. At the predetermined end of the exposure, the upstream transport transistor transfers the charge to the floating diffusion layer.

11. The solid-state imaging element according to claim 4, further comprising: The control circuit controls the reset power supply voltage of the upstream circuit. Wherein, the first reset transistor initializes the voltage of the floating diffusion layer to the reset power supply voltage, and During the readout period for reading out the reset level and the signal level, the control circuit sets the reset power supply voltage to a voltage different from the voltage during exposure.

12. The solid-state imaging element according to claim 11, wherein, The difference between the reset power supply voltage during the readout period and the reset power supply voltage during the exposure period is substantially consistent with the variation caused by the reset feedthrough of the first reset transistor.

13. The solid-state imaging element according to claim 4, wherein, A first reset signal is input to the gate of the first reset transistor, and The amplitude of the first reset signal is a value obtained by adding a predetermined margin to the value corresponding to the dynamic range.

14. The solid-state imaging element according to claim 1, further comprising: The digital signal processing unit adds consecutive pairs of frames together. Specifically, the upstream circuit causes one of the first and second capacitor elements to maintain the reset level during the exposure period of one of the pair of frames, and then causes the other of the first and second capacitor elements to maintain the signal level. The upstream circuit causes the other of the first and second capacitor elements to maintain the reset level during the exposure period of the other of the pair of frames, and then causes the first of the first and second capacitor elements to maintain the signal level.

15. The solid-state imaging element according to claim 1, further comprising: An analog-to-digital converter that sequentially converts the output reset level and the output signal level into digital signals.

16. The solid-state imaging element according to claim 15, wherein, The analog-to-digital converter includes: A comparator that compares the level of the vertical signal line used to transmit the reset level and the signal level with a predetermined ramp signal and outputs the comparison result; and A counter that counts the count value during the period until the comparison result is reversed, and outputs the digital signal representing the count value.

17. The solid-state imaging element according to claim 16, wherein, The comparator includes: The comparator compares the levels of a pair of input terminals and outputs the comparison result; and An input-side selector selects either the vertical signal line or the node having a predetermined reference voltage, and connects the selected vertical signal line or the node to one of the pair of input terminals. The ramp signal is input to one of the pair of input terminals.

18. The solid-state imaging element according to claim 17, further comprising: The control unit determines whether the illuminance is higher than a predetermined value based on the comparison result, and outputs the determination result. The correlated double sampling processing unit performs correlated double sampling processing on the digital signal; and An output-side selector, based on the determination result, outputs the digital signal that has undergone the correlated double sampling process or a digital signal with a predetermined value.

19. The solid-state imaging element according to claim 1, further comprising: A vertical scanning circuit, for multiple rows in which a predetermined number of pixels are arranged in each row, performs control to cause the multiple rows to begin exposure simultaneously. Each pixel is provided with a first capacitor element, a second capacitor element, an upstream circuit, a selection circuit, a downstream reset transistor, and a downstream circuit.

20. The solid-state imaging element according to claim 19, wherein, The vertical scanning circuit also performs control to control the multiple rows to start exposure sequentially.

21. The solid-state imaging element according to any one of claims 1 to 20, wherein, The upstream circuit is located on the first chip, and The first capacitor element, the second capacitor element, the selection circuit, the downstream reset transistor, and the downstream circuit are disposed on the second chip.

22. The solid-state imaging element according to claim 21, further comprising: An analog-to-digital converter (ADC) sequentially converts the output reset level and the output signal level into digital signals. The analog-to-digital converter is located on the second chip.

23. The solid-state imaging element according to claim 21, further comprising: An analog-to-digital converter (ADC) sequentially converts the output reset level and the output signal level into digital signals. The analog-to-digital converter is located on the third chip.

24. Solid-state camera elements, including: The photoelectric conversion unit converts incident light into electrical charge; A first amplifying transistor converts the charge into voltage; Signal lines, which output pixel signals; A first capacitor element, the first end of the first capacitor element is connected to a first node, the first node is the output destination of the first amplifying transistor; A second capacitor element is disposed in parallel with the first capacitor element between the first amplifying transistor and the signal line, and a first end of the second capacitor element is connected to the first node; A first selection transistor is connected to the first capacitor element at a second terminal of the first capacitor element; A second selection transistor is connected to the second capacitor element at the second end of the second capacitor element; A reset transistor, the source or drain of which is connected to a second node, wherein the first selection transistor and the second selection transistor are connected at the second node; as well as A second amplifying transistor, the gate of which is connected to the second node, and the second amplifying transistor outputs the pixel signal.

Images