Overload detection method, device, medium and equipment for delay line in semiconductor equipment

Abstract

The present disclosure relates to the field of semiconductors and integrated circuits, and is a method, device, medium and device for detecting overload of a delay line in a semiconductor device. The method for detecting overload of a delay line in a semiconductor device comprises: applying a voltage signal to the delay line, the voltage signal comprising a DC signal to be measured and an AC disturbance signal, the AC disturbance signal having a target frequency and a target amplitude; obtaining a response signal of a transistor in the delay line to the AC disturbance signal; and detecting whether the delay line is overloaded based on the phase difference between the response signal and the AC disturbance signal. In the delay line overload detection method disclosed herein, the AC disturbance signal has a target frequency, which can characterize the interface characteristics between the gate oxide layer and the substrate of the transistor, so that whether the delay line is overloaded can be detected by the phase difference between the response signal of the transistor to the AC disturbance signal and the AC disturbance signal. The detection method disclosed herein can improve the detection efficiency of delay line overload detection.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors and integrated circuits, and in particular to a method, apparatus, medium, and device for detecting an overload of a delay line in a semiconductor device. Background Art

[0002] Delay lines, a key module in the DRAM delay-locked loop (DRAM-DLL), play a crucial role in ensuring high-speed DRAM read and write performance. During product aging and voltage loading, the delay line layer can overload and cause failures, such as ELFR / HTOL failures, impacting product time to market.

[0003] Currently, there are two main methods for determining whether a delay line layer is experiencing overstress: 1. Dot-probe testing; 2. Form factor fitting. Dot-probe testing requires physically damaging the chip surface down to the delay line layer, while form factor fitting can be incomplete due to inaccurate acceleration factors. Both methods have limitations.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a method, device, medium and equipment for overload detection of a delay line in a semiconductor device.

[0006] According to one aspect of the present disclosure, a method for detecting an overload of a delay line in a semiconductor device is provided, wherein the delay line includes a transistor, and the method includes: continuously applying a voltage signal to the delay line, the voltage signal including a DC signal to be measured and an AC disturbance signal, the AC disturbance signal having a target frequency and a target amplitude; obtaining a response signal of the transistor in the delay line to the AC disturbance signal after a preset time length; and detecting whether the delay line is overloaded based on a phase difference between the response signal and the AC disturbance signal.

[0007] In an exemplary embodiment of the present disclosure, obtaining the response signal of the transistor in the delay line to the AC disturbance signal after a preset time length includes: obtaining the response signal of the interface between the substrate and the gate oxide layer of the transistor in the delay line to the AC disturbance signal after a preset time length.

[0008] In an exemplary embodiment of the present disclosure, the response signal is an AC signal, and the frequency of the response signal is the same as the frequency of the AC disturbance signal.

[0009] In an exemplary embodiment of the present disclosure, detecting whether the delay line is overloaded based on the phase difference between the response signal and the AC disturbance signal includes: determining the phase difference between the current response signal and the AC disturbance signal; if the phase difference is greater than or equal to a preset phase difference threshold, determining that the delay line is overloaded.

[0010] In an exemplary embodiment of the present disclosure, before determining the phase difference between the current response signal and the AC disturbance signal, the method further includes: continuously applying a first voltage signal to the delay line, the first voltage signal including a first DC signal and a target AC signal, the target AC signal having a target amplitude and a target frequency; obtaining a first delay time of the transistor in the delay line after the first voltage signal acts for a preset time; comparing the first delay time with a preset delay threshold; if the first delay time is less than the preset delay threshold, increasing the signal amplitude on the basis of the first DC signal to obtain a second DC signal, applying the second voltage signal to the delay line, and the second The voltage signal includes a second DC signal and the target AC signal; obtaining the second delay time of the transistor in the delay line after the second voltage signal acts for a preset time length; comparing the second delay time with the delay threshold; if the second delay time is less than the preset delay threshold, repeating the steps of determining the second voltage signal and applying the second voltage signal and comparing the second delay time until it is determined that the delay time of the transistor under a certain voltage signal reaches the delay threshold, obtaining the current response signal of the transistor to the target AC signal, and determining the phase difference between the current response signal and the target AC signal as the phase difference threshold.

[0011] In an exemplary embodiment of the present disclosure, the target frequency of the AC disturbance signal matches the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor in the delay line.

[0012] In an exemplary embodiment of the present disclosure, a ratio of the target frequency of the AC disturbance signal to the characteristic frequency is greater than or equal to 0.8 and less than or equal to 1.5.

[0013] In an exemplary embodiment of the present disclosure, before continuously applying a voltage signal to the delay line, the method further includes: obtaining an AC impedance spectrum of a transistor in the delay line; determining a characteristic frequency of an interface between a gate oxide layer and a substrate of the transistor based on the AC impedance spectrum; and determining the target frequency of the AC disturbance signal based on the characteristic frequency.

[0014] In an exemplary embodiment of the present disclosure, determining the target amplitude of the AC disturbance signal includes: continuously applying an initial voltage signal to the delay line, the initial voltage signal including a DC signal to be measured and an initial AC disturbance signal, and the initial AC disturbance signal having an initial amplitude; verifying whether the initial AC disturbance signal is valid based on a response result of an interface between the gate oxide layer and the substrate of the transistor to the initial voltage signal after a preset time period; if the initial AC disturbance signal is valid, increasing the amplitude of the AC disturbance signal on the basis of the initial amplitude, and repeating the steps of applying the initial voltage signal and verifying whether the initial AC disturbance signal is valid, until it is determined that the AC disturbance signal is invalid, and determining the signal amplitude of the previous valid AC disturbance signal of the invalid AC disturbance signal as the target amplitude of the AC disturbance signal.

[0015] In an exemplary embodiment of the present disclosure, the verification of whether the initial AC disturbance signal is valid based on the response result of the interface between the gate oxide layer of the transistor and the substrate to the initial voltage signal after a preset time period includes: detecting a current response signal of the interface between the gate oxide layer of the transistor and the substrate corresponding to the initial AC disturbance signal after a preset time period; determining the initial AC impedance of the interface between the gate oxide layer of the transistor and the substrate based on the initial AC disturbance signal and the initial current response signal; and detecting whether the real part and the imaginary part of the initial AC impedance conform to the Kramers-Kronig relationship to verify whether the initial AC disturbance signal is valid.

[0016] In an exemplary embodiment of the present disclosure, the DC signal to be measured is smaller than an intrinsic breakdown voltage of a transistor in the delay line.

[0017] In an exemplary embodiment of the present disclosure, the AC disturbance signal is a periodic clock signal or a periodic sinusoidal signal.

[0018] According to the second aspect of the present disclosure, an overload detection device for a delay line in a semiconductor device is also provided, including: a detection signal application module for continuously applying a voltage signal to the delay line, the voltage signal including a DC signal to be measured and an AC disturbance signal, the AC disturbance signal having a target frequency and a target amplitude; an acquisition module for acquiring a response signal of a transistor in the delay line to the AC disturbance signal after a preset time length; and a detection module for detecting whether the delay line is overloaded based on a phase difference between the response signal and the AC disturbance signal.

[0019] According to a third aspect of the present disclosure, a computer-readable storage medium is further provided, on which a computer program is stored. When the program is executed by a processor, the method for detecting an overload of a delay line in a semiconductor device according to any embodiment of the present disclosure is implemented.

[0020] According to the fourth aspect of the present disclosure, a detection device is also provided, including: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the overload detection method of the delay line in the semiconductor device described in any embodiment of the present disclosure.

[0021] The delay line overload detection method disclosed in the present invention superimposes an AC disturbance signal on the DC signal to be measured. The AC disturbance signal has a target frequency and can characterize the interface characteristics of the gate oxide layer and the substrate of the transistor. Therefore, the phase difference between the response signal of the transistor to the AC disturbance signal and the AC disturbance signal can reflect the delay characteristics of the transistor to the DC signal to be measured, that is, detect whether NBTI occurs in the transistor, thereby reflecting whether the delay line is overloaded. The AC disturbance signal superimposed in the present invention has a target amplitude, which does not affect the electrical stress characteristics of the DC signal to be measured for the transistor. The detection method disclosed in the present invention can quickly determine whether the existing acceleration conditions cause the delay line layer to be overloaded, thereby improving the detection efficiency of the delay line overload detection.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0024] Figure 1 is a flow chart of a method for detecting an overload of a delay line in a semiconductor device according to the present disclosure;

[0025] Figure 2 Schematic diagram of the structure of a transistor according to one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 Equivalent circuit diagram of

[0027] Figure 4 Schematic diagram of a transistor's response signal to an AC signal when a delay line is overloaded according to an embodiment of the present disclosure;

[0028] Figure 5 1 is a structural block diagram of an overload detection device for a delay line in a semiconductor device according to an embodiment of the present disclosure;

[0029] Figure 6 It is a structural schematic diagram of a detection device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0031] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0032] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0033] Figure 1 The flowchart of a method for detecting an overload of a delay line in a semiconductor device according to the present disclosure is provided. The semiconductor device may be, for example, a memory, including but not limited to DRAM, SRAM, etc. The detection method may be used, for example, in a product aging test of a DRAM to detect whether an applied voltage signal causes an overload of the DRAM's delay line. The method may be executed by a detection device, which may be, for example, a computer or server running specific software. Figure 1 As shown, the method may include the following steps:

[0034] S110, continuously applying a voltage signal to the delay line, where the voltage signal includes a DC signal to be measured and an AC disturbance signal, where the AC disturbance signal has a target frequency and a target amplitude;

[0035] S120, obtaining a response signal of the transistor in the delay line to the AC disturbance signal after a preset time period;

[0036] S130 : Detect whether the delay line is overloaded based on the phase difference between the response signal and the AC disturbance signal.

[0037] The delay line overload detection method disclosed in the present invention superimposes an AC disturbance signal on the DC signal to be measured. The AC disturbance signal has a target frequency and can characterize the interface characteristics of the gate oxide layer and the substrate of the transistor. Therefore, the phase difference between the response signal of the transistor to the AC disturbance signal and the AC disturbance signal can reflect the delay characteristics of the transistor to the DC signal to be measured, that is, it can be detected whether the DC signal to be measured causes NBTI of the transistor, thereby reflecting whether the delay line is overloaded. The AC disturbance signal superimposed in the present invention has a target amplitude, which does not affect the electrical stress characteristics of the DC signal to be measured for the transistor. The detection method disclosed in the present invention can quickly determine whether the existing acceleration conditions cause the delay line layer to be overloaded, thereby improving the detection efficiency of the delay line overload detection.

[0038] The above steps of this exemplary embodiment are described in more detail below.

[0039] In step S110 , a voltage signal is continuously applied to the delay line, where the voltage signal includes a DC signal to be measured and an AC disturbance signal, and the AC disturbance signal has a target frequency and a target amplitude.

[0040] The delay line is typically composed of multiple inverters connected in series. The inverters can be composed of transistors with opposite polarities, such as PMOS and NMOS transistors. The voltage signal applied to the delay line is ultimately applied to the transistors.

[0041] The voltage signal includes a DC signal to be measured and an AC perturbation signal. This means that the AC perturbation signal is superimposed on the DC signal to be measured applied to the delay line. This means that by superimposing the AC perturbation signal on the DC signal to be measured, the interface characteristics between the gate oxide layer and the substrate of the transistor are characterized by the superimposed AC perturbation signal. Furthermore, after applying the voltage signal, the duration of the applied voltage signal can be recorded to detect the transistor's response signal to the AC perturbation signal after a certain period of time in a subsequent step. The duration of the applied voltage signal can be found in the description of subsequent embodiments and will not be detailed here.

[0042] Figure 2 FIG. 1 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure, as shown in FIG. Figure 2 As shown, the transistor includes a stacked substrate 210, a gate oxide layer 220, and a gate metal layer 230. The gate metal layer 230 applies a gate control signal, and the substrate 210 is grounded. Figure 3 for Figure 2The equivalent circuit diagram of Figure 3 It can be seen that the transistor can be equivalent to three parallel branches connected in series. Specifically, the equivalent circuit includes a first RC parallel circuit, a second RC parallel circuit and a third RC parallel circuit connected in series in sequence. The first RC parallel circuit is an interface equivalent circuit between the gate oxide layer 220 and the gate metal layer 230, which includes a first equivalent resistor R in parallel. OB and the first equivalent capacitance C OB The second RC parallel circuit is the equivalent circuit of the gate oxide layer 220, which includes a second equivalent resistor Roxide and a second equivalent capacitor Coxide in parallel. The third RC parallel circuit is the interface equivalent circuit between the gate oxide layer 220 and the substrate 210, which includes a third equivalent resistor Rmo and a third equivalent capacitor Cmo in parallel.

[0043] It is known that if the applied DC signal to be measured causes the delay line to overload, it will cause the transistors in the delay line to experience NBTI (Negative Bias Temperature Instability), resulting in traps at the interface between the gate oxide layer and the substrate of the transistors in the delay line, causing interface defects. Such interface defects will cause the signal transmission rate (driving slew rate) of the transistors to slow down.

[0044] The present disclosure superimposes an AC perturbation signal on the DC signal to be measured, and the AC perturbation signal has a target frequency, so that the AC perturbation signal can characterize the interface information between the gate oxide layer and the substrate of the transistor. Moreover, because the superimposed AC perturbation signal has a target amplitude, it does not affect the electrical stress characteristics of the AC perturbation signal. Therefore, it is possible to reflect whether the DC signal to be measured has caused NBTI of the transistor, that is, whether the DC signal to be measured has caused overload of the delay line, based on the phase difference between the response signal of the transistor to the AC perturbation signal detected in step S130 and the AC perturbation signal.

[0045] It can be understood that the signal amplitude of the DC signal to be tested applied in the present disclosure is smaller than the intrinsic breakdown voltage of the transistor to be tested, so as to avoid causing hard breakdown of the transistor to be tested.

[0046] The AC disturbance signal is an AC signal with a fixed period, and may be, for example, a periodic clock signal or a periodic sinusoidal signal. For example, the AC disturbance signal that meets the requirements may be obtained by adjusting the frequency and amplitude of the clock signal.

[0047] Combine Figure 2 and Figure 3It can be seen that the interface between the gate oxide layer and the gate metal layer of the transistor, the gate oxide layer, and the interface between the gate oxide layer and the substrate have different response results to AC signals of different frequencies. Therefore, in order to enable the AC disturbance signal to characterize the interface characteristics of the gate oxide layer and the substrate of the transistor, the present disclosure needs to pre-process the AC disturbance signal to be superimposed according to the interface parameters of the gate oxide layer and the substrate of the transistor. Specifically, the target frequency and target amplitude of the AC disturbance signal are determined through pre-processing.

[0048] In an exemplary embodiment, before step S110, the detection method may further include the following steps:

[0049] S101, obtaining an AC impedance spectrum of a transistor in a delay line;

[0050] S102, determining a characteristic frequency of an interface between a gate oxide layer of the transistor and a substrate based on an AC impedance spectrum;

[0051] S103: Determine a target frequency of the AC disturbance signal based on the characteristic frequency.

[0052] Wherein, the AC impedance spectrum of the transistor is used to determine the characteristic frequency of the AC disturbance signal to be superimposed in a subsequent step. The AC impedance spectrum can be determined, for example, by a Bode plot or a Nyquist plot of the transistor. After obtaining the AC impedance spectrum of the transistor, the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor can be determined, and then the target frequency of the AC disturbance signal to be superimposed can be determined by the characteristic frequency of the interface between the gate oxide layer and the substrate.

[0053] In an exemplary embodiment, the target frequency of the AC perturbation signal matches the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor in the delay line. The target frequency and the characteristic frequency are matched, for example, by the target frequency and the characteristic frequency being the same, or by the difference between the target frequency and the characteristic frequency being within a set range, or by the ratio between the target frequency and the characteristic frequency being within a set range. For example, the target frequency and the characteristic frequency are matched by the ratio between the target frequency and the characteristic frequency being greater than or equal to 0.8 and less than or equal to 1.5, for example, the ratio can be 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, etc.

[0054] In an exemplary embodiment, multiple attempts may be made based on the characteristic frequencies to select a frequency with the best disturbance effect as the target frequency of the AC disturbance signal to be superimposed when performing delay line overload detection.

[0055] The present disclosure sets the target frequency of the AC disturbance signal to match the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor, so that the target frequency can produce a disturbance effect on the interface between the gate oxide layer and the substrate, and thus the phase difference between the AC disturbance signal and the response signal can characterize the interface information between the gate oxide layer and the substrate of the transistor.

[0056] In an exemplary embodiment, before step S110, the detection method may further include the following steps:

[0057] S104: Determine a target amplitude of the AC disturbance signal.

[0058] It should be understood that the AC disturbance signal superimposed in the present disclosure cannot change the electrical stress characteristics of the DC signal under test on the transistor. This requires that the signal amplitude of the AC disturbance signal meet certain requirements. In an exemplary embodiment, the AC disturbance signal can be verified for effectiveness to determine a target amplitude for the AC disturbance signal. The AC disturbance signal with the target amplitude not only does not change the electrical stress characteristics of the DC signal under test, but also improves the signal-to-noise ratio of the transistor's response signal to the AC disturbance signal, thereby reducing noise interference.

[0059] In an exemplary embodiment, the validity of the superimposed AC disturbance signal is verified, specifically, whether the AC disturbance signal satisfies the causality, stability and linearity conditions. When the AC disturbance signal satisfies the causality, stability and linearity conditions, it indicates that the superimposed AC disturbance signal is a valid signal, which does not affect the electrical stress characteristics of the DC signal to be measured.

[0060] The so-called causality requires that the response signal only depends on the input signal at this moment and before this moment.

[0061] Stability refers to the ability of a system to return to its initial state after a certain period of time after the AC disturbance signal is removed. Generally, the greater the system impedance, the better its stability. The gate oxide material of the transistor under test is typically SiO2, which has excellent stability. Accordingly, the amplitude of the superimposed AC disturbance signal can be relatively large.

[0062] The so-called linear condition means that the response signal and the AC disturbance signal have the same angular frequency.

[0063] The following further describes the process of verifying the validity of the AC disturbance signal to determine the target amplitude of the AC disturbance signal.

[0064] In an exemplary embodiment, an initial AC disturbance signal can be determined first, and the signal amplitude of the AC disturbance signal can be gradually increased through multiple attempts until an AC disturbance signal with the largest amplitude that meets the effectiveness requirements is found. The amplitude corresponding to this AC disturbance signal is the target amplitude of the AC disturbance signal superimposed during the final delay line overload detection. The process of determining the target amplitude of the AC disturbance signal can include the following steps:

[0065] S1041. Continuously applying an initial voltage signal to the delay line, where the initial voltage signal includes a DC signal to be measured and an initial AC disturbance signal, and the initial AC disturbance signal has an initial amplitude;

[0066] S1042, verifying whether the initial AC disturbance signal is effective based on a response result of an interface between the gate oxide layer of the transistor and the substrate to the initial voltage signal after a preset time period;

[0067] S1043. If the initial AC disturbance signal is valid, the amplitude of the AC disturbance signal is increased based on the initial amplitude, and the steps of applying the initial voltage signal and verifying whether the initial AC disturbance signal is valid are repeated until it is determined that the AC disturbance signal is invalid, and the signal amplitude of the previous valid AC disturbance signal before the invalid AC disturbance signal is determined as the target amplitude of the AC disturbance signal.

[0068] Because the SiO2 gate oxide layer has a high impedance and good stability, the initial amplitude of the initial AC perturbation signal can be set to a large value. For example, referring to the nanoscale thin film Cr2O3, the amplitude of the initial AC perturbation signal can be 50mV. The effectiveness of the initial AC perturbation signal is then tested by detecting the response of the gate oxide layer to the initial AC perturbation signal after a preset duration. In other words, it is determined whether the initial AC perturbation signal meets the causality, stability, and linearity conditions.

[0069] It's worth noting that the specific duration of the preset time depends on the actual reliability test requirements. For example, the DRAM ppm reliability assessment test, also known as the ELFR test, has a duration of 48 hours. This means that within 48 hours of the aging voltage application, the delay line should not be overloaded (i.e., wear out) but should instead experience an infant fail. Accordingly, the preset duration is 48 hours. It should be understood that the preset duration must match the reliability test requirements.

[0070] If the initial AC disturbance signal is determined to be valid, the initial amplitude of the initial AC disturbance signal can be used as the target amplitude of the AC disturbance signal superimposed when the delay line overload detection is finally performed. Otherwise, if the initial AC disturbance signal is determined to be invalid, the amplitude of the AC disturbance signal can be increased based on the initial amplitude, and the AC disturbance signal with the increased amplitude can be superimposed on the DC signal to be measured and applied to the delay line. The validity of the AC disturbance signal with the increased amplitude can be verified based on the response of the transistors in the delay line to the AC disturbance signal with the increased amplitude. Through multiple attempts in this way, a valid AC disturbance signal with the maximum signal amplitude can be finally determined. This maximum amplitude can be determined as the target amplitude of the AC disturbance signal superimposed when the delay line overload detection is performed. It should be understood that after each adjustment of the amplitude of the AC disturbance signal, validity verification needs to be performed until the valid maximum amplitude is found. The present disclosure determines the maximum amplitude of the AC disturbance signal that can be superimposed through effectiveness verification, and performs delay line overload detection by superimposing the AC disturbance signal with the maximum amplitude, which can fully improve the signal-to-noise ratio of the transistor's response signal to the AC disturbance signal, that is, fully reduce the interference of the noise signal, and help to distinguish the effective response signal. Then, based on the phase difference between the response signal and the AC disturbance signal, it is possible to detect whether the delay line is overloaded, thereby improving the accuracy of the detection result.

[0071] In an exemplary embodiment, the validity of the AC disturbance signal may be detected specifically by the following method:

[0072] Detecting a current response signal of the interface between the gate oxide layer and the substrate of the transistor corresponding to the current AC disturbance signal after a preset time period;

[0073] Determining a current AC impedance at an interface between a gate oxide layer and a substrate of the transistor based on a current AC disturbance signal and a current current response signal;

[0074] Check whether the real and imaginary parts of the current AC impedance conform to the Kramers-Kronig relationship to verify whether the current AC disturbance signal is valid.

[0075] For example, when verifying the validity of the initial AC perturbation signal, the initial current response signal of the interface between the gate oxide layer and the substrate of the transistor is first obtained after the initial AC perturbation signal has been applied for a preset duration. Then, the AC impedance of the interface between the corresponding gate oxide layer and the substrate is calculated using the initial AC perturbation signal and the initial current response signal. The real and imaginary parts of the AC impedance currently obtained are then tested to see if they conform to the Kramers-Kronig relationship. If they do, the initial AC perturbation signal is valid. Otherwise, if the real and imaginary parts of the AC impedance do not conform to the Kramers-Kronig relationship, the initial AC perturbation signal is invalid. The specific calculation method for the Kramers-Kronig relationship will not be described in detail here.

[0076] In step S120 , a response signal of a transistor in the delay line to an AC disturbance signal after a preset time period is obtained.

[0077] The transistor's response signal to the AC perturbation signal specifically refers to the response signal of the interface between the substrate and the gate oxide layer in the transistor to the AC perturbation signal. It should be understood that this response signal is a current response signal. As described above, the value of the preset duration needs to be determined based on the actual reliability test requirements and will not be further described here.

[0078] After the AC disturbance signal is superimposed, a transistor's response signal to the AC disturbance signal can be detected at the semiconductor device's power pin. It can be understood that the detected current signal having the same frequency as the AC disturbance signal is the transistor's response signal to the AC disturbance signal. For example, if the semiconductor device is a DRAM, a current signal having the same frequency as the AC disturbance signal can be detected at the DRAM's power pin, representing the transistor's response signal to the AC disturbance signal superimposed on the delay line.

[0079] In step S130 , whether the delay line is overloaded is detected based on the phase difference between the response signal and the AC disturbance signal.

[0080] As described above, when the applied DC signal to be measured causes the delay line to be overloaded, it will cause interface defects between the gate oxide layer and the substrate of the transistor in the delay line, and then the interface between the gate oxide layer and the substrate will produce a delayed response to the AC disturbance signal. Therefore, by detecting the phase difference between the response signal of the transistor to the AC disturbance signal and the AC disturbance signal, it is possible to indicate whether the delay line is overloaded.

[0081] In an exemplary embodiment, step S130 may include the following steps:

[0082] S1301, determining a phase difference between a response signal and an AC disturbance signal;

[0083] S1302: If the phase difference is greater than or equal to a preset phase difference threshold, determine that the delay line is overloaded.

[0084] The phase difference threshold can be obtained by testing the transistor. In some embodiments, the phase difference threshold may include a lower threshold and an upper threshold. Accordingly, if the phase difference determined in step S1301 is greater than the upper threshold, the delay line is determined to be overloaded.

[0085] For example, Figure 4 FIG1 is a schematic diagram of a transistor's response signal to an AC signal when a delay line is overloaded according to an embodiment of the present disclosure. In the figure, k1 represents the transistor's response signal to an AC signal when no NBTI occurs, and k2 represents the transistor's response signal to an AC signal when NBTI occurs. Figure 4 As shown, when a transistor experiences NBTI, defects at the interface between the transistor's gate oxide layer and the substrate slow the transistor's response to the AC signal, changing the original square wave signal k1 to a slowly rising signal k2. Clearly, there's a delay, or phase difference, between k2 and k1, while k1 is in phase with the input signal. This means the phase difference between k2 and k1 is the same as the phase difference between the transistor's response signal and the input signal. This allows multiple transistor tests to determine the phase difference threshold between the transistor's response signal and the input AC signal when the delay line is overloaded, before conducting a delay line overload test.

[0086] Then, when performing delay line overload detection, the phase difference between the response signal obtained in step S1301 and the superimposed AC disturbance signal is compared with a predetermined phase difference threshold. If the phase difference is less than the phase difference threshold, it can be determined that the DC signal under test has not caused NBTI in the transistor, that is, the delay line is not overloaded. Conversely, if the phase difference is greater than or equal to the phase difference threshold, it can be determined that the DC signal under test has caused NBTI in the transistor, that is, the delay line has been overloaded.

[0087] The detection method disclosed herein is a method of superimposing an AC disturbance signal on a DC signal to be measured. The disturbance frequency of the AC disturbance signal is determined according to the characteristic frequency of the interface between the gate oxide layer of the transistor and the substrate in the delay line, so that the superimposed AC disturbance signal can reflect the interface characteristics between the gate oxide layer of the transistor and the substrate. The signal amplitude of the superimposed AC disturbance signal meets the requirements of causality, stability and linearity, so the superimposed AC disturbance signal will not affect the electrical stress characteristics of the DC signal to be measured. Thus, by detecting the phase difference between the response signal of the transistor to the AC disturbance signal and the AC disturbance signal, it is determined whether the DC signal to be measured causes the transistor NBTI, that is, whether the delay line is overloaded. Compared with the detection method of using a dot needle test to detect whether the delay line is overloaded in the related art, the detection time of the method disclosed herein is short, and it can quickly detect whether the delay line is overloaded, thereby improving the reliability detection efficiency of the product. In addition, the detection method disclosed in the present invention can test in-situ characterization, that is, during the aging process (the DC signal application process is the aging process), the NBTI effect of the delay line can be monitored in-situ by in-situ detecting the phase difference between the AC response signal and the AC disturbance signal.

[0088] The present disclosure also provides an overload detection device for a delay line in a semiconductor device. Figure 5 FIG. 1 is a structural block diagram of an overload detection device for a delay line in a semiconductor device according to an embodiment of the present disclosure. Figure 5 As shown, the detection device 500 may include: a detection signal applying module 510, a response signal acquiring module 520 and a detection module 530, wherein:

[0089] A detection signal applying module 510 is used to continuously apply a voltage signal to the delay line, where the voltage signal includes a DC signal to be measured and an AC disturbance signal, where the AC disturbance signal has a target frequency and a target amplitude;

[0090] A response signal acquisition module 520 is used to acquire a response signal of a transistor in a delay line to an AC disturbance signal after a preset time period;

[0091] The detection module 530 is configured to detect whether the delay line is overloaded based on a phase difference between the response signal and the AC disturbance signal.

[0092] In an exemplary embodiment of the present disclosure, the response signal acquisition module 520 is further configured to:

[0093] A response signal of an interface between a substrate and a gate oxide layer of a transistor in a delay line to an AC disturbance signal after a preset time period is obtained.

[0094] In an exemplary embodiment of the present disclosure, the response signal is an AC signal, and the frequency of the response signal is the same as the frequency of the AC disturbance signal.

[0095] In an exemplary embodiment of the present disclosure, the detection module 530 includes:

[0096] a phase difference determining unit, configured to determine a phase difference between the current response signal and the AC disturbance signal;

[0097] The detection unit is configured to determine that the delay line is overloaded if the phase difference is greater than or equal to a preset phase difference threshold.

[0098] In an exemplary embodiment of the present disclosure, the detection device 500 may further include:

[0099] A first signal applying module, configured to continuously apply a first voltage signal to the delay line, wherein the first voltage signal includes a first DC signal and a target AC signal, and the target AC signal has a target amplitude and a target frequency;

[0100] A delay time response signal acquisition module 520 is used to obtain a first delay time of a transistor in a delay line after a first voltage signal acts for a preset time period;

[0101] A comparison module, configured to compare the first delay time with a preset delay threshold;

[0102] The first signal applying module is further configured to increase the signal amplitude of the first DC signal to obtain a second DC signal if the first delay time is less than a preset delay threshold, and apply a second voltage signal to the delay line, where the second voltage signal includes the second DC signal and a target AC signal;

[0103] The delay time response signal acquisition module 520 is further used to obtain a second delay time of the transistor in the delay line under the action of the second voltage signal;

[0104] The comparison module is further configured to: compare the second delay time with the delay threshold;

[0105] The first repeating module is used to repeatedly execute the steps of determining the second voltage signal and applying the second voltage signal, and comparing the second delay time, if the second delay time is less than a preset delay threshold, until it is determined that the delay time of the transistor under the action of a certain voltage signal reaches the delay threshold, obtain the current response signal of the transistor to the target AC signal, and determine the phase difference between the current response signal and the target AC signal as the phase difference threshold.

[0106] In an exemplary embodiment of the present disclosure, the target frequency of the AC disturbance signal matches the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor in the delay line.

[0107] In an exemplary embodiment of the present disclosure, a ratio of a target frequency to a characteristic frequency of the AC disturbance signal is greater than or equal to 0.8 and less than or equal to 1.5.

[0108] In an exemplary embodiment of the present disclosure, the detection device 500 may further include:

[0109] AC impedance spectrum response signal acquisition module 520, used to obtain the AC impedance spectrum of the transistor in the delay line;

[0110] A characteristic frequency determination module, configured to determine a characteristic frequency of an interface between a gate oxide layer of a transistor and a substrate based on an AC impedance spectrum;

[0111] The target frequency determination module is used to determine the target frequency of the AC disturbance signal based on the characteristic frequency.

[0112] In an exemplary embodiment of the present disclosure, the detection device 500 may further include:

[0113] An initial voltage signal applying module is used to continuously apply an initial voltage signal to the delay line, wherein the initial voltage signal includes a DC signal to be measured and an initial AC disturbance signal, and the initial AC disturbance signal has an initial amplitude;

[0114] A verification module, configured to verify whether the initial AC disturbance signal is effective based on a response result of an interface between a gate oxide layer of the transistor and a substrate to the initial voltage signal after a preset time period;

[0115] The second repetitive module is used to increase the amplitude of the AC disturbance signal on the basis of the initial amplitude if the initial AC disturbance signal is valid, and repeat the steps of applying the initial voltage signal and verifying whether the initial AC disturbance signal is valid, until it is determined that the AC disturbance signal is invalid, and the signal amplitude of the previous valid AC disturbance signal before the invalid AC disturbance signal is determined as the target amplitude of the AC disturbance signal.

[0116] In an exemplary embodiment of the present disclosure, the verification module is further configured to:

[0117] detecting a current response signal at an interface between a gate oxide layer and a substrate of the transistor corresponding to an initial AC disturbance signal after a preset time period;

[0118] Determining an initial AC impedance of an interface between a gate oxide layer of the transistor and a substrate based on the initial AC disturbance signal and the initial current response signal;

[0119] The real and imaginary parts of the initial AC impedance are detected to see whether they conform to the Kramers-Kronig relationship, so as to verify whether the initial AC disturbance signal is effective.

[0120] In an exemplary embodiment of the present disclosure, the DC signal to be measured is smaller than the intrinsic breakdown voltage of the transistors in the delay line.

[0121] In an exemplary embodiment of the present disclosure, the AC disturbance signal is a periodic clock signal or a periodic sinusoidal signal.

[0122] Figure 6 This is a schematic diagram of the structure of a detection device according to an embodiment of the present disclosure. It should be noted that: Figure 6 The detection device 600 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure. Figure 6 As shown, the detection device 600 may include but is not limited to a PC running preset software, a server, etc.

[0123] like Figure 6 As shown, the detection device 600 includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 into the random access memory (RAM) 603. Various programs and data required for system operation are also stored in the (RAM) 603. The (CPU) 601, the (ROM) 602 and the (RAM) 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0124] The following components are connected to the (I / O) interface 605: an input section 606 including a keyboard, a mouse, and the like; an output section 607 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 608 including a hard disk; and a communication section 609 including a network interface card such as a LAN card or a modem. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the (I / O) interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 610 as needed, so that computer programs read therefrom can be installed into the storage section 608 as needed.

[0125] In particular, according to the embodiments of the present disclosure, the above reference process Figure 3 The described process can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a computer-readable storage medium, the computer program containing program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609 and / or installed from a removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the various functions defined in the method and apparatus of the present disclosure are performed.

[0126] It should be noted that the computer-readable storage medium shown in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable storage medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code contained on a computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, or any suitable combination thereof.

[0127] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be included in the detection device 600 described in the above embodiment; or may exist independently without being assembled into the detection device 600. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed by the detection device 600, the detection device 600 implements the method in the above embodiment. For example, the detection device 600 may implement the following. Figure 1 The various steps shown, etc.

[0128] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A method for detecting an overload of a delay line in a semiconductor device, characterized in that: The delay line includes a transistor, and the method includes: Continuously applying a voltage signal to the delay line, wherein the voltage signal includes a DC signal to be measured and an AC disturbance signal, and the AC disturbance signal has a target frequency and a target amplitude; Acquiring a current response signal of a transistor in the delay line to the AC disturbance signal after a preset time period; Whether the delay line is overloaded is detected based on a phase difference between the current response signal and the AC disturbance signal.

2. The method according to claim 1, characterized in that The obtaining of a current response signal of a transistor in the delay line to the AC disturbance signal after a preset time period includes: A current response signal of an interface between a substrate and a gate oxide layer of a transistor in the delay line to the AC disturbance signal after a preset time period is obtained.

3. The method according to claim 2, characterized in that The current response signal is an AC signal, and the frequency of the current response signal is the same as the frequency of the AC disturbance signal.

4. The method according to claim 1, wherein The detecting whether the delay line is overloaded based on the phase difference between the current response signal and the AC disturbance signal includes: determining a phase difference between the current response signal and the AC disturbance signal; If the phase difference is greater than or equal to a preset phase difference threshold, it is determined that the delay line is overloaded.

5. The method according to claim 4, characterized in that Before determining the phase difference between the current response signal and the AC disturbance signal, the method further includes: continuously applying a first voltage signal to the delay line, wherein the first voltage signal includes a first DC signal and a target AC signal, and the target AC signal has a target amplitude and a target frequency; Obtaining a first delay time of a transistor in the delay line after the first voltage signal acts for a preset time period; comparing the first delay time with a preset delay threshold; If the first delay time is less than a preset delay threshold, the signal amplitude is increased on the basis of the first DC signal to obtain a second DC signal, and a second voltage signal is applied to the delay line, where the second voltage signal includes the second DC signal and the target AC signal; Obtaining a second delay time of the transistor in the delay line after the second voltage signal acts for a preset time period; comparing the second delay time with the delay threshold; If the second delay time is less than a preset delay threshold, the steps of determining the second voltage signal and applying the second voltage signal and the step of comparing the second delay time are repeated until it is determined that the delay time of the transistor under the action of a certain voltage signal reaches the delay threshold, the current response signal of the transistor to the target AC signal is obtained, and the phase difference between the current response signal and the target AC signal is determined as the phase difference threshold.

6. The method according to claim 1, characterized in that The target frequency of the AC disturbance signal matches the characteristic frequency of the interface between the gate oxide layer and the substrate of the transistor in the delay line.

7. The method according to claim 6, characterized in that The ratio of the target frequency of the AC disturbance signal to the characteristic frequency is greater than or equal to 0.8 and less than or equal to 1.

5.

8. The method according to claim 6, characterized in that Before continuously applying the voltage signal to the delay line, the method further includes: Obtaining an AC impedance spectrum of a transistor in the delay line; Determining a characteristic frequency of an interface between a gate oxide layer and a substrate of a transistor based on the AC impedance spectrum; The target frequency of the AC disturbance signal is determined based on the characteristic frequency.

9. The method according to claim 1, characterized in that Before continuously applying the voltage signal to the delay line, the method further includes: Continuously applying an initial voltage signal to the delay line, wherein the initial voltage signal includes a DC signal to be measured and an initial AC disturbance signal, and the initial AC disturbance signal has an initial amplitude; Verifying whether the initial AC disturbance signal is effective based on a response result of an interface between the gate oxide layer of the transistor and the substrate to the initial voltage signal after a preset time period; If the initial AC disturbance signal is valid, the amplitude of the AC disturbance signal is increased based on the initial amplitude, and the steps of applying the initial voltage signal and verifying whether the initial AC disturbance signal is valid are repeated until it is determined that the AC disturbance signal is invalid, and the signal amplitude of the previous valid AC disturbance signal before the invalid AC disturbance signal is determined as the target amplitude of the AC disturbance signal.

10. The method according to claim 9, characterized in that The verifying whether the initial AC disturbance signal is effective based on a response result of an interface between the gate oxide layer of the transistor and the substrate to the initial voltage signal after a preset time period includes: detecting an initial current response signal at an interface between a gate oxide layer and a substrate of the transistor corresponding to the initial AC disturbance signal after a preset time period; Determining an initial AC impedance of an interface between a gate oxide layer and a substrate of the transistor based on the initial AC disturbance signal and the initial current response signal; Whether the real part and the imaginary part of the initial AC impedance conform to the Kramers-Kronig relationship is detected to verify whether the initial AC disturbance signal is valid.

11. The method according to claim 1, wherein The DC signal to be measured is smaller than the intrinsic breakdown voltage of the transistor in the delay line.

12. The method according to claim 1, characterized in that The AC disturbance signal is a periodic clock signal or a periodic sinusoidal signal.

13. An overload detection device for a delay line in a semiconductor device, characterized in that: include: A detection signal applying module, configured to continuously apply a voltage signal to the delay line, wherein the voltage signal includes a DC signal to be measured and an AC disturbance signal, and the AC disturbance signal has a target frequency and a target amplitude; a response signal acquisition module, configured to acquire a current response signal of the transistor in the delay line to the AC disturbance signal after a preset time period; A detection module is used to detect whether the delay line is overloaded based on a phase difference between the current response signal and the AC disturbance signal.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method for detecting an overload of a delay line in a semiconductor device according to any one of claims 1 to 12 is implemented.

15. A detection device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the one or more processors to implement the overload detection method for a delay line in a semiconductor device according to any one of claims 1 to 12.

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