Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first functional layer and a first metal layer; the first functional layer includes a first insulating layer and a first pattern layer, which are arranged on the base substrate and located in the peripheral area, the first insulating layer includes a material removal area arranged along at least part of the edge of the base substrate, in which the material of the first insulating layer is removed, the first pattern layer includes a plurality of insulating patterns arranged in the material removal area and spaced along at least part of the edge, and gaps respectively located between adjacent insulating patterns; the first metal layer is arranged on a side of the first insulating layer away from the base substrate and located in the peripheral area, the first metal layer includes a plurality of first contact pads arranged at intervals, at least part of the plurality of first contact pads respectively extending toward the plurality of gaps or toward the plurality of insulating patterns. The display substrate has a higher manufacturing yield.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first functional layer and a first metal layer; the first functional layer includes a first insulating layer and a first pattern layer, which are arranged on the base substrate and located in the peripheral area, wherein the first insulating layer includes a material removal area arranged along at least a portion of the edge of the base substrate, in which material of the first insulating layer is removed, and the first pattern layer includes a plurality of insulating patterns arranged in the material removal area and spaced apart along at least a portion of the edge, and gaps respectively located between adjacent insulating patterns among the plurality of insulating patterns; the first metal layer is arranged on a side of the first insulating layer away from the base substrate and located in the peripheral area, wherein the first metal layer includes a plurality of first contact pads arranged at intervals, and at least some of the plurality of first contact pads extend toward the plurality of gaps or toward the plurality of insulating patterns, respectively.

[0004] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a metal material disposed in at least a portion of the plurality of notches.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the metal material is the same as the material of the first metal layer.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first insulating layer and the first pattern layer are made of the same material, and the first insulating layer is integrally connected to the plurality of insulating patterns.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of first contact pads are located on a side of the material removal area close to the display region.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, the extension direction of the plurality of first contact pads is substantially perpendicular to the at least partial edge.

[0009] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a circuit board, including a plurality of second contact pads, wherein, when the plurality of first contact pads respectively extend toward the plurality of notches, the plurality of second contact pads are respectively located on a side of the plurality of notches away from the base substrate, and are correspondingly connected to the plurality of first contact pads; when the plurality of first contact pads respectively extend toward the plurality of insulating patterns, the plurality of second contact pads are respectively located on a side of the plurality of insulating patterns away from the base substrate, and are correspondingly connected to the plurality of first contact pads.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least part of the edge of the base substrate includes an edge of a first side of the base substrate or edges of a first side and a second side opposite to each other of the base substrate.

[0011] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a plurality of pixel driving circuits, which are arranged on the base substrate and in the display area, wherein each of the plurality of pixel driving circuits includes a thin film transistor and a storage capacitor, the thin film transistor includes a gate and a source-drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the gate is arranged in the same layer as the first capacitor electrode, the second capacitor electrode is arranged on a side of the first capacitor electrode away from the base substrate, and the source-drain electrode is arranged on a side of the second capacitor electrode away from the base substrate.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first metal layer and the source-drain electrode are arranged in the same layer.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area further includes: a first gate insulating layer, arranged on a side of the gate electrode and the first capacitor electrode close to the base substrate, a second gate insulating layer, arranged on a side of the gate electrode and the first capacitor electrode away from the base substrate, and an interlayer insulating layer, arranged on a side of the second capacitor electrode away from the base substrate, wherein the first insulating layer is arranged on the same layer as at least one of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.

[0014] At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first functional layer and a first metal layer; the first functional layer includes a first insulating layer and a first pattern layer, which are arranged on the base substrate and located in the peripheral area, wherein the first insulating layer includes a material removal area arranged along at least a portion of the edge of the base substrate, in which material of the first insulating layer is removed, and the first pattern layer is arranged in the material removal area; the first metal layer is arranged on a side of the first insulating layer away from the base substrate and located in the peripheral area, wherein the first metal layer includes a plurality of first contact pads arranged at intervals, and wherein the first pattern layer is covered with metal material.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the metal material is the same as the material of the first metal layer.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first insulating layer includes an inorganic insulating material, and the first pattern layer includes an organic insulating material.

[0017] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a circuit board, including multiple second contact pads, wherein the multiple second contact pads are respectively located on a side of the first pattern layer away from the base substrate, and are correspondingly connected to the multiple first contact pads.

[0018] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a plurality of pixel driving circuits, which are arranged on the base substrate and in the display area, wherein each of the plurality of pixel driving circuits includes a thin film transistor and a storage capacitor, the thin film transistor includes a gate and a source-drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the gate is arranged in the same layer as the first capacitor electrode, the second capacitor electrode is arranged on a side of the first capacitor electrode away from the base substrate, and the source-drain electrode is arranged on a side of the second capacitor electrode away from the base substrate.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first metal layer and the source-drain electrode are arranged in the same layer.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area further includes: a first gate insulating layer, arranged on a side of the gate electrode and the first capacitor electrode close to the base substrate, a second gate insulating layer, arranged on a side of the gate electrode and the first capacitor electrode away from the base substrate, and an interlayer insulating layer, arranged on a side of the second capacitor electrode away from the base substrate, wherein the first insulating layer is arranged on the same layer as at least one of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area further includes: a planarization layer, arranged on a side of the source and drain electrodes away from the base substrate, wherein the first pattern layer is arranged on the same layer as the planarization layer.

[0022] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0024] Figure 1 is a schematic plan view of a display substrate;

[0025] Figure 2 for Figure 1 A schematic cross-sectional view of a display substrate along line AA;

[0026] Figure 3 for Figure 1 A schematic cross-sectional view of the display substrate along line BB;

[0027] Figure 4 A schematic plan view of a display substrate provided for at least one embodiment of the present disclosure;

[0028] Figure 5 for Figure 4 A schematic cross-sectional view of a display substrate along line AA;

[0029] Figure 6 for Figure 4 A schematic cross-sectional view of the display substrate along line BB;

[0030] Figure 7 for Figure 4 A schematic cross-sectional view of a display substrate along line CC;

[0031] Figure 8A schematic plan view of a display substrate connected to a circuit board provided in at least one embodiment of the present disclosure;

[0032] Fig. 9 A schematic plan view of another display substrate provided for at least one embodiment of the present disclosure;

[0033] Fig.10 for Fig. 9 A schematic cross-sectional view of a display substrate along line AA;

[0034] Fig.11 for Fig. 9 A schematic cross-sectional view of the display substrate along line BB;

[0035] Fig.12 for Fig. 9 A schematic cross-sectional view of a display substrate along line CC;

[0036] Fig.13 A schematic plan view of another display substrate connected to a circuit board provided in at least one embodiment of the present disclosure;

[0037] Fig.14 A partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided in at least one embodiment of the present disclosure;

[0038] Fig.15 A schematic plan view of yet another display substrate provided for at least one embodiment of the present disclosure;

[0039] Fig.16 for Fig.15 A schematic cross-sectional view of the display substrate along line BB;

[0040] Fig.17 A schematic plan view of another display substrate connected to a circuit board provided for at least one embodiment of the present disclosure; and

[0041] Fig.18 A schematic plan view of a display substrate during the preparation process provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] Figure 1 A schematic plan view of a display substrate is shown. Figure 1 As shown, the display substrate generally includes a display area AA and a peripheral area NA at least partially surrounding the display area AA, and a plurality of signal lines L located in the display area AA are respectively connected to a plurality of contact pads 12 of a driving circuit board through a plurality of contact pads 11 located in the peripheral area NA to obtain electrical signals from the driving circuit board or output electrical signals to the driving circuit board.

[0045] Figure 2 for Figure 1 A schematic cross-sectional view of the display substrate along line AA in FIG. Figure 3 for Figure 1 A schematic cross-sectional view of the display substrate along line BB in FIG. Figure 1-Figure 3 In some embodiments, the insulating layer 13 of the display substrate has a material removal area N at the edge E of the display substrate, and the material of the insulating layer 13 is removed in the material removal area N to avoid cutting the insulating layer 13 when the display substrate is cut, thereby avoiding the formation of cracks in the insulating layer 13.

[0046] In the preparation process of the above-mentioned display substrate, for example, when a plurality of contact pads 11 are formed on the insulating layer 13 by a patterning process, the materials of the plurality of contact pads 11 are formed on the insulating layer 13 and the material removal area N of the insulating layer 13 by a process such as sputtering or deposition, and then the plurality of contact pads 11 are formed by etching. However, in actual operation, due to the step difference between the film layers, the material at the edge of the material removal area N is often difficult to be completely etched and removed, so that a metal residue R is formed at a position close to the edge E of the insulating layer 13, as shown in FIG. Figure 3 shown.

[0047] like Figure 2As shown in FIG. 1 , the metal residue R often forms a continuous strip pattern at the edge of the insulating layer 13. At this time, when the plurality of contact pads 12 are connected to the plurality of contact pads 11, as shown in FIG. Figure 3 As shown, the multiple contact pads 12 are all in contact with the metal residue R, which causes the multiple contact pads 12 to be electrically connected, resulting in signal crosstalk, which affects the signal transmission of the display substrate.

[0048] At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate has a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a first functional layer and a first metal layer; the first functional layer includes a first insulating layer and a first pattern layer, which are arranged on the base substrate and located in the peripheral area, wherein the first insulating layer includes a material removal area arranged along at least a portion of the edge of the base substrate, in which the material of the first insulating layer is removed, and the first pattern layer includes a plurality of insulating patterns arranged in the material removal area and spaced apart along at least a portion of the edge, and gaps respectively located between adjacent insulating patterns in the plurality of insulating patterns; the first metal layer is arranged on a side of the first insulating layer away from the base substrate and located in the peripheral area, wherein the first metal layer includes a plurality of first contact pads arranged at intervals, and at least a portion of the plurality of first contact pads extend toward the plurality of gaps or toward the plurality of insulating patterns, respectively.

[0049] The display substrate provided by the embodiment of the present disclosure can avoid the formation of continuous metal material in the material removal area by setting a plurality of spaced insulating patterns and gaps respectively located between adjacent insulating patterns in the material removal area of ​​the first insulating layer. This can avoid unnecessary connection between other contact pads when the plurality of first contact pads are connected to other contact pads, thereby ensuring the connection accuracy of the contact pads and improving the circuit connection accuracy of the display substrate.

[0050] The display substrate and the display device provided by the embodiments of the present disclosure are described below through several specific embodiments.

[0051] At least one embodiment of the present disclosure provides a display substrate. Figure 4 shows a schematic plan view of the display substrate, Figure 5 FIG. 4 shows a schematic cross-sectional view of the display substrate along line AA, Figure 6 FIG. 4 shows a schematic cross-sectional view of the display substrate along line BB, Figure 7 Schematic cross-sectional views of the display substrate along the CC line are shown. For example, these schematic cross-sectional views simultaneously show the cross section along the above-mentioned cutting line and the structure behind the cross section that can be seen from the cross section. For example, Figure 5 It also shows Figure 4 A cross section of the display substrate along line AA in FIG. 1 and the metal material R and the first contact pad 1031 behind the cross section that can be seen from the cross section; Figure 6It also shows Figure 4 A cross section of the display substrate along line BB in FIG. 1 and an insulating pattern 1022A behind the cross section that can be seen from the cross section; Figure 7 It also shows Figure 4 A cross section of the display substrate along line CC in FIG. 1 and a first contact pad 1031 behind the cross section that can be seen from the cross section.

[0052] like Figure 4-Figure 7 As shown, the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA, and includes a base substrate 101 , a first functional layer 102 and a first metal layer 103 .

[0053] The first functional layer 102 includes a first insulating layer 1021 and a first pattern layer 1022. The first insulating layer 1021 and the first pattern layer 1022 are disposed on the base substrate 101 and are located in the peripheral area NA. The first insulating layer 1021 includes a first insulating layer 1021 and a first pattern layer 1022. Figure 4 The first pattern layer 1022 includes a material removal area 1021A provided in the material removal area 1021A and along at least a portion of the edge (shown as the upper edge) of the substrate 101. In the material removal area 1021A, the material of the first insulating layer 1021 is removed. Figure 4 A plurality of insulating patterns 1022A are spaced apart from each other (shown as the upper edge in FIG. 1 ), and gaps 1022B are respectively located between adjacent insulating patterns 1022A in the plurality of insulating patterns 1022A.

[0054] The first metal layer 103 is disposed on a side of the first insulating layer 1021 away from the base substrate 101 and located in the peripheral area NA. The first metal layer 103 includes a plurality of first contact pads 1031 disposed at intervals. At least a portion of the plurality of first contact pads 1031 extend toward the plurality of notches 1022B, respectively ( Figure 4-Figure 7 The contact pads 1022A and 1022B may extend toward the plurality of insulating patterns 1022A (as shown) or toward the plurality of insulating patterns 1022A (described later) so as to be connected to other contact pads through the plurality of notches 1022B or the plurality of insulating patterns 1022A.

[0055] For example, in some embodiments, Figure 5 and Figure 6 As shown, the display substrate further includes a metal material R disposed in at least a portion of the notch 1022B. For example, the metal material R is a metal residue formed when preparing the plurality of first contact pads 1031 of the first metal layer 103 during the preparation of the display substrate, and thus the metal material R is the same as the material of the first metal layer 103 .

[0056] For example, in some embodiments, the first insulating layer 1021 and the first pattern layer 1022 are made of the same material, and the first insulating layer 1021 is integrally connected with the plurality of insulating patterns 1022A. Figure 7 shown.

[0057] In the embodiments of the present disclosure, “integrated connection” means that the materials of the two structures are continuous without obvious dividing lines, and can be formed at one time using the same preparation process during the preparation process, thereby simplifying the preparation process of the display substrate.

[0058] For example, in other embodiments, the materials of the first insulating layer 1021 and the first pattern layer 1022 may also be different. In this case, in the process of displaying the substrate, the first insulating layer 1021 may be formed first, and then the first pattern layer 1022 may be formed. In this embodiment, the material of the first pattern layer 1022 may be an organic insulating material or an inorganic insulating material.

[0059] In the embodiment of the present disclosure, due to the presence of the plurality of insulating patterns 1022A, the metal material R is not continuously disposed in the material removal area 1021A, and the metal material R may only exist in the gaps 1022B between the plurality of insulating patterns 1022A, thereby forming a plurality of disconnected portions, such as Figure 5 shown.

[0060] For example, in some embodiments, Figure 4 As shown, multiple first contact pads 1031 are located on one side of the material removal area 1021A close to the display area AA, that is, multiple first contact pads 1031 do not extend to the material removal area 1021A, which is conducive to accurately preparing multiple first contact pads 1031 in the flat area of ​​the first insulating layer 1021.

[0061] For example, in some embodiments, Figure 4 As shown, the extension direction of the plurality of first contact pads 1031 ( Figure 4 The vertical direction in the figure) is substantially perpendicular to at least a portion of the edge of the substrate 101 ( Figure 4 The upper edge shown in the figure) is advantageous for arranging more first contact pads 1031 in the same space and for connecting the plurality of first contact pads 1031 to other contact pads.

[0062] For example, in some embodiments, Figure 8 As shown, the display substrate further includes a circuit board 105, such as a flexible circuit board (FPC). The circuit board 105 includes a plurality of second contact pads 1051. When the plurality of first contact pads 1031 extend toward the plurality of notches 1022B respectively, the plurality of second contact pads 1051 are respectively located on a side of the plurality of notches 1022B away from the base substrate 101, and are correspondingly connected to the plurality of first contact pads 1031, for example, one-to-one correspondingly.

[0063] In the embodiment of the present disclosure, due to the presence of the plurality of insulating patterns 1022A, the metal material R will not be continuously disposed in the material removal area 1021A. Therefore, when the plurality of second contact pads 1051 are correspondingly connected to the plurality of first contact pads 1031, since the plurality of first contact pads 1031 extend toward the plurality of notches 1022B respectively, the plurality of second contact pads 1051 extend respectively on the side of the plurality of notches 1022B away from the base substrate 101, so as to be correspondingly connected to the plurality of first contact pads 1031, for example, one-to-one correspondingly connected. Therefore, even if the plurality of notches 1022B contain the metal material R, since the metal material R under the plurality of second contact pads 1051 will not be connected together, the plurality of second contact pads 1051 will not be connected to each other, and thus no signal crosstalk will be generated.

[0064] For example, the "at least part of the edge of the base substrate" in the embodiment of the present disclosure refers to the edge of the display substrate where the first contact pad 1031 is provided, that is, the edge where the contact pad electrically connected to the circuit board 105 is provided, that is, the edge for electrically connecting to the circuit board 105. For example, in some embodiments, the at least part of the edge of the base substrate includes the edge of the first side (the upper side in the figure) of the base substrate 101, that is, Figure 4 ; or, in some other embodiments, at least part of the edge of the above-mentioned base substrate includes the edge of the first side (e.g., the upper side) and the second side (e.g., the lower side) of the base substrate 101. In this case, the edges of the first side and the second side of the base substrate 101 are both provided with first contact pads, and both have the design of the first insulating layer 1021 and the first pattern layer 1022 as described above. Or, in some other embodiments, the edges of the first side and the second side of the base substrate 101 can also be the edges of the left and right sides of the display substrate, which is not specifically limited in the embodiments of the present disclosure.

[0065] For example, in some embodiments, Figure 4 As shown, one end of the multiple first contact pads 1031 close to the display area AA is connected to the multiple signal lines L1 in the display area AA. The multiple signal lines L1 can be, for example, gate lines, data lines, power lines, light control lines, reset lines, etc., which are signal lines that provide electrical signals to the multiple sub-pixels in the display area AA, so that the multiple first contact pads 1031 connect the multiple signal lines L1 in the display area AA to the circuit board 105.

[0066] For example, in some embodiments, Figure 5-Figure 7As shown, other functional layers such as a functional layer 104 may also be provided on the base substrate 101. The functional layer 104 may include, for example, a buffer layer, a barrier layer, and other functional layers. These functional layers may be made of, for example, inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The embodiments of the present disclosure do not specifically limit other structures on the display substrate.

[0067] At least one embodiment of the present disclosure further provides a display substrate, Fig. 9 shows a schematic plan view of the display substrate, Fig.10 FIG. 4 shows a schematic cross-sectional view of the display substrate along line AA, Fig.11 FIG. 4 shows a schematic cross-sectional view of the display substrate along line BB, Fig.12 The cross-sectional schematic diagrams of the display substrate along the CC line are shown. For example, these cross-sectional schematic diagrams simultaneously show the cross section along the above-mentioned cutting line and the structure behind the cross section that can be seen from the cross section.

[0068] like Figure 9-12 As shown, the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA, and includes a base substrate 101 , a first functional layer 102 and a first metal layer 103 .

[0069] The first functional layer 102 includes a first insulating layer 1021 and a first pattern layer 1022. The first insulating layer 1021 and the first pattern layer 1022 are disposed on the base substrate 101 and are located in the peripheral area NA. The first insulating layer 1021 includes a first insulating layer 1021 and a first pattern layer 1022. Figure 4 The first pattern layer 1022 includes a material removal area 1021A disposed in the material removal area 1021A and spaced along at least a portion of the edge of the base substrate 101, and gaps 1022B respectively located between adjacent insulation patterns 1022A in the plurality of insulation patterns 1022A.

[0070] The first metal layer 103 is disposed on a side of the first insulating layer 1021 away from the base substrate 101 and located in the peripheral area NA. The first metal layer 103 includes a plurality of first contact pads 1031 disposed at intervals. At least a portion of the plurality of first contact pads 1031 extends toward the plurality of insulating patterns 1022A, respectively (e.g., Fig. 9 As shown), so as to facilitate connection with other contact pads through multiple insulating patterns 1022A.

[0071] For example, in some embodiments, Fig. 9 and Fig.12As shown, the display substrate further includes a metal material R disposed in at least a portion of the notch 1022B. For example, the metal material R is a metal residue formed when preparing the plurality of first contact pads 1031 of the first metal layer 103 during the preparation of the display substrate, and thus the metal material R is the same as the material of the first metal layer 103 .

[0072] For example, in some embodiments, the first insulating layer 1021 and the first pattern layer 1022 are made of the same material, and the first insulating layer 1021 is integrally connected with the plurality of insulating patterns 1022A. Figure 7 shown.

[0073] For example, in other embodiments, the materials of the first insulating layer 1021 and the first pattern layer 1022 may also be different. In this case, in the process of displaying the substrate, the first insulating layer 1021 may be formed first, and then the first pattern layer 1022 may be formed. In this embodiment, the material of the first pattern layer 1022 may be an organic insulating material or an inorganic insulating material.

[0074] For example, Fig.13 As shown, the display substrate further includes a circuit board 105, such as a flexible circuit board (FPC). The circuit board 105 includes a plurality of second contact pads 1051. When the plurality of first contact pads 1031 extend toward the plurality of insulating patterns 1022A, the plurality of second contact pads 1051 are respectively located on a side of the plurality of insulating patterns 1022A away from the base substrate 101, and are correspondingly connected to the plurality of first contact pads 1031, for example, one-to-one.

[0075] In the embodiment of the present disclosure, due to the presence of the plurality of insulating patterns 1022A, the metal material R will not be continuously disposed in the material removal area 1021A. Therefore, when the plurality of second contact pads 1051 are correspondingly connected to the plurality of first contact pads 1031, since the plurality of first contact pads 1031 extend toward the plurality of insulating patterns 1022A respectively, the plurality of second contact pads 1051 extend respectively on the side of the plurality of insulating patterns 1022A away from the base substrate 101 to be correspondingly connected to the plurality of first contact pads 1031, for example, one-to-one correspondingly connected. Thus, even if the plurality of notches 1022B contain the metal material R, since the plurality of second contact pads 1051 are respectively disposed on the plurality of insulating patterns 1022A, they will not contact the metal material R. Therefore, the plurality of second contact pads 1051 will not be connected to each other, and thus no signal crosstalk will be generated.

[0076] For example, for Figure 9-12 Display substrate, other structures and references in the embodiments Figure 4-Figure 8 The embodiments of the present invention will not be described in detail here.

[0077] For example, for Figure 4-Figure 8 Embodiments and Figure 9-12 In the embodiment of the present invention, the display area AA may have substantially the same configuration. For example, the display area AA has a plurality of sub-pixels for display, each of which includes a light emitting device and a pixel driving circuit for driving the light emitting device.

[0078] For example, Fig.14 A partial cross-sectional schematic diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure is shown. For example, the display substrate includes a plurality of pixel driving circuits D for a plurality of sub-pixels, the plurality of pixel driving circuits D are arranged on the base substrate 101 and arranged in the display area AA, each of the plurality of pixel driving circuits A includes a plurality of thin film transistors and a storage capacitor, Fig.14 A thin film transistor T and a storage capacitor C are shown in FIG. 1 . The thin film transistor T includes a gate active layer Ta, a gate Tg, and source and drain electrodes Ts and Td. The storage capacitor C includes a first capacitor electrode C1 and a second capacitor electrode C2.

[0079] For example, Fig.14 As shown, the gate Tg is arranged in the same layer as the first capacitor electrode C1, the second capacitor electrode C2 is arranged on the side of the first capacitor electrode C1 away from the base substrate 101, and the source and drain electrodes Ts and Td are arranged on the side of the second capacitor electrode C2 away from the base substrate 101.

[0080] For example, in some embodiments, the first metal layer 103 is disposed in the same layer as the source-drain electrodes Ts and Td.

[0081] It should be noted that in the embodiments of the present disclosure, "same-layer arrangement" means that two (or more) functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two (or more) functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process.

[0082] For example, Fig.14 As shown, the display area AA further includes a first gate insulating layer GI1, a second gate insulating layer GI2 and an interlayer insulating layer ILD. The first gate insulating layer GI1 is disposed on the side of the gate electrode Tg and the first capacitor electrode C1 close to the substrate 101, and on the side of the active layer Ta away from the substrate 101; the second gate insulating layer GI2 is disposed on the side of the gate electrode Tg and the first capacitor electrode C1 away from the substrate 101; and the interlayer insulating layer ILD is disposed on the side of the second capacitor electrode C2 away from the substrate 101. For example, the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, respectively; the materials of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may be the same or different.

[0083] For example, in some embodiments, the first insulating layer 1021 is disposed at the same layer as at least one of the first gate insulating layer GI1 , the second gate insulating layer GI2 , and the interlayer insulating layer ILD.

[0084] That is, when the first insulating layer 1021 has only one layer, the first insulating layer 1021 is arranged on the same layer as the first gate insulating layer GI1, the second gate insulating layer GI2 or the interlayer insulating layer ILD; when the first insulating layer 1021 has two sub-layers, the two sub-layers are respectively arranged on the same layer as two of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD; when the first insulating layer 1021 has three sub-layers, the three sub-layers are respectively arranged on the same layer as the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD.

[0085] For example, Fig.14 As shown, the display area AA further includes a planarization layer PLN, which is disposed on the side of the source and drain electrodes Ts and Td away from the base substrate 101 to provide a substantially flat surface on the pixel driving circuit. For example, the planarization layer PLN may be made of an organic insulating material such as polyimide or resin.

[0086] For example, Fig.14 As shown, the light emitting device EL is arranged on the side of the planarization layer PLN away from the base substrate 101. For example, the light emitting device EL may be an organic light emitting device (OLED), including a stacked first electrode E1 (e.g., an anode), an organic light emitting layer E2, and a second electrode E3 (e.g., a cathode); or, the light emitting device EL may also be a quantum dot light emitting device (QLED), including a stacked first electrode E1 (e.g., an anode), a quantum dot light emitting layer E2, and a second electrode E3 (e.g., a cathode). For example, in some embodiments, the second electrode E3 of the light emitting device EL may be a surface electrode continuously arranged on the display substrate.

[0087] For example, Fig.14 As shown, a pixel defining layer PDL is arranged on the first electrode E1, and the pixel defining layer PDL includes a plurality of sub-pixel openings O for defining the light-emitting area of ​​the sub-pixel, and the organic light-emitting layer E2 is at least arranged in the sub-pixel opening O, so that the organic light-emitting layer E2 in the sub-pixel opening O can directly contact the first electrode E1 and the second electrode E3, and emit light under the drive of the first electrode E1 and the second electrode E3.

[0088] For example, Fig.14As shown, an encapsulation layer EN is provided on the light-emitting device EL. For example, the encapsulation layer EN may be a composite encapsulation layer, including a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer (not shown in the figure). The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, such as silicon oxide, silicon nitride or silicon oxynitride, etc., and the second encapsulation layer may be made of organic materials, such as polyimide, resin, etc. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting device EL.

[0089] For example, the display area AA of the display substrate may further include other structures such as spacers, and the embodiments of the present disclosure do not limit other structures and will not be described in detail.

[0090] At least one embodiment of the present disclosure further provides a display substrate, Fig.15 shows a schematic plan view of the display substrate, Fig.16 A schematic cross-sectional view of the display substrate along line BB is shown.

[0091] like Fig.15 and Fig.16 As shown, the display substrate has a display area AA and a peripheral area NA at least partially surrounding the display area AA, and includes a base substrate 101 , a first functional layer 102 and a first metal layer 103 .

[0092] The first functional layer 102 includes a first insulating layer 1021 and a first pattern layer 1022. The first insulating layer 1021 and the first pattern layer 1022 are disposed on the base substrate 101 and are located in the peripheral area NA. The first insulating layer 1021 includes a first insulating layer 1021 and a first pattern layer 1022. Fig.14 A material removal area 1021A is set in the material removal area 1021A), in which the material of the first insulating layer 1021 is removed, and the first pattern layer 1022 is set in the material removal area 1021A, for example, at least partially fills the material removal area 1021A, for example, completely fills the material removal area 1021A.

[0093] The first metal layer 103 is disposed on a side of the first insulating layer 1021 away from the base substrate 101 and located in the peripheral area NA. The first metal layer 103 includes a plurality of first contact pads 1031 disposed at intervals. The first pattern layer 1022 is covered with a metal material R.

[0094] For example, the metal material R is a metal residue formed when preparing the plurality of first contact pads 1031 of the first metal layer 103 during the preparation process of the display substrate, and thus the metal material R is the same as the material of the first metal layer 103 .

[0095] For example, in some embodiments, the first insulating layer 1021 includes an inorganic insulating material, and the first pattern layer 1022 includes an organic insulating material. For example, in the preparation process of the display substrate, the first pattern layer 1022 is formed after the first metal layer 103 is formed, so even if there is a metal material R in the material removal area 1021A, the subsequently formed first pattern layer 1022 can completely cover the metal material R to prevent the metal material R from being exposed.

[0096] For example, in some embodiments, Fig.17 As shown, the display substrate also includes a circuit board 105, such as a flexible circuit board (FPC), and the circuit board 105 includes a plurality of second contact pads 1051, and the plurality of second contact pads 1051 are respectively located on a side of the first pattern layer 1022 away from the base substrate 101, and are correspondingly connected to the plurality of first contact pads 1051, for example, one-to-one.

[0097] In the embodiment of the present disclosure, since the first pattern layer 1022 covers the metal material R, the metal material R will not be exposed. When the multiple second contact pads 1051 are arranged on the first pattern layer 1022, they will not be connected to the metal material R, thereby ensuring the connection accuracy between the multiple second contact pads 1051 and the multiple first contact pads 1051.

[0098] For example, the display area AA of the display substrate is substantially the same as that of the above embodiment.

[0099] For example, refer to Fig.14 The display substrate further includes a plurality of pixel driving circuits D, which are arranged on the base substrate 101 and in the display area AA. Each of the plurality of pixel driving circuits A includes a thin film transistor T and a storage capacitor C. The thin film transistor T includes an active layer Ta, a gate Tg, and source-drain electrodes Ts and Td. The storage capacitor C includes a first capacitor electrode C1 and a second capacitor electrode C2. The gate Tg is arranged in the same layer as the first capacitor electrode C1, the second capacitor electrode C2 is arranged on a side of the first capacitor electrode C1 away from the base substrate 101, and the source-drain electrodes Ts and Td are arranged on a side of the second capacitor electrode C2 away from the base substrate 101.

[0100] For example, the first metal layer 103 is provided in the same layer as the source-drain electrodes Ts and Td.

[0101] For example, Fig.14As shown, the display area AA further includes a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD. The first gate insulating layer GI1 is disposed on a side of the gate electrode Tg and the first capacitor electrode C1 close to the substrate 101 and on a side of the active layer Ta away from the substrate 101, the second gate insulating layer GI2 is disposed on a side of the gate electrode Tg and the first capacitor electrode C1 away from the substrate 101, and the interlayer insulating layer ILD is disposed on a side of the second capacitor electrode C2 away from the substrate 101.

[0102] For example, the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and the materials of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may be the same or different.

[0103] For example, the first insulating layer 1021 is disposed at the same layer as at least one of the first gate insulating layer GI1 , the second gate insulating layer GI2 , and the interlayer insulating layer ILD.

[0104] That is, when the first insulating layer 1021 has only one layer, the first insulating layer 1021 is arranged on the same layer as the first gate insulating layer GI1, the second gate insulating layer GI2 or the interlayer insulating layer ILD; when the first insulating layer 1021 has two sub-layers, the two sub-layers are respectively arranged on the same layer as two of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD; when the first insulating layer 1021 has three sub-layers, the three sub-layers are respectively arranged on the same layer as the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD.

[0105] For example, Fig.14 As shown, the display area A further includes a planarization layer PLN, which is disposed on the side of the source and drain electrodes Ts and Td away from the base substrate 101 to provide a substantially flat surface on the pixel driving circuit. For example, the planarization layer PLN may be made of an organic insulating material such as polyimide or resin.

[0106] For example, in some embodiments, the first pattern layer 1022 is disposed on the same layer as the planarization layer PLN.

[0107] Alternatively, in other embodiments, the first pattern layer 1022 may not be provided on the same layer as the planarization layer PLN, but may be an insulating layer formed separately after the functional layers of the display substrate are formed. In this case, the insulating layer may be made of organic insulating material or inorganic insulating material.

[0108] For example, for Figure 15-17 Display substrate, other structures and references in the embodiments Figure 4-Figure 8 Embodiments and Figure 9-12The embodiments of the present invention will not be described in detail here.

[0109] For example, in an embodiment of the present disclosure, the base substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0110] For example, the material of the active layer Ta includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.). During the preparation process, part of the semiconductor material of the active layer 121 is conductorized to have good conductivity.

[0111] For example, the gate Tg and the source-drain electrodes Td and Ts may be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc. For example, the gate Tg and the source-drain electrodes Td and Ts may be a single-layer or multi-layer structure, such as a multi-layer metal structure such as Ti / Al / Ti or Mo / Al / Mo.

[0112] For example, the first electrode E1 of the light-emitting device EL can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or a stack of transparent metal oxides and metals (such as silver), and the material of the second electrode E2 can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0113] For example, the pixel definition layer PDL may be made of organic materials, such as polyimide, resin, etc.

[0114] The embodiments of the present disclosure do not specifically limit the materials of each functional layer on the display substrate.

[0115] For example, Fig.14 The thin film transistor T shown in the figure is a top gate type, and the gate Tg is arranged on the side of the active layer Ta close to the base substrate 101. For example, in other embodiments, the thin film transistor TFT may also be a bottom gate type, and the gate Tg is arranged on the side of the active layer Ta away from the base substrate 101. The embodiments disclosed in this disclosure do not limit the specific form of the thin film transistor T.

[0116] For example, in the preparation process of the above display substrate, Figure 4-Figure 8 Taking the display substrate in the embodiment of as an example, Fig.18FIG. 1 shows a partial plan view of the display substrate during the preparation process. For the sake of clarity, Fig.18 The metal material R is not shown.

[0117] In some embodiments, the display substrate may be formed by using a motherboard, a structure of multiple display substrates may be formed on the motherboard, and then individual display substrates may be formed by cutting. Fig.18 FIG. 4 shows a case where at least a portion of the edge (the upper edge in the figure) of the display substrate has not been cut. Fig.18 As shown, multiple insulating patterns 1022A and multiple cutouts 1022B extend in a direction away from the display area AA, and a cutting line CL passes through multiple insulating patterns 1022A and multiple cutouts 1022B. After the motherboard is cut along the cutting line CL, the insulating patterns 1022A and the cutouts 1022B below the cutting line CL remain on the display substrate, while the insulating patterns 1022A and the cutouts 1022B above the cutting line CL are cut and removed and will not remain on the finally formed display substrate. Therefore, the insulating patterns 1022A and the cutouts 1022B remain at the edge of the display substrate, that is, located at the outermost side of the display substrate.

[0118] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure. For example, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The embodiment of the present disclosure does not limit the specific form of the display device.

[0119] There are a few points to note:

[0120] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0121] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0122] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0123] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: Substrate substrate, a first functional layer, comprising a first insulating layer and a first pattern layer, disposed on the substrate and located in the peripheral region, wherein the first insulating layer comprises a material removal region disposed along at least a portion of an edge of the substrate, wherein the material of the first insulating layer is removed in the material removal region, and the first pattern layer comprises a plurality of insulating patterns disposed in the material removal region and spaced apart along at least a portion of the edge, and gaps respectively located between adjacent insulating patterns in the plurality of insulating patterns, and A first metal layer is disposed on a side of the first insulating layer away from the substrate and located in the peripheral area, wherein the first metal layer includes a plurality of first contact pads disposed at intervals, Wherein, at least parts of the plurality of first contact pads extend toward the plurality of gaps or toward the plurality of insulation patterns respectively. 2 . The display substrate according to claim 1 , further comprising a metal material disposed in at least a portion of the plurality of notches.

3. The display substrate according to claim 2, wherein: The metal material is the same as that of the first metal layer.

4. The display substrate according to any one of claims 1 to 3, wherein: The first insulating layer and the first pattern layer are made of the same material, and the first insulating layer is integrally connected to the plurality of insulating patterns.

5. The display substrate according to any one of claims 1 to 3, wherein: The plurality of first contact pads are located on a side of the material removal area close to the display area.

6. The display substrate according to any one of claims 1 to 3, wherein: An extension direction of the plurality of first contact pads is substantially perpendicular to the at least partial edge.

7. The display substrate according to any one of claims 1 to 3, further comprising: A circuit board comprising a plurality of second contact pads, Wherein, when the plurality of first contact pads extend toward the plurality of notches respectively, the plurality of second contact pads are respectively located on a side of the plurality of notches away from the base substrate and are connected to the plurality of first contact pads correspondingly; In a case where the plurality of first contact pads extend respectively toward the plurality of insulating patterns, the plurality of second contact pads are respectively located at a side of the plurality of insulating patterns away from the base substrate and are correspondingly connected to the plurality of first contact pads.

8. The display substrate according to any one of claims 1 to 3, wherein: At least a portion of the edge of the base substrate includes an edge of a first side of the base substrate or edges of opposite first and second sides of the base substrate.

9. The display substrate according to any one of claims 1 to 3, further comprising: A plurality of pixel driving circuits are arranged on the substrate and in the display area, wherein each of the plurality of pixel driving circuits comprises a thin film transistor and a storage capacitor, The thin film transistor includes a gate and a source-drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the gate is arranged in the same layer as the first capacitor electrode, the second capacitor electrode is arranged on a side of the first capacitor electrode away from the base substrate, and the source-drain electrode is arranged on a side of the second capacitor electrode away from the base substrate.

10. The display substrate according to claim 9, wherein: The first metal layer is arranged in the same layer as the source and drain electrodes.

11. The display substrate according to claim 9, wherein: The display area also includes: A first gate insulating layer is provided on a side of the gate electrode and the first capacitor electrode close to the substrate. a second gate insulating layer, disposed on a side of the gate electrode and the first capacitor electrode away from the substrate, and an interlayer insulating layer, arranged on a side of the second capacitor electrode away from the base substrate, The first insulating layer is disposed in the same layer as at least one of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.

12. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: Substrate substrate, a first functional layer, comprising a first insulating layer and a first pattern layer, disposed on the substrate and located in the peripheral region, wherein the first insulating layer comprises a material removal region disposed along at least a portion of an edge of the substrate, in which material of the first insulating layer is removed, and the first pattern layer is disposed in the material removal region, and A first metal layer is disposed on a side of the first insulating layer away from the substrate and located in the peripheral area, wherein the first metal layer includes a plurality of first contact pads disposed at intervals, Wherein, the first pattern layer is covered with metal material.

13. The display substrate according to claim 12, wherein: The metal material is the same as that of the first metal layer.

14. The display substrate according to claim 12 or 13, wherein: The first insulating layer includes an inorganic insulating material, and the first pattern layer includes an organic insulating material.

15. The display substrate according to claim 12 or 13, further comprising: A circuit board comprising a plurality of second contact pads, The plurality of second contact pads are respectively located on a side of the first pattern layer away from the base substrate and are correspondingly connected to the plurality of first contact pads.

16. The display substrate according to claim 12 or 13, further comprising: A plurality of pixel driving circuits are arranged on the substrate and in the display area, wherein each of the plurality of pixel driving circuits comprises a thin film transistor and a storage capacitor, The thin film transistor includes a gate and a source-drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the gate is arranged in the same layer as the first capacitor electrode, the second capacitor electrode is arranged on a side of the first capacitor electrode away from the base substrate, and the source-drain electrode is arranged on a side of the second capacitor electrode away from the base substrate.

17. The display substrate according to claim 16, wherein: The first metal layer is arranged in the same layer as the source and drain electrodes.

18. The display substrate according to claim 16, wherein: The display area also includes: A first gate insulating layer is provided on a side of the gate electrode and the first capacitor electrode close to the substrate. a second gate insulating layer, disposed on a side of the gate electrode and the first capacitor electrode away from the substrate, and an interlayer insulating layer, arranged on a side of the second capacitor electrode away from the base substrate, The first insulating layer is disposed in the same layer as at least one of the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer.

19. The display substrate according to claim 16, wherein: The display area also includes: a planarization layer, arranged on a side of the source and drain electrodes away from the substrate, Wherein, the first pattern layer and the planarization layer are arranged on the same layer.

20. A display device, comprising the display substrate according to any one of claims 1 to 11 or the display substrate according to any one of claims 12 to 19.

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