Display substrate and display device

Abstract

The utility model provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a substrate which comprises a display area and a peripheral area surrounding the display area, and the peripheral area comprises a binding area located on one side of the display area; the plurality of sub-pixels are located on one side of the substrate and located in the display area; the data lines are located in the display area and extend to the binding area, and the data lines are electrically connected with the sub-pixels and configured to provide data signals for the sub-pixels; the plurality of first contact pads are positioned in the binding area and are connected with the plurality of data lines; the multiple second contact pads are located in the binding area and located on the sides, away from the display area, of the multiple first contact pads, and the multiple first contact pads and the multiple second contact pads are configured to be bound with the driving chip; the plurality of virtual wires are located on the sides, close to the display area, of the plurality of first contact pads and located on at least one side of the plurality of data lines in the first direction. The display effect can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices have been listed as a next-generation display technology with great development prospects due to their advantages such as thinness, lightness, wide viewing angle, active luminescence, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high luminous efficiency and flexible display. Utility Model Content

[0003] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device, which can improve the display effect of the display device.

[0004] To solve the above technical problems, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display substrate is provided, comprising:

[0006] a substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located on one side of the display area;

[0007] a plurality of sub-pixels, located on one side of the substrate and in the display area;

[0008] a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0009] a plurality of first contact pads located in the binding area and connected to the plurality of data lines;

[0010] a plurality of second contact pads located in the binding area and on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driver chip;

[0011] A plurality of dummy wirings are located on a side of the plurality of first contact pads close to the display area and are located on at least one side of the plurality of data lines along a first direction.

[0012] In some embodiments, the multiple data lines include a first group of data lines and a second group of data lines arranged along the first direction, the multiple virtual lines are located on at least one side of the first group of data lines along the first direction, and / or the multiple virtual lines are located on at least one side of the second group of data lines along the first direction.

[0013] In some embodiments, the plurality of virtual lines are located on both sides of the first group of data lines along the first direction, and on both sides of the second group of data lines.

[0014] In some embodiments, the display substrate further includes virtual data lines, which are located on both sides of the first group of data lines along the first direction and on both sides of the second group of data lines, and are arranged in one-to-one correspondence with the multiple virtual lines along the second direction, and the second direction intersects with the first direction.

[0015] In some embodiments, the plurality of first contact pads include a first group of contact pads and a second group of contact pads, the first group of contact pads and the second group of contact pads are arranged along the first direction, the first group of data lines are connected to the first group of contact pads, and the second group of data lines are connected to the second group of contact pads.

[0016] In some embodiments, the connection between the dummy trace and the first contact pad is disconnected.

[0017] In some embodiments, an extension direction of the virtual routing line located between the first group of data lines and the second group of data lines is parallel to an extension direction of at least part of the data lines.

[0018] In some embodiments, the virtual line between the first group of data lines and the second group of data lines is parallel to the first direction.

[0019] In some embodiments, the virtual lines located between the first group of data lines and the second group of data lines are in a block shape and are arranged in an array between the first group of data lines and the second group of data lines.

[0020] In some embodiments, the dummy trace extends between the first contact pads.

[0021] In some embodiments, the display substrate includes a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer, a first source-drain metal layer, a third insulating layer, a second source-drain metal layer, and a fourth insulating layer sequentially located on the substrate;

[0022] The data lines and the dummy lines are both made of the first gate metal layer.

[0023] In some embodiments, the display substrate further includes:

[0024] a binding region interlayer insulating layer located in the binding region and between the plurality of first contact pads and the data line;

[0025] a first gate insulating layer in the binding region, located in the binding region and on a side of the interlayer insulating layer in the binding region close to the substrate; and

[0026] a second gate insulating layer in the binding region, located in the binding region, between the first gate insulating layer in the binding region and the interlayer insulating layer in the binding region, and stacked with the interlayer insulating layer in the binding region;

[0027] The second gate insulation layer in the binding area includes a first contact pad via, the interlayer insulation layer in the binding area includes a second contact pad via, and at least one of the multiple data lines is electrically connected to the first contact pad through the first contact pad via and the second contact pad via.

[0028] In some embodiments, the display substrate further includes a third insulating layer in the binding area.

[0029] The third insulating layer of the binding region is located in the binding region and is arranged on a side of the first contact pad away from the substrate to cover the first contact pad.

[0030] The third insulating layer in the bonding region has a third contact pad via hole to expose the surface of the first contact pad.

[0031] In some embodiments, the display substrate further includes an auxiliary conductive layer.

[0032] The auxiliary conductive layer is located in the binding area and is arranged on a side of the third insulating layer in the binding area away from the substrate.

[0033] The auxiliary conductive layer includes a second switching electrode pattern located in the binding area,

[0034] The second transfer electrode pattern is electrically connected to the first contact pad through the third contact pad via.

[0035] An embodiment of the present disclosure further provides a display device including the display substrate described above.

[0036] The embodiments of the present disclosure have the following beneficial effects:

[0037] In the above scheme, a virtual routing line is set on the side of the multiple first contact pads close to the display area, and the virtual routing line is located on at least one side of the data line. The virtual routing line can make the stress in the edge area of the data line and the stress in the center area of the data line uniform, so that the heat dissipation in the edge area of the data line and the heat dissipation in the center area of the data line are uniform, avoiding deformation of the display substrate in the area where the multiple contact pads are located, and avoiding cracks or peeling of the local film layer, thereby improving the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1A This is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0039] Figure 1B is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0040] Figure 2 This is a partial schematic diagram of a first signal access area according to an embodiment of the present disclosure;

[0041] Figure 3 for Figure 2 Detailed enlarged view of the middle region S;

[0042] Figure 4 for Figure 1A The schematic cross-sectional view of the display area of the display substrate taken along line aa' is shown;

[0043] Figure 5 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S1 region;

[0044] Figure 6 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S2 region;

[0045] Figure 7 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S3 region;

[0046] Figure 8 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S4 region;

[0047] Figure 9 A partial schematic diagram of a peripheral area of a display substrate;

[0048] Figure 10 A partial schematic diagram showing a peripheral area of a substrate according to an embodiment of the present disclosure;

[0049] Figure 11 A partial schematic diagram showing a peripheral area of a substrate according to another embodiment of the present disclosure;

[0050] Figure 12 A partial schematic diagram showing a peripheral area of a substrate according to another embodiment of the present disclosure;

[0051] Figure 13 A partial schematic diagram showing a peripheral area of a substrate according to another embodiment of the present disclosure;

[0052] Figure 14 A partial schematic diagram showing a peripheral area of a substrate according to another embodiment of the present disclosure;

[0053] Figure 15 FIG. 1 is a schematic cross-sectional view of a contact pad according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0055] It will be understood that the various figures in the embodiments of the present disclosure are only used to schematically illustrate the connection relationship between the various components. The sizes of the various components in the figures are not drawn to scale, and their relative positions do not necessarily correspond completely to the actual positions.

[0056] In this disclosure, unless otherwise specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood according to the specific circumstances.

[0057] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0058] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0059] The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be performed by any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be performed by any one or more selected from spray coating and spin coating, and etching can be performed by any one or more selected from dry etching and wet etching. "Thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" still requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0060] Figure 1A A schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1B FIG. 4 is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1A and Figure 1B All shown are planar schematic diagrams of display substrates before the bending process is performed.

[0061] In some examples, such as Figure 1A and Figure 1B As shown, the display substrate may include: a display area AA, and a peripheral area BB surrounding the periphery of the display area AA. For example, the peripheral area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on the other side of the display area AA (for example, may include a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display panel, the second border area B2 may be, for example, the top border of the display panel, the third border area B3 may be, for example, the left border of the display panel, and the fourth border area B4 may be, for example, the right border of the display panel.

[0062] In some examples, such as Figure 1A and Figure 1B As shown, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX can be configured to display dynamic images or still images. The display area AA can be referred to as an active area. In some examples, the display area AA can be a rectangle. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as a circle or an ellipse. In some examples, the display panel can be a flexible panel, and thus the display panel can be deformable, such as curling, bending, folding, or rolling up.

[0063] In some examples, such as Figure 1A and Figure 1BAs shown, the display area AA may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be provided in each sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light-emitting control signal, or may include a scan signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0064] In some examples, such as Figure 1A and Figure 1B As shown, the first direction X may be the extending direction of the gate lines GL in the display area AA (e.g., the row direction), and the second direction Y may be the extending direction of the data lines DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0065] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0066] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0067] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit (e.g., Figure 1A Please note that for simplicity, Figure 1A(The light-emitting element L is shown only in one sub-pixel PX, which does not limit the present disclosure). The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0068] In some examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, that is, LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0069] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0070] In some examples, the display substrate may be integrated with a touch structure. The display substrate may include: an organic light-emitting diode display structure, or a plasma display structure, or an electrophoretic display structure. For example, the display substrate may include an OLED display structure and a touch structure. The touch structure may be provided on the encapsulation layer of the display structure to form a touch structure on thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure. The display structure and the touch structure are integrated together, which has the advantages of being light, thin, and foldable, and can meet product requirements such as flexible folding and narrow bezels.

[0071] In some examples, the structure of the touch structure on the thin film package mainly includes a flexible multi-layer covering surface type (Flexible Multi-Layer On Cell, referred to as FMLOC) structure and a flexible single-layer covering surface type (Flexible Single-Layer On Cell, referred to as FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0072] Figure 4 for Figure 1A FIG. 1 is a schematic cross-sectional view of a display substrate in a display area taken along line aa′. Figure 4 The structure of a sub-pixel in the display area is used as an example for illustration. In this example, the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, the multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example uses the display panel integrated with a mutual capacitance touch structure to form an FMLOC structure as an example for illustration.

[0073] In some examples, such as Figure 4As shown, in a direction perpendicular to the display panel, the display area of the display panel may include: a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially arranged on the substrate 100. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least: light-emitting elements for multiple sub-pixels.

[0074] In some examples, Figure 4 The following example illustrates a thin film transistor 21 and a capacitor 22 included in each sub-pixel. In some examples, the circuit structure layer 20 in the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 may be provided between the second gate metal layer and the first source / drain metal layer, a passivation layer 204 and a first planarizing layer 205 may be provided between the first source / drain metal layer and the second source / drain metal layer, a second planarizing layer 206 may be provided between the second source / drain metal layer and the third source / drain metal layer, and a third planarizing layer 207 may be provided on the side of the third source / drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, and the first planarizing layer 205, the second planarizing layer 206, and the third planarizing layer 207 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer close to the substrate, and the buffer layer may prevent harmful substances in the substrate from invading the interior of the display substrate, and may also increase the adhesion of the film layer in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer close to the substrate, and the bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to prevent external light from affecting the performance of the thin film transistor. In other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only a first flat layer may be provided between the first source-drain metal layer and the second source-drain metal layer.

[0075] In some examples, such as Figure 4 As shown, the semiconductor layer in the display area may include at least the active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin film transistor 21 and the first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 100 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer may include at least the second plate 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap, for example, they may coincide. The first source and drain metal layer may include at least the source 211 and drain 212 of the thin film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via provided in the passivation layer 204 and the first planar layer 205. The third source-drain metal layer can include at least a second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through a fourth pixel via provided in the second planar layer 206. The first transfer electrode 231 can be electrically connected to the first electrode 301 (e.g., an anode) of the light-emitting element through a fifth pixel via provided in the third planar layer 207. In this example, electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transfer electrode 231 and the second transfer electrode 232.

[0076] In some examples, the gate lines of the display area may be located in the first gate metal layer or the second gate metal layer, the data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, and the high-potential power lines of the display area may be located in at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited to this. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging a large number of traces within a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0077] In some examples, such as Figure 4 As shown, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the third planar layer 207 and electrically connected to the second transfer electrode 232 through a fifth pixel via provided in the third planar layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 207. The pixel definition layer 304 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on and connected to the organic light-emitting layer 302. Driven by the first electrode 301 and the second electrode 303, the organic light-emitting layer 302 may emit light of a corresponding color. An isolation column layer may be further provided on a side of the pixel definition layer 304 away from the substrate 100 . The isolation column layer may include a plurality of isolation columns (PS).

[0078] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0079] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0080] In some examples, such as Figure 4 As shown, in a direction perpendicular to the substrate, the encapsulation structure layer 40 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 402 may be made of an organic material and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of an organic material, for example, a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to flatten the surface of the display panel and relieve stress in the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other absorbent material to absorb intruding water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0081] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0082] In some examples, such as Figure 4As shown, in a direction perpendicular to the substrate, the touch structure layer 50 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, which are arranged in sequence. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integrated structure connected to each other. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an interconnected integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0083] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0084] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0085] In some examples, such as Figure 4As shown, in a direction perpendicular to the substrate, the color filter layer (Color filter On Encapsulation, COE) 60 may include: an insulating layer 601, a color filter layer and an OC film (overcoat) 602 arranged in sequence, wherein the color filter layer includes a black matrix 610 and a color filter unit 611 arranged between the black matrix 610, and the color filter unit 611 may be, for example, a red filter unit, a green filter unit or a blue filter unit.

[0086] In some examples, such as Figure 1A As shown, the first border area B1 of the display panel may include: a fan-out wiring area B11 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1A In the figure, only a number of lines in the first frame area are shown for illustration. This example does not limit the number of lines in the first frame area.

[0087] In some examples, such as Figure 1A As shown, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can be provided with at least a plurality of data fan-out lines 42. The plurality of data fan-out lines 42 can be electrically connected to the plurality of data lines DL in the display area AA. For example, the plurality of data fan-out lines 42 and the plurality of data lines DL can be electrically connected one-to-one. The plurality of data fan-out lines 42 can extend to the signal access area B12 in a fan-out routing manner. The plurality of data fan-out lines 42 and the plurality of data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias opened in the insulating layer.

[0088] In some examples, such as Figure 1A As shown, the signal access area B12 may include at least one first signal access area B121. This example uses one first signal access area as an example for illustration and explanation. In other examples, the display panel is a large-size panel, and the display panel may include multiple first signal access areas, and the multiple first signal access areas may be arranged sequentially along the first direction X.

[0089] In some examples, such as Figure 1AAs shown, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 can be provided with a plurality of contact pads 31, and the plurality of contact pads 31 can be configured to be bound and connected to at least one driver chip. The driver chip can be configured to generate a driving signal required for driving the sub-pixel and provide the driving signal to the data line DL of the display area AA. For example, the driving signal can be a data signal for driving the sub-pixel. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the driver chip can also include hardware circuits and computer executable code, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit can also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0090] In some examples, such as Figure 1A As shown, the signal access area B12 can be provided with at least a plurality of data lines 101, and the plurality of data lines 101 can be electrically connected to the plurality of data fan-out lines 42 of the fan-out routing area B11, for example, in a one-to-one electrical connection. For example, the data line 101 and the connected data fan-out line 42 can be an integrated structure connected to each other. That is, the plurality of data lines 101 are electrically connected to the plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one electrical connection. The plurality of data lines 101 can extend into the first signal access area B121 and be electrically connected to the plurality of contact pads 31 in the first signal access area B121. For example, the plurality of data lines 101 can be electrically connected to the plurality of contact pads 31 in a one-to-one electrical connection, or one data line 101 can be electrically connected to at least one contact pad 31. The data lines 101 and the data fan-out lines 42 can transmit the data signals provided by the driver chip to the data lines DL in the display area.

[0091] In some examples, such as Figure 1B As shown, the first frame area B1 of the display substrate may include: a fan-out routing area B11, a bending area B13 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1B In the figure, only a number of lines in the first frame area are shown for illustration. This example does not limit the number of lines in the first frame area.

[0092] In some examples, such as Figure 1BAs shown, the bending area B13 can be connected between the fan-out routing area B11 and the signal access area B12, and can be configured to bend the signal access area B12 to the back of the display area AA. The bending area B13 can be provided with at least a plurality of data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out routing area B11, and the other end can be connected to the data line 101 in the signal access area B12. The multiple data bending connection lines 43 can be a same-layer structure, for example, located in the first source and drain metal layer or the second source and drain metal layer. The remaining structure of the first border area B1 of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0093] like Figure 1A and Figure 1B As shown, the signal access area B12 may also include a second signal access area B122. Multiple contact pads 32 are provided in the second signal access area B122 for bonding to the flexible printed circuit board. The contact pads described below in this disclosure refer to the contact pads 31 in the first signal access area B121, which are used to bond to at least one driver chip.

[0094] Figure 2 FIG is a partial enlarged view of the first signal access area of the embodiment of the present disclosure. In some examples, such as Figure 2 As shown, the multiple contact pads 31 of the first signal access area B121 can be arranged in multiple rows (for example, four rows). The multiple contact pads 31 included in each row can be arranged sequentially along the first direction X, and the multiple rows of contact pads 31 can be arranged sequentially along the second direction Y. The contact pads 31 of two adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the multiple contact pads of the first signal access area B121 can be arranged in a row.

[0095] In some examples, the plurality of contact pads 31 of the first signal access area may be divided into at least a plurality of groups (eg, two groups). Figure 2Two groups of contact pads (e.g., a first group of contact pads 31A and a second group of contact pads 31B, where the first group of contact pads 31A includes multiple first contact pads 311 and the second group of contact pads 31B includes multiple second contact pads 312) are used as an example for illustration and description. The second group of contact pads 31B can be located on a side of the first group of contact pads 31A away from the display area. The first group of contact pads 31A can include three rows of multiple first contact pads 311 arranged along the first direction X. The second group of contact pads 31B can include a row of multiple second contact pads 312 arranged along the first direction X. In some examples, the second group of contact pads 31B is used to input signals, which are converted by the bound IC and then output to the first group of contact pads 31A. The first group of contact pads 31A then transmits the signals (e.g., data signals) to multiple sub-pixels PX via multiple signal lines (e.g., multiple data lines DL). The first group of contact pads 31A and the second group of contact pads 31B can be staggered in the first direction X. For example, the contact pads within the first group of contact pads 31A and the second group of contact pads 31B may not be aligned in the second direction Y. There may be spaces between adjacent contact pads within the same group, and there may be spaces between contact pads in adjacent groups. In some embodiments, a group of contact pads may be one row of contact pads, two rows of contact pads, or three rows of contact pads. The present disclosure does not limit the number of rows of contact pads or the number of contact pads in each row.

[0096] Figure 3 for Figure 2 Detailed enlarged view of region S. In some examples, such as Figure 3 As shown, a plurality of data lines 101 may extend substantially along the second direction Y between the plurality of contact pads 31. For example, two data lines 101 may be provided between two adjacent contact pads 31 of a group of contact pads. One data line 101 may be electrically connected to at least one contact pad 31, for example, one data line 101 may be connected to one contact pad 31.

[0097] When the driver chip is bonded to the lower frame of the display substrate, the display substrate is affected by the bonding stress in the bonding area of the driver chip and is prone to deformation. When the deformation is severe, it may cause cracks in the local film layer of the driver chip or cause the film layer to peel, thereby affecting the reliability and stability of the display product.

[0098] An embodiment of the present disclosure provides a display substrate, comprising:

[0099] a substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located on one side of the display area;

[0100] a plurality of sub-pixels, located on one side of the substrate and in the display area;

[0101] a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0102] a plurality of first contact pads, located in the binding area and connected to the plurality of data lines;

[0103] a plurality of second contact pads located in the binding area and on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driver chip;

[0104] A plurality of dummy wirings are located on a side of the plurality of first contact pads close to the display area and are located on at least one side of the plurality of data lines along a first direction.

[0105] In this embodiment, a dummy line is provided on one side of the plurality of first contact pads close to the display area, and the dummy line is located on at least one side of the data line. The dummy line can make the stress in the edge area of the data line and the stress in the center area of the data line uniform, and the heat dissipation in the edge area of the data line and the heat dissipation in the center area of the data line uniform, thereby avoiding deformation of the display substrate in the area where the plurality of contact pads are located, and avoiding cracks or peeling of the local film layer, thereby improving the display effect of the display device.

[0106] Figure 5 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S1 region; Figure 6 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S2 region; Figure 7 for Figure 1A and Figure 1B Enlarged schematic diagram of the middle S3 region; Figure 8 for Figure 1A and Figure 1B Schematic diagram of the magnified S4 region.

[0107] like Figure 5-Figure 8 As shown, a plurality of first contact pads 311 are arranged along the first direction, a plurality of second contact pads 312 are arranged along the first direction, and the data lines 101 are connected to the first contact pads 311 .

[0108] The multiple data lines include a first group of data lines A1 and a second group of data lines A2 arranged along the first direction, and the multiple first contact pads 311 include a first group of contact pads E1 and a second group of contact pads E2 arranged along the first direction, the first group of contact pads E1 and the second group of contact pads E2 are arranged along the first direction, the first group of data lines A1 is connected to the first group of contact pads E1, and the second group of data lines A2 is connected to the second group of contact pads E2.

[0109] If the first group of data lines A1 is far away from the second group of data lines A2, the area C1 between the first group of data lines A1 and the gate drive circuit lead 411, that is, the edge area of the first group of data lines A1, is not provided with data lines, which will lead to different routing density between the area C1 and the area where the first group of data lines A1 are located, resulting in uneven stress and heat dissipation, and the data lines are likely to fall off. Figure 5 As shown, in this embodiment, a plurality of virtual routing lines 313 can be set in the direction in which the first group of data lines A1 is away from the second group of data lines A2. The plurality of virtual routing lines 313 are located along the first direction on the side of the first group of data lines A1 away from the second group of data lines A2, that is, in the area C1; this can uniformly distribute the heat dissipation and stress in the area C1 and the area where the first group of data lines A1 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, and further avoid cracks or peeling of the local film layer, thereby improving the display effect of the display device.

[0110] In some embodiments, a virtual data line 314 is further provided in region C1, and the virtual data line 314 is provided in a one-to-one correspondence with the multiple virtual lines 313 along the second direction. The multiple virtual data lines 314 are located on the side of the first group of data lines A1 away from the second group of data lines A2 along the first direction. This can further even out the heat dissipation and stress in region C1 and the area where the first group of data lines A1 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, and further avoid cracks or peeling of the local film layer, thereby improving the display effect of the display device.

[0111] like Figure 6 As shown, in this embodiment, a plurality of virtual routing lines 313 can be set in the direction where the first group of data lines A1 is close to the second group of data lines A2. The plurality of virtual routing lines 313 are located along the first direction on the side of the first group of data lines A1 close to the second group of data lines A2, that is, in the area C2; this can uniformly distribute the heat and stress in the area C2 and the area where the first group of data lines A1 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, avoid cracks in the local film layer or film peeling, thereby improving the display effect of the display device.

[0112] In some embodiments, a virtual data line 314 is further provided in region C2, and the virtual data line 314 is provided in a one-to-one correspondence with the multiple virtual lines 313 along the second direction. The multiple virtual data lines 314 are located on the side of the first group of data lines A1 close to the second group of data lines A2 along the first direction. This can further even out the heat dissipation and stress in the region C2 and the region where the first group of data lines A1 are located, avoid deformation of the display substrate in the region where the multiple contact pads are located, and further avoid cracks or peeling of the local film layer, thereby improving the display effect of the display device.

[0113] like Figure 7 As shown, in this embodiment, a plurality of virtual routing lines 313 can be set in the direction where the second group of data lines A2 is close to the first group of data lines A1, and the plurality of virtual routing lines 313 are located along the first direction on the side of the second group of data lines A2 close to the first group of data lines A1, that is, in area C3; in this way, the heat dissipation and stress in area C3 and the area where the first group of data lines A1 are located can be uniformed, deformation of the display substrate in the area where the multiple contact pads are located can be avoided, cracks or peeling of the local film layer can be avoided, and the display effect of the display device can be improved.

[0114] In some embodiments, a virtual data line 314 is further provided in region C3, and the virtual data line 314 is provided in a one-to-one correspondence with the multiple virtual lines 313 along the second direction. The multiple virtual data lines 314 are located on the side of the second group of data lines A2 close to the first group of data lines A1 along the first direction. This can further even out the heat dissipation and stress in the region C3 and the area where the second group of data lines A2 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, and further avoid cracks or peeling of the local film layer, thereby improving the display effect of the display device.

[0115] like Figure 8 As shown, in this embodiment, a plurality of virtual routing lines 313 can be set in the direction in which the second group of data lines A2 is away from the first group of data lines A1. The plurality of virtual routing lines 313 are located along the first direction on the side of the second group of data lines A2 away from the first group of data lines A1, that is, in area C4; this can uniformly distribute heat dissipation and stress in area C4 and the area where the first group of data lines A1 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, avoid cracks in the local film layer or film peeling, thereby improving the display effect of the display device.

[0116] In some embodiments, a virtual data line 314 is further provided in region C4, and the virtual data line 314 is provided in a one-to-one correspondence with the multiple virtual lines 313 along the second direction. The multiple virtual data lines 314 are located on the side of the second group of data lines A2 away from the first group of data lines A1 along the first direction. This can further even out the heat dissipation and stress in the region C4 and the area where the second group of data lines A2 are located, avoid deformation of the display substrate in the area where the multiple contact pads are located, avoid cracks or peeling of the local film layer, and thus improve the display effect of the display device.

[0117] In this embodiment, the dummy trace 313 is only used to make stress and heat dissipation in different areas uniform. The dummy trace 313 is not used to transmit signals. Therefore, the connection between the dummy trace 313 and the first contact pad 311 is disconnected.

[0118] In this embodiment, the virtual data line 314 is only used to make the stress and heat dissipation of different areas uniform. The virtual data line 314 is not used to transmit signals. Therefore, the connection between the virtual trace 313 and the virtual data line 314 is disconnected.

[0119] In this embodiment, the virtual line 313 may be in a straight line shape or other shapes; the extension direction of the virtual line 313 may be parallel to the extension direction of the data line 101 or other directions.

[0120] Take area S2 and area S3 as an example. Figure 9 As shown, the data line 101 extends from the fan-out routing area B11 to the first signal access area B121 and connects to the first contact pad 311. No data line 101 is provided in the area S2 and the area S3 between the first group of data lines A1 and the second group of data lines A2.

[0121] In some embodiments, such as Figure 10 As shown, a dummy trace 313 is provided between the first group of data lines A1 and the second group of data lines A2. The dummy trace 313 is straight and extends between adjacent first contact pads 311. The data line 101 includes a portion perpendicular to the first direction, and the dummy trace 313 is parallel to this portion of the data line. In this embodiment, the dummy trace 313 can be provided at portions of regions S2 and S3, or at all locations of regions S2 and S3. The distribution density of the dummy trace 313 can be substantially the same as that of the data line 101. The dummy trace 313 can be provided in the same layer and material as the data line 101. In this way, the dummy trace 313 can be formed using the same patterning process as the data line 101, eliminating the need for a dedicated patterning process to form the dummy trace 313, thereby simplifying the manufacturing process of the display substrate. In this embodiment, virtual routing lines 313 are set in areas S2 and S3. The virtual routing lines 313 can evenly distribute the heat dissipation and stress in areas S2, S3 and the area where the data lines 101 are located, thereby preventing the display substrate from being deformed in areas S2 and S3, and further preventing the data lines in the first group of data lines A1 near area S2 from being peeled off and the data lines in the second group of data lines A2 near area S3 from being peeled off, thereby improving the display effect of the display device.

[0122] In some embodiments, such as Figure 11As shown, a dummy trace 313 is provided between the first group of data lines A1 and the second group of data lines A2. The dummy trace 313 is straight and extends between adjacent first contact pads 311. The dummy trace 313 is parallel to the extension direction of the data line 101. To avoid electrical connection between the dummy trace 313 and the first contact pad 311, the dummy trace 313 is discontinuous. In this embodiment, the dummy trace 313 can be provided at portions of regions S2 and S3, or at all locations in regions S2 and S3. The distribution density of the dummy trace 313 can be substantially the same as that of the data line 101. The dummy trace 313 can be provided in the same layer and material as the data line 101. In this way, the dummy trace 313 can be formed using the same patterning process as the data line 101, eliminating the need for a dedicated patterning process to form the dummy trace 313, thereby simplifying the manufacturing process of the display substrate. In this embodiment, virtual routing lines 313 are set in areas S2 and S3. The virtual routing lines 313 can evenly distribute the heat dissipation and stress in areas S2, S3 and the area where the data lines 101 are located, thereby preventing the display substrate from being deformed in areas S2 and S3, and further preventing the data lines in the first group of data lines A1 near area S2 from being peeled off and the data lines in the second group of data lines A2 near area S3 from being peeled off, thereby improving the display effect of the display device.

[0123] In some embodiments, such as Figure 12 As shown, a dummy trace 313 is provided between the first group of data lines A1 and the second group of data lines A2. The dummy trace 313 is linear. A first portion of the dummy trace 3131 extends between adjacent first contact pads 311. The first portion of the dummy trace 3131 is parallel to the extension direction of the data line 101. To prevent electrical connection between the first portion of the dummy trace 3131 and the first contact pad 311, the first portion of the dummy trace 3131 is discontinuous. The display substrate also includes a second portion of the dummy trace 3132 in an inverted V shape. The inverted V-shaped dummy trace 3132 is located between regions S2 and S3. In this embodiment, the distribution density of the dummy trace 313 can be approximately the same as that of the data line 101. The dummy trace 313 can be provided in the same layer and material as the data line 101. This allows the dummy trace 313 to be formed simultaneously with the data line 101 using the same patterning process, eliminating the need for a dedicated patterning process to create the dummy trace 313, thus simplifying the display substrate manufacturing process. In this embodiment, virtual routing lines 313 are set in areas S2 and S3. The virtual routing lines 313 can evenly distribute the heat dissipation and stress in areas S2, S3 and the area where the data lines 101 are located, thereby preventing the display substrate from being deformed in areas S2 and S3, and further preventing the data lines in the first group of data lines A1 near area S2 from being peeled off and the data lines in the second group of data lines A2 near area S3 from being peeled off, thereby improving the display effect of the display device.

[0124] In some embodiments, such as Figure 13 As shown, a virtual trace 313 is provided between the first group of data lines A1 and the second group of data lines A2. The virtual trace 313 is in a straight line. A first portion of the virtual trace 3131 extends between adjacent first contact pads 311. The first portion of the virtual trace 3131 is parallel to the extension direction of the data line 101. To avoid electrical connection between the first portion of the virtual trace 3131 and the first contact pad 311, the first portion of the virtual trace 3131 is discontinuous. In this embodiment, the display substrate also includes a third portion of virtual trace 3133 parallel to the first direction. The virtual trace 3133 is located between region S2 and region S3. The virtual trace 313 can be provided in the same layer and material as the data line 101. In this way, the virtual trace 313 can be formed using the same patterning process as the data line 101. There is no need to use a special patterning process to produce the virtual trace 313, which can simplify the manufacturing process of the display substrate. In this embodiment, virtual routing lines 313 are set in areas S2 and S3. The virtual routing lines 313 can evenly distribute the heat dissipation and stress in areas S2, S3 and the area where the data lines 101 are located, thereby preventing the display substrate from being deformed in areas S2 and S3, and further preventing the data lines in the first group of data lines A1 near area S2 from being peeled off and the data lines in the second group of data lines A2 near area S3 from being peeled off, thereby improving the display effect of the display device.

[0125] In some embodiments, such as Figure 14As shown, a virtual trace 313 is provided between the first group of data lines A1 and the second group of data lines A2; wherein the first portion of the virtual trace 3131 is in a straight line shape, and the first portion of the virtual trace 3131 extends between adjacent first contact pads 311. The first portion of the virtual trace 3131 is parallel to the extension direction of the data line 101. In order to avoid electrical connection between the first portion of the virtual trace 3131 and the first contact pad 311, the first portion of the virtual trace 3131 is discontinuous. In this embodiment, the display substrate also includes a fourth portion of virtual traces 3134, which is in a block shape and arranged in an array between area S2 and area S3. The virtual trace 313 can be provided in the same layer and material as the data line 101. In this way, the virtual trace 313 can be formed using the same patterning process as the data line 101. There is no need to use a special patterning process to produce the virtual trace 313, which can simplify the manufacturing process of the display substrate. In this embodiment, virtual routing lines 313 are set in areas S2 and S3. The virtual routing lines 313 can evenly distribute the heat dissipation and stress in areas S2, S3 and the area where the data lines 101 are located, thereby preventing the display substrate from being deformed in areas S2 and S3, and further preventing the data lines in the first group of data lines A1 near area S2 from being peeled off and the data lines in the second group of data lines A2 near area S3 from being peeled off, thereby improving the display effect of the display device.

[0126] In this embodiment, the contact pad 31 may adopt a multi-layer metal structure. Figure 15 As shown, the display substrate may include multiple leads 2220 and at least one group of contact pads. The at least one group of contact pads includes multiple contact pads 31. The display substrate includes a bonding region buffer layer 2241 located on the substrate 2000, and a bonding region first gate insulating layer 2242 located on a side of the bonding region buffer layer 2241 away from the substrate 2000. The multiple contact pads 31 are arranged in a single row or multiple rows. There are gaps between the multiple contact pads 31 in the same row, and there are also gaps between the multiple contact pads 31 in different rows.

[0127] The display substrate may further include a first insulating layer 2230 and a third insulating layer 2260 in the binding region, disposed on the binding region 2200. The first insulating layer 2230 covers at least a portion of the edges of the plurality of contact pads 31. The contact pads 31 include at least one contact pad metal layer, for example, multiple contact pad metal layers. In the illustrated example, the at least one contact pad metal layer of the contact pads 31 may include a first contact pad metal layer 2215 and a second contact pad metal layer 2217, with the second contact pad metal layer 2217 being stacked on the side of the first contact pad metal layer 2215 away from the substrate 2000. The third insulating layer 2260 in the binding region covers the first insulating layer 2230 and the plurality of contact pads 31. Therefore, during the display substrate manufacturing process, the first insulating layer can protect the edges of the contact pads, preventing the etching solution from etching the exposed edges of the contact pads, thereby improving the product yield and reliability of the display substrate.

[0128] like Figure 15 As shown, the display substrate may further include a second gate insulating layer 2243 in the bonding region and a bonding region interlayer insulating layer 2244. The bonding region interlayer insulating layer 2240 is located in the bonding region and between the plurality of contact pads 31, the first insulating layer 2230, and the substrate 2000. The second gate insulating layer 2243 in the bonding region is located between the first gate insulating layer 2242 in the bonding region and the bonding region interlayer insulating layer 2244, and is stacked with the bonding region interlayer insulating layer 2244. The second gate insulating layer 2243 in the bonding region includes a first contact pad via 2216, and the bonding region interlayer insulating layer 2244 includes a second contact pad via 2219. At least one of the data lines 101 is electrically connected to the contact pad 31 through the first contact pad via 2216 and the second contact pad via 2219.

[0129] in, Figure 4 The second touch conductive layer 512 and the second transfer electrode pattern 2270 are located in the same layer. Figure 4 The touch interlayer insulating layer 502 and the third insulating layer 2260 in the bonding area are located in the same layer. Figure 4 The first transfer electrode 231 and the second contact pad metal layer 2217 are located in the same layer. Figure 4 The drain electrode 212 and the first contact pad metal layer 2215 are located in the same layer. Figure 4 The gate 213 and the lead 2220 are located in the same layer. Figure 4 The interlayer insulating layer 203 in the bonding area is located in the same layer as the interlayer insulating layer 2244 in the bonding area. Figure 4 The second gate insulating layer 202 in the bonding region is located in the same layer as the second gate insulating layer 2243 in the bonding region.

[0130] For example, Figure 15As shown, the second contact pad metal layer 2217 is formed on the first contact pad metal layer 2215 and covers the edges of the first contact pad metal layer 2215 to prevent the first contact pad metal layer 2215 from being exposed and corroded by the etching solution in the subsequent patterning process. The first insulating layer 2230 covers at least a portion of the edge of the second contact pad metal layer 2217 of the contact pad 31. The height of the first insulating layer 2230 relative to the surface of the substrate 2000, that is, the vertical distance from the surface of the first insulating layer 2230 to the surface of the substrate 2000, is no greater than the distance from the surface of the second contact pad metal layer 2217 to the surface of the substrate 2000 of the contact pad 31. Limiting the height of the first insulating layer 2230, that is, the thickness of the first insulating layer 2230, can improve poor contact in the bonding area and increase product yield. In addition, the second contact pad metal layer 2217 directly covers the edge of the first contact pad metal layer 2215, which can reduce the thickness of the film layer of the contact pad 31, thereby reducing the step difference of the film layer, further improving poor contact in the bonding area.

[0131] For example, Figure 15 As shown, the display substrate may further include an auxiliary conductive layer. This auxiliary conductive layer is located in the binding area and the display area and is disposed on the third insulating layer 2260 in the binding area. The auxiliary conductive layer includes a second transfer electrode pattern 2270 located in the binding area. The second transfer electrode pattern 2270 is implemented to perform a binding process with an external circuit. A third contact pad via 2218 is formed in the third insulating layer 2260 in the binding area. The second transfer electrode pattern 2270 is electrically connected to the contact pad through the third contact pad via 2218 to transmit electrical signals. The first insulating layer 2230 is configured to expose the surface of the contact pad 31 facing away from the substrate 2000. That is, the area outside the contact pad 31 in the binding area 2200 is covered by the first insulating layer 2230, including but not limited to the gaps between contact pads in the same row and the gaps between contact pads in different rows.

[0132] For example, in some examples of the present disclosure, the height of the second transfer electrode pattern 2270 relative to the surface of the substrate 2000 is not greater than the height of the third insulating layer 2260 in the bonding area relative to the surface of the substrate 2000 to avoid poor contact in the bonding area.

[0133] An embodiment of the present disclosure further provides a display device including the display substrate described above.

[0134] The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not constitute a limitation on the display device, and the display device may include more or fewer of the above-mentioned components, or a combination of certain components, or a different arrangement of components. In the embodiments of the present disclosure, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0135] The display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0136] In the accompanying drawings, the thickness of certain areas and layers may be exaggerated for clarity. The same reference numerals in the figures represent the same or similar structures, and their detailed descriptions will be omitted. The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the description of the present disclosure, many specific details are provided so as to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0137] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0138] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of above and below. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0139] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily need to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0140] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0141] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0142] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0143] As will be appreciated by those skilled in the art, although the various steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in that particular order unless the context clearly indicates otherwise. Additionally or alternatively, multiple steps may be combined into a single step and / or a single step may be broken down into multiple steps and performed. In addition, other method steps may be inserted between steps. An inserted step may represent an improvement to a method such as that described herein, or may be unrelated to the method. In addition, a given step may not be fully completed before the next step begins.

[0144] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: a substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located on one side of the display area; a plurality of sub-pixels, located on one side of the substrate and in the display area; a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of first contact pads, located in the binding area and connected to the plurality of data lines; a plurality of second contact pads located in the binding area and on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driver chip; A plurality of dummy wirings are located on a side of the plurality of first contact pads close to the display area and are located on at least one side of the plurality of data lines along a first direction.

2. The display substrate according to claim 1, wherein: The multiple data lines include a first group of data lines and a second group of data lines arranged along the first direction, the multiple virtual lines are located on at least one side of the first group of data lines along the first direction, and / or the multiple virtual lines are located on at least one side of the second group of data lines along the first direction.

3. The display substrate according to claim 2, wherein: The plurality of virtual lines are located on both sides of the first group of data lines along the first direction, and are located on both sides of the second group of data lines.

4. The display substrate according to claim 2, wherein: The display substrate further includes virtual data lines located on both sides of the first group of data lines along the first direction and on both sides of the second group of data lines, and arranged in one-to-one correspondence with the multiple virtual lines along the second direction, and the second direction intersects the first direction.

5. The display substrate according to claim 2, wherein: The plurality of first contact pads include a first group of contact pads and a second group of contact pads, the first group of contact pads and the second group of contact pads are arranged along the first direction, the first group of data lines are connected to the first group of contact pads, and the second group of data lines are connected to the second group of contact pads.

6. The display substrate according to claim 1, wherein: The connection between the dummy trace and the first contact pad is disconnected.

7. The display substrate according to claim 2, wherein: An extension direction of the virtual routing line located between the first group of data lines and the second group of data lines is parallel to an extension direction of at least part of the data lines.

8. The display substrate according to claim 2, wherein: The virtual lines located between the first group of data lines and the second group of data lines are parallel to the first direction.

9. The display substrate according to claim 2, wherein: The virtual lines located between the first group of data lines and the second group of data lines are in a block shape and are arranged in an array between the first group of data lines and the second group of data lines.

10. The display substrate according to claim 1, wherein The virtual wiring extends between the first contact pads.

11. The display substrate according to claim 1, wherein The display substrate comprises a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer, a first source-drain metal layer, a third insulating layer, a second source-drain metal layer and a fourth insulating layer sequentially located on the substrate; The data lines and the dummy lines are both made of the first gate metal layer.

12. The display substrate according to claim 1, wherein The display substrate further includes: a binding region interlayer insulating layer located in the binding region and between the plurality of first contact pads and the data line; a first gate insulating layer in the binding region, located in the binding region and on a side of the interlayer insulating layer in the binding region close to the substrate; and a second gate insulating layer in the binding region, located in the binding region, between the first gate insulating layer in the binding region and the interlayer insulating layer in the binding region, and stacked with the interlayer insulating layer in the binding region; The second gate insulation layer in the binding area includes a first contact pad via, the interlayer insulation layer in the binding area includes a second contact pad via, and at least one of the multiple data lines is electrically connected to the first contact pad through the first contact pad via and the second contact pad via.

13. The display substrate according to claim 12, wherein: The display substrate further includes a third insulating layer in the binding area. The third insulating layer of the binding region is located in the binding region and is arranged on a side of the first contact pad away from the substrate to cover the first contact pad. The third insulating layer in the bonding region has a third contact pad via hole to expose the surface of the first contact pad.

14. The display substrate according to claim 13, wherein: The display substrate further includes an auxiliary conductive layer, The auxiliary conductive layer is located in the binding area and is arranged on a side of the third insulating layer in the binding area away from the substrate. The auxiliary conductive layer includes a second switching electrode pattern located in the binding area, The second transfer electrode pattern is electrically connected to the first contact pad through the third contact pad via.

15. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 14.

Images