DC-dc converter connected with inductor and load detection method and chip thereof

Abstract

The application discloses a DC-DC converter connected with an inductor and a load detection method and chip thereof, and the detection method comprises the following steps: in a first switch tube opening stage, a first signal used for representing the end of a Miller platform corresponding to the first switch tube opening stage is acquired; in the rising process of a node voltage at a first connection node, a second signal used for representing that the node voltage reaches a preset value is acquired; and based on the time sequence between the first signal and the second signal, a representation signal used for judging the load state of the DC-DC converter is acquired. The DC-DC converter connected with the inductor and the load detection method and chip thereof have the advantages that the first signal corresponding to the end of the Miller platform in the switch tube opening stage and the second signal corresponding to the rising of the node voltage at the first connection node to the preset value are utilized, and the physical characteristics of the reverse charge recovery of the parasitic diode of the switch tube are combined, so that the second signal leads or lags the first signal, and thus the detection of the load state can be realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a DC-DC converter connected to an inductor and its load detection method and chip. Background Technology

[0002] In DC-DC power conversion chips, the control loop is divided into current-mode, voltage-mode, fixed on-time, and fixed off-time. In traditional DC-DC structures, load current information is typically obtained by detecting the amplitude of the voltage at the COMP node output of amplifier EA. However, the COMP node voltage is coherent with both the duty cycle and the load, making it complex to separate the duty cycle information and only detect the load point. Furthermore, the amplitude of this COMP node voltage only represents steady-state load current information and cannot improve real-time load detection. Finally, using traditional COMP node voltage detection to identify the load is only suitable for current-mode structures; therefore, a more universal and simpler load detection technology is needed.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a DC-DC converter connected to an inductor and a load detection method and chip thereof, which can detect the load of the DC-DC converter in a universal and simple manner.

[0005] To achieve the above objectives, embodiments of the present invention provide a load detection method for a DC-DC converter connected to an inductor. The DC-DC converter includes a first switching transistor, a second switching transistor, and an inductor. The first and second switching transistors are connected in series and connected to a first terminal of the inductor to form a first connection node. The second terminal of the inductor is the output terminal. The first switching transistor is simultaneously connected to a power supply voltage, and the second switching transistor is simultaneously connected to ground voltage. The load detection method includes:

[0006] During the first switch-on phase, a first signal is acquired to characterize the end of the Miller platform during the first switch-on phase.

[0007] During the rise of the node voltage at the first connection node, a second signal is acquired to characterize that the node voltage has reached a preset value;

[0008] Based on the timing between the first signal and the second signal, a characterization signal for determining the load state of the DC-DC converter is obtained.

[0009] In one or more embodiments of the present invention, obtaining a characterization signal for determining the load state of the DC-DC converter based on the timing between the first signal and the second signal includes:

[0010] Based on the timing that the second signal leads the first signal, a characterization signal is obtained to characterize the load state of the DC-DC converter as a light load state.

[0011] Based on the timing of the second signal lagging behind the first signal, a characterization signal is obtained to represent the load state of the DC-DC converter as being in a heavy-load state.

[0012] In one or more embodiments of the present invention, the load detection method further includes:

[0013] The magnitude of the drive current at the control terminal of the first switching transistor is controlled based on the characterization signal, so as to adjust the switching speed of the first switching transistor according to the load state of the DC-DC converter.

[0014] In one or more embodiments of the present invention, when the DC-DC converter is under light or heavy load, the drive current is gradually increased to the control terminal of the first switch during the turn-on phase of the first switch.

[0015] In one or more embodiments of the present invention, when the DC-DC converter is under light or heavy load, a first drive current is provided to the control terminal of the first switching transistor before the Miller plateau ends, and a second drive current is provided to the control terminal of the first switching transistor after the Miller plateau ends.

[0016] In one or more embodiments of the present invention, the front drive current provided by the DC-DC converter under heavy load is less than the front drive current provided by the DC-DC converter under light load, and the rear drive current provided by the DC-DC converter under heavy load is less than the rear drive current provided by the DC-DC converter under light load.

[0017] This invention also discloses a DC-DC converter connected to an inductor. The DC-DC converter includes a first switching transistor, a second switching transistor, and an inductor. The first and second switching transistors are connected in series and connected to a first terminal of the inductor to form a first connection node. The second terminal of the inductor is the output terminal. The first switching transistor is simultaneously connected to a power supply voltage, and the second switching transistor is simultaneously connected to ground voltage. The invention is characterized in that the DC-DC converter further includes:

[0018] A load detection circuit, comprising a Miller platform detection circuit, a voltage detection circuit, and a timing monitoring circuit;

[0019] The Miller platform detection circuit outputs a first signal to characterize the end of the Miller platform corresponding to the first switch transistor's turn-on phase, based on the voltage change between the control terminal of the first switch transistor and the first connection node.

[0020] The voltage detection circuit outputs a second signal to characterize that the node voltage has reached a preset value based on the change in the node voltage at the first connection node.

[0021] The timing monitoring circuit outputs a characterization signal to characterize the load state of the DC-DC converter based on the timing between the first signal and the second signal.

[0022] In one or more embodiments of the present invention, the DC-DC converter further includes a latch for buffering the characterization signal.

[0023] In one or more embodiments of the present invention, the DC-DC converter further includes a drive control circuit for receiving a characterization signal and providing a corresponding drive current to the control terminal of the first switching transistor.

[0024] In one or more embodiments of the present invention, the drive control circuit includes multiple groups of drive transistors, each group of drive transistors includes several drive transistors, the source of each drive transistor is connected to the control terminal of the first switch transistor, and the drain of each drive transistor is connected to the power supply voltage. Depending on the different load states of the DC-DC converter, different numbers of drive transistors are controlled to conduct during the turn-on phase of the first switch transistor to provide corresponding drive current to the control terminal of the first switch transistor.

[0025] In one or more embodiments of the present invention, the driving transistor group includes a first driving transistor group and a second driving transistor group. The first driving transistor group includes a first driving transistor and a second driving transistor, and the second driving transistor group includes a third driving transistor and a fourth driving transistor. According to different load states of the DC-DC converter, during the first switch turn-on phase, one or more of the first driving transistor, the second driving transistor, the third driving transistor, and the fourth driving transistor are controlled to be turned on to provide a corresponding driving current to the control terminal of the first switch transistor.

[0026] In one or more embodiments of the present invention, depending on the different load states of the DC-DC converter, the first driving transistor and / or the second driving transistor are controlled to turn on before the Miller plateau ends during the first switching transistor turn-on phase, and the third driving transistor and / or the fourth driving transistor are controlled to turn on after the Miller plateau ends.

[0027] The present invention also discloses a chip including the aforementioned DC-DC converter connected to the inductor.

[0028] Compared with existing technologies, the DC-DC converter connected to an inductor and its load detection method and chip according to the present invention utilize a first signal corresponding to the end of the Miller plateau during the switching transistor's turn-on phase and a second signal corresponding to the rise of the node voltage at the first connection node to a preset value. Combined with the physical characteristics of the reverse charge recovery of the parasitic diode of the switching transistor itself, the node voltage at the first connection node rises to the preset value at different times depending on the load state. This causes the second signal to lead or lag the first signal, thereby enabling load state detection. Selecting an appropriate switching transistor drive strength according to different load states maximizes the utilization of the switching transistor's safe operating range and reduces switching transistor losses. Especially in light and medium load ranges where switching losses account for a relatively large proportion, this method can effectively improve power conversion efficiency. Under heavy load conditions, reducing the switching speed prevents the generation of sudden voltage fluctuations and avoids damage to the switching transistor due to overvoltage. Attached Figure Description

[0029] Figure 1 This is a circuit schematic of a current-technology DC-DC converter.

[0030] Figure 2 This is a waveform diagram of a current-technical DC-DC converter during cyclic operation.

[0031] Figure 3 This is a schematic diagram of the physical current characteristics of the parasitic diode of a current-carrying switching transistor in the prior art.

[0032] Figure 4 This is a circuit schematic diagram of a DC-DC converter according to an embodiment of the present invention.

[0033] Figure 5 This is a circuit schematic diagram of a load detection circuit according to an embodiment of the present invention.

[0034] Figure 6 This is a waveform diagram of each signal in a load detection circuit according to an embodiment of the present invention.

[0035] Figure 7 This is a flowchart of a load detection method for a DC-DC converter connected to an inductor according to an embodiment of the present invention. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0037] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0038] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled to or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0039] like Figure 1 As shown, the synchronous buck switching power supply DC-DC includes a first switching transistor HS, a second switching transistor LS, a drive control circuit Driver, and an inductor L1. The source of the first switching transistor HS and the drain of the second switching transistor LS are connected and connected to the first terminal of the inductor L1 to form a first connection node SW. The drive control circuit Driver is connected to the gates of the first switching transistor HS and the second switching transistor LS to control the switching timing of the first switching transistor HS and the second switching transistor LS. When the synchronous buck switching power supply DC-DC is packaged in a chip, a first parasitic inductance Lv and a second parasitic inductance Lg are generated. The first parasitic inductance Lv includes the first parasitic inductance Lvin generated by the chip VIN pin package and the first parasitic inductance Lvinpcb generated by the PCB board. Correspondingly, the second parasitic inductance Lg includes the parasitic inductance Lgnd generated by the chip GND pin package and the second parasitic inductance Lgndpcb generated by the PCB board.

[0040] To prevent a short circuit in the DC power supply caused by the simultaneous conduction of the first switch HS and the second switch LS, a dead time is required during the switching process between the two switches HS and LS. During the dead time, the node voltage of the first connection node SW is low, and the first parasitic diode D1 of the second switch LS will freewheel the current IL of the inductor L. After the dead time ends, the first switch HS turns on, and the sudden current in the first parasitic inductor Lv will cause a voltage surge. See [link to documentation] for details. Figure 2 The voltage waveform of VIN, and the surge voltage are:

[0041] V=Lv*di / dt (1)

[0042] Where Lv = Lvin + Lvinpcb, and di / dt is determined by the switching speed of the first switching transistor HS.

[0043] As can be seen from expression (1), when the chip package and PCB board are determined, the first parasitic inductance Lvin generated by the chip VIN pin package and the first parasitic inductance Lvinpcb generated by the PCB board no longer change, that is, the first parasitic inductance Lv is a fixed value. Since an excessively high amplitude of the surge voltage can cause the switching transistor to be damaged by overvoltage, and the switching transistor is prone to generating a high amplitude surge voltage when it is turned on under heavy load, controlling the switching speed di / dt of the switching transistor under heavy load can limit the amplitude of the surge voltage, prevent the switching transistor from being damaged by overvoltage, and protect the safety of the switching transistor.

[0044] After the first switching transistor HS is turned on, the magnitude of the current IL in inductor L1 depends on the magnitude of the load current. Under light load conditions, the load current is relatively small; under heavy load conditions, the load current is relatively large. The freewheeling current in the first parasitic diode D1 of the second switching transistor LS also differs depending on the magnitude of the load current.

[0045] Because diodes have special physical current characteristics, such as Figure 3 As shown, when a diode is forward-biased, the current flowing through it is labeled as the forward current. When the voltage across the diode suddenly reverses, the diode does not immediately turn off; instead, a reverse current flows through it. This reverse current decays to zero after a time Trr, at which point the diode is completely turned off. The process from forward conduction to reverse cutoff in diode switching is called the diode's reverse recovery process, and Trr is the diode's reverse recovery time.

[0046] Under light and heavy load conditions, the magnitude of the freewheeling current on the first parasitic diode D1 of the second switching transistor LS is different, and the amount of charge stored inside the parasitic diode D1 is also different. Therefore, the reverse recovery time of the parasitic diode in reverse charge recovery is also different.

[0047] Specifically, during the dead time when the first switch HS is not turned on and the second switch LS is turned off, the first parasitic diode D1 continues forward. After the dead time, the first switch HS turns on, and the power supply voltage VIN acts on the first parasitic diode D1 and generates a reverse current. After the reverse recovery time Trr, the reverse current of the first parasitic diode D1 decays to 0, and the current of the power supply voltage VIN charges the (to ground) capacitor at the first connection node SW. Finally, the node voltage of the first connection node SW reaches the voltage of the power supply voltage VIN and outputs voltage VOUT. At this time, the circuit is in a steady state. When the circuit operates under light load, the forward freewheeling current on the first parasitic diode D1 of the second switch LS is small during the dead time, and its internal charge is also small. After the dead time, the reverse current acting on it by the power supply voltage VIN is small, the reverse recovery time Trr for the reverse current on the first parasitic diode D1 of the second switch LS to decay to 0 is short, the time for the power supply voltage VIN to complete charging of the first connection node SW is short, the time for the voltage at the first connection node SW to reach the power supply voltage VIN is also short, and the time for the circuit to establish a steady state is short. When the circuit operates under heavy load, the forward freewheeling current on the first parasitic diode D1 of the second switch LS is large during the dead time, and its internal charge is also large. After the dead time, the reverse current acting on it by the power supply voltage VIN is large, the reverse recovery time Trr for the reverse current on the first parasitic diode D1 of the second switch LS to decay to 0 is long, the time for the power supply voltage VIN to complete charging of the first connection node SW is long, the time for the voltage at the first connection node SW to reach the power supply voltage VIN is also long, and the time for the circuit to establish a steady state is long.

[0048] The following is in conjunction with the appendix Figure 4-6 The present invention will be further described below.

[0049] like Figure 4 As shown, a DC-DC converter connected to an inductor includes: a first switching transistor HS, a second switching transistor LS, an inductor L1, and a drive control circuit Driver. Both the first switching transistor HS and the second switching transistor LS are NMOS transistors. The source of the first switching transistor HS and the drain of the second switching transistor LS are connected together and connected to the first terminal of the inductor L1 to form a first connection node SW. The second terminal of the inductor L1 is the output terminal. The drive control circuit Driver is connected to the gates (control terminals) of the first switching transistor HS and the second switching transistor LS, and is used to control the switching timing of the first switching transistor HS and the second switching transistor LS.

[0050] When the drain of the first switching transistor HS is simultaneously connected to the power supply voltage VIN, and the DC-DC converter is packaged within the chip, a first parasitic inductance Lv exists between the drain of the first switching transistor HS and the power supply voltage VIN. This first parasitic inductance Lv mainly consists of the first parasitic inductance Lvin generated by the chip's VIN pin packaging and the first parasitic inductance Lvinpcb generated by the PCB board. Similarly, when the source of the second switching transistor LS is simultaneously connected to the ground voltage GND, and the DC-DC converter is packaged within the chip, a second parasitic inductance Lg exists between the source of the second switching transistor LS and the ground voltage GND. Correspondingly, this second parasitic inductance Lg mainly consists of the parasitic inductance Lgnd generated by the chip's GND pin packaging and the second parasitic inductance Lgndpcb generated by the PCB board.

[0051] A second parasitic diode D2 exists between the drain and source of the first switching transistor HS. The drain of the first switching transistor HS is connected to the cathode of the second parasitic diode D2, and the source of the first switching transistor HS is connected to the anode of the second parasitic diode D2. A first parasitic diode D1 exists between the drain and source of the second switching transistor LS. The drain of the second switching transistor LS is connected to the cathode of the first parasitic diode D1, and the source of the second switching transistor LS is connected to the anode of the first parasitic diode D1.

[0052] like Figure 5 As shown, the DC-DC converter also includes a load detection circuit, which is connected to the drive control circuit (Driver). The load detection circuit includes a Miller plateau detection circuit 10, a voltage detection circuit 20, a timing monitoring circuit 30, and a latch 40.

[0053] Miller platform detection circuit 10 is used to monitor the voltage V between the control terminal HG of the first switching transistor HS and the first connection node SW. HG-SW The change in voltage is used to monitor the end time of the Miller platform and output the first signal HG_DET. Voltage detection circuit 20 is used to monitor the node voltage V at the first connection node SW. SW Changes in V are used to monitor node voltage V. SW The system reaches the preset value Vo at the designated time point and outputs a second signal SW_DET. The timing monitoring circuit 30 compares the first signal HG_DET output by the Miller platform detection circuit 10 and the second signal SW_DET output by the voltage detection circuit 20 to determine the Miller platform end time point and the node voltage V. SW The timing sequence of the points when the preset value Vo is reached determines whether the circuit is in a light-load or heavy-load state, and outputs the characteristic signal LOAD_DET. Latch 40 is used to buffer the characteristic signal LOAD_DET and the enable signal HSON, and outputs the load signal LOAD_flag to the drive control circuit Driver.

[0054] Combined with appendix Figure 4-6 The specific working process of the circuit is as follows: When the circuit operates under light load, a Miller plateau is generated during the turn-on phase of the first switching transistor HS. The Miller plateau detection circuit 10 monitors the voltage V. HG-SW The change in voltage is used to determine the end time point t2 of the Miller platform, at which point the first signal HG_DET jumps from low to high; the voltage detection circuit 20 monitors the node voltage V. SW At time t1, when the preset value V0 is reached, the second signal SW_DET transitions from low to high. The preset value V0 can be selected as needed. Due to the small freewheeling current of the first parasitic diode D1 of the second switching transistor LS under light load conditions, the reverse recovery time of the first parasitic diode D1 is relatively short, as shown in the attached diagram. Figure 6 As shown, the node voltage V SW The time to reach the preset value Vo is relatively short, and the node voltage V SW The time point t1 that first reaches the preset value Vo comes first, and the Miller plateau ends at time t2, meaning time point t1 is earlier than time point t2. Therefore, the timing monitoring circuit 30 determines that the circuit is operating in a light-load state by comparing time point t1 with time point t2, and outputs the characterization signal LOAD_DET, which is low at this time.

[0055] When the circuit operates under heavy load, a Miller plateau is generated during the turn-on phase of the first switching transistor HS. The Miller plateau detection circuit 10 monitors the voltage V... HG-SW The change in voltage is used to determine the end time point t4 of the Miller platform, at which point the first signal HG_DET jumps from low to high; the voltage detection circuit 20 monitors the node voltage V. SW At time t3, when the preset value V0 is reached, the second signal SW_DET transitions from low to high. The preset value V0 can be selected as needed. Due to the large freewheeling current of the first parasitic diode D1 of the second switch LS under heavy load conditions, the reverse recovery time of the first parasitic diode D1 is relatively long, as shown in the attached diagram. Figure 6 As shown, the node voltage V SW The time to reach the preset value Vo is relatively long, and the node voltage V SW The time point t3 for reaching the preset value Vo is later than the time point t4 for the Miller platform to end, meaning time point t3 is later than time point t4. Therefore, the timing monitoring circuit 30 determines that the circuit is operating in a heavy load state by comparing time point t4 with time point t3, and outputs the characterization signal LOAD_DET, which is high at this time.

[0056] The conversion efficiency and switching losses of a DC-DC converter are both related to the conduction losses of the switching transistor. Under heavy load, the conduction losses of the switching transistor dominate, while under light load, the switching losses dominate. Therefore, different switching intensity controls for light and heavy loads can meet the high efficiency requirements under both conditions. Furthermore, when the parasitic inductance of the chip package and PCB is relatively large, the switching speed under heavy load can affect the lifespan of the power transistor and may even cause it to burn out due to overvoltage. Therefore, controlling the switching speed of the switching transistor is particularly important.

[0057] In this embodiment, the drive control circuit Driver receives the load signal LOAD_flag and provides different magnitudes of drive current to the control terminal HG of the first switching transistor HS. The drive control circuit Driver also receives the turn-on signal HSON to control the first switching transistor HS to turn on.

[0058] The drive control circuit includes multiple groups of drive transistors, each group containing several drive transistors. The source of each drive transistor is connected to the control terminal of the first switching transistor HS, and the drain of each drive transistor is connected to the power supply voltage VDD. Depending on the load condition, different numbers of drive transistors are turned on to provide drive current to the control terminal HG of the first switching transistor HS.

[0059] like Figure 4 As shown, the driving transistor group specifically includes a first driving transistor group 51 and a second driving transistor group 52. The first driving transistor group 51 includes a first driving transistor M1 and a second driving transistor M2, and the second driving transistor group 52 includes a third driving transistor M3 and a fourth driving transistor M4. Depending on the different load states of the DC-DC converter, during the turn-on phase of the first switch transistor HS, the first driving transistor M1 and the second driving transistor M2 are controlled to conduct, and one or more of the third driving transistor M3 and the fourth driving transistor M4 in the second driving transistor group 52 are turned on to provide the corresponding driving current to the control terminal of the first switch transistor. For example, the first driving transistor M1 and / or the second driving transistor M2 are controlled to conduct before the Miller plateau corresponding to the turn-on phase of the first switch transistor HS ends, and the third driving transistor M3 and / or the fourth driving transistor M4 are controlled to conduct after the Miller plateau corresponding to the start-up phase of the first switch transistor HS ends.

[0060] Specifically, the first driving transistor M1 and the second driving transistor M2 are the first-stage switching drivers, and the third driving transistor M3 and the fourth driving transistor M4 are the second-stage switching drivers. When the DC-DC converter is under light load, the first driving transistor M1 and the second driving transistor M2 are simultaneously turned on before the Miller plateau ends during the first switching transistor HS's turn-on phase. The third driving transistor M3 and the fourth driving transistor M4 are then simultaneously turned on after the Miller plateau ends during the first switching transistor HS's turn-on phase. This significantly increases the drive current supplied to the gate of the first switching transistor HS, improving the switching speed of the first switching transistor HS under light load. When the DC-DC converter is under heavy load, the first driving transistor M1 is turned on before the Miller plateau ends during the first switching transistor HS's turn-on phase. The third driving transistor M3 is then turned on after the Miller plateau ends during the first switching transistor HS's turn-on phase. This reduces the switching speed of the first switching transistor HS under heavy load. In other embodiments, other sequences can be used to turn on the driving transistors.

[0061] In this embodiment, the width-to-length ratio of the first driving transistor M1, the second driving transistor M2, the third driving transistor M3, and the fourth driving transistor M4 is 1:4:2:4. This width-to-length ratio is also the same as the ratio of the driving current supplied to the gate of the first switching transistor HS, i.e., the driving current ratio is 1:4:2:4. Correspondingly, the ratio of the driving current simultaneously provided by the first driving transistor M1 and the second driving transistor M2 to the driving current simultaneously provided by the third driving transistor M3 and the fourth driving transistor M4 is 5:6, and the ratio of the driving current solely provided by the first driving transistor M1 to the driving current solely provided by the third driving transistor M3 is 1:2. In other embodiments, the width-to-length ratio of the first driving transistor M1, the second driving transistor M2, the third driving transistor M3, and the fourth driving transistor M4 can also be other ratios.

[0062] like Figure 4 As shown, the drive control circuit Driver also includes a first inverter 61 and a second inverter 62 connected in series. The input terminal of the first inverter 61 receives the enable signal HSON. It should be noted that the first driving transistor M1 forms part of the second inverter 62; that is, when the enable signal HSON is generated and the first switching transistor HS is turned on, the first driving transistor M1 is already conducting. In other embodiments, if there is no first inverter 61 and a second inverter 62, the enable signal HSON is directly input to the gate of the first driving transistor M1 or it can be directly input to the gate of the first switching transistor HS to control the first switching transistor HS to turn on.

[0063] In this embodiment, the circuit for controlling the second switch LS is largely the same as the circuit for controlling the first switch HS. The difference is that the circuit for controlling the second switch LS does not need to include a voltage detection circuit and a timing monitoring circuit. Instead, it controls the sequential conduction of the corresponding drive transistors based on the Miller plateau that the second switch LS turns on, thereby controlling the magnitude of the current supplied to the gate of the second switch LS and thus controlling the switching speed of the second switch LS.

[0064] The present invention also discloses a chip including the aforementioned DC-DC converter connected to an inductor.

[0065] like Figure 7 As shown, based on the aforementioned DC-DC converter connected to an inductor, this invention also discloses a load detection method for a DC-DC converter connected to an inductor, comprising:

[0066] S1. During the turn-on phase of the first switch HS, a first signal HG_DET is acquired to characterize the end of the Miller plateau during the turn-on phase of the first switch HS. In this embodiment, the first signal HG_DET characterizes the end of the Miller plateau by transitioning from a low level to a high level.

[0067] S2, the node voltage V at the first connection node SW SW During the rise of the node voltage V, the data is obtained to characterize the node voltage V. SW The second signal SW_DET reaches the preset value V0. In this embodiment, the preset value V0 is the voltage value of the power supply voltage VIN, and the second signal SW_DET represents the node voltage V by transitioning from a low level to a high level. SW The preset value V0 has been reached.

[0068] S3. Based on the timing between the first signal HG_DET and the second signal SW_DET, obtain the characterization signal LOAD_DET used to determine the load state of the DC-DC converter. Under light load conditions, the time node of the second signal SW_DET transitioning from low to high precedes the time node of the first signal HG_DET transitioning from low to high. In this case, the characterization signal LOAD_DET uses a low-level signal to characterize the load state of the DC-DC converter as light load. Under heavy load conditions, the time node of the second signal SW_DET transitioning from low to high lags the time node of the first signal HG_DET transitioning from low to high. In this case, the characterization signal LOAD_DET uses a high-level signal to characterize the load state of the DC-DC converter as heavy load.

[0069] In this embodiment, the load detection method further includes: S4, controlling the magnitude of the drive current at the control terminal of the first switching transistor HS based on the characterization signal LOAD_DET, so as to adjust the switching speed of the first switching transistor HS according to the load state of the DC-DC converter.

[0070] Specifically, when the DC-DC converter is under light load, a first drive current is provided to the control terminal (gate) of the first switch HS before the Miller plateau ends during the turn-on phase. After the Miller plateau corresponding to the turn-on phase of the first switch HS ends, a second drive current is provided to the control terminal of the first switch HS, thereby increasing the drive current to the control terminal of the first switch HS in stages, thus improving the switching speed of the first switch HS. In other embodiments, multiple stages of increasing drive current can be formed during the turn-on phase of the first switch HS. The end of the Miller plateau can be used as the critical point for increasing the drive current, or other times can be used as the critical point, such as the beginning of the Miller plateau, the formation of the Miller plateau to the midpoint, etc.

[0071] When the DC-DC converter is under heavy load, a third drive current is provided to the control terminal of the first switch HS before the Miller plateau ends during the turn-on phase of the first switch HS. After the Miller plateau corresponding to the turn-on phase of the first switch HS ends, a fourth drive current is provided to the control terminal of the first switch HS, thus forming a step-by-step increase in drive current to the control terminal of the first switch HS. In other embodiments, multiple stages of increasing drive current can be formed during the turn-on phase of the first switch HS. The end of the Miller plateau can be used as the critical point for increasing the drive current, or other times can be used as the critical point, such as the start of the Miller plateau, the formation of the Miller plateau to its midpoint, etc.

[0072] The first and third drive currents are the front drive currents, and the second and fourth drive currents are the rear drive currents. These currents are generally set in proportion, but can be configured in various proportions as needed. In this embodiment, the first drive current is 3 to 6 times the third drive current, and the second drive current is 2 to 5 times the fourth drive current and the first drive current. The third drive current is less than the first drive current, and the fourth drive current is less than the second drive current, thereby reducing the switching speed of the first switching transistor HS when the DC-DC converter is under heavy load.

[0073] In this embodiment, the driving method for the second switch LS is as follows: it is only necessary to monitor the Miller plateau of the second switch LS during the turn-on phase, and provide corresponding driving currents before and after the Miller plateau ends. The magnitude of the driving current provided is the same as the magnitude of the driving current received by the first switch HS during the turn-on phase, which will not be elaborated here.

[0074] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A load detection method for a DC-DC converter connected to an inductor, the DC-DC converter comprising a first switching transistor and a second switching transistor, the first and second switching transistors being connected in series and the connection node of the first and second switching transistors being connected to a first terminal of an inductor to form a first connection node, the second terminal of the inductor being an output terminal, the first switching transistor being simultaneously connected to a power supply voltage, and the second switching transistor being simultaneously connected to ground voltage, characterized in that, The load detection method includes: During the first switch-on phase, a first signal is acquired to characterize the end of the Miller platform during the first switch-on phase. During the rise of the node voltage at the first connection node, a second signal is acquired to characterize that the node voltage has reached a preset value; Based on the timing between the first signal and the second signal, a characterization signal for determining the load state of the DC-DC converter is obtained.

2. The load detection method for a DC-DC converter connected to an inductor as described in claim 1, characterized in that, The step of obtaining a characterizing signal for determining the load state of the DC-DC converter based on the timing between the first signal and the second signal includes: Based on the timing that the second signal leads the first signal, a characterization signal is obtained to characterize the load state of the DC-DC converter as a light load state. Based on the timing of the second signal lagging behind the first signal, a characterization signal is obtained to represent the load state of the DC-DC converter as being in a heavy-load state.

3. The load detection method for a DC-DC converter connected to an inductor as described in claim 1 or 2, characterized in that, The load detection method further includes: The magnitude of the drive current at the control terminal of the first switching transistor is controlled based on the characterization signal, so as to adjust the switching speed of the first switching transistor according to the load state of the DC-DC converter.

4. The load detection method for a DC-DC converter connected to an inductor as described in claim 3, characterized in that, When the DC-DC converter is under light or heavy load, the drive current is gradually increased to the control terminal of the first switch during the turn-on phase.

5. The load detection method for a DC-DC converter connected to an inductor as described in claim 4, characterized in that, When the DC-DC converter is under light or heavy load, a front drive current is provided to the control terminal of the first switching transistor before the Miller plateau ends, and a rear drive current is provided to the control terminal of the first switching transistor after the Miller plateau ends.

6. The load detection method for a DC-DC converter connected to an inductor as described in claim 5, characterized in that, The front drive current provided by the DC-DC converter under heavy load is less than the front drive current provided by the DC-DC converter under light load, and the rear drive current provided by the DC-DC converter under heavy load is less than the rear drive current provided by the DC-DC converter under light load.

7. A DC-DC converter connected to an inductor, the DC-DC converter comprising a first switching transistor and a second switching transistor, the first switching transistor and the second switching transistor being connected in series and the connection node of the first switching transistor and the second switching transistor being connected to a first terminal of the inductor to form a first connection node, the second terminal of the inductor being an output terminal, the first switching transistor being simultaneously connected to a power supply voltage, and the second switching transistor being simultaneously connected to ground voltage, characterized in that, The DC-DC converter also includes: A load detection circuit, comprising a Miller platform detection circuit, a voltage detection circuit, and a timing monitoring circuit; The Miller platform detection circuit outputs a first signal to characterize the end of the Miller platform corresponding to the first switch transistor's turn-on phase, based on the voltage change between the control terminal of the first switch transistor and the first connection node. The voltage detection circuit outputs a second signal to characterize that the node voltage has reached a preset value based on the change in the node voltage at the first connection node. The timing monitoring circuit outputs a characterization signal to characterize the load state of the DC-DC converter based on the timing between the first signal and the second signal.

8. The DC-DC converter connected to an inductor as described in claim 7, characterized in that, The DC-DC converter also includes a latch for buffering the characterization signal.

9. The DC-DC converter connected to an inductor as described in claim 7, characterized in that, The DC-DC converter also includes a drive control circuit for receiving characterization signals and providing corresponding drive current to the control terminal of the first switching transistor.

10. The DC-DC converter connected to an inductor as described in claim 9, characterized in that, The drive control circuit includes multiple groups of drive transistors, each group containing several drive transistors. The source of each drive transistor is connected to the control terminal of the first switching transistor, and the drain of each drive transistor is connected to the power supply voltage. Depending on the different load states of the DC-DC converter, different numbers of drive transistors are controlled to conduct during the turn-on phase of the first switching transistor to provide corresponding drive current to the control terminal of the first switching transistor.

11. The DC-DC converter connected to an inductor as described in claim 10, characterized in that, The driving transistor group includes a first driving transistor group and a second driving transistor group. The first driving transistor group includes a first driving transistor and a second driving transistor. The second driving transistor group includes a third driving transistor and a fourth driving transistor. According to different load states of the DC-DC converter, during the first switch turn-on phase, the driving current provided to the control terminal of the first switch is gradually increased by controlling one or more of the first driving transistor, the second driving transistor, the third driving transistor and the fourth driving transistor to be turned on.

12. The DC-DC converter connected to an inductor as described in claim 11, characterized in that, Depending on the different load states of the DC-DC converter, the first drive transistor and / or the second drive transistor are turned on before the Miller platform ends during the first switching transistor turn-on phase, and the third drive transistor and / or the fourth drive transistor are turned on after the Miller platform ends.

13. A chip, characterized in that, Includes the DC-DC converter connected to an inductor as described in any one of claims 7 to 12.

Images