Multi-phase delay control circuit

Abstract

The embodiment of the present disclosure provides a multi-phase delay control circuit, wherein the multi-phase delay control circuit comprises a slow opening control circuit, a fast opening control circuit, an OR gate and an RS flip-flop; a pulse width modulation signal of an i-th phase is transmitted to the RS flip-flop to obtain a pulse width modulation signal of an i+1-th phase through different delays set in the slow opening control circuit and the fast opening control circuit. The problem that the output voltage obviously drops at a fixed switching frequency of the existing multi-phase delay control circuit when the load is switched and the system transient response is affected is solved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to multi-phase delay control circuits. Background Technology

[0002] In the design of control circuits for multi-phase switching converters, the number of phases activated is typically determined based on the severity of the applied load. In applications with all phases open, as long as the applied load does not exceed the maximum load limit, loop regulation can be achieved by activating only the primary phase or by activating both the primary and all secondary phases. When the applied load instantaneously switches from a light load to a heavy load, the control system switches from activating only the primary phase to activating both the primary and all secondary phases to maintain a stable output voltage. During this load switching process, the activation of the secondary phases is usually done with a sequential delay, and the delay between adjacent phases is related to the set system switching frequency. When the switching frequency is high, the delay is designed to be shorter; when the switching frequency is low, the delay is designed to be longer, thus maintaining a uniform energy distribution under steady state. Due to the limitation of the set system switching frequency, the delay between adjacent phases is a fixed value at the same switching frequency. In practical applications, especially in low-frequency applications, the gradual activation of all phases at the set system switching frequency can cause a significant drop in output voltage, adversely affecting the system's transient response. Summary of the Invention

[0003] The embodiments described herein provide a multi-phase delay control circuit to address the problem that, when applying existing multi-phase delay control circuits during load switching, a significant drop in output voltage occurs, adversely affecting the transient response of the system.

[0004] This disclosure provides a multi-phase delay control circuit comprising: a slow-on control circuit, a fast-on control circuit, an OR gate, and an RS flip-flop; wherein, the slow-on control circuit is configured to control the delay between adjacent phases according to a first delay during a stable period; the fast-on control circuit is configured to control the delay between adjacent phases according to a second delay during an unstable period, wherein the unstable period is a preset number of periods corresponding to load switching, and the first delay is greater than the second delay; the OR gate is configured to select the output signal of the slow-on control circuit or the output signal of the fast-on control circuit; the RS flip-flop is configured to implement different delays between adjacent phases according to different output signals selected by the OR gate; the pulse width modulation signal of the i-th phase is transmitted to the RS flip-flop after passing through different delays set in the slow-on control circuit and the fast-on control circuit to obtain the pulse width modulation signal of the (i+1)-th phase, where i is an integer greater than or equal to 1.

[0005] Optionally, the fast-start control circuit includes: a delay control circuit, a selector, a first D flip-flop, a counter, a first AND gate, and a first NOT gate; wherein, the delay control circuit is configured to control the delay between adjacent phases according to the second delay, the input terminal of the delay control circuit is connected to the pulse width modulation signal of the i-th phase, and the output terminal of the delay control circuit is respectively connected to the counter and the second input terminal of the first AND gate; the selector is configured to control a preset number corresponding to the unstable period according to the setting of an external number and in conjunction with the counter, the selector receives the external number, and the input terminal of the selector is also connected to... The output of the counter and the output of the selector are respectively connected to the first D flip-flop and the first input of the first AND gate; the first D flip-flop receives a phase-on indication signal, and the output of the first D flip-flop is respectively connected to the counter, the third input of the first AND gate, and the delay control circuit; the output of the first D flip-flop is also connected to the slow-on control circuit through the first NOT gate; the counter is configured to cooperate with the selector to control a preset number corresponding to the unstable period; the output of the first AND gate serves as the output of the fast-on control circuit and is connected to one input of the OR gate.

[0006] Optionally, the delay control circuit includes: a second D flip-flop, a first delay unit, a second delay unit, a second NOT gate, and a second AND gate; the second D flip-flop includes three input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal, the second input terminal is connected to the pulse width modulation signal of the i-th phase, the third input terminal is connected to the output terminal of the second AND gate, and the first output terminal is connected to the input terminal of the first delay unit; the output terminal of the first delay unit serves as the output terminal of the delay control circuit, and the output terminal of the first delay unit is also connected to the input terminal of the second delay unit, wherein the second delay is set in the first delay unit; the output terminal of the second delay unit is connected to the second NOT gate and then connected to one input terminal of the second AND gate; the other input terminal of the second AND gate is connected to the output terminal of the first D flip-flop.

[0007] Optionally, the first D flip-flop includes three input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal, the second input terminal receives the phase-on indication signal, the third input terminal is connected to the output terminal of the selector, the first output terminal is connected to the counter, the third input terminal of the first AND gate, and the delay control circuit, and the first output terminal is also connected to the slow-on control circuit through the first NOT gate.

[0008] Optionally, the counter includes n D flip-flops: each of the n D flip-flops includes three inputs and two outputs, the first input of each D flip-flop is connected to its own second output, and n is an integer greater than or equal to 1; the second input of the first D flip-flop is connected to the output of the first delay unit, and the second inputs of the other D flip-flops are connected to the intermediate node between the first input and the second output of the previous D flip-flop; the third inputs of all n D flip-flops are connected together and connected to the first output of the first D flip-flop; the second outputs of all n D flip-flops are connected to the input of the selector.

[0009] Optionally, the number of bits at the input terminal of the selector to receive external digital data is determined according to the number of D flip-flops in the counter.

[0010] Optionally, the slow-on control circuit includes a third D flip-flop, a third delay unit, a fourth delay unit, a third NOT gate, and a third AND gate. The third D flip-flop has three inputs and two outputs. The first input is connected to the second output, and the second input receives the pulse width modulation signal of the i-th phase. The third input is connected to the output of the third AND gate, and the first output is connected to the input of the third delay unit. The output of the third delay unit is connected to the other input of the OR gate, and the output of the third delay unit is also connected to the input of the fourth delay unit. The first delay is set in the third delay unit. The output of the fourth delay unit is connected to the third NOT gate and then to one input of the third AND gate. The other input of the third AND gate is connected to the output of the first NOT gate.

[0011] Optionally, the RS flip-flop includes two input terminals and two output terminals. The first input terminal receives the peak sampling signal of the inductor current of the (i+1)th phase control circuit, the second input terminal is connected to the output terminal of the OR gate, and the first output terminal outputs the pulse width modulation signal of the (i+1)th phase.

[0012] Optionally, the delays set in both the second delay unit and the fourth delay unit are less than the second delay.

[0013] Optionally, the pulse width modulation signal is the pulse width modulation signal of the power switch of the multi-phase switching converter.

[0014] The multi-phase delay control circuit of this disclosure includes: a slow-on control circuit, a fast-on control circuit, an OR gate, and an RS flip-flop; wherein, the slow-on control circuit is configured to control the delay between adjacent phases according to a first delay during a stable period; the fast-on control circuit is configured to control the delay between adjacent phases according to a second delay during an unstable period, the unstable period being a preset number of periods corresponding to load switching, and the first delay being greater than the second delay; the OR gate is configured to select the output signal of the slow-on control circuit or the output signal of the fast-on control circuit; the RS flip-flop is configured to implement different delays between adjacent phases according to different output signals selected by the OR gate, and the pulse width modulation signal of the i-th phase is transmitted to the RS flip-flop after passing through the different delays set in the slow-on control circuit and the fast-on control circuit to obtain the pulse width modulation signal of the (i+1)-th phase, where i is an integer greater than or equal to 1. The multi-phase delay control circuit of this disclosure can control the delay between adjacent phases according to the system's set switching frequency (first delay) during the stable period, and can also shorten the delay between adjacent phases by a smaller delay (second delay) during the unstable period, thereby effectively solving the problem of a significant drop in output voltage caused by all phases being turned on slowly in succession, and thus optimizing the transient response of the system. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0016] Figure 1 This is an exemplary circuit diagram of an existing multi-phase delay control circuit;

[0017] Figure 2 This is a schematic diagram of the structure of a multi-phase delay control circuit according to an embodiment of the present disclosure;

[0018] Figure 3 This is a schematic diagram of a fast-start control circuit according to an embodiment of the present disclosure;

[0019] Figure 4 This is an exemplary circuit diagram of a multi-phase delay control circuit according to an embodiment of the present disclosure;

[0020] Figure 5 This is an exemplary circuit diagram of another multi-phase delay control circuit according to an embodiment of the present disclosure.

[0021] Figure 6 yes Figure 5 Waveform diagram of timing signals of key nodes in the multi-phase delay control circuit.

[0022] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 This is an exemplary circuit diagram of a conventional multi-phase delay control circuit 100, where PWM_i is the pulse width modulation signal of the i-th phase (which can be the current main phase or sub-phase), i represents the phase order corresponding to the current PWM signal, i≥1, and PWM_i+1 is the pulse width modulation signal of the (i+1)-th phase. When the signal PWM_i has not yet been input or is input at a low level to the CLK terminal of the D flip-flop, the D flip-flop is in an enabled state because the SET terminal of the RS flip-flop is reset, and the output of the PWM_i+1 terminal is low. When the rising edge of the signal PWM_i is input to the CLK terminal of the D flip-flop, this rising edge will be input to the SET terminal of the RS flip-flop after the propagation delay set in the delay unit Dely_Freq, setting the flip-flop output, causing the output level of PWM_i+1 to flip from low to high, thus creating a fixed delay between the rising edge of the signal PWM_i+1 and the rising edge of the signal PWM_i. Figure 1In this context, the delay selection of the delay unit Dely_Freq is related to the switching frequency of the current multiphase control system. When the switching frequency is high, the delay is designed to be shorter; when the switching frequency is low, the delay is designed to be longer. Taking a 6-phase control system with a maximum switching frequency of 1MHz as an example, the single-phase switching period of the system is designed to be 1µs. To maintain a uniform energy distribution in steady state when all phases are on, the delay τ in the delay unit Dely_Freq should satisfy: τ=1µs / 6≈167ns; Figure 1 In the circuit, signal Ipeak is the peak sampling signal of the inductor current of the (i+1)th phase control circuit. When the inductor current of the (i+1)th phase reaches its peak value, the rising edge of signal Ipeak is input to the RESET terminal of the RS flip-flop, which resets the flip-flop output, causing the output level of signal PWM_i+1 to flip from high to low, and then waits for the rising edge of signal PWM_i of the next switching cycle.

[0027] exist Figure 1 In the process, the rising edge of the signal PWM_i is input to the delay unit Dely_15ns after passing through the delay unit Dely_Freq, and a low-level reset signal lasting 15ns is generated by output inversion, which clears the output state of the D flip-flop to ensure that the rising edge of the signal PWM_i in the next cycle can still maintain the same delay as the rising edge of the current cycle signal PWM_i+1.

[0028] from Figure 1 As can be seen, under the premise that the switching frequency set by the system is fixed, the delay between the i-th phase and the (i+1)-th phase is fixed. Taking a 6-phase control system with a maximum switching frequency of 1MHz as an example, when the load is switched, the successive opening of all phases at the set system switching frequency with a delay of 167ns will cause the output voltage to drop. Especially in low-frequency applications, the output voltage drops more significantly, which has an adverse effect on the transient response of the system.

[0029] To address the problem that existing multi-phase delay control circuits cause significant output voltage drops during load switching, adversely affecting the system's transient response, this disclosure proposes a novel multi-phase delay control circuit. This circuit shortens the delay between phases during load switching, primarily from light load to heavy load, providing timely and sufficient energy supply. This effectively aids in the undershoot recovery of the output voltage when switching from light load to heavy load, optimizing the system's transient response. Furthermore, within the stable period after load switching, it can control the delay between adjacent phases according to the system's set switching frequency, thereby maintaining a uniform energy distribution in steady state. The multi-phase delay control circuit of this disclosure can be applied not only to low-frequency applications but also to high-frequency applications. A detailed description of the multi-phase delay control circuit of this disclosure follows.

[0030] like Figure 2 The diagram shown is a structural schematic of a multi-phase delay control circuit 200 according to an embodiment of the present disclosure. The multi-phase delay control circuit 200 includes: a slow-on control circuit 21, a fast-on control circuit 22, an RS flip-flop 23, and an OR gate 24. The slow-on control circuit 21 receives the PWM signal PWM_i of the i-th phase, where i is an integer greater than or equal to 1. The slow-on control circuit 21 is connected to the OR gate 24 and the fast-on control circuit 22. The slow-on control circuit 21 is configured to control the delay between adjacent phases according to a first delay within a stable period, wherein the first delay is a delay determined according to the set switching frequency of the system. The fast-start control circuit 22 receives the PWM signal PWM_i of the i-th phase and connects to OR gate 24 and slow-start control circuit 21 respectively. It is configured to control the delay between adjacent phases according to a second delay during an unstable period, where the unstable period is the preset number of periods corresponding to load switching, and the first delay is greater than the second delay. The input of OR gate 24 is connected to both slow-start control circuit 21 and fast-start control circuit 22, and the output of OR gate 24 is connected to RS flip-flop 23. OR gate 24 is configured to select either the output signal of the slow-start control circuit or the output signal of the fast-start control circuit. RS flip-flop 23 is connected to the output of OR gate 24 and outputs the pulse width modulation signal PWM_i+1 of the (i+1)-th phase. RS flip-flop 23 is configured to achieve different delays between adjacent phases based on different output signals selected by the OR gate. As can be seen in this embodiment, the pulse width modulation signal PWM_i of the i-th phase is transmitted to the RS flip-flop after different delays set in the slow-start control circuit 21 and fast-start control circuit 22 to obtain the pulse width modulation signal of the (i+1)-th phase. Figure 2 The multi-phase delay control circuit 200 can control the delay between adjacent phases according to the system's set switching frequency during the stable period (first delay), and can also shorten the delay between adjacent phases by a smaller delay (second delay) during the unstable period, thereby effectively solving the problem of a significant drop in output voltage caused by the successive and slow opening of all phases, and thus optimizing the transient response of the system.

[0031] Furthermore, such as Figure 3The diagram shown is an exemplary circuit diagram of a fast-start control circuit 22 according to an embodiment of this disclosure. The fast-start control circuit 22 includes: a delay control circuit 221, a selector 222, a first D flip-flop 223, a counter 224, a first AND gate 225, and a first NOT gate 226; wherein, the delay control circuit 221 is configured to control the delay between adjacent phases according to a second delay control; the input terminal of the delay control circuit 221 is connected to the pulse width modulation signal PWM_i of the i-th phase, and the output terminal of the delay control circuit 221 is connected to the second input terminals of the counter 224 and the first AND gate 225 respectively; the selector 222 is configured to control the delay between adjacent phases according to the setting of an external digital signal, and is configured to... The counter 224 controls a preset quantity corresponding to the unstable period. The selector 222 receives external digital data. The input of the selector 222 is also connected to the output signal Q1 of the counter 224. The output of the selector 222 is connected to the first input of the first D flip-flop 223 and the first input of the first AND gate 225 (from top to bottom: first input, second input, third input). The first D flip-flop 223 receives the phase-on indication signal PHASE_ADD, which indicates phase activation. Its high or low state depends on the current external load level of the system. Specifically, when the external load instantaneously switches from light load to heavy load, the PHASE_ADD signal transitions from low to high. The first D flip-flop 223 outputs an enable signal CYC_EN. The output of the first D flip-flop 223 is connected to the counter 224, the third input of the first AND gate 225, and the delay control circuit 221. The output of the first D flip-flop 223 is also connected to the slow-on control circuit 21 through the first NOT gate 226. The counter 224 is configured to cooperate with the selector 222 to control the preset number corresponding to the unstable period. The output of the first AND gate 225 serves as the output of the fast-on control circuit 22 and is connected to one input of the OR gate 24.

[0032] The fast-start control circuit 22 works as follows: when the applied load instantly switches from light load to heavy load, the PHASE_ADD signal flips from low to high, and then the first D flip-flop 223 outputs an enable signal CYC_EN. This enable signal enables the counter 224, and simultaneously disables the slow-start control circuit 21 through the first NOT gate 226. This causes the rising edge of the PWM_i signal to be input to the RS flip-flop 23 through the delay control circuit 221, achieving a second delay between the rising edge of the PWM_i signal and the rising edge of the PWM_i+1 signal. Furthermore, the rising edge of the PWM_i signal is simultaneously input to the counter 224 after passing through the delay control circuit 221. Then, by inputting the output of the counter 224 to the selector 222, the number of PWM_i+1 pulses that rapidly flip to high on the rising edge input to the RS flip-flop 23 can be determined by an external digital setting. This is the number of fast-start cycles during full-phase activation, i.e., the number of cycles corresponding to the unstable cycle (a preset value).

[0033] Furthermore, such as Figure 4 The diagram shown is an exemplary circuit diagram of a multi-phase delay control circuit 200 according to an embodiment of the present disclosure. The delay control circuit 221 includes: a second D flip-flop 2211, a first delay unit 2212, a second delay unit 2213, a second NOT gate 2214, and a second AND gate 2215. The second D flip-flop 2211 includes three input terminals and two output terminals, wherein the first input terminal D is connected to the second output terminal. The second input terminal CLK is connected to the pulse width modulation signal PWM_i of the i-th phase, the third input terminal Reset is connected to the output terminal of the second AND gate 2215, and the first output terminal Q is connected to the input terminal of the first delay unit 2212. The output terminal of the first delay unit 2212 serves as the output terminal of the delay control circuit 221. The output terminal of the first delay unit 2212 is also connected to the input terminal of the second delay unit 2213. The second delay is set in the first delay unit 2212, and the second delay is designed according to the load requirements of the system input voltage under different actual applications. The output terminal of the second delay unit 2213 is connected to the second NOT gate 2214 and then connected to one input terminal of the second AND gate 2215. The other input terminal of the second AND gate 2215 is connected to the output terminal of the first D flip-flop 223.

[0034] The first D flip-flop 223 includes three input terminals and two output terminals, wherein the first input terminal D is connected to the second output terminal. The second input terminal CLk receives the phase-on indication signal PHASE_ADD, the third input terminal Reset is connected to the output terminal of selector 222, the first output terminal Q is connected to counter 224, the third input terminal of first AND gate 225, and delay control circuit 221 respectively, and the first output terminal Q is also connected to slow-on control circuit 21 through first NOT gate 226.

[0035] Counter 224 comprises n D flip-flops: each of the n D flip-flops includes three inputs and two outputs, and the first input D of each D flip-flop is connected to its own second output. The connection is as follows: n is an integer greater than or equal to 1; the second input terminal CLk of the first D flip-flop among the n D flip-flops is connected to the output terminal of the first delay unit 2212, and the second input terminals CLk of the other D flip-flops are connected to the first input terminal D and the second output terminal of the previous D flip-flop. Intermediate nodes; the third input terminals Reset of all n D flip-flops are connected together and connected to the first output terminal Q of the first D flip-flop 223; the second output terminals of all n D flip-flops Connected to the input of selector 222, the second output of all n D flip-flops The corresponding signal is the output signal Q1 of the aforementioned counter.

[0036] The number of bits at the input terminals Bit0 to BitM of the selector 222 that receive external digital data is determined according to the number of D flip-flops in the counter 224.

[0037] The slow-start control circuit 21 includes a third D flip-flop 2101, a third delay unit 2102, a fourth delay unit 2103, a third NOT gate 2104, and a third AND gate 2105. The third D flip-flop 2101 has three input terminals and two output terminals, wherein the first input terminal D is connected to the second output terminal. The second input terminal CLK receives the pulse width modulation signal PWM_i of the i-th phase. The third input terminal Reset is connected to the output of the third AND gate 2105. The first output terminal Q is connected to the input of the third delay unit 2102. The output of the third delay unit 2102 is connected to the other input of the OR gate 24. The output of the third delay unit 2102 is also connected to the input of the fourth delay unit 2103. The output of the fourth delay unit 2103 is connected to the third NOT gate 2104 and then to one input of the third AND gate 2105. The other input of the third AND gate 2105 is connected to the output of the first NOT gate 226. Additionally, it should be noted that the first delay is set in the third delay unit 2102, and the first delay set in the third delay unit 2102 is set externally via Freq_Select.

[0038] RS flip-flop 23 includes two input terminals and two output terminals. The first input terminal R receives the peak sampling signal Ipeak of the inductor current from the (i+1)th phase control circuit. The second input terminal S is connected to the output terminal of OR gate 24. The first output terminal Q outputs the pulse width modulation signal of the (i+1)th phase.

[0039] Additionally, it should be noted that the delays set in the second delay unit 2213 and the fourth delay unit 2103 are both shorter than the second delay. The delays in the second delay unit 2213 and the fourth delay unit 2103 are to clear the output states of the second D flip-flop 2211 and the third D flip-flop 2101, allowing the rising edge of the PWM_i signal in the next cycle to arrive. Therefore, the delays corresponding to the second delay unit 2213 and the fourth delay unit 2103 are relatively small, such as 15ns or 10ns.

[0040] Furthermore, this disclosure also provides an exemplary circuit diagram of a multi-phase delay control circuit 200, such as... Figure 5As shown, the first delay is set to 167ns, the second delay is 100ns, the delays of the second delay unit 2213 and the fourth delay unit 2103 are both 15ns, the counter 224 contains four D flip-flops, the selector 222 has two bits for its external digital input, and the selector 222 is a 4-to-1 selector. Combined with... Figure 5 The circuit principle of the multi-phase delay control circuit 200 disclosed herein is explained as follows: When the applied load instantaneously switches from light load to heavy load, the PHASE_ADD signal transitions from low to high. This enables the counter 224, composed of D flip-flops 1 to 4, via the Q terminal of the first D flip-flop 223. Simultaneously, the enable signal CYC_EN disables the third D flip-flop 2101. The rising edge of the signal PWM_i is then input to the SET terminal (S terminal) of the RS flip-flop 23 via the second D flip-flop 2211 and the first delay unit 2212, achieving a delay of only 100ns from the rising edge of signal PWM_i to the rising edge of signal PWM_i+1. The first delay unit 2212 ensures that the delay from the rising edge of signal PWM_i to the rising edge of signal PWM_i+1 is lower than the fixed delay (167ns) selected by the system's maximum switching frequency, thus enabling rapid activation of the phase. In addition, the rising edge of the PWM_i signal is simultaneously input to the counter 224 through the second D flip-flop 2211 and the first delay unit 2212. By inputting the output of the counter 224 to the 4-to-1 selector 222, the number of PWM_i+1 pulses whose rising edge rapidly flips high at the SET terminal of the RS flip-flop 23 can be determined by the external 2BITS digital setting, i.e., the number of cycles that are rapidly enabled when all-phase is enabled. Specifically, when the external digital is set to 00, the adjacent phase of the previous cycle is enabled with a 100ns delay when the load switches; when the external digital is set to 01, the adjacent phase of the first two cycles is enabled with a 100ns delay when the load switches; when the external digital is set to 10, the adjacent phase of the first four cycles is enabled with a 100ns delay when the load switches; and when the external digital is set to 11, the adjacent phase of the first eight cycles is enabled with a 100ns delay when the load switches. When the selected fast-on cycle ends, the output of selector 222 resets the first D flip-flop 223, and the output of the first AND gate 225 is 0, so the 100ns delay cannot be input to the SET terminal of RS flip-flop 23. The third D flip-flop 2101 is activated, and the 167ns delay is input to RS flip-flop 23, so that the delay between adjacent phases is a fixed phase delay of 167ns selected according to the current system switching frequency, thereby maintaining a uniform energy distribution in steady state.

[0041] To further illustrate the effects of the multi-phase delay control circuit 200 in the embodiments of this disclosure Figure 6 The result of selecting the first two cycles as the fast on cycle is shown. Figure 5The waveforms of timing signals at key nodes in the multi-phase delay control circuit 200 are shown below. From top to bottom, they are: PHASE_ADD signal, CYC_EN signal, PWM_i signal, RE_SET signal corresponding to the Re_set terminals of the second D flip-flop 2211 and the third D flip-flop 2101 (the first two cycles correspond to the second D flip-flop 2211, and the latter to the third D flip-flop 2101), inductor current iL + sampling current iL_SNS, Ipeak signal, and PWM_i+1 signal. Figure 6 As can be seen, after the PHASE_ADD signal goes high, there is a delay of 100ns between the PWM_i signal and the PWM_i+1 signal in the first two cycles, and then it recovers to 167ns.

[0042] In summary, the multi-phase delay control circuit of this disclosure can control the delay between adjacent phases according to the system's set switching frequency during the stable period, and can also shorten the delay between adjacent phases according to a higher switching frequency during the unstable period, thereby effectively solving the problem of a significant drop in output voltage caused by all phases being turned on slowly and successively, and thus optimizing the transient response of the system.

[0043] The descriptions of the same or corresponding module units in the various embodiments of this disclosure can be referenced in turn.

[0044] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0045] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

[0046] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0047] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0048] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A multiphase delay control circuit, characterized by, The multi-phase delay control circuit comprises a slow start control circuit, a fast start control circuit, an OR gate, and an RS flip-flop. The slow start control circuit receives a PWM signal of an i-th phase and is configured to control a delay between adjacent phases according to a first delay in a stable period. The fast start control circuit receives the PWM signal of the i-th phase and is configured to control the delay between the adjacent phases according to a second delay in a non-stable period, the non-stable period being a preset number of periods corresponding to a load switching, and the first delay being greater than the second delay; when an external load is switched from light load to heavy load, the phase start instruction signal is flipped from low to high, and then an enable signal is output by a first D flip-flop, the enable signal is disabled by a first NOT gate, the rising edge of the PWM signal of the i-th phase is input to the RS flip-flop through the delay control circuit, and the delay between the rising edge of the PWM signal of the i-th phase and the rising edge of the PWM signal of an i+1-th phase is the second delay. The OR gate is configured to select an output signal of the slow start control circuit or an output signal of the fast start control circuit. The RS flip-flop is configured to realize different delays between adjacent phases according to different output signals selected by the OR gate. The PWM signal of the i-th phase is transmitted to the RS flip-flop to obtain the PWM signal of the i+1-th phase after being subjected to different delays in the slow start control circuit and the fast start control circuit, and i is an integer greater than 1 or equal to 1.

2. The multiphase delay control circuit of claim 1, wherein, The fast start control circuit comprises a delay control circuit, a selector, a first D flip-flop, a counter, a first AND gate, and a first NOT gate. The delay control circuit is configured to control the delay between the adjacent phases according to the second delay, an input end of the delay control circuit is connected to the PWM signal of the i-th phase, and output ends of the delay control circuit are respectively connected to the counter and a second input end of the first AND gate. The selector is configured to control a preset number corresponding to the non-stable period in cooperation with the counter according to an external number, the selector receives the external number, an input end of the selector is further connected to an output end of the counter, and output ends of the selector are respectively connected to the first D flip-flop and a first input end of the first AND gate. The first D flip-flop receives a phase start instruction signal, an output end of the first D flip-flop is respectively connected to the counter, a third input end of the first AND gate, and the delay control circuit, and the output end of the first D flip-flop is further connected to the slow start control circuit through the first NOT gate. The counter is configured to control the preset number corresponding to the non-stable period in cooperation with the selector. An output end of the first AND gate is connected to one input end of the OR gate as an output end of the fast start control circuit.

3. The multiphase delay control circuit of claim 2, wherein, The delay control circuit comprises a second D flip-flop, a first delay unit, a second delay unit, a second NOT gate, and a second AND gate. The second D flip-flop comprises three input terminals and two output terminals, wherein the first input terminal is connected with the second output terminal, the second input terminal is connected with the i-th phase pulse width modulation signal, and the third input terminal is connected with the output terminal of the second AND gate; the first output terminal is connected with the input terminal of the first delay unit; The output terminal of the first delay unit is the output terminal of the delay control circuit, and the output terminal of the first delay unit is also connected with the input terminal of the second delay unit, and the second delay is set in the first delay unit; The output terminal of the second delay unit is connected with the second NAND gate and one input terminal of the second AND gate; The other input terminal of the second AND gate is connected with the output terminal of the first D flip-flop.

4. The multiphase delay control circuit of claim 3, wherein, The first D flip-flop comprises three input terminals and two output terminals, wherein the first input terminal is connected with the second output terminal, the second input terminal receives the phase-on indication signal, the third input terminal is connected with the output terminal of the selector, the first output terminal is connected with the counter, the third input terminal of the first AND gate and the delay control circuit respectively, and the first output terminal is also connected with the slow-on control circuit through the first NAND gate; 5. The multiphase delay control circuit of claim 4, wherein, The counter comprises n D flip-flops: Each D flip-flop in the n D flip-flops comprises three input terminals and two output terminals, the first input terminal of each D flip-flop is connected with the second output terminal of itself, and n is an integer greater than or equal to 1; The second input terminal of the first D flip-flop in the n D flip-flops is connected with the output terminal of the first delay unit, the second input terminal of the other D flip-flop is connected with the first input terminal and the second output terminal of the previous D flip-flop; The third input terminals of all the n D flip-flops are connected together and connected with the first output terminal of the first D flip-flop; The second output terminals of all the n D flip-flops are connected with the input terminals of the selector.

6. The multiphase delay control circuit of claim 5, wherein, The number of bits of the input terminal of the selector receiving external numbers is determined according to the number of D flip-flops in the counter.

7. The multiphase delay control circuit of claim 2, wherein, The slow-on control circuit comprises a third D flip-flop, a third delay unit, a fourth delay unit, a third NAND gate and a third AND gate: The third D flip-flop comprises three input terminals and two output terminals, wherein the first input terminal is connected with the second output terminal, the second input terminal receives the i-th phase pulse width modulation signal, and the third input terminal is connected with the output terminal of the third AND gate; the first output terminal is connected with the input terminal of the third delay unit; The output terminal of the third delay unit is connected with the other input terminal of the OR gate, and the output terminal of the third delay unit is also connected with the input terminal of the fourth delay unit; the first delay is set in the third delay unit; The output terminal of the fourth delay unit is connected with the third NAND gate and one input terminal of the third AND gate; The other input terminal of the third AND gate is connected with the output terminal of the first NAND gate.

8. The multiphase delay control circuit of claim 7, wherein, The RS flip-flop comprises two input terminals and two output terminals, wherein the first input terminal receives an inductive current peak value sampling signal of an i+1 phase control circuit, the second input terminal is connected with the output terminal of the OR gate, and the first output terminal outputs a pulse width modulation signal of the i+1 phase.

9. The multiphase delay control circuit of claim 7, wherein, The delay time set in the second delay unit and the fourth delay unit is less than the second delay time.

10. The multiphase delay control circuit of claim 6, wherein, The counter comprises four D flip-flops, and the number of bits of the external digital input terminal of the selector is 2.

Images