A physical layer interface verification apparatus, method, device and storage medium

Abstract

The application discloses a physical layer interface verification device, method, equipment and storage medium. The device comprises: a general message processing module, which is used for generating a general verification message and sending the general verification message to a physical layer interface sensing module; and receiving the verification message sent by the physical layer interface sensing module for verification processing; the physical layer interface sensing module is used for calling a verification environment configuration file, driving the general verification message to a first target bus interface according to a first target physical layer chip interface type, and transferring the general verification message to the first target physical layer chip interface; and / or receiving the verification message by a second target bus interface according to a second target physical layer chip interface type and sending the verification message to the general message processing module; wherein the verification environment configuration file comprises configuration information of bus interfaces corresponding to a plurality of physical layer chip interfaces respectively. The application realizes the verification of various physical layer interfaces by using a set of verification environments, reduces the development cost and reduces the risk of verification errors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip function verification, and in particular to a physical layer interface verification device, method, equipment and storage medium. BACKGROUND

[0002] The physical layer interface can connect the media access control (MAC) layer and external devices, and there are various types of interfaces. Some chips may integrate one type of physical layer interface, and some chips may integrate multiple types of physical layer interfaces.

[0003] In the prior art, when verifying the physical layer interface in a chip, a verification environment is built for each type of physical layer interface. However, this approach has the following problems: the number of verification environments increases, more manpower is needed to build and maintain them, resulting in increased labor costs; common code is repeatedly used in different verification environments, and a change or addition needs to be notified to other places in time, otherwise risks will be caused, resulting in increased risks; the unique function code of each type of physical layer interface needs to be effectively separated from the common code, otherwise the verification of other physical layer interfaces will fail. SUMMARY

[0004] The present application provides a physical layer interface verification device, method, equipment and storage medium to solve the problem of the need to build a verification environment for each type of physical layer chip interface, and to achieve the verification of various physical layer chip interfaces using one set of verification environment, thereby reducing development costs and reducing the risk of verification errors.

[0005] According to an aspect of the present application, a physical layer interface verification device is provided, comprising:

[0006] a general message processing module configured to generate a general verification message and send the general verification message to a physical layer interface sensing module, and receive a verification message sent by the physical layer interface sensing module for verification processing;

[0007] a physical layer interface sensing module configured to call a verification environment configuration file, determine a first target physical layer chip interface type and / or a second target physical layer chip interface type, and drive the general verification message to a first target bus interface according to the first target physical layer chip interface type, and transmit the general verification message to the first target physical layer chip interface through the first target bus interface; and / or, according to the second target physical layer chip interface type, determine that a verification message sent by the second target physical layer chip is received by a second target bus interface, and send the verification message to the general message processing module;

[0008] The verification environment configuration file includes configuration information for the bus interfaces corresponding to various physical layer chip interfaces.

[0009] Optionally, the physical layer interface awareness module includes:

[0010] A message conversion unit is used to convert the generalized verification message into an initial byte stream of default width;

[0011] The bus driver unit is used to process the initial byte stream according to the data width of the first target bus interface corresponding to the interface type of the first target physical layer chip to obtain a first byte stream; and drive the first byte stream onto the first target bus interface.

[0012] Optionally, the bus driver unit is specifically used for:

[0013] Based on the data width of the first target bus interface, the initial byte stream of the default width is grouped in order from least significant bit to most significant bit;

[0014] If the data width of the first target bus interface is greater than the default width, then for the initial byte stream in each group, they are concatenated in the order of high byte first and low byte last to obtain the first byte stream;

[0015] If the data width of the first target bus interface is less than or equal to the default width, then the initial byte stream after grouping is used as the first byte stream.

[0016] Optionally, the physical layer interface awareness module includes:

[0017] The data transmission unit is used to obtain the data transmission mode corresponding to the interface type of the first target physical layer chip from the verification environment configuration file;

[0018] If the data transmission mode is serial mode, the first byte stream is transmitted bit by bit to the first target physical layer chip interface through the first target bus interface in order from low bit to high bit.

[0019] If the data transmission mode is parallel mode, then the first byte stream is transmitted to the first target physical layer chip interface in order from low bit to high bit through the first target bus interface, according to the data width of the first target bus interface.

[0020] Optionally, the physical layer interface awareness module includes:

[0021] The message receiving unit is used to receive the second byte stream sent by the second target physical layer chip through the second target bus interface corresponding to the interface type of the second target physical layer chip;

[0022] The second byte stream is grouped and spliced ​​or split to obtain a third byte stream of default width, and the third byte stream is converted into a verification message.

[0023] Optionally, the message receiving unit is specifically used for:

[0024] Obtain the data transmission mode corresponding to the interface type of the second target physical layer chip from the verification environment configuration file;

[0025] If the data transmission mode is serial mode, then the second byte stream is filled bit by bit in order from least significant bit to most significant bit according to the data received from the second target bus interface;

[0026] If the data transmission mode is parallel mode, then according to the data received by the second target bus interface, the second byte stream is filled in order from low bit to high bit according to the data width of the second target bus interface.

[0027] Optionally, the general message processing module is used for:

[0028] If the verification message matches the expected message corresponding to the second target physical layer chip interface type, then the second target physical layer chip interface that matches the second target physical layer chip interface type is determined to be performing normally.

[0029] If the verification message is inconsistent with the expected message corresponding to the second target physical layer chip interface type, then the performance of the second target physical layer chip interface that matches the second target physical layer chip interface type is determined to be abnormal.

[0030] According to another aspect of the present invention, a physical layer interface verification method is provided, comprising:

[0031] The general message processing module generates a generalized verification message and sends the generalized verification message to the physical layer interface awareness module.

[0032] The physical layer interface sensing module calls the verification environment configuration file to determine the interface type of the first target physical layer chip and / or the interface type of the second target physical layer chip.

[0033] The physical layer interface sensing module drives the generalized verification message to the first target bus interface according to the interface type of the first target physical layer chip, and transmits the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or,

[0034] The physical layer interface sensing module determines, based on the interface type of the second target physical layer chip, that the verification message sent by the second target physical layer chip is received by the second target bus interface, and sends the verification message to the general message processing module.

[0035] The general message processing module receives and processes the verification messages sent by the physical layer interface sensing module.

[0036] The verification environment configuration file includes configuration information for the bus interfaces corresponding to various physical layer chip interfaces.

[0037] The verification environment configuration file includes configuration information for the bus interfaces corresponding to various physical layer chip interfaces.

[0038] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0039] At least one processor; and

[0040] A memory that is communicatively connected to at least one processor; wherein,

[0041] The memory stores a computer program that can be executed by at least one processor, such that the at least one processor is able to execute a physical layer interface verification method according to any embodiment of the present invention.

[0042] According to another aspect of the present invention, a computer-readable storage medium is provided, which stores computer instructions for causing a processor to execute and implement a physical layer interface verification method according to any embodiment of the present invention.

[0043] This invention provides a physical layer interface verification device, comprising a general message processing module for generating a generalized verification message and sending it to a physical layer interface sensing module; and receiving verification messages sent by the physical layer interface sensing module for verification processing; the physical layer interface sensing module for invoking a verification environment configuration file to determine a first target physical layer chip interface type and / or a second target physical layer chip interface type; driving the generalized verification message to a first target bus interface according to the first target physical layer chip interface type, and transmitting the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or, determining, according to the second target physical layer chip interface type, that the second target bus interface receives the verification message sent by the second target physical layer chip, and sending the verification message to the general message processing module; wherein the verification environment configuration file includes configuration information of bus interfaces corresponding to various physical layer chip interfaces.

[0044] This invention transcends the low-level verification approach of physical layer chip interfaces. Based on the premise that all physical layer chip interfaces must implement parallel-to-serial or serial-to-parallel conversion functions and ensure correct data transmission, it verifies physical layer chip interfaces from the protocol layer. This allows for the use of a single verification environment to verify multiple physical layer chip interfaces, solving the problem of needing to build separate verification environments for verifying multiple physical layer chip interfaces. It achieves the beneficial effects of using a single verification environment to verify various physical layer chip interfaces, reducing development costs, and lowering the risk of verification errors.

[0045] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a physical layer interface verification device according to Embodiment 1 of the present invention;

[0048] Figure 2 This is a flowchart of a physical layer interface verification method provided in Embodiment 2 of the present invention;

[0049] Figure 3 This is a verification diagram of a physical layer interface applicable to Embodiment 2 of the present invention;

[0050] Figure 4 This is a schematic diagram of a message structure applicable to Embodiment 2 of the present invention;

[0051] Figure 5 This is a schematic diagram of an initial byte stream structure adapted according to Embodiment 2 of the present invention;

[0052] Figure 6 This is a schematic diagram of a serial data transmission method applicable to Embodiment 2 of the present invention;

[0053] Figure 7 This is a schematic diagram of a parallel data transmission method applicable to Embodiment 2 of the present invention;

[0054] Figure 8 This is a schematic diagram of a serial data receiving method applicable to Embodiment 2 of the present invention;

[0055] Figure 9 This is a schematic diagram of a parallel data receiving method applicable to Embodiment 2 of the present invention;

[0056] Figure 10 This is a schematic diagram of the structure of an electronic device that implements a physical layer interface verification method according to an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] Example 1

[0060] Figure 1 This is a schematic diagram of a physical layer interface verification device according to Embodiment 1 of the present invention. This embodiment is applicable to situations where a common verification environment is used to uniformly verify multiple physical layer chip interfaces integrated in a physical layer chip. Figure 1 As shown, the device includes:

[0061] The general message processing module 110 is used to generate a generalized verification message and send the generalized verification message to the physical layer interface awareness module 120; and to receive the verification message sent by the physical layer interface awareness module 120 and perform verification processing.

[0062] The physical layer interface sensing module 120 is used to call the verification environment configuration file to determine the interface type of the first target physical layer chip and / or the interface type of the second target physical layer chip; and to drive the generalized verification message to the first target bus interface according to the interface type of the first target physical layer chip, and to transmit the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or, to determine, according to the interface type of the second target physical layer chip, to receive the verification message sent by the second target physical layer chip by the second target bus interface, and to send the verification message to the generalized message processing module 110;

[0063] The verification environment configuration file includes configuration information for the bus interfaces corresponding to various physical layer chip interfaces.

[0064] The physical layer chip can integrate various types of physical layer chip interfaces, such as GPHY, T1PHY, SPCS+SerDes, and XPCS+SerDes interfaces. The verification environment can be used to perform functional simulation verification of any one of the physical layer chip interfaces. The verification environment configuration file includes configuration information for the bus interfaces corresponding to the various physical layer chip interfaces, including: the physical layer chip interface, the bus interface that matches the physical layer chip interface, and the data width corresponding to the bus interface.

[0065] In this embodiment, the generalized verification message can be configured as an IPV4 message, an IPV6 message, or other types of messages. The first target physical layer chip interface is the interface of the first target physical layer chip that performs performance verification using the generalized verification message sent by the local physical layer chip. The first target bus interface is the bus interface configured for the first target physical layer chip interface. The second target physical layer chip interface is the interface in the local physical layer chip that performs performance verification using the generalized verification message sent by the second target physical layer chip. The second target bus interface is the bus interface configured for the second target physical layer chip interface.

[0066] In this embodiment, to achieve the goal of verifying various physical layer chip interfaces integrated in the physical layer chip using a single verification environment, interface verification is no longer performed at the physical layer level, but rather at the network protocol layer. Based on the characteristics of physical layer chip interfaces during data transmission—namely, the need to convert parallel to serial or serial to parallel while ensuring data accuracy—a verification mechanism is implemented to verify various physical layer chip interfaces. Therefore, when verifying whether a physical layer chip interface in a physical layer chip is functioning effectively, the configuration information of the bus interface of that physical layer chip interface is read from a uniformly configured verification environment configuration file to determine the bus interface that matches the physical layer chip interface. For example, the Media Independent Interface (MII) might match the GPHY interface of the physical layer chip. A generic verification message generated by the local device is then transmitted to the physical layer chip interface to be verified via this bus interface, or a generic verification message generated by other devices is transmitted to the physical layer chip interface to be verified within the local physical layer chip. Finally, the validity of the physical layer chip interface is determined by comparing the received verification message with a known expected message.

[0067] Optionally, the physical layer interface sensing module includes: a message conversion unit, used to convert the generalized verification message into an initial byte stream of default width; and a bus driving unit, used to process the initial byte stream according to the data width of the first target bus interface corresponding to the first target physical layer chip interface type to obtain a first byte stream; and to drive the first byte stream onto the first target bus interface.

[0068] In this embodiment, before sending the generalized verification message to the first target physical layer chip interface of the first physical layer chip for verification, the generalized verification message needs to be converted into an 8-bit wide initial byte stream (i.e., an 8-bit array) that can be transmitted at the physical layer by a message conversion unit. To send the initial byte stream through the first target bus interface, the bus driver unit concatenates or splits the 8-bit wide initial byte stream according to the data width supported by the first target bus interface, obtaining a first byte stream with a data width that meets the transmission requirements of the first target bus interface. The first byte stream is then sent to the first target physical layer chip interface of the first physical layer chip through the first target bus interface, that is, to the first target pin corresponding to the first target bus interface. The first target pin is related to the data transmission mode.

[0069] Optionally, the bus driver unit is specifically configured to: group the initial byte stream of the default width according to the data width of the first target bus interface, in order from low to high bits; if the data width of the first target bus interface is greater than the default width, then for the initial byte stream in each group, concatenate them in order of high bits first and low bits last to obtain a first byte stream; if the data width of the first target bus interface is less than or equal to the default width, then use the grouped initial byte stream as the first byte stream.

[0070] For example, if the first target bus interface is an XGMII interface, then a 32-bit wide array data[31:0] needs to be obtained. Since 32 bits is four times the default 8-bit width, in the initial byte stream byte_item, data of 4 8-bit widths are grouped together in ascending order of low to high bits. Within each group, the data is concatenated in ascending order of high bits first, resulting in the first byte stream data[31:0]. Specifically, the first 32-bit data in data[31:0] is the concatenation of data[7:0][3], data[7:0][2], data[7:0][1], and data[7:0][0] from byte_item; the second 32-bit data is the concatenation of data[7:0][7], data[7:0][6], data[7:0][5], and data[7:0][4] from byte_item; and so on.

[0071] For example, if the target bus interface is an MII interface, then a 4-bit wide array data[3:0] needs to be obtained. Since 4 bits is half the default 8-bit width, in the initial byte stream byte_item, each half of the 8-bit wide data can be grouped together in ascending order of the least significant bit, resulting in the first byte stream data[3:0]. Specifically, the first 4-bit wide data in data[3:0] is data[3:0][0] in byte_item; the second 4-bit wide data is data[7:4][0] in byte_item; the third 4-bit wide data is data[3:0][1] in byte_item; the fourth 4-bit wide data is data[7:4][1] in byte_item; and so on.

[0072] Optionally, the physical layer interface sensing module includes: a data transmission unit, configured to obtain a data transmission mode corresponding to the first target physical layer chip interface type from the verification environment configuration file; if the data transmission mode is a serial mode, then the first byte stream is transmitted to the first target physical layer chip interface in bit order from low bit to high bit through the first target bus interface; if the data transmission mode is a parallel mode, then the first byte stream is transmitted to the first target physical layer chip interface in order from low bit to high bit according to the data width of the first target bus interface through the first target bus interface.

[0073] In this embodiment, the data transmission unit can read the data transmission mode in the verification environment configuration file and, in combination with the data width corresponding to the first target bus interface, send the first byte stream to the first target pin on the first physical layer chip corresponding to the first target bus interface. For example, if the data transmission mode is serial, the bits of the first byte stream are obtained bit by bit, starting from the least significant bit, and each bit is sequentially sent to the serial pin on the first physical layer chip. If the data transmission mode is parallel, the first byte stream is sent to the parallel pin on the first physical layer chip, starting from the least significant bit, according to the data width of the first target bus interface. For example, when the first target bus interface is an XGMII interface, each 32-bit width of data in the first byte stream data[31:0], data[31:0][0], data[31:0][1], etc., is sequentially sent to the parallel pin on the first physical layer chip; the same applies when the first target bus interface is another type of bus interface.

[0074] Optionally, the physical layer interface sensing module includes: a message receiving unit, configured to receive a second byte stream sent by the second target physical layer chip through a second target bus interface corresponding to the interface type of the second target physical layer chip; perform grouping and splicing or splitting processing on the second byte stream to obtain a third byte stream of default width; and convert the third byte stream into a verification message.

[0075] In this embodiment, when verifying the interface of the second target physical layer chip of the local physical layer chip based on the verification message sent by the second target physical layer chip, the message receiving unit obtains the value of the second target pin corresponding to the second target bus interface in the second target physical layer chip, and generates a second byte stream of a specified width according to the data transmission mode. Then, based on the relationship between the data width of the second byte stream and the default width, the second byte stream is spliced ​​or split to generate a third byte stream with a width of 8 bits, and the third byte stream is converted into a verification message.

[0076] Optionally, the message receiving unit is specifically configured to: obtain, from the verification environment configuration file, a data transmission mode corresponding to the interface type of the second target physical layer chip; if the data transmission mode is a serial mode, then fill the second byte stream bit by bit according to the data received from the second target bus interface in the order of least bit to most bit; if the data transmission mode is a parallel mode, then fill the second byte stream according to the data width of the second target bus interface in the order of least bit to most bit according to the data received from the second target bus interface.

[0077] In this embodiment, the message receiving unit can receive the second byte stream from the second target pin of the second target physical layer chip by reading the data transmission mode in the verification environment configuration file and combining it with the data width corresponding to the second target bus interface. For example, if the data transmission mode is serial, the value on the serial pin of the second target physical layer chip is obtained, and the second byte stream is filled bit-by-bit starting from the least significant bit. If the data transmission mode is parallel, the value on the parallel pin of the second target physical layer chip is obtained, and the second byte stream is filled according to the data width of the second target bus interface, starting from the least significant bit. For example, when the second target bus interface is an XGMII interface, the 32-bit value on the parallel pin of the second target physical layer chip is placed in the lower 32 bits of the second byte stream; when the second target bus interface is a GMII interface, the 8-bit value on the parallel pin of the second target physical layer chip is placed in the lower 8 bits of the second byte stream; and so on when the second target bus interface is another type of bus interface.

[0078] Optionally, the general message processing module is configured to: if the verification message is consistent with the expected message corresponding to the second target physical layer chip interface type, determine that the performance of the second target physical layer chip interface matching the second target physical layer chip interface type is normal; if the verification message is inconsistent with the expected message corresponding to the second target physical layer chip interface type, determine that the performance of the second target physical layer chip interface matching the second target physical layer chip interface type is abnormal.

[0079] The expected message refers to the message ultimately received by the second target physical layer chip interface after the generalized verification message has undergone serial-to-parallel or parallel-to-serial conversion, assuming the second target physical layer chip interface is functioning normally. In this embodiment, the generalized message processing module parses the verification message and compares it with the expected message to determine whether the second target physical layer chip interface guarantees the correctness of the transmitted data. Since the second target physical layer interface completes parallel-to-serial or serial-to-parallel conversion during data transmission, as long as the transmitted data is correct, the second target physical layer chip interface connection can be considered normal.

[0080] The physical layer interface verification device provided in this embodiment of the invention includes a general message processing module for generating a generalized verification message and sending the generalized verification message to a physical layer interface sensing module; and receiving the verification message sent by the physical layer interface sensing module for verification processing; the physical layer interface sensing module is used to call a verification environment configuration file to determine a first target physical layer chip interface type and / or a second target physical layer chip interface type; and to drive the generalized verification message to a first target bus interface according to the first target physical layer chip interface type, and transmit the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or, according to the second target physical layer chip interface type, determine that the second target bus interface receives the verification message sent by the second target physical layer chip, and send the verification message to the general message processing module; wherein, the verification environment configuration file includes configuration information of bus interfaces corresponding to various physical layer chip interfaces, which solves the problem that verification of multiple physical layer interfaces requires separate construction of verification environments, realizes the use of a single verification environment to verify various physical layer chip interfaces, reduces development costs, and reduces the risk of verification errors.

[0081] Example 2

[0082] Figure 2 This is a flowchart of a physical layer interface verification method according to Embodiment 2 of the present invention. This embodiment is applicable to situations where a common verification environment is used to uniformly verify multiple physical layer chip interfaces integrated in a physical layer chip. This method can be executed by a physical layer interface verification device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 2 As shown, the method includes:

[0083] S210. Generate a generalized verification message through the generalized message processing module, and send the generalized verification message to the physical layer interface awareness module.

[0084] In this embodiment, it can be used as Figure 3The following diagram illustrating the verification process of a physical layer interface serves as an example. In this diagram, the data transmission mode in the sending direction (TX) is serial, and the data transmission mode in the receiving direction (RX) is parallel. The sending direction can be the local physical layer chip sending a generic verification message to a first target physical layer chip to perform performance verification on the first target physical layer chip's interface. The receiving direction can be the local physical layer chip receiving a generic verification message sent by a second target physical layer chip to perform performance verification on the second target physical layer chip's interface. When performance verification of the first target physical layer chip's interface is required, a generic verification message (ethernet_item) is generated by the generic message processing module and sent to the physical layer interface sensing module.

[0085] For example, such as Figure 4 As shown, the fields contained in ethernet_item are: destination MAC address dmac, source MAC address smac, message type eth_type, payload content and frame check sequence FCS.

[0086] S220. Through the physical layer interface sensing module, call the verification environment configuration file to determine the interface type of the first target physical layer chip and / or the interface type of the second target physical layer chip.

[0087] The verification environment configuration file includes configuration information for bus interfaces corresponding to various physical layer chip interfaces. The first target physical layer chip interface is the interface of the first target physical layer chip used for performance verification via a generic verification message sent by the local physical layer chip; the first target bus interface is the bus interface configured for the first target physical layer chip interface. The second target physical layer chip interface is the interface in the local physical layer chip used for performance verification via a generic verification message sent by the second target physical layer chip; the second target bus interface is the bus interface configured for the second target physical layer chip interface.

[0088] S230. Through the physical layer interface sensing module, the generalized verification message is driven to the first target bus interface according to the interface type of the first target physical layer chip, and the generalized verification message is transmitted to the first target physical layer chip interface through the first target bus interface.

[0089] Optionally, driving the generalized verification message to the first target bus interface according to the first target physical layer chip interface type includes: converting the generalized verification message into an initial byte stream of default width through a message conversion unit; processing the initial byte stream according to the data width of the first target bus interface corresponding to the first target physical layer chip interface type through a bus driving unit to obtain a first byte stream; and driving the first byte stream to the first target bus interface.

[0090] In this embodiment, through Figure 3 In the transmission direction, the message conversion unit `item_trans` packages all fields in the generalized authentication message `ethernet_item` into 8-bit wide data and stores it in an array, resulting in... Figure 5 The initial byte stream `byte_item` is shown. The default width is not limited to 8; it can be adjusted to other values ​​as needed. Figure 3 In the transmission direction, the bus driver unit (bfm) reads the first target bus interface that matches the interface type of the first target physical layer chip from the verification environment configuration file. According to the data width supported by the first target bus interface, it organizes the initial byte stream byte_item into a first byte stream whose data width meets the transmission requirements of the first target bus interface, and drives the first byte stream onto the first target bus interface.

[0091] For example, if the first target bus interface is a 10Gigabit Media Independent Interface (XGMII), the initial byte stream is organized into a 32-bit wide array; if the first target bus interface is a Gigabit Media Independent Interface (GMII), the initial byte stream is organized into an 8-bit wide array; if the first target bus interface is an MII bus interface, the initial byte stream is organized into a 4-bit wide array; and if the first target bus interface is a Reduced Media Independent Interface (RMII), the initial byte stream is organized into a 4-bit wide array.

[0092] Optionally, the initial byte stream is processed by the bus driver unit according to the data width of the first target bus interface corresponding to the first target physical layer chip interface type to obtain a first byte stream, including: grouping the initial byte stream of the default width according to the data width of the first target bus interface in order from low to high bits; if the data width of the first target bus interface is greater than the default width, then for the initial byte stream in each group, concatenating them in order of high bits first and low bits last to obtain a first byte stream; if the data width of the first target bus interface is less than or equal to the default width, then using the grouped initial byte stream as the first byte stream.

[0093] For example, if the first target bus interface is an XGMII interface, then a 32-bit wide array data[31:0] needs to be obtained. Since 32 bits is four times the default 8-bit width, in the initial byte stream byte_item, data of 4 8-bit widths are grouped together in ascending order of low to high bits. Within each group, the data is concatenated in ascending order of high bits first, to obtain the first byte stream data[31:0]. Specifically, the first 32-bit wide data in data[31:0] is the concatenation of data[7:0][3], data[7:0][2], data[7:0][1], and data[7:0][0] from byte_item; the first 32-bit wide data is the concatenation of data[7:0][7], data[7:0][6], data[7:0][5], and data[7:0][4] from byte_item; and so on.

[0094] For example, if the first target bus interface is an MII interface, then a 4-bit wide array data[3:0] needs to be obtained. Since 4 bits is half the default 8-bit width, in the initial byte stream byte_item, each half of the 8-bit wide data can be grouped together in ascending order of the least significant bit, resulting in the first byte stream data[3:0]. Specifically, the first 4-bit wide data in data[3:0] is data[3:0][0] in byte_item; the second 4-bit wide data is data[7:4][0] in byte_item; the third 4-bit wide data is data[3:0][1] in byte_item; the fourth 4-bit wide data is data[7:4][1] in byte_item; and so on.

[0095] Among them, Figure 3In the data[127:0] obtained after processing by the bus driver unit bfm in the transmission direction, it is indicated that the maximum data width of the first byte stream can be 128.

[0096] Optionally, transmitting the generalized verification message to the first target physical layer chip interface via the first target bus interface includes: obtaining a data transmission mode corresponding to the type of the first target physical layer chip interface from the verification environment configuration file via the data transmission unit; if the data transmission mode is a serial mode, transmitting the first byte stream to the first target physical layer chip interface bit-by-bit in order from least significant bit to most significant bit via the first target bus interface; if the data transmission mode is a parallel mode, transmitting the first byte stream to the first target physical layer chip interface according to the data width of the first target bus interface in order from least significant bit to most significant bit via the first target bus interface.

[0097] In this embodiment, the data transmission unit Connect in the sending direction can read the data transmission mode in the verification environment configuration file, and in combination with the data width corresponding to the target bus interface, send the first byte stream to the first target pin of the first target physical layer chip. For example, as shown... Figure 6 As shown, in serial mode, the bits of the first byte stream are acquired bit by bit, starting from the least significant bit, and each bit is sequentially sent to the serial pin of the first target physical layer chip. Figure 6 In the diagram, rxm, mdi_p, and rxp are the names of the serial pins corresponding to each bus interface. They are used to distinguish the various bus interfaces in the transmission direction. The chip may have only one serial pin or multiple serial pins. A serial pin can be pre-configured for each bus interface, but when verifying the physical layer interface, it is necessary to ensure that all serial pins can work properly.

[0098] For example, such as Figure 7 As shown, if the data transmission mode is parallel mode, the first byte stream is sent to the parallel pins of the first target physical layer chip, starting from the least significant bit, according to the data width of the first target bus interface. For example, when the first target bus interface is an XGMII interface, the 32-bit data in the first byte stream data[31:0], data[31:0][0], data[31:0][1], etc., are sent sequentially to the parallel pins of the first target physical layer chip; the same logic applies when the first target bus interface is another type of bus interface. Figure 7xgmii_rxd, gmii_rxd, mii_rxd, and rmii_rxd in the diagram are the names of the parallel pins corresponding to each bus interface. They are used to distinguish the various bus interfaces in the transmission direction in the diagram. The chip may have only one parallel pin or multiple parallel pins. A parallel pin can be pre-configured for each bus interface, but when verifying the physical layer interface, it is necessary to ensure that all parallel pins can work properly.

[0099] In this embodiment, the message conversion unit, bus driver unit, and data transmission unit are reusable. Regardless of the type of physical layer chip interface under test, these code blocks can be directly used in both the sending and receiving directions according to the configuration. This allows for the verification of any type of physical layer chip interface using a single verification mechanism and environment, reducing manpower investment and development costs. Simultaneously, it avoids the repeated use of duplicate code in multiple verification environments, reducing the workload of code modification and communication when duplicate code is modified, thus mitigating risk. Furthermore, it effectively isolates the code for unique functions of various physical layer chip interfaces, such as code for data processing based on different bus interface types, eliminating mutual interference between the physical layer interface and the verification environment.

[0100] S240. Through the physical layer interface sensing module, determine the verification message sent by the second target physical layer chip by the second target bus interface according to the interface type of the second target physical layer chip, and send the verification message to the general message processing module.

[0101] In this embodiment, the physical layer interface sensing module can not only send the generalized verification message generated by the local physical layer chip to other physical layer chips, such as the first target physical layer chip, to verify the physical layer chip interface, but also receive generalized verification messages sent by other physical layer chips, such as the second target physical layer chip, to perform performance verification on the second target physical layer chip interface of the local physical layer chip.

[0102] Optionally, based on the interface type of the second target physical layer chip, it is determined that the verification message sent by the second target physical layer chip will be received by the second target bus interface, including: receiving the second byte stream sent by the second target physical layer chip through the message receiving unit via the second target bus interface corresponding to the interface type of the second target physical layer chip; performing group splicing or splitting processing on the second byte stream to obtain a third byte stream of default width; and converting the third byte stream into a verification message.

[0103] In this embodiment, when verifying the interface of the second target physical layer chip of the local physical layer chip based on the verification message sent by the second target physical layer chip, the message receiving unit obtains the value of the second target pin corresponding to the second target bus interface in the second target physical layer chip, and generates a second byte stream of a specified width according to the data transmission mode. Then, based on the relationship between the data width of the second byte stream and the default width, the second byte stream is spliced ​​or split to generate a third byte stream with a width of 8 bits, and the third byte stream is converted into a verification message.

[0104] Optionally, receiving the second byte stream sent by the second target physical layer chip through the second target bus interface corresponding to the interface type of the second target physical layer chip includes: obtaining the data transmission mode corresponding to the interface type of the second target physical layer chip from the verification environment configuration file; if the data transmission mode is serial mode, then filling the second byte stream bit by bit according to the data received by the second target bus interface in the order of least significant bit to most significant bit; if the data transmission mode is parallel mode, then filling the second byte stream according to the data width of the second target bus interface in the order of least significant bit to most significant bit according to the data received by the second target bus interface.

[0105] In this embodiment, the data transmission unit Connect in the receiving direction can read the data transmission mode in the verification environment configuration file, and in combination with the data width corresponding to the second target bus interface, receive the second byte stream from the second target pin of the second target physical layer chip. For example, as shown... Figure 8 As shown, if it is in serial mode, the value on the chip's serial pin is obtained and filled bit by bit starting from the least significant bit of the second byte stream. Wherein, Figure 8 In the diagram, txm, mdo_p, and txp are the names of the serial pins corresponding to each bus interface. They are used to distinguish the various bus interfaces in the receiving direction. The second target physical layer chip may have only one serial pin or multiple serial pins. A serial pin can be pre-configured for each bus interface, but when verifying the physical layer interface, it is necessary to ensure that all serial pins can work properly.

[0106] For example, such as Figure 9As shown, in parallel mode, the value from the parallel pin of the second target physical layer chip is obtained, and the data is filled starting from the low-order bits of the second byte stream according to the data width of the second target bus interface. For example, when the second target bus interface is an XGMII interface, the 32-bit value from the parallel pin of the physical layer chip is placed in the lower 32 bits of the second byte stream; when the second target bus interface is a GMII interface, the 8-bit value from the parallel pin of the physical layer chip is placed in the lower 8 bits of the second byte stream; and so on for other types of bus interfaces. Figure 9 xgmii_txd, gmii_txd, mii_txd, and rmii_txd in the diagram are the names of the parallel pins corresponding to each bus interface. They are used to distinguish the various bus interfaces in the receiving direction in the diagram. The second target physical layer chip may have only one parallel pin or multiple parallel pins. A parallel pin can be pre-configured for each bus interface, but when verifying the physical layer interface, it is necessary to ensure that all parallel pins can work properly.

[0107] If data with the same width as the data width of the second target bus interface cannot be obtained from the second target pin of the second target physical layer chip, the interface of the second target physical layer chip may malfunction.

[0108] S250. The verification message sent by the physical layer interface sensing module is received and verified through the general message processing module.

[0109] Optionally, a general message processing module receives the verification message sent by the physical layer interface sensing module and performs verification processing, including: if the verification message is consistent with the expected message corresponding to the second target physical layer chip interface type, then it is determined that the performance of the second target physical layer chip interface matching the second target physical layer chip interface type is normal; if the verification message is inconsistent with the expected message corresponding to the second target physical layer chip interface type, then it is determined that the performance of the second target physical layer chip interface matching the second target physical layer chip interface type is abnormal.

[0110] The technical solution of this invention involves generating a generalized verification message through a generalized message processing module and sending the generalized verification message to a physical layer interface sensing module. The physical layer interface sensing module then calls a verification environment configuration file to determine the interface type of a first target physical layer chip and / or a second target physical layer chip. Based on the first target physical layer chip interface type, the generalized verification message is driven onto a first target bus interface, and the generalized verification message is transmitted to the first target physical layer chip interface through the first target bus interface. Alternatively, based on the second target physical layer chip interface type, the physical layer interface sensing module determines that the verification message sent by the second target physical layer chip will be received by the second target bus interface, and sends the verification message to the generalized message processing module. The generalized message processing module receives the verification message sent by the physical layer interface sensing module and performs verification processing. The verification environment configuration file includes configuration information for the bus interfaces corresponding to various physical layer chip interfaces. This solves the problem of needing to build separate verification environments for verifying multiple physical layer interfaces, enabling the use of a single verification environment to verify various physical layer chip interfaces, reducing development costs and the risk of verification errors.

[0111] Example 3

[0112] Figure 10 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0113] like Figure 10As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0114] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0115] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as physical layer interface verification methods.

[0116] In some embodiments, the physical layer interface verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the physical layer interface verification method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the physical layer interface verification method by any other suitable means (e.g., by means of firmware).

[0117] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0118] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0119] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0120] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0121] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0122] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0123] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A physical layer interface verification device, characterized in that, include: A general message processing module is used to generate a generalized verification message and send the generalized verification message to the physical layer interface awareness module. And receive the verification message sent by the physical layer interface sensing module and perform verification processing; The physical layer interface awareness module is used to call the verification environment configuration file to determine the interface type of the first target physical layer chip and / or the interface type of the second target physical layer chip; and to drive the generalized verification message to the first target bus interface according to the interface type of the first target physical layer chip, and to transmit the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or, to determine, according to the interface type of the second target physical layer chip, that the verification message sent by the second target physical layer chip is received by the second target bus interface, and to send the verification message to the generalized message processing module; The physical layer interface sensing module includes: A message conversion unit is used to convert the generalized verification message into an initial byte stream of default width; The bus driver unit is used to process the initial byte stream according to the data width of the first target bus interface corresponding to the interface type of the first target physical layer chip to obtain a first byte stream; and drive the first byte stream onto the first target bus interface. The verification environment configuration file includes configuration information for bus interfaces corresponding to various physical layer chip interfaces; the first target physical layer chip interface is the interface of the first target physical layer chip that performs performance verification using a generalized verification message sent by the local physical layer chip; the second target physical layer chip interface is the interface of the local physical layer chip that performs performance verification using a generalized verification message sent by the second target physical layer chip.

2. The apparatus according to claim 1, characterized in that, The bus driver unit is specifically used for: Based on the data width of the first target bus interface, the initial byte stream of the default width is grouped in order from least significant bit to most significant bit; If the data width of the first target bus interface is greater than the default width, then for the initial byte stream in each group, they are concatenated in the order of high byte first and low byte last to obtain the first byte stream; If the data width of the first target bus interface is less than or equal to the default width, then the initial byte stream after grouping is used as the first byte stream.

3. The apparatus according to claim 1, characterized in that, The physical layer interface sensing module includes: The data transmission unit is used to obtain the data transmission mode corresponding to the interface type of the first target physical layer chip from the verification environment configuration file; If the data transmission mode is serial mode, the first byte stream is transmitted bit by bit to the first target physical layer chip interface through the first target bus interface in order from low bit to high bit. If the data transmission mode is parallel mode, the first byte stream is transmitted to the first target physical layer chip interface in order from low bit to high bit through the first target bus interface, according to the data width of the first target bus interface.

4. The apparatus according to claim 1, characterized in that, The physical layer interface sensing module includes: The message receiving unit is used to receive the second byte stream sent by the second target physical layer chip through the second target bus interface corresponding to the interface type of the second target physical layer chip; The second byte stream is grouped and spliced ​​or split to obtain a third byte stream of default width, and the third byte stream is converted into a verification message.

5. The apparatus according to claim 4, characterized in that, The message receiving unit is specifically used for: Obtain the data transmission mode corresponding to the interface type of the second target physical layer chip from the verification environment configuration file; If the data transmission mode is serial mode, then the second byte stream is filled bit by bit in order from least significant bit to most significant bit according to the data received from the second target bus interface; If the data transmission mode is parallel mode, then according to the data received by the second target bus interface, the second byte stream is filled in order from low bit to high bit according to the data width of the second target bus interface.

6. The apparatus according to claim 1, characterized in that, The general message processing module is used for: If the verification message matches the expected message corresponding to the second target physical layer chip interface type, then the second target physical layer chip interface that matches the second target physical layer chip interface type is determined to be functioning normally. If the verification message is inconsistent with the expected message corresponding to the second target physical layer chip interface type, then the performance of the second target physical layer chip interface that matches the second target physical layer chip interface type is determined to be abnormal.

7. A physical layer interface verification method, characterized in that, include: The general message processing module generates a generalized verification message and sends the generalized verification message to the physical layer interface awareness module. The physical layer interface sensing module calls the verification environment configuration file to determine the interface type of the first target physical layer chip and / or the interface type of the second target physical layer chip. The physical layer interface sensing module drives the generalized verification message to the first target bus interface according to the interface type of the first target physical layer chip, and transmits the generalized verification message to the first target physical layer chip interface through the first target bus interface; and / or, The physical layer interface sensing module determines, based on the interface type of the second target physical layer chip, that the verification message sent by the second target physical layer chip is received by the second target bus interface, and sends the verification message to the general message processing module. The general message processing module receives and processes the verification messages sent by the physical layer interface sensing module. The step of driving the generalized verification message onto the first target bus interface according to the interface type of the first target physical layer chip includes: The message conversion unit converts the generalized verification message into an initial byte stream of default width. The initial byte stream is processed by the bus driver unit according to the data width of the first target bus interface corresponding to the interface type of the first target physical layer chip to obtain the first byte stream; the first byte stream is then driven onto the first target bus interface. The verification environment configuration file includes configuration information for bus interfaces corresponding to various physical layer chip interfaces; the first target physical layer chip interface is the interface of the first target physical layer chip that performs performance verification using a generalized verification message sent by the local physical layer chip; the second target physical layer chip interface is the interface of the local physical layer chip that performs performance verification using a generalized verification message sent by the second target physical layer chip.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the physical layer interface verification method of claim 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute and implement the physical layer interface verification method of claim 7.

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