Imaging device

Abstract

An imaging device includes: an image sensing device, which includes one or more first image detection pixels and one or more second image detection pixels configured to convert light incident on the image detection pixels into pixel signals representing an image; a first transistor, which is connected to the one or more first image detection pixels and is configured to generate physically unclonable function PUF data including information about at least one fixed pattern noise FPN data and at least one random telegraph noise RTN data; and a second transistor, which is connected to the one or more second image detection pixels and is configured to generate image data acquired by converting light corresponding to the image; a private key generation unit, which is configured to generate a private key based on at least one FPN data and at least one RTN data of the PUF data; and an image encryption unit, which is configured to encrypt the image data using the private key.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to imaging devices having encryption functions for image data. Background Art

[0002] An image sensing device is a semiconductor device for capturing light of an optical image and converting the light of the optical image into an electrical signal for displaying the captured image and for further processing the captured image. Recent developments in various industries and sectors including the automotive, medical, computer, and communication industries have created various demands for high-performance image sensors in various devices such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, security cameras, and medical micro cameras.

[0003] Image sensing devices can be roughly divided into CCD (charge coupled device) image sensing devices and CMOS (complementary metal oxide semiconductor) image sensing devices. CCD image sensing devices provide better image quality, but CCD image sensing devices tend to consume more power and are larger than CMOS image sensing devices. CMOS image sensing devices are smaller in size and consume less power than CCD image sensing devices. In addition, CMOS sensors are manufactured using CMOS manufacturing technology, and therefore photosensors and other signal processing circuits can be integrated into a single chip, enabling miniaturized image sensing devices to be produced at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications including mobile devices. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to an imaging device having an encryption function with high stability against hacking of image data.

[0005] According to an embodiment of the disclosed technology, an imaging device may include: an image sensing device, the image sensing device including: an image generator configured to generate image data by converting incident light carrying an image into an electrical signal indicating the image; and a physical unclonable function PUF generator configured to generate physical unclonable PUF data, the PUF data being associated with a unique physical property of the image sensing device and including at least one fixed pattern noise FPN data corresponding to a fixed pattern noise of the image sensing device and at least one random telegraph noise RTN data corresponding to a random telegraph noise of the image sensing device; a private key generation unit communicating with the image sensing device and configured to generate a private key based on the at least one FPN data and the at least one RTN data acquired from the PUF data; and an image encryption unit communicating with the image sensing device and the private key generation unit and configured to encrypt the image data using the private key. The PUF generator includes a first transistor, and the image generator includes a second transistor corresponding to the first transistor, and wherein the first transistor exhibits a different property from the second transistor.

[0006] According to another embodiment of the disclosed technology, an imaging device may include: an image sensing device, the image sensing device including: one or more first image detection pixels and one or more second image detection pixels, the one or more first image detection pixels and the one or more second image detection pixels being configured to convert light incident on the image detection pixels into pixel signals representing an image; a first transistor, the first transistor being coupled to the one or more first image detection pixels and being configured to generate physically unclonable function PUF data including information about at least one fixed pattern noise FPN data and at least one random telegraph noise RTN data; and a second transistor, the second transistor being coupled to the one or more second image detection pixels and being configured to generate image data acquired by converting light corresponding to the image; a private key generation unit, the private key generation unit being configured to generate a private key based on the at least one FPN data and the at least one RTN data of the PUF data; and an image encryption unit, the image encryption unit being configured to encrypt the image data using the private key. The first transistor exhibits a different noise shape from the second transistor.

[0007] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example of a system in which an imaging device transmits image data to a host device through a network is illustrated.

[0009] Figure 2 This is an example of some implementations based on the disclosed technology. Figure 1 A block diagram of an example of an imaging device is shown.

[0010] Figure 3 Some implementations of the disclosed technology are illustrated. Figure 2 A block diagram of an example of an image sensing device is shown.

[0011] Figure 4 This is an example of some implementations based on the disclosed technology. Figure 3 A block diagram of an example of a pixel array is shown.

[0012] Figure 5 This is an example of some implementations based on the disclosed technology. Figure 3 A circuit diagram of an example of a unit pixel and an analog-to-digital converter (ADC) connected to the unit pixel is shown.

[0013] Figure 6 This is an example of some implementations based on the disclosed technology. Figure 5 A circuit diagram of an example of a comparator is shown.

[0014] Figure 7 is a timing diagram illustrating an example of how Physical Unclonable Function (PUF) data may be generated based on some implementations of the disclosed technology.

[0015] Figure 8 is a timing diagram illustrating another example of how PUF data may be generated based on some implementations of the disclosed technology.

[0016] Fig. 9 is a timing diagram illustrating another example of how PUF data may be generated based on some implementations of the disclosed technology.

[0017] Fig.10 is a diagram illustrating an example of how random telegraph noise (RTN) may be generated based on some implementations of the disclosed technology. DETAILED DESCRIPTION

[0018] This patent document provides implementations and examples of imaging devices that can encrypt image data. In some embodiments, the disclosed technology can be implemented to provide an image data encryption scheme for high data security. An imaging device implemented based on some embodiments of the disclosed technology can encrypt image data using (1) information associated with internal unique characteristics of the imaging device and (2) information randomly generated based on such unique characteristics, thereby improving data security.

[0019] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure allows for various modifications and alternative forms, specific embodiments thereof are illustrated in the accompanying drawings by way of example. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0020] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutes of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0021] Figure 1 An example of the system 1 in which an imaging device transmits image data to a host device through a network is illustrated.

[0022] Reference Figure 1 , the system 1 may include an imaging device 10 , a host device 20 , and a network 30 .

[0023] In some implementations, the imaging device 10 may include any mechanical, digital or electronic viewing device, still camera, video camera, motion picture camera or any other instrument, device or format capable of recording, storing or transmitting visual images. Examples of the imaging device 10 may include a mobile device (e.g., a smart phone, a digital camera, etc.), a personal computer (PC), a laptop computer, a home system or an industrial system including a surveillance camera (e.g., a closed-circuit television CCTV), etc.

[0024] The imaging device 10 may generate image data by capturing an image of a scene based on a request of the host device 20 or a predefined rule (e.g., at a specific interval or when a specific condition is satisfied), and may transmit the image data to the host device 20 through the network 30. Here, the imaging device 10 may generate a private key (KEY) using a physical unclonable function (PUF), which refers to a unique identifier for the physical properties of a specific device such as a semiconductor device. The PUF may be based on unique physical changes or specific unique random characteristics that occur naturally during a semiconductor manufacturing process. The imaging device 10 may encrypt the image data using a private key (KEY) based on the PUF, and may output the encrypted image data to another device (e.g., the host device 20).

[0025] Here, PUF may refer to information generated based on a unique characteristic or unique physical change of the imaging device 10. The PUF may include fixed pattern noise (FPN) or FPN data corresponding to the FPN. In one example, the FPN may indicate a specific noise pattern on the imaging device 10. This specific noise pattern may occur due to a unique characteristic or unique physical change of the imaging device 10. The PUF may also include random telegraph noise (RTN) or RTN data corresponding to the RTN. In one example, the RTN may indicate a sudden transition between two or more discrete voltage or current levels at random and unpredictable times. The RTN may be caused by a unique characteristic or unique physical change of the imaging device 10. In some implementations, the PUF may include at least one FPN data and at least one RTN data.

[0026] The imaging device 10 may perform a bitwise operation (e.g., AND, OR, XOR, NOT, etc.) on at least one FPN data and at least one RTN data of the PUF to generate a private key (KEY). In some implementations, assuming that the PUF includes one FPN data (e.g., first FPN data) and two RTN data (e.g., first RTN data and second RTN data), the imaging device 10 may generate a private key (KEY) by performing a first XOR operation on the first FPN data and the first RTN data and by performing a second XOR operation on the second RTN data and the result of the first XOR operation. In other implementations, the order of operations for performing bitwise operations on at least one FPN data and at least one RTN data may be different from the order discussed above.

[0027] The imaging device 10 may use a private key (KEY) to encrypt image data generated by capturing light corresponding to an image of a scene and generate encrypted image data (IDATA_E). The imaging device 10 may divide the image data into a plurality of blocks, and may encrypt each block using a private key (KEY) to generate encrypted image data (IDATA_E). In some implementations, a symmetric key encryption method such as the Advanced Encryption Standard (AES) may be used to encrypt the image data.

[0028] The imaging device 10 may transmit the encrypted image data (IDATA_E) to the host device 20 through the network 30 .

[0029] The host device 20 may include a device configured to communicate with the imaging device 10. In some implementations, the host device 20 may be configured to perform operations associated with generating, collecting, processing, and / or storing image data, for example, in the same manner as in the imaging device 10. In one example, the host device 20 may include a server (e.g., a cloud server) configured to collect and store image data.

[0030] The host device 20 may receive the encrypted image data (IDATA_E) from the image data 10, and may decrypt the encrypted image data (IDATA_E) using the private key (KEY) to generate decrypted image data (IDATA_D). In this case, the method for performing such a decryption operation may be a symmetric key decryption method. That is, the imaging device 10 performs the decryption operation so that the decrypted image data (IDATA_D) is the same as the image data formed before encryption.

[0031] The network 30 may provide a channel for data communication between the imaging device 10 and the host device 20. For example, the network 30 may provide a channel for mobile communication or near field communication (NFC), a wired network channel for Ethernet communication or serial communication (e.g., Universal Serial Bus USB), or a combination thereof.

[0032] In the case where the network 30 is an unsecured network, the image data transmitted from the imaging device 10 to the host device 20 may be exposed to the risk of data leakage, malicious exploitation, or unauthorized use of the image data. Exposure of images with personal information or private images of individuals to unauthorized persons may cause serious damage to the privacy of the individual.

[0033] In order to protect the privacy of the user, some embodiments of the disclosed technology can generate encrypted image data (IDATA_E) based on PUF encryption, which is determined based on the unique physical characteristics of the imaging device 10. The encrypted image data (IDATA_E) is communicated between the imaging device 10 and the host device 20 through the network 30, thereby providing a higher level of security and preventing unauthorized persons from using or changing the image data. The PUF may include (1) first information including a fixed value determined based on the unique characteristics of the imaging device 10, and (2) second information including a randomly changing value that changes according to the unique characteristics of the imaging device 10. Therefore, even when the first information of the imaging device 10 is fraudulently obtained by others, the second information can provide additional protection to the first information to prevent unauthorized use of the image data.

[0034] Figure 2 This is an example of some implementations based on the disclosed technology. Figure 1 A block diagram of an example of an imaging device 10 is shown.

[0035] Reference Figure 2 , the imaging device 10 may include an image sensing device 100 , a physical unclonable function (PUF) acquisition unit 200 , a private key (KEY) generation unit 300 , and an image encryption unit 500 .

[0036] The image sensing device 100 may capture light corresponding to an image of a scene to generate image data (IDATA), and may generate PUF data (PDATA) provided with information associated with a physical unclonable function (PUF) (hereinafter referred to as PUF information).

[0037] The image sensing device 100 may operate in any one of a plurality of PUF modes, and each PUF mode may correspond to information included in the PUF. For example, assuming that the PUF includes one FPN data (e.g., first FPN data) and two RTN data (e.g., first RTN data and second RTN data), the plurality of modes may include a first PUF mode for generating the first FPN data, a second PUF mode for generating the first RTN data, and a third PUF mode for generating the second RTN data. As will be discussed below, the image sensing device 100 may include Figure 3 The functional blocks shown.

[0038] The PUF acquisition unit 200 may receive PUF data (PDATA) to implement a physically unclonable function (PUF). For example, the PUF acquisition unit 200 may acquire first FPN data from PUF data (PDATA) generated by an image sensing device operating in a first PUF mode. In addition, the PUF acquisition unit 200 may acquire first RTN data from PUF data (PDATA) generated by an image sensing device 100 operating in a second PUF mode. The PUF acquisition unit 200 may also acquire second RTN data from PUF data (PDATA) generated by an image sensing device 100 operating in a third PUF mode. The PUF acquisition unit 200 may receive information about a PUF mode from the image sensing device 100 to identify a mode corresponding to the generated PUF data (PDATA).

[0039] The KEY generation unit 300 may receive the PUF from the PUF acquisition unit 200, and may generate a private key (KEY) based on the received PUF. In some implementations, the KEY generation unit 300 may perform a bitwise operation (e.g., AND, OR, XOR, NOT, etc.) on at least one FPN data and at least one RTN data of the PUF to generate a private key (KEY). In this case, the KEY generation unit 300 may select at least one FPN data and at least one RTN data, and arrange and calculate the selected at least one FPN data and the selected at least one RTN data according to a predetermined algorithm. For example, the KEY generation unit 300 may select a specific PUF pixel from among the PUF pixels, or may select a specific PUF ADC from among the PUF ADCs. The KEY generation unit 300 may arrange at least one FPN data obtained from the selected PUF pixel or at least one RTN data obtained from the selected PUF ADC in a predetermined order, and may perform a predetermined operation on the arranged FPN data and RTN data.

[0040] In some implementations, the KEY generation unit 300 selects one or more FPN data and one or more RTN data, and arranges and calculates the selected FPN data and the selected RTN data according to a predetermined algorithm, and / or may predetermine the interval between patterns or noise signals.

[0041] The image encryption unit 500 may encrypt the image data (IDATA) generated by capturing incident light and converting it into an electrical signal using a private key (KEY) to generate encrypted image data (IDATA_E). The imaging device 10 may divide the image data (IDATA) into a plurality of blocks and may encrypt each block using a private key (KEY) to generate encrypted image data (IDTA_E).

[0042] Figure 3 An example of an embodiment of the disclosed technology is shown in FIG. Figure 2 A block diagram of an image sensing device 100 is shown.

[0043] Reference Figure 3 , the image sensing device 100 may include a pixel array 110 , a row driver 120 , a correlated double sampler (CDS) 130 , an analog-to-digital converter (ADC) 140 , an output buffer 150 , a column driver 160 , and a timing controller 170 . Figure 3 The components of image sensing device 100 shown are discussed merely as an example, and this patent document encompasses numerous other alterations, substitutions, variations, changes, and modifications.

[0044] The pixel array 110 may include a plurality of unit pixels arranged in rows and columns. In one example, the plurality of unit pixels may be arranged as a two-dimensional pixel array including rows and columns. In another example, the plurality of unit pixels may be arranged as a three-dimensional pixel array. The plurality of unit pixels may convert optical signals into electrical signals based on unit pixels or pixel groups, wherein the unit pixels in the pixel groups share at least some internal circuits. The pixel array 110 may receive a drive signal including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 120. Upon receiving the drive signal, the corresponding imaging pixel in the pixel array 110 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0045] The row driver 120 may activate the pixel array 110 based on the command and control signals provided by the controller circuit (e.g., the timing controller 170) to perform certain operations on the imaging pixels in the corresponding row. In some implementations, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row selection signal to select one or more rows among a plurality of rows. The row driver 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row and a transmission signal for the pixels corresponding to at least one selected row. Thus, a reference signal and an image signal (which is an analog signal generated by each of the imaging pixels of the selected row) may be sequentially transmitted to the CDS 130. The reference signal may be an electrical signal provided to the CDS 130 when a sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the CDS 130 when a photocharge generated by the imaging pixel is accumulated in the sensing node.

[0046] CMOS image sensors can use correlated double sampling (CDS) to remove the undesired offset value of a pixel, known as fixed pattern noise, by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) can remove the undesired offset value of a pixel by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the sensing node, so that only the pixel output voltage based on the incident light can be measured. In some embodiments of the disclosed technology, CDS130 can sequentially sample and hold the voltage levels of the reference signal and the image signal of each of the multiple column lines provided to the pixel array 110. That is, CDS130 can sample and hold the voltage levels of the image signal and the reference signal corresponding to each column of the pixel array 110.

[0047] In some implementations, the CDS 130 may transmit the image signal and the reference signal of each column as a correlated double sampling signal to the ADC 140 based on a control signal from the timing controller 170 .

[0048] ADC 140 is used to convert the analog CDS signal into a digital signal. In some implementations, ADC 140 can be implemented as a ramp comparison ADC. The ramp comparison ADC may include a comparator circuit for comparing an analog pixel signal with a reference signal (e.g., a ramp signal that ramps up or down), and a timer that counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 may convert the correlated double sampling signal generated by CDS 130 for each column into a digital signal and output the digital signal. ADC 140 may perform counting operations and calculation operations based on the correlated double sampling signal for each column and the ramp signal provided from the timing controller 170. In this way, ADC 140 may eliminate or reduce noise (e.g., reset noise generated by imaging pixels) when generating digital image data.

[0049] The ADC 140 may include a plurality of column counters. Each column of the pixel array 110 is connected to a column counter, and image data may be generated by converting a correlated double sampling signal received from each column into a digital signal using the column counter. In another embodiment of the disclosed technology, the ADC 140 may include a global counter to convert a correlated double sampling signal corresponding to a column into a digital signal using a global code provided from the global counter.

[0050] The output buffer 150 may temporarily hold the column-based image data provided from the ADC 140 to output the image data. In one example, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0051] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and sequentially output the image data temporarily stored in the selected column of the output buffer 150. In some implementations, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal and select a column of the output buffer 150, and output the image data from the selected column of the output buffer 150 as an output signal.

[0052] The timing controller 170 may control operations of the row driver 120 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0053] The timing controller 170 may provide a clock signal required for the operation of each component of the image sensing device 100, a control signal for timing control, and an address signal for selecting a row or column to the row driver 120, the column driver 160, and the output buffer 150. In an embodiment of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0054] Figure 4 This is an example of some implementations based on the disclosed technology. Figure 3 A block diagram of an example of a pixel array 110 is shown.

[0055] Reference Figure 4 , the pixel array 110 may include an active pixel array 400 and a PUF pixel array 410 .

[0056] The active pixel array 400 may include at least one image pixel for generating image data (IDATA) by capturing and converting light corresponding to an image of a scene. The PUF pixel array 410 may include at least one PUF pixel for generating PUF data (PDATA) including information about the PUF. The image pixel and the PUF pixel may be connected to Figure 3 The multiple unit pixels shown correspond to each other.

[0057] Although for ease of description Figure 4The PUF pixel array 410 is illustrated as being disposed at one side (e.g., the lower side) of the active pixel array 400, but the disclosed technology is not limited thereto. In some implementations, the PUF pixel array 410 may be disposed at the upper side, the lower side, the left side, and / or the right side of the active pixel array 400. In some implementations, the active pixel array 400 may include at least one PUF pixel.

[0058] Figure 5 This is an example of some implementations based on the disclosed technology. Figure 3 A circuit diagram of an example of a unit pixel 510 and an analog-to-digital converter (ADC) 520 connected to the unit pixel is shown. Figure 6 This is an example of some implementations based on the disclosed technology. Figure 5 A circuit diagram of an example of a comparator is shown.

[0059] Figure 5 The unit pixel 510 and the ADC 520 electrically coupled to the unit pixel 510 are illustrated. The unit pixel 510 and the ADC 520 may be electrically coupled to each other through the column line CL. Although for ease of description, Figure 5 Only one unit pixel 510 coupled to the column line CL is illustrated, but it should be noted that other unit pixels belonging to the same column as the unit pixel 510 may also be coupled to the column line CL.

[0060] The unit pixel 510 may be an image pixel or a PUF pixel. Here, the image pixel may be configured to generate image data, and the PUF pixel may be configured to generate PUF data. When the unit pixel 510 is an image pixel, the column line CL may be connected to other image pixels in the active pixel array 400 that belong to the same column as the unit pixel 510. When the unit pixel 510 is a PUF pixel, the column line CL may be connected to other PUF pixels in the PUF pixel array 410 that belong to the same column as the unit pixel 510. However, when the unit pixel 510 is an image pixel, the column line CL is not connected to the PUF pixel. Similarly, when the unit pixel 510 is a PUF pixel, the column line CL is not connected to the image pixel. In other words, the image pixel and the PUF pixel may be connected to different ADCs 520 that operate independently of each other. Although the image pixel and the PUF pixel belong to the same column, the image pixel and the PUF pixel may be connected to different column lines, and the pixel signals may be output to different ADCs 520.

[0061] The image sensing device 100 may include an image generation unit for generating image data (IDATA) and a PUF generation unit for generating PUF data (PDATA). The image generation unit may include image pixels and an image ADC coupled to the image pixels. The PUF generation unit may include PUF pixels and a PUF ADC coupled to the PUF pixels.

[0062] The image pixel and the PUF pixel may have a similar or identical structure (e.g., the structure of the unit pixel 510). One ADC coupled to the image pixel and another ADC coupled to the PUF pixel may have substantially the same structure (e.g., the structure of ADC520). The ADC coupled to the image pixel may be defined as an image ADC for converting analog image data into digital image data, and the ADC coupled to the PUF pixel may be defined as a PUF ADC for converting analog PUF data into digital PUF data.

[0063] The unit pixel 510 may include a photoelectric conversion element PD, a transfer transistor TX, a reset transistor RX, a floating diffusion region FD, a first capacitor C1, a drive transistor DX, and a selection transistor SX. Although for ease of description, Figure 5 The unit pixel 510 is illustrated as including only one photoelectric conversion element PD, but the unit pixel 510 may include a plurality of photoelectric conversion elements (PD). In this case, the unit pixel 510 may include a plurality of transfer transistors (TX) coupled to the plurality of photoelectric conversion elements (PD).

[0064] Each photoelectric conversion element (PD) can generate a photocharge corresponding to the intensity of the incident light, and the photocharge is accumulated at or near the photoelectric conversion element (PD). For example, each photoelectric conversion element (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0065] If the photoelectric conversion element PD is implemented as a photodiode, the photoelectric conversion element PD may include a region in which second conductive impurities (eg, N-type impurities) are doped in a substrate including first conductive impurities (eg, P-type impurities).

[0066] The transfer transistor TX may be coupled between the photoelectric conversion element PD and the floating diffusion region FD. The transfer transistor TX may be turned on or off in response to a transfer signal TG. If the transfer transistor TX is turned on, photocharges generated / accumulated in the corresponding photoelectric conversion element PD may be transferred to the floating diffusion region FD.

[0067] The reset transistor RX may be set between the floating diffusion region FD and the power supply voltage (VDD px ), and the voltage of the floating diffusion region FD may be reset to the power supply voltage (VDD) in response to the reset control signal RG. px ).

[0068] The floating diffusion region FD may hold the photocharge received from the transfer transistor TX. The floating diffusion region FD may be coupled to a first capacitor C1 connected to a ground voltage terminal. For example, the floating diffusion region FD may be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate (e.g., a P-type substrate) including a first conductive impurity. In this case, the substrate and the impurity-doped region may constitute Figure 5 The first capacitor C1 that acts as a junction capacitor is illustrated. That is, the first capacitor C1 may include one or more capacitive elements that constitute the capacitance of the floating diffusion region FD. In another embodiment, the first capacitor C1 may include the floating diffusion region FD and a separate capacitive element (e.g., a metal-insulator-metal (MIM) capacitor, etc.). The capacitance of the separate capacitive element is added to the capacitance of the floating diffusion region FD. In another embodiment, the separate capacitive element may be selectively coupled to the floating diffusion region FD via a dual conversion gain (DCG) transistor, so that the unit pixel 510 may have a large dynamic range.

[0069] The driver transistor DX can be connected to the power supply voltage (VDD px ) and the selection transistor SX, the voltage or potential of the floating diffusion region FD having the photocharge transferred from the photoelectric conversion element PD can be converted into a voltage signal, and the voltage signal can be transmitted to the selection transistor SX.

[0070] The gate electrode of the drive transistor DX of the image pixel may be larger in size than the gate electrode of the drive transistor DX of the PUF pixel.

[0071] The selection transistor SX may be coupled between the driving transistor DX and the column line CL, may be turned on by the row selection signal SEL, and may output an electrical signal received from the driving transistor DX as a pixel signal (V px ).

[0072] is configured to receive a pixel signal (V px ) may include a second capacitor C2, a comparator reset transistor (Tcr), a comparator 530 and a counter 540.

[0073] The second capacitor C2 may be coupled between the column line CL and the first input terminal of the comparator 530 to remove the px ) in the image (e.g., high frequency noise).

[0074] The comparator reset transistor (Tcr) may be coupled between the first input terminal of the comparator 530 and the output terminal of the comparator 530. The comparator reset transistor (Tcr) may be turned on by the comparator reset signal CRG and may reset the first input terminal of the comparator 530 to the voltage of the output terminal of the comparator 530. The voltage of the output terminal of the comparator 530 may have the same voltage as the ramp signal (V ramp ) and pixel signal (V px ) corresponds to the voltage difference between the two. Since the ramp signal (V ramp ) gradually decreases, so the voltage of the output terminal of the comparator 530 can converge to a logic low level after a predetermined time. In this case, the logic low level can refer to a voltage of the first input terminal for resetting the comparator 530.

[0075] The ramp signal generator (not shown) may generate a ramp signal (V ramp ), so that the ramp signal generator can increase the ramp signal (V ramp ) is applied to the second input terminal of the comparator 530.

[0076] The comparator 530 can convert the pixel signal (V px ) and the ramp signal (V ramp ) to generate a pixel signal (V px ) and the ramp signal (V ramp ) corresponds to the comparison signal of the voltage difference between them. For example, when the pixel signal (V px ) than the ramp signal (V ramp ) is larger in magnitude (or higher in level), the comparison signal may have a logic low level. Conversely, when the pixel signal (V px ) is smaller than the ramp signal (V ramp ), the comparison signal can have a logic high level.

[0077] Reference Figure 6 , the comparator 600 may be Figure 5 An example of a comparator 530 is shown.

[0078] The comparator 600 may include a load stage 610, a separation stage 620, an input stage 630, and a bias stage 640. The comparator 600 may include an operational amplifier (OP AMP) to which no feedback signal is applied.

[0079] The load stage 610, the separation stage 620, the input stage 630 and the bias stage 640 can be connected to a first bias voltage (V dda ) and the second bias voltage (V ssa ) between the differential amplifiers.

[0080] The load stage 610 may include a first PMOS transistor MP1 and a second PMOS transistor MP2. The gate electrode of the first PMOS transistor MP1 may be coupled to the gate electrode of the second PMOS transistor MP2. Each of the source electrode of the first PMOS transistor MP1 and the source electrode of the second PMOS transistor MP2 may receive a first bias voltage (V dda The drain electrode of the first PMOS transistor MP1 may be coupled to the gate electrode of the first PMOS transistor MP1 so that the comparison signal (V c ) can be output through the drain electrode of the second PMOS transistor MP2.

[0081] The input stage 630 may include a first NMOS transistor MN1 and a second NMOS transistor MN2. The gate electrode of the first NMOS transistor MN1 may receive a ramp signal (V ramp ), and the gate electrode of the second NMOS transistor MN2 can receive the pixel signal (V px ).

[0082] Assume that the gate electrode of the first NMOS transistor MN1 has the same size as the gate electrode of the second NMOS transistor MN2. In this case, the gate electrode of the first NMOS transistor MN1 of the image ADC may be larger in size than the gate electrode of the first NMOS transistor MN1 of the PUF ADC, and the gate electrode of the second NMOS transistor MN2 of the image ADC may be larger in size than the gate electrode of the second NMOS transistor MN2 of the PUF ADC.

[0083] The separation stage 620 may include a third NMOS transistor MN3 coupled between the first PMOS transistor MP1 and the first NMOS transistor MN1, and a fourth NMOS transistor MN4 coupled between the second PMOS transistor MP2 and the second NMOS transistor MN2. The gate electrode of the third NMOS transistor MN3 and the gate electrode of the fourth NMOS transistor MN4 may be coupled to a first bias voltage (V dda The separation stage 620 can compare the signal (V c ) output while stabilizing the comparison signal (V c ) voltage level.

[0084] The bias stage 640 may include a bias voltage source connected in series between the input stage 630 and a second bias voltage source (V ssa ) between the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6.

[0085] The fifth NMOS transistor MN5 can receive the cascode control voltage (Vcasc ), and the cascade connection between the input stage 630 and the sixth NMOS transistor MN6 can be controlled. That is, when the fifth NMOS transistor MN5 is turned on, a bias current can be provided to the input stage 630 through the sixth NMOS transistor MN6.

[0086] The sixth NMOS transistor MN6 can receive a bias control voltage (V bias ), and a bias current may be applied to the input stage 630. In this case, the bias control voltage (V bias ) determines the magnitude of the bias current.

[0087] The gate electrode of the sixth NMOS transistor MN6 of the image ADC may be larger in size than the gate electrode of the sixth NMOS transistor MN6 of the PUF ADC.

[0088] The cascade control voltage (V casc ) and the bias control voltage (V bias ).

[0089] As described above, when the pixel signal (V px ) is higher in level than the ramp signal (V ramp ) is higher, the comparison signal (V c ) may have a voltage corresponding to a logic low level (eg, a second bias voltage V ssa ). On the contrary, when the pixel signal (V px ) is higher in level than the ramp signal (V ramp ) is lower, the comparison signal (V c ) may have a voltage corresponding to a logic high level (eg, a first bias voltage V dda ).

[0090] Return to reference Figure 5 , the counter 540 may be synchronized with the edge (e.g., rising edge or falling edge) of the clock signal provided from the timing controller 170, so that the counter 540 may perform counting in response to the level of the comparison signal. The time period in which the counter 540 may perform counting may be defined as a countable range. The countable range may refer to the time period from the ramp signal (V ramp ) starts to decrease at a constant slope to an end point after a predetermined time has passed from the starting point.

[0091] The counter 540 may perform counting during the countable range until the comparison signal transitions from a first level (eg, a logic high level) to a second level (eg, a logic low level), and may output the accumulated count value as image data (IDATA) or PUF data (PDATA).

[0092] Figure 7 is a timing diagram illustrating an example of how PUF data may be generated based on some implementations of the disclosed technology.

[0093] As from Figure 7 It can be seen that when the image sensing device 100 operates in the first PUF mode, the image sensing device 100 may be controlled using the plurality of control signals MS, RG, TG, SEL, and CRG, and PUF data (PDATA) may be generated by the image sensing device 100 .

[0094] First, when the image sensing device 100 operates in the first PUF mode, the mechanical shutter control signal MS may be at a logic low level (L). The mechanical shutter control signal MS may be used to control the operation of a mechanical shutter (not shown) designed to control the amount of light incident on the pixel array 110. When the mechanical shutter control signal MS is at a logic low level (L), the mechanical shutter (not shown) may block the light incident on the pixel array 110. When the mechanical shutter control signal MS is at a logic high level (H), the mechanical shutter (not shown) may allow the light incident on the pixel array to pass through the mechanical shutter.

[0095] In the first PUF mode, the image sensing device 100 may operate sequentially in the following order: (1) pixel reset section PXRS, (2) comparator reset section CPRS, (3) reset readout section RSRO, (4) pixel transfer section PXTR, and (5) signal readout section SGRO.

[0096] The pixel reset section PXRS may include removing photocharges from the PUF pixel 510 and resetting the floating diffusion region FD to a power supply voltage (VDD px ) operation. In the pixel reset section PXRS, each of the pixel reset signal RG, the transfer signal TG, and the row selection signal SEL may have a logic high level (H), and the comparator reset signal CRG may have a logic low level (L). Therefore, the reset transistor RX, the transfer transistor TX, and the selection transistor SX may be turned on.

[0097] The comparator reset section CPRS may refer to an operation section in which the PUF comparator 530 is reset to initialize the voltage of the first input terminal of the PUF comparator 530. In the comparator reset section CPRS, each of the row selection signal SEL and the comparator reset signal CRG may have a logic high level (H), and each of the pixel reset signal RG and the transfer signal TG may have a logic low level (L). Therefore, the selection transistor SX and the comparator reset transistor (Tcr) may be turned on.

[0098] During the reset readout section RSRO, the PUF pixel 510 outputs a reference signal corresponding to the voltage of the reset floating diffusion region, and the PUF ADC 520 compares the reference signal with the ramp signal (V ramp ) to generate a reference signal and a ramp signal (V ramp ) between the comparison result. In the reset readout section RSRO, the row selection signal SEL may have a logic high level (H), and each of the pixel reset signal RG, the transfer signal TG, and the comparator reset signal CRG may have a logic low level (L). Therefore, the selection transistor SX may be turned on. In the reset readout section RSRO, the counter 540 of the PUF ADC 520 may count down from the initial value (e.g., sequentially subtract from the initial value) until the comparison signal changes from a logic high level to a logic low level. After completing the down-counting operation, the counter 540 may retain the accumulated count value.

[0099] In the pixel transfer section PXTR, the photocharge accumulated in the photoelectric conversion element PD may be transferred to the floating diffusion area FD, and an image signal corresponding to the voltage of the floating diffusion area FD may be transferred from the PUF pixel 510 to the PUF ADC 520. In the pixel transfer section PXTR, each of the transfer signal TG and the row selection signal SEL may have a logic high level (H), and the pixel reset signal RG and the comparator reset signal CRG may have a logic low level (L). Therefore, the transfer transistor TX and the selection transistor SX may be turned on.

[0100] During the signal readout section SGRO, the PUF ADC 520 combines the image signal with the ramp signal (V ramp ) is compared, and PUF data (PDATA) corresponding to the comparison result is generated. In the signal readout section SGRO, the row selection signal SEL may have a logic high level (H), and each of the pixel reset signal RG, the transfer signal TG, and the comparator reset signal CRG may have a logic low level (L). Therefore, the selection transistor SX may be turned on. In the signal readout section SGRO, the counter 540 of the PUF ADC 520 may perform upcounting (in which a sequential increase starting from the current value is performed) until the comparison signal is changed from a logic high level to a logic low level. After completing the up-counting operation, the counter 540 may retain the accumulated count value.

[0101] The counter 540 performs down-counting in the reset readout section RSRO and performs up-counting in the signal readout section SGRO, so that the count value corresponding to the reference signal can be subtracted from another count value corresponding to the image signal, thereby forming PUF data (PDATA) from which reset noise is removed. That is, the imaging device based on some implementations of the disclosed technology can enable the PUF ADC 520 to further perform the function of the correlated double sampler (CDS) 130 without using a separate CDS 130.

[0102] That is, the first PUF mode may refer to an operation mode in which fixed pattern noise (FPN) caused by leakage current generated from the PUF pixel may be obtained in a specific condition (ie, a dark condition) in which light is not transmitted to the pixel array 110 .

[0103] The PUF acquisition unit 200 may determine the first FPN data based on a result of a comparison between the PUF data (PDATA) received from the image sensing device 100 operating in the first PUF mode and a predetermined first threshold. When the PUF data (PDATA) is equal to or greater than the first threshold, the PUF acquisition unit 200 may determine the first FPN data as a first logic level (e.g., 1). When the PUF data (PDATA) is less than the first threshold, the PUF acquisition unit 200 may determine the first FPN data as a second logic level (e.g., 0).

[0104] although Figure 7 The exemplary PUF data (PDATA) is generated in a state where a dark condition is formed by the operation of a mechanical shutter (not shown), but it should be noted that the PUF data (PDATA) corresponding to the FPN can also be generated without using the mechanical shutter (not shown). For example, in the pixel transfer section PXTR, the transfer transistor TX is kept off, and the PUF data (PDATA) corresponding to the leakage current flowing into the floating diffusion area FD is generated, so that the PUF data (PDATA) corresponding to the FPN can also be generated without using the mechanical shutter (not shown).

[0105] Figure 8 is a timing diagram illustrating another example of how PUF data (PDATA) may be generated based on some implementations of the disclosed technology.

[0106] As from Figure 8 It can be seen that when the image sensing device 100 operates in the second PUF mode, the plurality of control signals MS, RG, TG, SEL, and CRG may be used to control the image sensing device 100 , and PUF data (PDATA) may be generated by the image sensing device 100 .

[0107] First, when the image sensing device 100 operates in the second PUF mode, the mechanical shutter control signal MS may be maintained at a logic high level (H). Therefore, the mechanical shutter (not shown) may allow light incident on the pixel array 110 to pass through the mechanical shutter.

[0108] In the second PUF mode, the image sensing device 100 may operate in the order of the first image acquisition section IMG1 and the second image acquisition section IMG2. Each of the first image acquisition section IMG1 and the second image acquisition section IMG2 may operate in the following order: (1) pixel reset section PXRS, (2) comparator reset section CPRS, (3) reset readout section RSRO, (4) pixel transfer section PXTR, and (5) signal readout section SGRO.

[0109] Figure 8 The operation of the image sensing device 100 configured to operate in the pixel reset section PXRS, the comparator reset section CPRS, the reset readout section RSRO, the pixel transfer section PXTR, and the signal readout section SGRO is similar to that shown in FIG. Figure 7 The operations are the same or similar.

[0110] In the second PUF mode, the image sensing device 100 can continuously generate PUF data (PDATA) corresponding to the intensity of light incident on the PUF pixel. The time gap between the first image acquisition segment IMG1 and the second image acquisition segment IMG2 can be set to a very short time. In this case, it is highly likely that the PUF data (PDATA) generated in the first image acquisition segment IMG1 and the other PUF data (PDATA) generated in the second image acquisition segment IMG2 have the same or very similar values.

[0111] However, the gate electrode of the driving transistor DX of the PUF pixel may be larger in size than the gate electrode of the driving transistor DX of the image pixel. The driving transistor DX may convert the voltage or potential of the floating diffusion region FD into a voltage signal. The driving transistor DX of the PUF pixel having a relatively smaller gate area may generate noise having a relatively high frequency or amplitude during the conversion process. In addition, the noise in the driving transistor DX of the PUF pixel may be generated in a random manner, and changes in such noise generated at a relatively high frequency or amplitude may be used as meaningful data.

[0112] Therefore, each of PUF data (PDATA) generated in the first image acquisition section IMG1 based on the voltage signal of the driving transistor DX and another PUF data (PDATA) generated in the second image acquisition section IMG2 based on the voltage signal of the driving transistor DX may include noise generated in the driving transistor DX.

[0113] That is, the second PUF mode may refer to an operation mode in which random telegraph noise (RTN) caused by a change in noise generated in the driving transistor DX of the PUF pixel that has detected the same incident light may be obtained.

[0114] When receiving the first PUF data (PDATA) of the first image acquisition segment IMG1 and the second PUF data (PDATA) of the second image acquisition segment IMG2 from the image sensing device 100 operating in the second PUF mode, the PUF acquisition unit 200 may perform a subtraction operation on the first PUF data (PDATA) and the second PUF data (PDATA) (e.g., subtracting the second PUF data (PDATA) from the first PUF data (PDATA)), and may determine the first RTN data by comparing the result of the subtraction with a predetermined second threshold. When the result of the subtraction is equal to or greater than the second threshold, the PUF acquisition unit 200 may determine the first RTN data as a first logic level (e.g., 1). When the result of the subtraction is less than the second threshold, the PUF acquisition unit 200 may determine the first RTN data as a second logic level (e.g., 0).

[0115] Fig. 9 is a timing diagram illustrating another example of how PUF data (PDATA) may be generated based on some implementations of the disclosed technology.

[0116] As from Fig. 9 It can be seen that when the image sensing device 100 operates in the third PUF mode, the plurality of control signals RG, TG, SEL, and CRG may be used to control the image sensing device 100 , and PUF data (PDATA) may be generated by the image sensing device 100 .

[0117] In the third PUF mode, the image sensing device 100 may operate in the following order: (1) pixel reset segment PXRS, (2) comparator reset segment CPRS, (3) reset readout segment RSRO, (4) pixel transfer segment PXTR, and (5) signal readout segment SGRO.

[0118] Fig. 9 The operation of the image sensing device 100 configured to operate in the pixel reset section PXRS, the comparator reset section CPRS, the reset readout section RSRO, the pixel transfer section PXTR, and the signal readout section SGRO is similar to that shown in FIG. Figure 7 For ease of description, the following will discuss Fig. 9 The operation of the image sensing device 100 is shown in FIG. Figure 7 The differences between the operations of the image sensing device 100 are shown.

[0119] The pixel reset section PXRS may include removing the photoelectric charge from the PUF pixel 510 and resetting the floating diffusion region FD to the power supply voltage (VDD). px ) operation. In the pixel reset section PXRS, each of the pixel reset signal RG and the transfer signal TG may have a logic high level (H), and the comparator reset signal CRG may have a logic low level (L). Therefore, the reset transistor RX and the transfer transistor TX may be turned on. Figure 7 The pixel reset section PXRS shown is different. Fig. 9 The selection transistor SX shown may be turned off.

[0120] The comparator reset section CPRS may refer to an operation section in which the PUF comparator 530 is reset to initialize the voltage of the first input terminal of the PUF comparator 530. In the comparator reset section CPRS, the comparator reset signal CRG may have a logic high level (H), and each of the pixel reset signal RG, the transfer signal TG, and the row selection signal SEL may have a logic low level (L). Therefore, the comparator reset transistor (Tcr) may be turned on. Figure 7 The comparator reset section CPRS shown is different. Fig. 9 The selection transistor SX shown may be turned off.

[0121] During the reset readout section RSRO, the PUF ADC 520 compares the voltage of the first input terminal of the reset PUF comparator 530 (ie, the comparator reset signal) with the ramp signal (V ramp ) and generates PUF data (PDATA) corresponding to the comparison result. In the reset readout section RSRO, the pixel reset signal RG, the transfer signal TG, the row selection signal SEL, and the comparator reset signal CRG may have a logic low level (L). In the reset readout section RSRO, the counter 540 of the PUF ADC 520 may count down from the initial value (e.g., sequentially subtract from the initial value) until the comparison signal changes from a logic high level to a logic low level. After completing the down-counting operation, the counter 540 may retain the accumulated count value. Figure 7 The reset readout section RSRO shown is different, Fig. 9 The selection transistor SX shown may be turned off. This is because during the reset readout section RSRO, a signal corresponding to the reset state of the PUF comparator 530 is read out, while a signal corresponding to the reset state of the PUF pixel 510 is not read out.

[0122] During the pixel transmission section PXTR, a reference signal corresponding to the voltage of the reset floating diffusion region FD is output from the PUF pixel 510 and then transmitted to the PUF ADC 520. In the pixel transmission section PXTR, the row selection signal SEL may have a logic high level (H), and each of the pixel reset signal RG, the transfer signal TG, and the comparator reset signal CRG may have a logic low level (L). Therefore, the selection transistor SX may be turned on. Figure 7 The pixel transfer section PXTR shown is different. Fig. 9 The transfer transistor TX shown may be turned off.

[0123] The signal readout section SGRO may refer to a section in which the PUF ADC 520 receives a reference signal, compares the received reference signal with a ramp signal (V ramp ) and thereby generate PUF data (PDATA) corresponding to the comparison result. In the signal readout section SGRO, each of the pixel reset signal RG, the transfer signal TG, the row selection signal SEL, and the comparator reset signal CRG may have a logic low level (L). In the signal readout section SGRO, the counter 540 of the PUF ADC 520 may count up from the current value (e.g., sequentially increase from the current value) until the comparison signal changes from a logic low level to a logic high level. After completing the up-counting operation, the counter 540 may retain the accumulated count value. Figure 7 The signal readout section SGRO shown is different. Fig. 9 The selection transistor SX shown can be turned off. This is because Fig. 9 During the signal readout section SGRO shown in , the reference signal generated from the PUF pixel 510 is read out, but the image signal generated from the PUF pixel 510 is not read out. In other words, the reference signal has been transmitted to the PUF ADC 520 in the pixel transmission section PXTR.

[0124] In the reset readout section RSRO, the counter 520 may perform down counting. In the signal readout section SGRO, the counter 540 may perform up counting. Therefore, the count value corresponding to the comparator reset signal may be subtracted from another count value corresponding to the reference signal, so that the PUF data (PDATA) from which the reset noise of the PUF comparator 530 is removed may be generated.

[0125] The gate electrode of the first NMOS transistor MN1 of the PUF ADC may be smaller in size than the gate electrode of the first NMOS transistor MN1 of the image ADC. In addition, the gate electrode of the second NMOS transistor MN2 of the PUF ADC may be smaller in size than the gate electrode of the second NMOS transistor MN2 of the image ADC.

[0126] The first NMOS transistor MN1 can receive a ramp signal (V ramp ), and the second NMOS transistor MN2 can receive the pixel signal (V px The voltage difference between the drain current generated by the first NMOS transistor MN1 and the drain current generated by the second NMOS transistor MN2 can be proportional to the ramp signal (V ramp ) and pixel signal (V px ). In other words, the first NMOS transistor MN1 and the second NMOS transistor MN2 can generate a voltage corresponding to the ramp signal (V ramp ) and pixel signal (V px ) corresponds to the drain current, making the comparison signal (V c ) has a voltage corresponding to a logic low level or a logic high level. Therefore, the ramp signal (V ramp ) and pixel signal (V px ) can be converted into a comparison signal (V c ).

[0127] The first NMOS transistor MN1 and the second NMOS transistor MN2 of the PUF ADC having a relatively smaller gate area may generate noise having a relatively high frequency or amplitude during a conversion process. In addition, the noise generated from the first NMOS transistor MN1 and the second NMOS transistor MN2 of the PUF ADC may appear randomly, and changes in the noise generated with a relatively high frequency or amplitude may be used as meaningful data.

[0128] The gate electrode of the sixth NMOS transistor MN6 of the PUF ADC may be smaller in size than the gate electrode of the sixth NMOS transistor MN6 of the image ADC.

[0129] The sixth NMOS transistor MN6 can be connected to the bias control voltage (V bias ) is applied to the input stage 630. Here, the bias current can determine the logic low level (V c For example, as the bias current increases, the comparison signal (V c ) can be reduced to a logic low level closer to the second bias voltage (V ssa ).

[0130] The sixth NMOS transistor MN6 of the PUF ADC having a relatively smaller gate area may generate noise having a relatively high frequency or amplitude during the process of generating the bias current. In addition, the noise generated in the sixth NMOS transistor MN6 of the PUF ADC may appear randomly, and changes in the noise generated with a relatively high frequency or amplitude may be used as meaningful data.

[0131] Therefore, the PUF data (PDATA) generated in the signal readout section SGRO after resetting the readout section RSRO may include noise generated in the PUF ADC.

[0132] In other words, the third PUF mode may refer to an operation mode in which the RTN caused by a change in noise generated by the PUF ADC 520 designed to generate PUF data (PDATA) corresponding to the reference signal of the PUF pixel 510 may be obtained.

[0133] The amount of noise generated in the PUF ADC 520 may be relatively greater than the amount of noise generated in the PUF pixel 510. That is, although pixels belonging to the same column connected to the PUF ADC 520 in which a relatively large amount of noise has occurred output various signals, PUF data (PDATA) generated by the PUF ADC 520 may represent the same value (e.g., 1).

[0134] In another embodiment, the pixel transmission section PXTR may be omitted from the third PUF mode operation. That is, the row selection signal SEL may be maintained at a logic low level (L) in a time section corresponding to the pixel transmission section PXTR. Therefore, the PUF data (PDATA) may include only the noise generated from the PUF ADC 520 in addition to the noise generated from the PUF pixel 510.

[0135] The PUF acquisition unit 200 may determine the second RTN data based on a result of a comparison between the PUF data (PDATA) received from the image sensing device 100 operating in the third PUF mode and the third threshold. When the PUF data (PDATA) is equal to or greater than the third threshold, the PUF acquisition unit 200 may determine the second RTN data as a first logic level (e.g., 1). When the PUF data (PDATA) is less than the third threshold, the PUF acquisition unit 200 may determine the second RTN data as a second logic level (e.g., 0).

[0136] Fig.10 is a graph illustrating an example of how random telegraph noise (RTN) may be generated based on some implementations of the disclosed technology.

[0137] Fig.10 is a graph illustrating the relationship between the frequency of occurrence of random telegraph noise (RTN) generated in one or more transistors and the noise amplitude. Fig.10 In the graph of , the X-axis represents the amplitude (or value) of RTN, and the Y-axis represents the occurrence frequency (or RTN occurrence probability) of RTN. The RTN of a transistor may refer to noise that occurs in an output current or output voltage output to a drain electrode or a source electrode of the transistor in response to an input voltage to be input to a gate electrode of the transistor.

[0138] Typically, the frequency of occurrence of RTN generated in a transistor may decrease as the magnitude of the RTN increases, and may increase as the magnitude of the RTN decreases. In addition, the magnitude of the RTN and the frequency of occurrence of the RTN may vary according to the size of the gate region of the transistor. That is, the magnitude of the RTN and the frequency of occurrence of the RTN may vary with the repeated square (power or exponentiation) of the gate region of the transistor.

[0139] When the size of the gate electrode of the transistor is reduced, the output current of the transistor may be reduced, and the signal-to-noise ratio (SNR) may also be reduced as the output current of the transistor is reduced, thereby increasing the frequency of occurrence of RTN at the same RTN amplitude.

[0140] In addition, when the size of the gate electrode of the transistor is reduced, the total amount of gate charge (or gate capacitance) corresponding to the amount of charge that should be injected into the gate electrode to operate (or turn on) the transistor can be reduced. As the total amount of gate charge in the gate electrode of the transistor is reduced, the RTN amplitude (corresponding to the slope of the straight line depicted in the graph) per the frequency of occurrence of RTN can be increased (that is, the slope of the straight line depicted in the graph can be reduced).

[0141] In the image sensing device 100 , one or more transistors related to the generation of the image data (IDATA) may be designed to generate less RTN so that noise that may occur in the image data (IDATA) may be minimized. Fig.10 is an example of a first RTN feature associated with a transistor gate for image data (IDATA) (denoted by Fig.10 An example graph of the “Gate for IDATA” representation in FIG.

[0142] However, a transistor associated with the generation of PUF data (PDATA) may be designed to have a gate region of a smaller size than another transistor for image data (IDATA), so that the transistor associated with the generation of PUF data (PDATA) may intentionally control the PUF data (PDATA) to include noise that may occur within a predetermined range of frequencies at which the noise occurs and within a predetermined range of noise amplitudes.

[0143] Since the transistor associated with the generation of the PUF data (PDATA) has a relatively small gate area, the output current of the transistor is reduced, making the first RTN feature (given by Fig.10 Compared with the "gate for IDATA" in the figure), the RTN occurrence frequency can be greatly increased at the same RTN amplitude (represented by Fig.10 The “reduced current” in the figure indicates the current at which the

[0144] As in Fig.10 As represented by "reduced gate capacitance", since the transistor associated with the generation of PUF data (PDATA) has a relatively small gate region, the total amount of gate charge (or gate capacitance) of the transistor is reduced, so that the RTN amplitude (corresponding to the slope of the straight line depicted in the graph) of the frequency of occurrence of each RTN can be increased (i.e., the slope of the straight line depicted in the graph can be reduced).

[0145] In other words, the transistors associated with the generation of the PUF data (PDATA) have a relatively small-sized gate region, so that the RTN occurrence frequency and the RTN amplitude can be increased simultaneously.

[0146] As from Fig.10 It can be seen that the transistor associated with the generation of PUF data (PDATA) has a relatively small gate area, so that the noise amplitude can increase in the following order: (1) the first noise amplitude V1 (generated in the transistor associated with the generation of image data (IDATA) at the same noise occurrence frequency), (2) the second noise amplitude V2 (corresponding to the case where only the output current of the transistor is reduced), and (3) the third noise amplitude V3 (corresponding to the case where the total amount of gate charge of the transistor is also reduced).

[0147] In this case, as described above, the transistor associated with the generation of the PUF data (PDATA) may be at least one of the driving transistor DX of the PUF pixel, the first NMOS transistor MN1 of the PUF ADC, the second NMOS transistor MN2, and the sixth NMOS transistor MN6. Although the above-mentioned implementation discloses only four transistors for ease of description, other implementations are possible, and the gate electrode of another transistor associated with the generation of the PUF data (PDATA) may be adjusted in size for the RTN to occur.

[0148] In addition, although the imaging device according to one embodiment of the disclosed technology has disclosed an image sensing device for generating random telegraph noise (RTN) in PUF data (PDATA) by adjusting the size of the gate region of the transistor related to the generation of PUF data (PDATA), other implementations are possible, and the imaging device according to another embodiment of the disclosed technology can generate RTN in PUF data (PDATA) by adjusting the threshold voltage of the transistor related to the generation of PUF data (PDATA). For example, the threshold voltage of the transistor related to the generation of PUF data (PDATA) can be greater than the threshold voltage of the relevant transistor among the transistors related to the generation of image data (IDATA).

[0149] In other words, the transistor (or first transistor) associated with the generation of PUF data (PDATA) may have characteristics different from another transistor (or second transistor) among the plurality of transistors associated with the generation of image data (IDATA) (corresponding to at least one transistor associated with the generation of PUF data PDATA). In this case, although the transistor characteristics of some implementations based on the disclosed technology have been disclosed using the gate region or the threshold voltage as an example, it should be noted that other characteristics capable of intentionally generating RTN may also be included in the transistor characteristics as needed.

[0150] It is obvious from the above description that the imaging device 10 based on some implementations of the disclosed technology can not only use information fixed by the internal unique characteristics of the imaging device 10 to encrypt image data, but also use information randomly generated based on the unique characteristics, and thus prevent malicious exploitation and unauthorized use of the image data by others.

[0151] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0152] Implementations of the disclosed technology can be implemented in various ways to obtain one or more advantages or desired effects.

[0153] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

[0154] CROSS-REFERENCE TO RELATED APPLICATIONS

[0155] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0068493, filed on May 27, 2021, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An imaging device, comprising: An image sensing device, the image sensing device comprising an image generator that generates image data by converting incident light carrying an image into electrical signals indicative of the image; as well as a physical unclonable function PUF generator, the PUF generator generating physical unclonable function PUF data associated with unique physical characteristics of the image sensing device and including at least one fixed pattern noise FPN data corresponding to a fixed pattern noise of the image sensing device and at least one random telegraph noise RTN data corresponding to a random telegraph noise of the image sensing device; a private key generation unit that communicates with the image sensing device and generates a private key based on the at least one FPN data and the at least one RTN data acquired from the PUF data; as well as an image encryption unit that communicates with the image sensing device and the private key generation unit and encrypts the image data using the private key, wherein the PUF generator comprises a first transistor and the image generator comprises a second transistor corresponding to the first transistor, and wherein the first transistor exhibits a different property than the second transistor.

2. The imaging device according to claim 1, wherein: The first transistor has a smaller gate area than the second transistor.

3. The imaging device according to claim 1, wherein: The first transistor has a higher threshold voltage than the second transistor.

4. The imaging device according to claim 1, wherein: The PUF generator generates the PUF data based on a pixel signal generated when incident light is blocked, The PUF data includes information about the at least one FPN data.

5. The imaging device according to claim 4, further comprising: a physical unclonable function PUF acquisition unit, the PUF acquisition unit acquiring the at least one FPN data from the PUF data, The PUF acquisition unit determines whether the at least one FPN data is a first logic level or a second logic level by comparing the PUF data with a first threshold.

6. The imaging device according to claim 1, wherein: Each of the image generator and the PUF generator comprises: A driving transistor converts a potential of a floating diffusion region holding photo charges into a voltage signal.

7. The imaging device according to claim 6, wherein: The first transistor corresponds to a driving transistor included in the PUF generator, and The second transistor corresponds to a driving transistor included in the image generator.

8. The imaging device according to claim 6, wherein: The PUF generator generates the PUF data in each of a first image acquisition section and a second image acquisition section which are continuously connected to each other based on the voltage signal of the driving transistor, The PUF data includes information about a first random telegraph noise RTN data among the at least one RTN data.

9. The imaging device according to claim 8, further comprising: a physical unclonable function PUF acquisition unit, wherein the PUF acquisition unit acquires the at least one RTN data from the PUF data, The PUF acquisition unit performs a subtraction operation on the first PUF data generated in the first image acquisition section and the second PUF data generated in the second image acquisition section, and determines whether the first RTN data is a first logic level or a second logic level by comparing a result of the subtraction operation with a second threshold.

10. The imaging device according to claim 1, wherein: Each of the image generator and the PUF generator comprises: a comparator that compares a pixel signal with a ramp signal and generates a comparison signal corresponding to a voltage difference between the pixel signal and the ramp signal based on a result of the comparison between the pixel signal and the ramp signal; and A counter performs a counting operation in response to a level of the comparison signal.

11. The imaging device according to claim 10, wherein: The comparator includes a transistor for receiving the pixel signal and a transistor for receiving the ramp signal. The first transistor includes a transistor included in the PUF generator and receiving the pixel signal, and a transistor receiving the ramp signal, and The second transistor includes a transistor included in the image generator and receiving the pixel signal, and a transistor receiving the ramp signal.

12. The imaging device according to claim 11, wherein: The comparator further includes a transistor for applying a bias current to a transistor receiving the pixel signal and a transistor receiving the ramp signal, The first transistor corresponds to a transistor included in the PUF generator to apply the bias current, and The second transistor corresponds to a transistor included in the image generator to apply the bias current.

13. The imaging device according to claim 10, wherein: The PUF generator generates the PUF data in a state where a selection transistor outputting the pixel signal is turned off, The PUF data includes information about second RTN data among the at least one RTN data.

14. The imaging device according to claim 13, further comprising: a physical unclonable function PUF acquisition unit, wherein the PUF acquisition unit acquires the at least one RTN data from the PUF data, The PUF acquisition unit determines the second RTN data as the first logic level or the second logic level by comparing the PUF data with a third threshold.

15. An imaging device, comprising: An image sensing device, the image sensing device comprising: one or more first image detection pixels and one or more second image detection pixels, the one or more first image detection pixels and the one or more second image detection pixels being configured to convert light incident on the image detection pixels into pixel signals representing an image; a first transistor coupled to the one or more first image detection pixels and configured to generate physically unclonable function (PUF) data including information about at least one fixed pattern noise (FPN) data and at least one random telegraph noise (RTN) data; and a second transistor coupled to the one or more second image detection pixels and configured to generate image data acquired by converting light corresponding to the image; a private key generation unit, the private key generation unit generating a private key based on the at least one FPN data and the at least one RTN data of the PUF data; and an image encryption unit, the image encryption unit encrypting the image data using the private key, The first transistor exhibits different noise properties than the second transistor.

16. The imaging device according to claim 15, wherein: The first transistor has a smaller gate area than the second transistor.

17. The imaging device according to claim 15, wherein: The first transistor has a higher threshold voltage than the second transistor.

18. The imaging device according to claim 15, wherein: The at least one FPN data and the at least one RTN data include a noise pattern unique to the image sensing device.

19. The imaging device according to claim 15, wherein: The private key includes an identifier for identifying the image data.

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