A laminate structure optimization method and system for reducing warping of printed circuit boards

Abstract

The present invention provides a laminate structure optimization method and system for reducing the warpage of a printed circuit board, designs preliminary different laminate structures of printed circuit boards; controls the characteristic impedance of each laminate structure of the printed circuit board to determine a reasonable laminate structure of the printed circuit board; establishes the geometric model and mathematical model required for the simulation of the press-molding of the printed circuit board for the reasonable laminate structure of the printed circuit board, and obtains different schemes corresponding to different laminate structures; solves the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board corresponding to different schemes during the press-molding process, and determines the warpage deformation morphology and warpage amount of the printed circuit board after pressing; determines the scheme with the minimum warpage amount as the final scheme. The present invention can meet the signal integrity requirements, and at the same time can control or reduce the out-of-plane warpage of the PCB after pressing, laying a foundation for the reliability of the IC packaging process of the subsequent reflow soldering chip and the packaging substrate.

Description

Technical Field

[0001] The invention belongs to the technical field of printed circuit boards, and relates to a laminate structure optimization method and system for reducing warping of printed circuit boards. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] With the continuous advancement of informatization, printed circuit boards (PCBs) as carriers of information transmission are playing an increasingly important role in aerospace, industrial Internet of Things, automotive consumer electronics, smart devices and other fields. With the miniaturization of devices and the refinement of circuits, the manufacturing process of traditional PCBs faces severe challenges. Due to the mismatch of thermal expansion coefficients of the materials that make up the PCB and the chemical shrinkage effect of the resin in the manufacturing process, the PCB will warp after lamination, which will continue to affect the quality of the subsequent reflow soldering chip process. Especially for ultra-thin PCBs and packaging substrates, the warpage exceeding the limit tolerance range will cause adverse consequences such as surface mount failure and solder joint cracking, thereby increasing manufacturing costs and delaying the design and production process of PCBs.

[0004] Controlling or reducing the warpage of PCB manufacturing process by changing the structure or material of PCB is one of the methods to improve the production quality of PCB. The composition structure of PCB includes copper clad laminate and prepreg. The circuit patterns have been etched on the upper and lower surfaces of copper clad laminate, and a layer of electronic glass fiber cloth reinforced epoxy resin adhesive sheet is sandwiched in the middle. The commonly used material is FR-4; the prepreg is an electronic glass fiber cloth reinforced epoxy resin composite material prepreg with the resin in the B stage state. After pressing, the resin undergoes a chemical cross-linking reaction and becomes the C stage, which firmly bonds the adjacent copper clad laminates and plays a reliable insulation role. Due to the presence of electronic glass fiber cloth, the mechanical properties of the warp and weft axes of the prepreg are different; the mechanical properties of different types of prepregs are also different.

[0005] At present, most of the research on warpage control in the PCB manufacturing process is based on experimental research and is limited to small-sized double-layer or four-layer PCBs. If a large number of tests are used to determine the effect of the PCB stacking structure on the warpage after PCB lamination, it will not only increase a lot of test costs, but also be affected by environmental factors and the manufacturing tolerance of the prepreg, and it is difficult to find a regularity in the results obtained; in addition, for high-speed and high-frequency signal lines, it also involves issues such as signal integrity and electromagnetic compatibility. Changes in the PCB stacking structure will also affect the transmission reliability of high-speed signals, especially the need to control the characteristic impedance of the signal transmission line. The physical meaning of impedance is the resistance to the transmission of square wave signals or pulses on the transmission line. When the instantaneous impedance of each area of ​​the transmission line is the same, the impedance becomes the characteristic impedance of the transmission line. A sudden change in instantaneous impedance will cause signal reflection and signal distortion. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a laminate structure optimization method and system for reducing the warping of a printed circuit board. On the one hand, the present invention can meet the signal integrity requirements, and on the other hand, it can control or reduce the out-of-plane warping amount of the PCB after pressing, laying a foundation for the reliability of the subsequent reflow soldering chip and the integrated circuit (IC) packaging process of the packaging substrate.

[0007] According to some embodiments, the present invention adopts the following technical solutions:

[0008] A laminate structure optimization method for reducing warping of a printed circuit board comprises the following steps:

[0009] Design preliminary different printed circuit board stackup structures;

[0010] Control the characteristic impedance of each printed circuit board stacking structure and determine a reasonable printed circuit board stacking structure;

[0011] For the reasonable printed circuit board stacking structure, a geometric model and a mathematical model required for the printed circuit board pressing and forming simulation are respectively established to obtain different schemes corresponding to different stacking structures;

[0012] Solve the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board during the pressing and forming process corresponding to different schemes, and determine the warping deformation morphology and warping amount of the printed circuit board after pressing;

[0013] The solution that minimizes the warpage is determined as the final solution.

[0014] As an optional implementation, the specific process of designing preliminary different printed circuit board stacking structures includes: determining the structural information of the printed circuit board, including the type of prepreg, the final thickness of the prepreg, the interlayer position of the prepreg in the printed circuit board, and the circuit characteristics of the wiring layer and the final thickness and relative position information of the copper clad core layer;

[0015] Using modeling software, different types of prepregs are marked with different colors, and different types of prepregs with the same thickness and prepregs with different thicknesses are adopted to establish different printed circuit board stacking structures.

[0016] As an optional implementation, the specific process of controlling the characteristic impedance of each printed circuit board stacking structure includes: based on the single-ended impedance and differential impedance calculation model, assuming that the line width, line spacing and line thickness of the signal transmission lines of all signal layers of a certain printed circuit board stacking structure remain unchanged, changing the thickness of the semi-cured sheet layer or the type of the semi-cured sheet layer, changing the relevant parameters, and calculating the characteristic impedance of the signal line.

[0017] As a further limitation, the related parameters include the line width, line thickness, line spacing of the signal lines of the wiring layer of the printed circuit board, and the final thickness and dielectric constant of the prepreg layer and the copper clad laminate core layer after lamination.

[0018] As an optional implementation, the specific process of determining a reasonable printed circuit board stacking structure includes: determining a printed circuit board stacking structure with continuous impedance as a reasonable printed circuit board stacking structure.

[0019] As a further limitation, impedance continuity means that after the laminate structure of the printed circuit board is changed, the value of the characteristic impedance of the corresponding signal line must satisfy that the change values ​​of the single-ended impedance and the differential impedance are both less than a given tolerance compared with the original value.

[0020] As an optional implementation method, the specific process of establishing the geometric model and the mathematical model includes: establishing geometric models for the wiring layer, the semi-cured sheet layer, and the copper-clad core board layer respectively according to the designed laminated structure, testing the material performance parameters of each layer through relevant experiments, performing numerical simulation based on the material performance parameters, and iteratively solving the heat transfer equation and the continuous medium mechanics equation.

[0021] As a further limitation, the specific process of establishing the geometric model includes establishing an equivalent three-dimensional geometric figure with uneven corners removed based on the actual three-dimensional dimensions of the semi-cured sheet layer, wiring layer, and copper clad laminate core layer, and then offsetting the three-dimensional geometric figures of all layers to the same position as the laminate structure.

[0022] As a further limitation, the material performance parameters include one or more of density, specific heat capacity, thermal conductivity, elastic modulus, shear modulus, Poisson's ratio, thermal expansion coefficient, curing reaction exothermic enthalpy, and chemical reaction volume shrinkage rate.

[0023] As an optional implementation method, after determining the warping deformation morphology and warping amount of the upper surface of the printed circuit board after lamination, a comparative analysis is performed on the warping deformation morphology and warping amount of the upper surfaces of different printed circuit boards after lamination, and the warping deformation morphologies of the upper surfaces of the printed circuit boards of different schemes are compared in pairs, and the differences in details are compared to determine the influence of the thickness of the semi-cured sheet layer or the type of the semi-cured sheet of the semi-cured sheet layer on the warping deformation morphology of the upper surface of the printed circuit board; a relationship diagram is drawn between the warping amount of the printed circuit board corresponding to different schemes and the scheme number, and the difference in warping amount is compared to determine that the scheme that minimizes the warping amount of the printed circuit board is the final scheme.

[0024] A laminate structure optimization system for reducing warpage of a printed circuit board, comprising:

[0025] The stacking structure design module is used to design preliminary stacking structures of different printed circuit boards;

[0026] The impedance calculation module is used to control the characteristic impedance of the designed printed circuit board stacking structure and determine a reasonable printed circuit board stacking structure;

[0027] A mathematical modeling module is used to establish geometric models and mathematical models required for printed circuit board pressing and forming simulation for the reasonable printed circuit board stacking structure, and obtain different solutions corresponding to different printed circuit board stacking structures;

[0028] Numerical simulation module, used to solve the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board in the pressing and forming process corresponding to different schemes, and determine the warping deformation morphology and warping amount of the upper surface of the printed circuit board after pressing;

[0029] The comparison and determination module is used to compare and analyze the warping deformation morphology and warping amount of the upper surface of printed circuit boards with different laminated structures after pressing, and determine the solution that minimizes the warping amount as the final solution.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention adopts a numerical simulation method and a small amount of experimental results to optimize the design of the PCB stacking structure. Based on the prediction of the warping deformation during the PCB pressing process and the PCB stacking structure design, by comparing the warping amounts of PCBs with different stacking structures after pressing, the PCB stacking structure design that minimizes the warping amount after the PCB pressing is found, which can achieve the purpose of reducing the warping deformation after the PCB pressing, reducing the R&D and design costs of the PCB, and improving the quality reliability of PCB production.

[0032] Based on the principles of numerical analysis and three-dimensional geometric modeling, the present invention can present the surface node displacement distribution diagram of the PCB after pressing and obtain the warping amount of the PCB upper surface, providing ideas and reference solutions for controlling the warping problem in the manufacturing process of large-size multi-layer PCBs or ultra-thin packaging substrates.

[0033] The PCB stacking structure design technology proposed in the present invention takes into account the characteristic impedance of the high-speed signal line, keeps the circuit pattern characteristics, the position of the copper clad laminate and the type of all copper clad laminate core layers unchanged, changes the two variables of the type and thickness of the prepreg layer, that is, the same type of prepreg but different thicknesses, the same thickness of prepreg but different types, to obtain different PCB stacking structure designs, visualize the different PCB stacking structures, calculate the characteristic impedance of each signal layer one by one, and leave the PCB stacking structure design that meets the impedance limit tolerance range, which is conducive to realizing the integration of PCB structure design and functional design. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0035] Figure 1 It is a flow chart of the stacked structure optimization method involved in the present invention;

[0036] Figure 2 is a three-dimensional diagram of a stacked structure in software N involved in Embodiment 1 of the present invention;

[0037] Figure 3 is a cross-sectional view of the original laminated structure of the PCB involved in the first embodiment of the present invention;

[0038] Figure 4 is a schematic diagram of a laminated structure design case involved in Embodiment 1 of the present invention;

[0039] Figure 5 It is a comparison between the numerical simulation results and the experimental results of the out-of-plane warpage of the PCBs corresponding to the six groups of PCB stacking structures when cooled to room temperature under the same process. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0042] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] The first part provides a laminate structure optimization method for reducing the warpage of a printed circuit board, comprising the following steps:

[0044] Step 1: Design preliminary stacking structures of different printed circuit boards;

[0045] Step 2: Control the characteristic impedance of each printed circuit board stacking structure to determine a reasonable printed circuit board stacking structure;

[0046] Step 3: establishing geometric models and mathematical models required for printed circuit board pressing and forming simulation for the reasonable printed circuit board stacking structures, and obtaining different solutions corresponding to different stacking structures;

[0047] Step 4: Solve the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board corresponding to different schemes during the pressing and forming process, and determine the warping deformation morphology and warping amount of the printed circuit board after pressing;

[0048] Step 5: Analyze and compare the warpage deformation morphology and warpage amount of different printed circuit boards after lamination, and determine the solution that minimizes the warpage amount as the final solution.

[0049] The stacked structure mentioned in the present invention may also be called a laminated structure or a multilayer structure.

[0050] The specific implementation process of designing the preliminary different printed circuit board stacking structures in step 1 includes:

[0051] (1) Determine the structural information of the PCB, including the type of prepreg, the final thickness of the prepreg, the interlayer position of the prepreg in the PCB, the circuit characteristics of the wiring layer, and the final thickness and relative position of the copper clad laminate core layer;

[0052] (2) Different types of prepregs are marked with different colors in software M. Different PCB stacking structures are established by using two methods: prepregs of different types with the same thickness, and prepregs of different thicknesses with the same type.

[0053] The specific implementation of step 2 includes:

[0054] Establish the same PCB stacking structure as in step (2) of step 1 in software N, select the impedance calculation model composed of the corresponding signal line and reference plane, input the parameters required for characteristic impedance calculation, and calculate the characteristic impedance of the high-speed signal line of each signal layer in the PCB;

[0055] Determine the impedance continuous PCB stacking structure, so as to reversely verify the rationality of the PCB stacking structure.

[0056] Specifically, based on the impedance calculation method of high-speed signal lines and the control variable method, the rationality of the PCB stacking structure corresponding to the two variables of changing the type of prepreg layer and the thickness of the prepreg layer is verified, and a batch of reasonable PCB stacking structures are determined to prepare for subsequent mathematical modeling and numerical simulation.

[0057] The prepreg type is determined according to the brand of electronic glass fiber cloth and the mass fraction of resin in the prepreg. For example, if the commercial brand of a prepreg is 2116 and the mass fraction of resin is 58%, the prepreg is defined as prepreg A.

[0058] The thickness and type of the prepreg layer are derived from the manufacturer and should be adjusted accordingly based on specific production conditions and manufacturers.

[0059] The thickness of the prepreg layer is the dielectric thickness between two adjacent wiring layers after the prepreg undergoes a chemical cross-linking reaction, and the specific thickness should be measured.

[0060] Preferably, the thickness of the prepreg layer is an integer multiple of the thickness of a specific type of prepreg, or the algebraic sum of the thicknesses of different types of prepregs.

[0061] Preferably, the number of prepregs in the prepreg layer is at most 6 and at least 1. Of course, the above parameters can be replaced or adjusted according to specific application scenarios.

[0062] Changing the thickness of the prepreg layer refers to changing the dielectric thickness of two adjacent wiring layers, and this purpose is achieved by increasing / deleting the number of prepregs.

[0063] Changing the type of the prepreg layer means keeping the dielectric thickness of two adjacent wiring layers unchanged, and selecting a certain number of prepregs of other types in an arrangement and combination manner to meet the requirement of the same or similar thickness.

[0064] The wiring layer circuit characteristics include the percentage of the in-plane circuit pattern area to the total area of ​​the wiring layer, the thickness of the conductive line, the width of the conductive line, the spacing between adjacent conductive lines, etc.

[0065] The establishment of the PCB stacking structure refers to inputting text, letters or other character marks that can represent a layer of information in pairs in the vertically adjacent cells in the software M, and then filling the same type of layers with the same background color to intuitively display the information of different layers and the cross-sectional view of the PCB thickness direction.

[0066] The software N is a multi-layer PCB stacking structure design software. Its built-in impedance calculation module can provide characteristic impedance prediction of high-speed signal lines for PCB designers and manufacturers who need to control characteristic impedance. The present invention uses this tool to calculate the characteristic impedance value of a multi-layer PCB with a certain number of layers and circuit pattern characteristics when transmitting high-speed signals. This is a method that can be obtained and mastered by professional technicians based on existing knowledge.

[0067] The physical meaning of the characteristic impedance of the PCB high-speed signal line is the resistance encountered by the square wave signal or pulse when it is transmitted on the high-speed signal line. It is an inherent property of the transmission line and has nothing to do with the length of the transmission line. The unit is Ω. The characteristic impedance includes single-ended impedance and differential impedance. In the field of circuit design, in order to reduce signal transmission loss, the single-ended impedance is generally required to be 50Ω and the differential impedance is 100Ω. Of course, according to the specific application scenario, the above parameters can be replaced or adjusted.

[0068] The impedance calculation model composed of the signal line and the reference plane refers to a microstrip line model and a stripline model; among them, the model containing a single transmission line and one or two reference planes is used to calculate the single-ended characteristic impedance, and the model containing two parallel transmission lines and one or two reference planes is used to calculate the differential impedance; the software N can have the above model built in, and the model includes the parameters required for calculating the impedance.

[0069] The parameters required for the characteristic impedance calculation should be determined according to different impedance calculation models, and should at least include the line width, line thickness, line spacing of the signal line of the wiring layer of the PCB, and the final thickness and dielectric constant of the prepreg layer and the copper clad core layer after lamination.

[0070] Whether the impedance is continuous refers to the calculation by software N that the characteristic impedance of the corresponding signal line after changing the PCB stacking structure must satisfy the change in single-ended impedance and differential impedance that is less than a given tolerance compared to the original. This is a judgment that professional technicians can make based on existing knowledge.

[0071] Preferably, the impedance variation tolerance depends on the type of signal transmission line. For high-frequency and high-speed signal transmission lines, the characteristic impedance tolerance is ±5% or less.

[0072] Changing the two variables of the thickness of the prepreg and the type of the prepreg means keeping the type of the prepreg layer unchanged while changing the thickness of the layer, or keeping the thickness of the prepreg layer unchanged while only changing the type of the prepreg layer.

[0073] Furthermore, the stacking structure of the specific PCB involved is controlled, the wiring pattern characteristics and the core layer position of the copper clad laminate remain unchanged, different stacking structures are designed, and then the characteristic impedance of each signal layer is calculated one by one to determine the impedance continuity.

[0074] The specific process of the step three includes establishing geometric models for the wiring layer, the prepreg layer, and the copper clad laminate core layer respectively according to the designed laminate structure, testing the material performance parameters of each layer through relevant experiments, and inputting the material performance parameters obtained from the experimental test or the material performance parameters retrieved from the material database into the pre-processing module of the numerical simulation software, iteratively solving the heat transfer equation and the continuous medium mechanics equation based on the solver module of the numerical simulation software, and visually presenting the numerical solution of the upper surface warpage of the PCB after pressing in the post-processing module of the numerical simulation software.

[0075] In some embodiments, a press-molding experiment can be carried out using PCBs with the same process conditions, and then a non-contact optical measurement method can be used to measure the warpage deformation of the upper surface of the actual PCB after pressing, so as to compare and verify the effectiveness of the prediction method.

[0076] The stacking structure mentioned in the above process is determined according to the PCB stacking structure drawing provided by the manufacturer or PCB designer, including the prepreg layer, wiring layer and copper clad core layer.

[0077] The establishment of the geometric model refers to establishing an equivalent three-dimensional geometric figure with uneven corners removed according to the three-dimensional dimensions of the prepreg layer, wiring layer, and copper clad laminate core layer in the three-dimensional modeling software, and then offsetting the three-dimensional geometric figures of all layers to the same position as the laminated structure.

[0078] The material performance parameters include, but are not limited to, one or more of density, specific heat capacity, thermal conductivity, elastic modulus, shear modulus, Poisson's ratio, thermal expansion coefficient, curing reaction exothermic enthalpy, and chemical reaction volume shrinkage rate.

[0079] The pre-processing module input into the numerical simulation software refers to using the PCB material performance parameters obtained from experimental tests or the material performance parameters retrieved from the material database as the necessary conditions for calculating the stress-strain constitutive relationship and temperature field of each layer of material, and inputting the parameters through the built-in graphical interface of the pre-processing module of the numerical simulation software or the custom code of the programming language recognizable by the software.

[0080] The solver module of the numerical simulation is based on the numerical calculation method built into the software, which is an implicit or explicit calculation method disclosed by commercial software or recognized by the industry, and can be mastered by professional technicians based on existing knowledge.

[0081] The heat transfer equation and continuous medium mechanics equation can be understood and mastered by technical personnel in this field based on existing knowledge, and should be adjusted accordingly based on actual problems.

[0082] The numerical solution of the warpage of the PCB after lamination refers to the difference between the maximum positive displacement and the maximum absolute negative displacement of all geometric points on the surface of the PCB three-dimensional geometric model in the thickness direction, calculated in the Cartesian coordinate system contained in the post-processing module based on mathematical modeling theory, material performance parameters and numerical calculation tools. The unit is length unit and corresponding adjustments are made according to the specific value.

[0083] In a second aspect, a laminate structure optimization system for reducing warping of a printed circuit board is provided, comprising a laminate structure design module, an impedance calculation module, a mathematical modeling module, a numerical simulation module and a comparison determination module.

[0084] The stacking structure design module is used to design different PCB stacking structure schematics in the software M and present them in a visual manner. Designers can change two variables, namely, the prepreg type and the final thickness of the prepreg, to obtain two different PCB stacking structure diagrams.

[0085] The impedance calculation module is used to control the characteristic impedance of the designed PCB stacking structure in the software N, that is, based on the single-ended impedance and differential impedance calculation model, assuming that the line width, line spacing and line thickness of the signal transmission lines of all signal layers of a certain PCB stacking structure remain unchanged, and the thickness of the prepreg layer or the type of the prepreg layer is changed, then the relevant parameters are changed, the characteristic impedance of the signal line is calculated, and it is verified that the value of the characteristic impedance does not exceed the limit tolerance range, so as to determine a reasonable PCB stacking structure.

[0086] The mathematical modeling module is used to establish the geometric model and mathematical model required for PCB press-forming simulation based on different PCB stacking structures in the three-dimensional modeling software, that is, to establish a visual three-dimensional geometric figure according to the designed PCB stacking structure diagram, and then establish mathematical equations and theoretical formulas based on thermal, mechanical, and chemical subject knowledge that meet physical reality, and obtain different solutions corresponding to different stacking structures.

[0087] The numerical simulation module is used to numerically solve the temperature field, curing degree field, stress field, strain field and node displacement field of the PCB corresponding to different schemes during the pressing and forming process in the numerical simulation software, and to present the warping deformation morphology and warping amount of the upper surface of the PCB after pressing in a visual manner through post-processing.

[0088] The comparison and determination module is used to compare and analyze the warping deformation morphology and warping amount of the upper surface of the PCB corresponding to different schemes after pressing, that is, to compare the warping deformation morphology of the upper surface of the PCB of different schemes in pairs, compare the differences in details, and determine the influence of the thickness of the semi-cured sheet layer or the semi-cured sheet type of the semi-cured sheet layer on the warping deformation morphology of the upper surface of the PCB; make a relationship diagram between the PCB warping amount corresponding to different schemes and the scheme number, compare the difference in warping amount, determine the influence of the thickness of the semi-cured sheet layer or the semi-cured sheet type of the semi-cured sheet layer on the warping amount of the upper surface of the PCB, and find the preferred scheme that minimizes the warping amount.

[0089] In the implementation manner of the present invention, the optimization design system should be adjusted according to the specific PCB stacking structure and geometric dimensions.

[0090] It should be noted that the software M and the software N can be designed by themselves according to the requirements, or existing software can be used.

[0091] The following is a detailed description with reference to specific embodiments.

[0092] Embodiment 1

[0093] A stacking structure optimization method for a ten-layer PCB is proposed. The initial PCB stacking structure is used as a control group, and different PCB stacking structures are designed based on two factors: the thickness of the prepreg layer between the wiring layers and the type of the prepreg. The method includes the following steps:

[0094] Step 1: Determine the multi-layer PCB stacking structure information. The types of prepregs used are 2116, 3313, and 1080. In the PCB stacking structure, the resin mass fraction of the 2116 prepreg is 58%, and its final thickness is 125μm. The resin mass fraction of the 3313 prepreg is 63%, and its final thickness is 100μm. The resin mass fraction of the 1080 prepreg is 64%, and its final thickness is 70μm.

[0095] Step 2: Ensure that the thickness of the prepreg layer remains unchanged and change the type of prepreg to obtain two sets of PCB stacking structures, that is, 4 2116 prepregs or 5 3313 prepregs form a 500μm thick prepreg layer;

[0096] Step 3: Ensure that the prepreg type of the prepreg layer remains unchanged and change the thickness, and continue to obtain four groups of PCB stacking structures, that is, the same 2116 prepreg or the same 3313 prepreg but the number of prepregs used is different, that is, three 2116 prepreg layers with a thickness of 375μm, five 2116 prepreg layers with a thickness of 625μm, four 3313 prepreg layers with a thickness of 400μm, and six 2116 prepreg layers with a thickness of 600μm.

[0097] Step 4: Use software N to establish the above six stacking structures, that is, select the graphics of different colors built into the software for stacking according to the designed interlayer structure, such as Figure 2 As shown in the figure, the graphic meaning includes copper foil, signal layer, power layer, ground layer, prepreg, copper clad laminate, solder mask, etc. Then the line width, line spacing, line thickness of the signal line and the thickness and dielectric constant of the prepreg layer are input to calculate the characteristic impedance of each signal layer. The results show that all six groups of PCB stacking structures meet the impedance matching requirements.

[0098] Step 5: Perform geometric modeling on the six groups of PCB stacking structures in the 3D modeling software respectively, input the material properties of the semi-cured sheet and copper-clad laminate tested in the experiment into the numerical simulation software, set the initial and boundary conditions of heat transfer and mechanics that are the same or equivalent to the actual pressing process, perform numerical simulation of PCB pressing and forming respectively, and obtain the warping deformation morphology and warping amount of the upper surface of the six groups of PCBs after pressing.

[0099] Step 6: Compare the warpage of six groups of PCBs with different laminate structures after lamination, and use the same laminate structure and the same lamination process parameters as the numerical simulation to obtain the measured warpage of the PCB after lamination, so as to verify the numerical simulation results, determine the law of the influence of the thickness and type of the prepreg layer on the warpage of the PCB, and take the PCB laminate structure corresponding to the minimum warpage as the preferred laminate structure.

[0100] In the embodiment, the original PCB stacking structure involved is as follows Figure 3 As shown, the schematic diagrams of the changes in the other five groups of PCB stacking structures are as follows Figure 4 As shown in the figure, the numerical simulation results and experimental results of the out-of-plane warpage of the PCB corresponding to these six stacked structures when cooled to room temperature under the same process are compared as shown in the figure Figure 5 As shown, it can be seen that design ⑤ is the preferred solution.

[0101] A stacking structure optimization design method for an eight-layer PCB for a server is disclosed. The initial PCB stacking structure is used as a control group, and different PCB stacking structures are designed based on two factors: the thickness of the prepreg layer between the wiring layers and the type of the prepreg. The difference from the first embodiment is that the number of wiring layers is reduced by two layers and the number of prepregs is also reduced accordingly, and the optional schemes for stacking structure design are reduced, but the stacking structure optimization method involved is universal.

[0102] The specific implementation steps have been described in detail in Example 1 and will not be described in detail here.

[0103] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0105] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0107] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0108] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A laminate structure optimization method for reducing warping of a printed circuit board, characterized in that: The following steps are involved: Design preliminary different printed circuit board stackup structures; Control the characteristic impedance of each printed circuit board stacking structure and determine a reasonable printed circuit board stacking structure; For the reasonable printed circuit board stacking structure, a geometric model and a mathematical model required for the printed circuit board pressing and forming simulation are respectively established to obtain different schemes corresponding to different stacking structures; Solve the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board during the pressing and forming process corresponding to different schemes, and determine the warping deformation morphology and warping amount of the printed circuit board after pressing; Determine the solution that minimizes the warpage as the final solution; The specific process of establishing geometric models and mathematical models includes: establishing geometric models for the wiring layer, prepreg layer, and copper-clad laminate core layer according to the designed laminate structure, testing the material performance parameters of each layer through relevant experiments, performing numerical simulation based on the material performance parameters, and iteratively solving the heat transfer equation and continuous medium mechanics equation; The specific process of establishing the geometric model includes establishing an equivalent three-dimensional geometric figure with uneven corners removed according to the actual three-dimensional dimensions of the prepreg layer, wiring layer, and copper-clad laminate core layer, and then offsetting the three-dimensional geometric figures of all layers to the same position as the laminate structure.

2. A laminate structure optimization method for reducing warping of a printed circuit board as claimed in claim 1, characterized in that: The specific process of designing preliminary different printed circuit board stacking structures includes: determining the structural information of the printed circuit board, including the type of prepreg, the final thickness of the prepreg, the interlayer position of the prepreg in the printed circuit board, and the circuit characteristics of the wiring layer and the final thickness and relative position information of the copper clad core layer; Using modeling software, different types of prepregs are marked with different colors, and different types of prepregs with the same thickness and prepregs with different thicknesses are adopted to establish different printed circuit board stacking structures.

3. The method for optimizing the laminate structure for reducing the warpage of a printed circuit board according to claim 1, characterized in that: The specific process of controlling the characteristic impedance of each printed circuit board stacking structure includes: based on the single-ended impedance and differential impedance calculation model, assuming that the line width, line spacing and line thickness of the signal transmission lines of all signal layers of a certain printed circuit board stacking structure remain unchanged, changing the thickness of the prepreg layer or the type of the prepreg layer, changing the relevant parameters, and calculating the characteristic impedance of the signal line.

4. A laminate structure optimization method for reducing warping of a printed circuit board as claimed in claim 3, characterized in that: The related parameters include the line width, line thickness, line spacing of the signal line of the wiring layer of the printed circuit board, and the final thickness and dielectric constant of the prepreg layer and the copper clad laminate core layer after lamination.

5. The method for optimizing the laminate structure for reducing the warpage of a printed circuit board according to claim 1, wherein: The specific process of determining a reasonable laminated structure of a printed circuit board includes: determining a laminated structure of a printed circuit board with continuous impedance as a reasonable laminated structure of a printed circuit board; Impedance continuity means that after changing the laminate structure of the printed circuit board, the characteristic impedance of the corresponding signal line must satisfy the change in single-ended impedance and differential impedance that is less than a given tolerance compared to the original value.

6. The method for optimizing the laminate structure for reducing the warpage of a printed circuit board as claimed in claim 1, characterized in that: The material performance parameters include one or more of density, specific heat capacity, thermal conductivity, elastic modulus, shear modulus, Poisson's ratio, thermal expansion coefficient, curing reaction exothermic enthalpy, and chemical reaction volume shrinkage rate.

7. The method for optimizing the laminate structure for reducing the warpage of a printed circuit board according to claim 1, characterized in that: After determining the warping deformation morphology and warping amount of the upper surface of the printed circuit board after lamination, a comparative analysis is conducted on the warping deformation morphology and warping amount of the upper surfaces of different printed circuit boards after lamination, and the warping deformation morphologies of the upper surfaces of the printed circuit boards of different schemes are compared in pairs. The differences in details are compared to determine the influence of the thickness of the semi-cured sheet layer or the type of the semi-cured sheet of the semi-cured sheet layer on the warping deformation morphology of the upper surface of the printed circuit board; a relationship diagram is drawn between the warping amount of the printed circuit board corresponding to different schemes and the scheme number, and the difference in warping amount is compared to determine that the scheme that minimizes the warping amount of the printed circuit board is the final scheme.

8. A laminate structure optimization system for reducing warpage of a printed circuit board, characterized in that: include: The stacking structure design module is used to design preliminary stacking structures of different printed circuit boards; The impedance calculation module is used to control the characteristic impedance of the designed printed circuit board stacking structure and determine a reasonable printed circuit board stacking structure; A mathematical modeling module is used to establish geometric models and mathematical models required for printed circuit board pressing and forming simulation for the reasonable printed circuit board stacking structure, and obtain different solutions corresponding to different printed circuit board stacking structures; Numerical simulation module, used to solve the temperature field, curing degree field, stress field, strain field and node displacement field of the printed circuit board in the pressing and forming process corresponding to different schemes, and determine the warping deformation morphology and warping amount of the upper surface of the printed circuit board after pressing; A comparison and determination module is used to compare and analyze the warping deformation morphology and warping amount of the upper surface of printed circuit boards with different laminated structures after lamination, and determine the solution with the minimum warping amount as the final solution; The specific process of establishing geometric models and mathematical models includes: establishing geometric models for the wiring layer, prepreg layer, and copper-clad laminate core layer according to the designed laminate structure, testing the material performance parameters of each layer through relevant experiments, performing numerical simulation based on the material performance parameters, and iteratively solving the heat transfer equation and continuous medium mechanics equation; The specific process of establishing the geometric model includes establishing an equivalent three-dimensional geometric figure with uneven corners removed according to the actual three-dimensional dimensions of the prepreg layer, wiring layer, and copper-clad laminate core layer, and then offsetting the three-dimensional geometric figures of all layers to the same position as the laminate structure.

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