Prototype verification method and device of DDR4 controller, equipment, medium and product

Abstract

The invention discloses a prototype verification method of a DDR4 controller in the technical field of chip verification, the method is applied to a prototype verification platform, a DDR controller and a PHY module in a chip to be verified are matched on the prototype verification platform, and the PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script; the prototype verification method comprises the steps that in response to a verification instruction received by a DDR controller, the DDR controller generates a control instruction according to the verification instruction and sends the control instruction to a DFI to phy only interface module; in response to the control instruction received by the DFI to phy only interface module, the DFI to phy only interface module converts the control instruction from a DFI protocol to a target control instruction of a PHY protocol, and sends the target control instruction to the standalone PHY only block module; in response to the control instruction received by the standalone PHY only block module, the standalone PHY only block module sends a target control instruction to a DDR particle externally connected with the prototype verification platform, so that read-write and verification with the DDR particle are realized; according to the method, the DDR memory interface IP prototype verification code coverage rate can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly relates to a method, device, equipment, medium and product for prototype verification of a DDR4 controller. Background Art

[0002] In SoC design, the DDR memory interface module is divided into a controller (Memory Controller, MC) and a physical layer (Physical Layer, PHY). The main function of the MC module is to receive commands and data sent by the CPU through the AXI interface. After being processed by modules such as the arbitration module and the memory access scheduling module, it decodes them and transmits them to the PHY through the DFI transmission module. The main function of the PHY module is to convert the data sent by the MC module into signals that conform to the DDR protocol, that is, the timing specified by the JESD79-4 standard protocol, and send them to the DDR particles. Through automatic calibration and training, the PHY continuously adjusts the input and output delays so that the timing window of each signal line reaches various optimal states.

[0003] FPGA prototype verification appears as a system function verification process for ASIC and SoC designs. Currently, the hardware devices for prototype verification are mainly divided into three categories: one is the FPGA board (Build Your Own, hereinafter referred to as BYO) made by chip design companies themselves. One is to directly purchase off-the-shelf development boards from FPGA manufacturers such as AMD and Altera. The other is the commercial prototype verification system provided by professional companies. When performing FPGA prototype verification on SoC designs, due to different physical structures, the ASIC code must be converted to some extent before it can be used as the input of the FPGA. The main conversion contents include: clock resources, PLL design, RAM design, and analog IP. Using FPGA software such as vivado to synthesize and implement the converted RTL code can generate a bitstream file that can run on the FPGA. FPGA prototype verification provides a real simulation test environment, while traditional software simulation methods cannot fully simulate SoC designs in terms of speed and capacity.

[0004] Since IP suppliers usually do not provide the source code of the DDR PHY but hard cores, and the PHY code provided by IP manufacturers is optimized for the process library and contains analog circuits, it cannot be compatible with FPGA design tools (such as Vivado), resulting in the necessity of converting the DDR PHY. Since the MC module cannot be directly connected to the DDR particles, in the absence of an alternative solution for the PHY, the common practice in the past was to replace the entire DDR memory interface with the MIG DDR IP built into the vivado software, resulting in the MC module that could originally be synthesized by vivado not being verified either. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art, and provide a prototype verification method, device, equipment, medium and product for a DDR4 controller, so as to solve the technical problem of low code coverage rate of the prototype verification code of the DDR memory interface IP.

[0006] To achieve the above object, the present invention is implemented by the following technical solutions: In the first aspect, the present invention provides a prototype verification method for a DDR4 controller, which is applied to a prototype verification platform. A DDR controller and a PHY module in a chip to be verified are adapted on the prototype verification platform. The PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script. The prototype verification method includes: In response to the DDR controller receiving a verification instruction, the DDR controller generates a control instruction according to the verification instruction and sends it to the DFI to phy only interface module; In response to the DFI to phy only interface module receiving the control instruction, the DFI to phy only interface module converts the control instruction from the DFI protocol to a target control instruction in the PHY protocol, and sends it to the standalone PHY only block module; In response to the standalone PHY only block module receiving the control instruction, the standalone PHY only block module sends the target control instruction to the DDR particles externally connected to the prototype verification platform, so as to realize reading, writing and verification with the DDR particles.

[0007] Optionally, the DFI to phy only interface module includes a frequency ratio conversion module, a command address decoding module, a write transaction transmission module, a read transaction transmission module and a CRC module; The frequency ratio conversion module is used to map signals of multiple phases into one phase; convert the signals of the DFI interface of the DDR controller into signals of the PHY interface according to the dfi_freq_ratio signal; generate and pull up the dfi_init_complete signal to feedback to the DDR controller after receiving the asserted calDon signal; be used to complete the conversion of data, address / command between different frequencies of the DFI interface and the PHY interface of the DDR controller, and include a state machine to control the progress of read and write transactions; The command address decoding module is used to decode the address command signal of the DFI interface and convert it into the address command signal protocol of the PHY interface for output; The write transaction transmission module is used to transfer data from the frequency ratio conversion module to the PHY interface; check the burst length value and send the data to the CRC module according to the burst length value; select whether the data stream has CRC check; The CRC module is used to, if the data stream has CRC check, send the data bit by bit to the LFSR to generate the CRC code, and send the CRC code to the write transaction transmission module; The read transaction transmission module is used to transmit the read data signal during the read operation and transfer the data from the PHY interface to the frequency ratio conversion module.

[0008] Optionally, the DFI to phy only interface module further includes a configuration register, and the configuration register adopts an APB interface and is used to store programmable parameters.

[0009] Optionally, the standalone PHY only block module is generated by calling vivado in a script manner, manually define the parameter file of the DDR particle according to the hardware requirements, and then load the configuration file.

[0010] Optionally, the CPU sends the verification instruction to the DDR controller through the AXI bus.

[0011] In a second aspect, the present invention provides a prototype verification device for a DDR4 controller, which is applied to a prototype verification platform. The prototype verification platform is adapted with the DDR controller and the PHY module in the chip to be verified. The PHY module integrates the DFI to phy only interface module and the standalone PHY only block module through a python script; the prototype verification device includes: An instruction processing module, configured to respond to the DDR controller receiving a verification instruction, and the DDR controller generates a control instruction according to the verification instruction and sends it to the DFI to phy only interface module; An instruction conversion module, configured to respond to the DFI to phy only interface module receiving a control instruction, and the DFI to phy only interface module converts the control instruction from the DFI protocol into a target control instruction of the PHY protocol and sends it to the standalone PHY only block module; An instruction execution module, configured to respond to the control instruction received by the standalone PHY only block module, and the standalone PHY only block module sends the target control instruction to the DDR particles externally connected to the prototype verification platform, so as to implement reading, writing and verification with the DDR particles.

[0012] In a third aspect, the present invention provides an electronic device, including a processor and a storage medium; The storage medium is used for storing instructions; The processor is used to operate according to the instructions to execute the steps of the above method.

[0013] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented.

[0014] In a fifth aspect, the present invention provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the above method are implemented.

[0015] Compared with the prior art, the beneficial effects achieved by the present invention: A prototype verification method, device, equipment, medium and product of a DDR4 controller provided by the present invention designs a protocol conversion interface between a DFI bus and a phy only interface bus, so that the CPU transmits commands and data to the MC module to be tested through the AXI bus, and then transmits them to the DFI to phy only interface module through the DFI interface, and then transmits them to the standalone PHY only block generated by vivado, and finally realizes reading and writing with external DDR4 particles to achieve prototype verification; improves the code coverage rate of the DDR memory interface IP prototype verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of a prototype verification platform provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a DFI to phy only interface module provided by an embodiment of the present invention; Figure 3 is a schematic flow diagram of a prototype verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The present invention will be further described below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and cannot be used to limit the protection scope of the present invention.

[0018] Embodiment 1:

[0019] The embodiment of the present invention provides a prototype verification method for a DDR4 controller, which is applied to a prototype verification platform. The DDR controller and the PHY module in the chip to be verified are adapted on the prototype verification platform. The PHY module integrates the DFI to phy only interface (the interface between the controller and the physical layer) module and the standalone PHY only block (the physical layer module) module through a python script.

[0020] As shown in the prototype verification platform Figure 1 shown, the entire IP generation process is based on a python script. Only by inputting the selected FPGA device model and external DDR particle parameters, the RTL code generation of the entire DDR PHY module can be realized.

[0021] Figure 1 In ①, the PHY module is the designed DDR4 PHY with a DFI interface. This module automatically integrates the two parts of ② and ③ through a python script and generates the final RTL.

[0022] Figure 1 In ②, it is the DFI to phy only interface module. As shown in Figure 2 shown, this part includes a frequency ratio conversion module, a command address decoding module, a write transaction transmission module, a read transaction transmission module, and a CRC module.

[0023] The frequency ratio conversion module is used to map signals of multiple phases into one phase; convert the signals of the DFI interface of the DDR controller into signals of the PHY interface according to the dfi_freq_ratio signal; generate and pull up the dfi_init_complete signal and feedback it to the DDR controller after receiving the asserted calDon signal; be used to complete the conversion of data, address / command between different frequencies of the DFI interface and the PHY interface of the DDR controller, and include a state machine to control the progress of read and write transactions. The signal list of this module is as follows, where the direction is relative to this module: Signal Name Direction Description dfi_wrdata_enable_pN input Write data and data mask enable signal dfi_wrdata_pN input Write data dfi_wrdata_mask_pN input Mask signal. Each bit of this signal is related to the mask of one byte of the write data. If the highest byte is not fully used, it may be a partial byte. dfi_reset_n_pN input Memory reset signal dfi_rddata_en_p0 / p1 output Read data enable dfi_rddata_w0 / w1 output Read data, sent to the MC module dfi_rddata_valid_w0 / w1 output Read data valid flag bit, sent to the MC module dfi_wrdata_enable output Write data enable, sent to the write transaction module dfi_wrdata_mask output Write data mask, sent to the write transaction module dfi_wrdata output Write data, sent to the write transaction module dfi_rddata_en output Read data enable, sent to the read transaction module dfi_rddata input Read data, from the read transaction module dfi_rddata_valid input Read data valid, from the read transaction module calDone input Indicates that the standalone PHY only block has been powered on, initialized, and calibrated. dfi_init_complete output Indicates that the PHY has been initialized and the MC module can send commands and data dfi_freq_ratio input Defines the clock frequency ratio from the MC to the PHY The command address decoding module is used to decode the address command signals of the DFI interface and convert them into the address command signal protocol of the PHY interface for output. The signal list of this module is as follows, where the direction is relative to this module: Signal Name Direction Description dfi_cs_n_pN input Chip select signal, used to control the strobe of the DDR memory dfi_address_pN input Memory address signal. When programming for a DDR4 memory system (dram_class = 'b1010), the dfi_address_pN

[14] signal bit will be used as the dfi_act_n_pN signal bit, and the dfi_address_pN

[15] signal bit will be used as the dfi_bg_pN[1] bit. dfi_bank_p0 / p1 input Memory bank information bit dfi_ras_n_bank_p0 / p1 input Memory row address strobe information dfi_cas_n_p0 / p1 input Memory column address strobe information dfi_we_n_p0 / p1 input Memory enable signal mcRdCAS output CAS command. This signal must be asserted within one system clock when and only when the read CAS command is asserted on one of the command slots of the PHY command / address input port. mcWrCAS output Write CAS command. This signal must be asserted within one system clock when and only when a write CAS command is asserted on one of the command slots at the PHY command / address input port. winRank output Specifies the target memory rank when issuing a CAS command to ensure correct data read and write. In a multi-rank design, the controller needs to select the corresponding calibration value based on this signal. In a single-rank design, winrank can be simplified to a fixed value (such as 0). mcCasSlot output CAS command slot selection. winInjTxn output By being asserted together with the mcRdCAS signal within the same clock cycle, the system can track these special read commands and indicate that the relevant data is valid at the rdData output through the per_rd_done signal. winRmw output The winRmw signal is used in the DDR4 SDRAM controller design to identify whether the ongoing read operation is part of a read-modify-write stream. winBuf output When mccrdcas or mcWrCAS is asserted, the PHY stores the value in the winBuf signal. gt_data_ready output Update VT tracking. This signal triggers the PHY to read the RIU register in the XIPHY, which measures the degree of central alignment between the DQS gate signal and the read DQS lead, and then adjusts the alignment if necessary. When the voltage and temperature drift, this signal must be asserted periodically to maintain DQS gate alignment. wrDataAddr output Write address, which is only valid when the PHY asserts wrDataEn. rdDataAddr output Read address, which is only valid when the PHY asserts rdDataEn, per_rd_done, or rmw_rd_done. The write transaction transfer module is used to transfer data from the frequency ratio conversion module to the PHY interface; check the burst length value and send the data to the CRC module according to the burst length value; select whether the data stream has CRC check. The signal list of this module is as follows, where the direction is relative to this module: Signal name Direction Description dfi_wrdata_enable input Write data enable dfi_wrdata_mask input Write data mask dfi_wrdata input Write data phy_CRC_mode input Select whether to include CRC CRC_code input CRC code CRC_in_data output Sent to the CRC module when CRC needs to be added. CRC_en output CRC module enable signal wrData output DRAM write data. Write data must be provided to the PHY one cycle after the wrDataEn output signal is asserted. wrDataMask output DRAM write DM / DBI interface wrDataEn output Write enable. wrData and wrDataMask must be provided at the PHY input port in the cycle after wrDataEn is asserted. The CRC module is used to send data bit by bit to the LFSR to generate the CRC code if the data stream has CRC check, and send the CRC code to the write transaction transfer module. The signal list of this module is as follows, where the direction is relative to this module: Signal name Direction Description CRC_in_data input Data to be sent CRC_en input Enable signal CRC_code output CRC code The read transaction transfer module is used to transfer the read data signal during the read operation, and transfer the data from the PHY interface to the frequency ratio conversion module. The signal list of this module is as follows, where the direction is relative to this module: Signal name Direction Description rdData input DRAM read data. rdData is valid only when rdDataEn, per_rd_done, or rmw_rd_done is asserted. rdDataEn input Read data valid. When this signal is asserted High, it indicates that the rdData and rdDataAddr signals are valid. per_rd_done input This signal indicates that a special type of read operation has been completed, and the associated rdData and rdDataAddr signals are valid. When the PHY input winInjTxn and mcRdCAS are both asserted High, the read is marked as a special type of read, and per_rd_done instead of rdDataEn is asserted when returning the data. rmw_rd_done input This signal indicates that a special type of read operation has been completed, and the associated rdData and rdDataAddr signals are valid. When the PHY input winRmw and mcRdCAS are both asserted High, the read is marked as a special type of read, and rmw_rd_done instead of rdDataEn is asserted when returning the data. dfi_rddata_en input Read enable, from the frequency ratio conversion module dfi_rddata output Read data, sent to the frequency ratio conversion module dfi_rddata_valid output Read valid, sent to the frequency ratio conversion module The DFI to phy only interface module also includes a configuration register. The configuration register uses the APB interface and is used to store programmable parameters. The signal list of this module is as follows, where the direction is relative to this module: Signal name Direction Description PCLK input APB working clock PRESETn input APB reset signal, active low PSEL input Strobe signal, generated by the APB bridge unit to the slave device PENABLE input Enable signal, this signal indicates the second and subsequent cycles of an APB transfer. PWRITE input Direction. This signal indicates that the APB performs a write access when the value is "1" and a read access when it is "0". PADDR input Address signal PWDATA input Write data PRDATA output Read data PREADY output READY indicates that the slave device interface is ready. The slave device can also use this signal to extend an APB transfer. PSLVERR output This signal indicates a transfer failure. dfi_freq_ratio output Defines the clock frequency ratio from the MC to the PHY, sent to the frequency ratio module phy_CRC_mode output Whether to carry the CRC code Figure 1 In ③, the standalone PHY only block generated by calling vivado in a script way is used. According to the hardware requirements, the parameter file of the DDR4 chip is manually defined, and then the configuration file (Custom Parts Data File), that is, the.csv file, is loaded.

[0024] Such as Figure 3 shown, the prototype verification method includes: Step S1: In response to the DDR controller receiving the verification instruction, the DDR controller generates a control instruction according to the verification instruction and sends it to the DFI to phy only interface module; among them, the CPU sends the verification instruction to the DDR controller through the AXI bus.

[0025] Step S2: In response to the DFI to phy only interface module receiving the control instruction, the DFI to phy only interface module converts the control instruction from the DFI protocol to the target control instruction of the PHY protocol and sends it to the standalone PHY only block module.

[0026] Step S3: In response to the standalone PHY only block module receiving a control instruction, the standalone PHY only block module sends the target control instruction to the DDR particles externally connected to the prototype verification platform, to achieve reading, writing, and verification with the DDR particles.

[0027] Verify the chip to be verified based on the result information. If the result information is that the data writing is completed, it is determined that the write data function verification of the chip to be verified passes; if the result information is that the data is not written, it is determined that the write data function verification of the chip to be verified fails.

[0028] The advantage of this embodiment is to form a standard DDR PHY IP based on the DFI interface, and this IP can be directly connected to the DDRMC module. The PHY module does not accept "memory transactions" like the MC module, and the latter converts the transactions into one or more DRAM commands that meet the DRAM protocol and timing requirements. The PHY interface does not perform DRAM protocol or timing checks, and its function is single, so it can be used to verify whether the DDR MC module can correctly process memory transactions, and to check whether the signals or transactions transmitted by the bus to the DDR MC module are abnormal.

[0029] Embodiment 2:

[0030] The embodiment of the present invention provides a prototype verification device for a DDR4 controller, which is applied to a prototype verification platform. The DDR controller and the PHY module in the chip to be verified are adapted on the prototype verification platform. The PHY module integrates the DFI to phy only interface module and the standalone PHY only block module through a python script; the prototype verification device includes: An instruction processing module, configured to, in response to the DDR controller receiving a verification instruction, the DDR controller generates a control instruction according to the verification instruction and sends it to the DFI to phy only interface module; An instruction conversion module, configured to, in response to the DFI to phy only interface module receiving a control instruction, the DFI to phy only interface module converts the control instruction from the DFI protocol to a target control instruction in the PHY protocol, and sends it to the standalone PHY only block module; An instruction execution module, configured to, in response to the standalone PHY only block module receiving a control instruction, the standalone PHY only block module sends the target control instruction to the DDR particles externally connected to the prototype verification platform, to achieve reading, writing, and verification with the DDR particles.

[0031] Example 3:

[0032] Based on Example 1, an embodiment of the present invention provides an electronic device, including a processor and a storage medium; The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the steps of the above method.

[0033] Example 4:

[0034] Based on Example 1, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented.

[0035] Example 5:

[0036] Based on Example 1, an embodiment of the present invention provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the above method are implemented.

[0037] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0038] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the specified functions in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0039] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions in one Figure 1 one flow or multiple flows and / or blocksFigure 1 The functions specified in one or more boxes.

[0040] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in one or more processes and / or boxes. Figure 1 One or more processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes.

[0041] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A prototype verification method for a DDR4 controller, applied to a prototype verification platform, characterized in that: The prototype verification platform is adapted with a DDR controller and a PHY module in the chip to be verified, and the PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script; the prototype verification method includes: In response to the DDR controller receiving the verification instruction, the DDR controller generates a control instruction according to the verification instruction and sends the control instruction to the DFI to phy only interface module; In response to the DFI to phy only interface module receiving the control instruction, the DFI to phy only interface module converts the control instruction from the DFI protocol to a target control instruction of the PHY protocol, and sends it to the standalone PHY only block module; In response to the standalone PHY only block module receiving the control instruction, the standalone PHY only block module sends the target control instruction to the DDR particles externally connected to the prototype verification platform to achieve reading, writing and verification with the DDR particles.

2. The prototype verification method of the DDR4 controller according to claim 1, characterized in that: The DFI to phyonly interface module includes a frequency ratio conversion module, a command address decoding module, a write transaction transmission module, a read transaction transmission module and a CRC module; The frequency ratio conversion module is used to map signals of multiple phases into one phase; convert the signal of the DFI interface of the DDR controller into the signal of the PHY interface according to the dfi_freq_ratio signal; generate and pull up the dfi_init_complete signal after receiving the asserted calDon signal to feed back to the DDR controller; complete the conversion of data, address / command between the DFI interface and the PHY interface of the DDR controller at different frequencies, and include a state machine to control the progress of read and write transactions; The command address decoding module is used to decode the address command signal of the DFI interface and convert it into the address command signal protocol of the PHY interface for output; The write transaction transmission module is used to transmit data from the frequency ratio conversion module to the PHY interface; check the burst length value and send the data to the CRC module according to the burst length value; select whether the data stream has a CRC check; The CRC module is used to send the data bit by bit to the LFSR to generate a CRC code if the data stream contains a CRC check, and send the CRC code to the write transaction transmission module; The read transaction transmission module is used to perform read data signal transmission during a read operation, and transmits data from the PHY interface to the frequency ratio conversion module.

3. The prototype verification method of the DDR4 controller according to claim 1, characterized in that: The DFI to phyonly interface module also includes a configuration register, and the configuration register adopts an APB interface and is used to store programmable parameters.

4. The prototype verification method of the DDR4 controller according to claim 1, characterized in that: The standalonePHY only block module uses a script to call vivado to generate, manually defines the parameter file of the DDR particles according to hardware requirements, and then loads the configuration file.

5. The prototype verification method of the DDR4 controller according to claim 1, characterized in that: The CPU sends the verification instruction to the DDR controller through the AXI bus.

6. A prototype verification device for a DDR4 controller, applied to a prototype verification platform, characterized in that: The prototype verification platform is adapted with a DDR controller and a PHY module in the chip to be verified, and the PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script; the prototype verification device includes: an instruction processing module, configured to generate a control instruction according to the verification instruction in response to the DDR controller receiving the verification instruction and send the control instruction to the DFI to phy only interface module; an instruction conversion module, configured to respond to the DFI to phy only interface module receiving a control instruction, the DFI to phy only interface module converting the control instruction from the DFI protocol to a target control instruction of the PHY protocol, and sending the control instruction to the standalone PHY only block module; The instruction execution module is configured to respond to the standalone PHY only block module receiving the control instruction, and the standalone PHY only block module sends the target control instruction to the DDR particles external to the prototype verification platform to achieve reading, writing and verification with the DDR particles.

7. An electronic device, characterized in that: including processor and storage medium; The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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