Register configuration method based on software and hardware, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a register configuration method based on software and hardware, electronic equipment and a medium, and the method comprises the following steps: S1, generating an original register configuration instruction based on a software configuration module; s2, determining a register address corresponding to the register name based on a register address mapping table; s3, inputting a register name corresponding to the original register configuration instruction and a corresponding register address into a direct programming interface in a configuration interface module to generate a target register configuration instruction based on a SystemVerilog language; s4, calling a test sequence module to generate a test task sequence based on the target register configuration instruction; and S5, calling a driving module to input the test task sequence into the to-be-tested chip design, and executing a corresponding register configuration operation in the to-be-tested chip design based on the test task sequence. The chip development efficiency is improved, and the chip development cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a register configuration method based on software and hardware, an electronic device, and a medium. Background Art

[0002] The chip development process undergoes different stages of chip verification. Hardware-level verification typically begins with hardware-level verification based on the chip's RTL (Register Transfer Level) code. After basic hardware verification, a chip hardware accelerator or physical chip is generated. System-level verification is then performed based on the hardware accelerator or physical chip. Once system-level verification passes, software-level verification is performed based on the hardware accelerator or physical chip. Hardware accelerators or physical chips are real entities, and if problems are discovered during the software verification phase, significant update costs are incurred, reducing chip development efficiency. Therefore, software engineers hope to implement register configuration based on the chip's RTL code before chip tape-out, allowing for pre-implemented software-level verification. However, software engineers typically issue instructions based on software and cannot directly interact with the chip's RTL code, making direct register configuration impossible. Therefore, how to implement register configuration based on software instructions in advance based on the RTL code, thereby improving chip development efficiency and reducing chip development costs, has become a pressing technical issue. Summary of the Invention

[0003] The purpose of the present invention is to provide a register configuration method based on software and hardware, an electronic device and a medium, which improves chip development efficiency and reduces chip development costs.

[0004] According to a first aspect of the present invention, a register configuration method based on software and hardware is provided, comprising:

[0005] Step S1: Generate an original register configuration instruction based on the software configuration module, and send the original register configuration instruction to the configuration interface module, wherein the original register configuration instruction includes a register name and is generated based on a software language;

[0006] Step S2: determining the register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store mapping relationship information between register names and register addresses based on the design configuration of the chip to be tested;

[0007] Step S3: input the register name and the corresponding register address corresponding to the original register configuration instruction into the direct programming interface in the configuration interface module to generate a target register configuration instruction based on the SystemVerilog language;

[0008] Step S4: calling a test sequence module based on the target register configuration instruction to generate a test task sequence;

[0009] Step S5: calling the driver module to input the test task sequence into the chip design to be tested, and performing corresponding register configuration operations in the chip design to be tested based on the test task sequence, wherein the chip design to be tested is generated based on RTL code.

[0010] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0011] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0012] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the software-hardware-based register configuration method, electronic device, and medium provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0013] The present invention generates original register configuration instructions implemented by software code based on a software configuration module. In the original register configuration instructions, only the register name needs to be specified, without specifying the register address. Different register address mapping tables can be configured in the configuration interface module according to different application scenarios, and the register address is determined based on the register address mapping table. Then, based on a preset direct programming interface, target register configuration instructions based on the SystemVerilog language are generated, realizing the interaction between the register configuration instructions issued by the software and the RTL code. This allows software engineers to perform register configuration based on the chip RTL code before chip tape-out, and perform software-level verification in advance, thereby improving chip development efficiency and reducing chip development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flowchart of a register configuration method based on software and hardware provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a register configuration method based on software and hardware, such as Figure 1 Shown, including:

[0018] Step S1: Generate an original register configuration instruction based on the software configuration module, and send the original register configuration instruction to the configuration interface module. The original register configuration instruction includes a register name and is generated based on a software language.

[0019] It should be noted that the software configuration module is implemented based on a software language and generates original register configuration instructions based on the software language, which may specifically be C language, C++ language, etc. The software configuration module is used to simulate the behavior of the CPU (Central Processing Unit) during the register configuration process.

[0020] Step S2: Determine the register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store mapping relationship information between register names and register addresses based on the design configuration of the chip to be tested.

[0021] It should be noted that the register address mapping table can be flexibly set based on the specific chip design to be tested. By setting the register address mapping table, upper-level software engineers only need to enter the register name. There is no need to frequently update the code because different register addresses are entered for different chip designs to be tested. This reduces the operating difficulty for software engineers and can flexibly adapt to different chip designs to be tested.

[0022] Step S3: input the register name and the corresponding register address corresponding to the original register configuration instruction into the direct programming interface in the configuration interface module to generate a target register configuration instruction based on the SystemVerilog language.

[0023] It should be noted that the Direct Programming Interface (DPI) is a standard interface that allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages. Therefore, based on DPI, conversion between software language and SystemVerilog language can be achieved, which will not be described in detail here. The target register configuration instruction is a register configuration instruction generated based on the PCIE protocol, and can also be a register configuration instruction generated based on the AXI protocol. The corresponding protocol is configured according to the specific application scenario. Both the PCIE protocol and the AXI protocol are existing bus protocols and will not be described in detail here.

[0024] Step S4: calling a test sequence module based on the target register configuration instruction to generate a test task sequence;

[0025] Step S5: calling the driver module to input the test task sequence into the chip design to be tested, and performing corresponding register configuration operations in the chip design to be tested based on the test task sequence, wherein the chip design to be tested is generated based on RTL code.

[0026] It should be noted that the test sequence module and driver module are both modules on the verification platform, which is used to verify the chip design under test. In addition, through the configuration and conversion of the configuration interface module, the register configuration instructions generated by the software engineer are converted into target register configuration instructions that can interact with the chip design under test. This allows software engineers to perform register configuration based on the chip RTL code before chip tape-out, performing software-level verification in advance, improving chip development efficiency and reducing chip development costs.

[0027] As an embodiment, the original register configuration instruction may specifically be an original register write instruction or an original register read instruction.

[0028] If the original register configuration instruction is an original register write instruction, step S1 includes:

[0029] Step S11 : calling the register write function Reg write based on the software configuration module to generate an original register write instruction, where the original register write instruction includes a register name and a target write value.

[0030] If the original register configuration instruction is an original register read instruction, step S1 includes:

[0031] Step C11: calling the register read function Reg read based on the software configuration module to generate an original register read instruction, where the original register write instruction includes a register name.

[0032] It should be noted that in step S1 , the original register write instruction may be generated only through step S11; the original register read instruction may be generated only through step C11; or the original register write instruction may be generated through both step S11 and step C11.

[0033] As an embodiment, step S4 includes:

[0034] Step S41 : Based on the target register configuration instruction, a test sequence module is called to generate test tasks, and the test tasks are stored in a preset storage queue in a sequential order to generate a test task sequence.

[0035] It should be noted that the tasks in the storage queue can be executed sequentially or in a jump manner according to the execution strategy.

[0036] As an embodiment, the test task sequence = (A1, A2, ..., A n ,...,A N ), A n The nth register configuration task, n ranges from 1 to N, N is the total number of register configuration tasks in the current test task sequence, A n =(A1 n ,A2 n ),A1 n A1 is the task type identifier. n =0 means A n For register read task, A1 n =1 means A n For register write task, A2 n A n Task completion status indicator, A2 n =0 means A n The task is not completed, A2 n =1 means A n Mission accomplished.

[0037] As an embodiment, step S5 includes:

[0038] Step S51: Call the driver module to convert (A1, A2, ..., A n ,...,A N ) is input into the chip design under test.

[0039] Step S52: Extract (A1, A2, ..., A n ,...,A N ) in A1 n =1 task, generate a test write task sequence (B1, B2, ..., B m ,...,BM ),{B1,B2,...,B m ,...,B M} is {A1,A2,...,A n ,...,A N}, B m is the mth register write task, the value range of m is 1 to M, M is the total number of register write tasks in the test task sequence, B m =(B1 m ,B2 m ), B1 m B1 is the task type identifier. m =1,B2 m Indicates B m Task completion status indicator.

[0040] It should be noted that the test write task sequence (B1, B2, ..., B m ,...,B M ) to facilitate the execution of subsequent register write tasks.

[0041] Step S53: Extract (A1, A2, ..., A n ,...,A N ) in A1 n =0 task, generate a test read task sequence (C1, C2, ..., C k ,...,C K ), {C1,C2,...,C k ,...,C K} is {A1,A2,...,A n ,...,A N}, C k is the kth register read task, the value range of k is 1 to K, K is the total number of register read tasks in the test task sequence, K+M=N, C k =(C1 k ,C2 k ), C1 k is the task type identifier, C1 k =2, C2 k Indicates C k Task completion status indicator.

[0042] It should be noted that generating a test read task sequence facilitates the execution of subsequent register read tasks.

[0043] Step S54: Based on (B1, B2, ..., B m ,...,B M)Execute the test register write task in the chip design under test, based on (A1, A2,..., A n ,..., A N ) and (C1, C2,..., C k ,..., C K ) Execute the test register read task in the chip design under test.

[0044] It should be noted that in order to meet different application requirements, different execution strategies for the register write task can be specified. The following will be illustrated by two embodiments of executing the register write task.

[0045] Embodiment 1

[0046] In step S54, execute the test register write task in the chip design under test based on (B1, B2,..., B m ,..., B M ), including:

[0047] Step S541: Initially set m = 1.

[0048] Step S542: If m = 1, directly execute step S544; if m > 1, execute step S543.

[0049] It should be noted that if m = 1, it means that the current register write task is the first register write task in the test write task sequence and there is no need to wait for the completion of other write tasks, so step S544 is directly executed. If m > 1, it is necessary to determine whether the register write task before B m is completed.

[0050] Step S543: Judge whether B2 m-1 is equal to 1. If so, execute step S544; otherwise, wait until B2 m-1 is equal to 1 and then execute step S544. Among them, when B m-1 is executed, a corresponding write completion instruction is generated, and based on the corresponding write completion instruction of B m-1 , B2 m-1 is updated to 1.

[0051] It should be noted that through step S543, it can be ensured that the register write task is executed strictly in accordance with the test write task sequence, avoiding write errors and improving the accuracy of the execution of the register write task, which is applicable to application scenarios with high requirements for the accuracy of write task execution.

[0052] Step S544: Send B m to the chip design under test to execute the corresponding register write operation. If m < M, set m = m + 1 and return to step S542; if m = M, wait until (A1, A2,..., An ,...,A N All tasks in ) are completed, and the process ends.

[0053] It should be noted that after B m is sent to the chip design under test, the chip design under test will write the target write value to the corresponding register address based on the execution on B m corresponding register address.

[0054] It should be noted that the execution strategy of the register write task in the first embodiment can ensure the accuracy of the execution of the register write task. However, since each register write task needs to wait for the previous register write task to be completed before it can be sent, the execution efficiency is relatively low. In some application scenarios, there may be no requirement for the write order of the register write task, or a higher requirement for the execution efficiency. Obviously, the execution strategy of the first embodiment is not applicable. Based on such application scenarios, the second embodiment is further proposed.

[0055] The second embodiment

[0056] In the step S54, based on (B1, B2,..., B m ,..., B M ) to execute the test register write task in the chip design under test, including:

[0057] Step C541: Initially set m = 1 and set the write task count value R = 0.

[0058] Among them, the write task count value is used to record the number of register write tasks that have been sent and not completed in real time.

[0059] Step C542: Send B m to the chip design under test to execute the corresponding register write operation, and set R = R + 1.

[0060] Step C543: If m < M, then set m = m + 1 and return to step C542. If m = M, then wait until all tasks in (A1, A2,..., A n ,..., A N ) are completed, and the process ends;

[0061] During the execution of steps C521 to C543, step C540 also needs to be executed: When any test write task is completed, a write completion instruction is generated. For each generated write completion instruction, set R = R - 1. When R = 0, update all the corresponding B2 of the current B1, B2,..., B m to 1. m-1

[0062] ​It should be noted that through steps C541-C543 and step C540, the register write task is quickly issued. Each register write task can be issued quickly without waiting for the previous register write task to be completed. In addition, the number of register write tasks that have been issued and not yet completed is recorded in real time through the task count value R. When R becomes 0, it means that all the currently issued register write tasks have been executed. Therefore, B2 can be updated in batches. m-1 , which improves the execution efficiency of register write tasks.

[0063] As an embodiment, in step S54, based on (A1, A2, ..., A n ,...,A N ) and (C1,C2,...,C k ,...,C K ) Perform test register read tasks in the chip design under test, including:

[0064] Step D541: Initially set k=1.

[0065] Step D542, judgment C k Corresponding A n Are all the task completion status flags corresponding to the register configuration tasks whose task type flag is 1 equal to 1? If so, execute step D543. Otherwise, wait for C k Corresponding A n If the task completion status flags corresponding to all the previous register configuration tasks with the task type flag of 1 are all equal to 1, then step D543 is executed.

[0066] It should be noted that if C k Corresponding A n All the previous register configuration tasks whose task type identifier is 1 have corresponding task completion status identifiers equal to 1, indicating that (A1, A2, ..., A n ,...,A N )C k Corresponding A n All previous write tasks have been completed. Only when this condition is met can C k Send it to the chip under test to execute the corresponding register read operation to ensure the correct execution of the write operation. If it is not satisfied, it is necessary to wait for C k Corresponding A n The C can be set only when all the task completion status flags of the register configuration tasks whose task type flag is 1 are all equal to 1. k Send it to the chip under test to perform the corresponding register read operation.

[0067] Step D543, Ck Send it to the待测芯片设计中执行对应的寄存器读操作,当C k After execution, generate a read return instruction, and set the corresponding C2 k to 1.

[0068] Step D544: If k < K, set k = k + 1 and return to Step D542. If k = K, wait until all tasks in (A1, A2,..., A n ,..., A N ) are completed, and end the process.

[0069] It should be noted that Steps D541 - D544 can be used in combination with the processing method of the register write task in Embodiment 1, or can be used in combination with the processing method of the write task in Embodiment 2.

[0070] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, sub - program, etc.

[0071] An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiments of the present invention.

[0072] An embodiment of the present invention further provides a computer - readable storage medium storing computer - executable instructions, and the computer instructions are used to execute the method described in the embodiments of the present invention.

[0073] [[]]Based on the software configuration module, the original register configuration instructions are generated by implementing. In the original register configuration instructions, only the register name needs to be specified, and the register address does not need to be specified. Different register address mapping tables can be configured in the configuration interface module according to different application scenarios, and the register address is determined based on the register address mapping table. Then, based on the preset direct programming interface, the target register configuration instructions based on the SystemVerilog language are generated, realizing the interaction between the register configuration instructions issued by software and the RTL code. This enables software engineers to perform register configuration based on the chip RTL code before chip tape - out, conduct software - level verification in advance, improve the chip development efficiency, and reduce the chip development cost.

[0074] It should be noted that the Chinese term "待测芯片设计中" in the original text seems to be an incomplete or incorrect expression. I translated it as "待测芯片设计中" as accurately as possible according to the rules. If there is a more accurate or complete expression, it may need to be adjusted accordingly.The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A register configuration method based on software and hardware, characterized in that: include: Step S1, generating an original register configuration instruction based on a software configuration module, and sending the original register configuration instruction to a configuration interface module, wherein the original register configuration instruction includes a register name and is generated based on a software language; Step S2: determining the register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store mapping relationship information between the register name and the register address based on the design configuration of the chip to be tested; Step S3, inputting the register name and the corresponding register address corresponding to the original register configuration instruction into the direct programming interface in the configuration interface module to generate a target register configuration instruction based on the SystemVerilog language; Step S4, calling a test sequence module based on the target register configuration instruction to generate a test task sequence; Step S5, calling the driving module to input the test task sequence into the chip design to be tested, and executing corresponding register configuration operations in the chip design to be tested based on the test task sequence, wherein the chip design to be tested is generated based on RTL code.

2. The method according to claim 1, characterized in that If the original register configuration instruction is an original register write instruction, step S1 includes: Step S11, calling the register write function Reg write based on the software configuration module to generate an original register write instruction, wherein the original register write instruction includes a register name and a target write value; If the original register configuration instruction is an original register read instruction, step S1 includes: Step C11: calling the register read function Reg read based on the software configuration module to generate an original register read instruction, wherein the original register write instruction includes a register name.

3. The method according to claim 2, characterized in that The step S4 comprises: Step S41 , calling a test sequence module based on the target register configuration instruction to generate a test task, and storing the test tasks in a preset storage queue in a sequential order to generate a test task sequence.

4. The method according to claim 2, characterized in that: The test task sequence = (A1, A2, ..., A n ,...,A N ), A n is the nth register configuration task, where n ranges from 1 to N, and N is the total number of register configuration tasks in the current test task sequence. n =(A1 n ,A2 n ),A1 n A1 is the task type identifier. n =0 means A n For register read task, A1 n =1 means A n For register write task, A2 n A n Task completion status indicator, A2 n =0 means A n The task has not been completed, A2 n =1 means A n Mission accomplished.

5. The method according to claim 4, characterized in that The step S5 comprises: Step S51: Call the driver module to convert (A1, A2, ..., A n ,...,A N ) is input into the chip design to be tested; Step S52: Extract (A1, A2, ..., A n ,...,A N ) n =1 task, generate a test write task sequence (B1, B2, ..., B m ,...,B M ),(B1,B2,...,B m ,...,B M ) is (A1,A2,...,A n ,...,A N ), B m is the mth register write task, the value range of m is 1 to M, M is the total number of register write tasks in the test task sequence, B m =(B1 m ,B2 m ), B1 m B1 is the task type identifier. m =1,B2 m Indicates B m Task completion status indicator; Step S53: Extract (A1, A2, ..., A n ,...,A N ) n =0 task, generate a test read task sequence (C1, C2, ..., C k ,...,C K ), (C1,C2,...,C k ,...,C K ) is (A1,A2,...,A n ,...,A N ), C k is the kth register read task, the value range of k is 1 to K, K is the total number of register read tasks in the test task sequence, K+M=N, C k =(C1 k ,C2 k ), C1 k is the task type identifier, C1 k =2, C2 k Represents C k Task completion status indicator; Step S54: Based on (B1, B2, ..., B m ,...,B M ) performs the test register write task in the chip design under test, based on (A1, A2, ..., A n ,...,A N ) and (C1,C2,...,C k ,...,C K )Perform the test register read task in the chip design under test.

6. The method according to claim 5, characterized in that In step S54, based on (B1, B2, ..., B m ,...,B M ) Perform test register write tasks in the chip design under test, including: Step S541, initially set m=1; Step S542: if m=1, directly execute step S544; if m>1, execute step S543; Step S543, determination B2 m-1 Is it equal to 1? If so, execute step S544. Otherwise, wait for B2 m-1 When B is equal to 1, step S544 is executed. m-1 When the execution is completed, the corresponding write completion instruction is generated based on B m-1 The corresponding write completion instruction will be B2 m-1 Updated to 1; Step S544: Send B m to the design of the chip under test to perform the corresponding register write operation. If m < M, set m = m + 1 and return to Step S542. If m = M, wait until all tasks in (A1, A2,..., A n ,..., A N ) are completed and end the process.

7. The method according to claim 5, characterized in that In step S54, based on (B1, B2, ..., B m ,...,B M ) Perform test register write tasks in the chip design under test, including: Step C541, initially set m=1, set the write task count value R=0; Step C542: B m Send it to the chip design to perform the corresponding register write operation and set R=R+1; Step C543: If m < M, then set m = m + 1 and return to Step C542. If m = M, then wait until all tasks in (A1, A2,..., A n ,..., A N ) have been completed, and end the process; During the execution of steps C521 to C543, step C540 needs to be executed. When any test write task is completed, a write completion instruction is generated. Each time a write completion instruction is generated, R=R-1 is set. When R=0, the current B1, B2, ..., B m Corresponding B2 m-1 All updated to 1.

8. The method according to claim 5, characterized in that In step S54, based on (A1, A2, ..., A n ,...,A N ) and (C1,C2,...,C k ,...,C K ) Perform test register read tasks in the chip design under test, including: Step D541, initially set k=1; Step D542, judgment C k The corresponding A n Are all the task completion status flags corresponding to the register configuration tasks whose task type flag is 1 equal to 1? If so, execute step D543. Otherwise, wait for C k The corresponding A n If all the task completion status flags corresponding to the register configuration tasks whose task type flag is 1 are all equal to 1, then execute step D543; Step D543: C k Send it to the chip under test to perform the corresponding register read operation. k After execution is completed, a read return instruction is generated, and the corresponding C2 k Updated to 1; Step D544: If k < K, then set k = k + 1 and return to Step D542. If k = K, then wait until all tasks in (A1, A2,..., A n ,..., A N ) are completed, and end the process.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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