Batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products

Abstract

The present invention provides a batch calculation method for the equivalent thermal conductivity of the wiring area of ​​an integrated circuit product. According to the geometric contour of the integrated circuit product, a wiring layer geometric model is established and geometric partitioning is performed; a circuit image of each wiring layer is obtained and image processing is performed on it; a two-dimensional array containing position and pixel information is generated for the processed circuit image; the processed circuit image is geometrically partitioned, and the anisotropic equivalent thermal conductivity of each partition of the wiring area is calculated and stored according to the mapping relationship between each pixel point in the geometric partition of the circuit image and each element in the two-dimensional array; the calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is imported into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize the batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer. The present invention can realize efficient automatic modeling, calculation and visual analysis.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and relates to a batch calculation method for equivalent thermal conductivity of wiring areas of integrated circuit products. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] At present, with the development of electronic information technology and the progress of integrated circuit design, manufacturing, and packaging, circuit functions are becoming increasingly complex and the scale is becoming increasingly large. However, as the size of integrated circuits becomes smaller, the design becomes more complex, the power density becomes higher, and the heat consumption becomes larger, the reliability problem of integrated circuits caused by thermal effects is becoming more and more serious. Therefore, how to quickly and accurately deal with the Joule heating effect of current or internal heat diffusion problems to achieve efficient thermal management is becoming one of the important bottlenecks in integrated circuit design. The formulation of an efficient thermal management strategy requires two key elements: one is the establishment of a thermal model to describe the thermal behavior of the circuit; the other is design technology to reduce the thermal gradient between three-dimensional stacking planes and maintain the operating temperature within an acceptable range. Among them, the main requirements for the thermal model include high precision and low computational complexity, and to accurately evaluate the thermal distribution of the entire circuit within acceptable computing time and cost.

[0004] In the multi-level design process of chip-package-system in the field of integrated circuits, the electrical connection between components is inseparable from the wiring structure. The multi-layer metal system formed by the metallization process in the chip manufacturing process, the packaging substrate involved in the chip packaging process, and the wiring layer in the printed circuit board all use patterned metal thin layers to realize the interconnection of components. The wiring structure is generally composed of conductive metal and insulating materials in between. Due to its structural complexity and uneven material distribution, the thermal properties of the circuit area during manufacturing and even in the service process are anisotropic, which is easy to cause uneven heat distribution. Therefore, it is necessary to describe the thermal model of the wiring structure more accurately to achieve the purpose of effective thermal management. In the process of establishing the thermal model of the wiring area, if the refined modeling is directly carried out according to the geometric model of the actual circuit, the calculation amount will be very large and it is not feasible for simulation analysis. Therefore, in the actual modeling process, it is necessary to simplify and equate the thermal properties of different partitions according to the position information and input them into the relevant thermal simulation software for calculation, so as to achieve the purpose of taking into account the calculation accuracy and calculation cost and efficiency.

[0005] There are three basic ways of heat transfer: heat conduction, heat convection, and heat radiation. Among them, heat conduction is the main method in heat transfer analysis of wiring structures. For wiring structure systems composed of metal and dielectric materials with significant differences in thermal properties, in order to describe the heat conduction process in the system space and determine the temperature distribution in the system, the equation should be solved Where λ is the thermal conductivity, T is the temperature, and Q is the heat generated. Therefore, achieving equivalent calculation of the anisotropic thermal conductivity of the wiring structure is of great significance for thermal analysis of the wiring area. For the calculation of the equivalent thermal conductivity, in addition to solving it according to the conventional definition formula, it can also be solved according to the relationship between thermal conductivity and thermal resistance: (where θ is the thermal resistance, S and L are the area and length of the heat conductor along the heat transfer direction, respectively). The equivalent thermal conductivity is derived by solving the equivalent thermal resistance of the heat conductor. In the process of calculating the equivalent thermal resistance of the thermal resistance network, the series / parallel equivalent calculation formula of the thermal resistance is needed (the series / parallel connection of the thermal resistance is similar to the series / parallel connection of the resistor). The specific formula is: θ 串联 =θ1+θ2+θ3+...(thermal resistance series formula) and

[0006] In the process of inputting the anisotropic equivalent thermal conductivity of the wiring layer into the finite element software to establish the equivalent thermal model, although the finite element software provides a graphical operation interface and software programming interface, it is difficult to directly input the equivalent material parameters of large amounts of data into the simulation software for modeling and parameter setting in an automated manner. If manual input is used for modeling and parameter setting, there will be problems such as huge workload, poor operability, and difficulty in modifying and updating existing models. Summary of the invention

[0007] In order to solve the above problems, the present invention proposes a batch calculation method for the equivalent thermal conductivity of the wiring area of ​​integrated circuit products. The present invention supports the automatic import of the anisotropic equivalent thermal conductivity data containing position information obtained by batch processing into the relevant finite element software model, overcoming the cumbersome and time-consuming shortcomings of manual modeling, thereby realizing efficient automatic modeling, calculation and visual analysis, and improving the accuracy of the thermal simulation model of large-scale integrated circuit products.

[0008] According to some embodiments, the present invention adopts the following technical solutions:

[0009] A batch calculation method for equivalent thermal conductivity of wiring areas of integrated circuit products comprises the following steps:

[0010] According to the geometric outline of the integrated circuit product, a wiring layer geometric model for finite element simulation is established and geometric partitioning is performed; the line image of each wiring layer is obtained and image processing is performed on it;

[0011] Generate a two-dimensional array containing position and pixel information for the processed line image;

[0012] Geometrically partitioning the processed line image, and calculating and storing the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the mapping relationship between each pixel point in the geometric partition of the line image and each element in the two-dimensional array;

[0013] The calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is imported into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer.

[0014] As an optional implementation, the finite element geometric model of the wiring layer is a geometric model established according to the outer contour of the entire wiring layer, and the geometric model does not contain an actual wiring structure.

[0015] As an optional implementation, the image processing includes preprocessing and binarization processing, wherein the preprocessing includes adjusting the wiring diagram resolution and grayscale processing of the image, and the binarization processing can effectively reduce pixel information and make the outline of the circuit pattern clear.

[0016] As an optional implementation, the processed circuit image is geometrically partitioned (i.e., geometric partitioning of the wiring diagram is achieved), and the method of geometric partitioning the processed circuit image is the same as the in-plane partitioning method of the finite element geometric model of the wiring layer, and the process of geometric partitioning is to divide the geometric model or image to be partitioned into multiple units of the same size.

[0017] As an optional implementation, the two-dimensional array is stored in a first text document to facilitate reading of material data in a subsequent equivalent thermal conductivity calculation process.

[0018] As an optional implementation, in the specific process of calculating the anisotropic equivalent thermal conductivity of each partition of the wiring area, when calculating the equivalent thermal conductivity of each partition in two directions within the plane of the wiring area, the equivalent thermal resistance of each partition is first calculated, and then the anisotropic equivalent thermal conductivity of each partition in two directions within the plane is obtained through the relationship between thermal resistance and thermal conductivity.

[0019] As a further limitation, when calculating the equivalent thermal resistance in two directions within the plane of any partition of the wiring area, the equivalent thermal resistance is calculated for the unit represented by each pixel point in the partition and regarded as a thermal resistance unit. Then, a series of series / parallel processing is performed on the above thermal resistance units according to the heat transfer direction to construct an equivalent thermal resistance network model in two directions within the plane of the partition. Since different equivalent thermal resistance network models will be obtained based on different assumptions, the equivalent thermal resistances obtained from different equivalent thermal resistance network models need to be averaged to reflect the actual heat transfer situation.

[0020] As an optional implementation, in the specific process of calculating the anisotropic equivalent thermal conductivity of each partition of the wiring area, when calculating the equivalent thermal conductivity in the thickness direction, the mixing rule is adopted to perform a weighted average of the thermal conductivity of each material component according to their respective volume fractions to obtain the equivalent thermal conductivity of each partition in the thickness direction.

[0021] As an optional implementation, the calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is automatically stored in the second text document in the form of a two-dimensional array according to the partition number, thereby facilitating parameter input in the subsequent finite element modeling process of the wiring layer.

[0022] A batch calculation system for equivalent thermal conductivity of wiring areas of integrated circuit products, comprising:

[0023] A modeling module is configured to establish a wiring layer geometry model for finite element simulation and perform geometry partitioning according to an external geometry profile of an integrated circuit product;

[0024] An image processing module, configured to perform image processing on all line images;

[0025] A data processing module configured to generate a two-dimensional array containing position and pixel information for the processed line image;

[0026] The batch calculation module is configured to calculate and store the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the geometric partitioning method of the line image and the mapping relationship between each pixel point in the geometric partition of the line image and each element in the two-dimensional array;

[0027] The automatic import module is configured to import the calculated anisotropic equivalent thermal conductivity into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] In the process of calculating the anisotropic equivalent thermal conductivity of the wiring area of ​​the integrated circuit product, the present invention directly and simply restores the complex fine circuit structure inside the wiring area through the pixel recognition method, and at the same time divides the wiring area into in-plane partitions and calculates the anisotropic equivalent thermal conductivity of each partition to reflect the material non-uniformity of the entire wiring area and the influence of the circuit orientation on the equivalent thermal conductivity.

[0030] When solving the equivalent thermal conductivity in two directions within the plane of each partition of the wiring area, the present invention uses the pixel unit in each partition of the wiring diagram as the basic unit in the thermal resistance network, and then performs certain series / parallel processing on the thermal resistance units in each partition to establish a suitable equivalent thermal resistance network model and obtain the corresponding equivalent thermal resistance, and further obtains the equivalent thermal conductivity through the relationship between thermal resistance and thermal conductivity; when calculating the equivalent thermal resistance, different equivalent thermal resistance network models are constructed according to the heat transfer direction to reflect the characteristics of anisotropic thermal conduction.

[0031] The script tool developed based on computer language in the present invention can realize batch processing of the anisotropic equivalent thermal conductivity of each partition of the wiring area, and automatically import the obtained large amount of anisotropic equivalent thermal conductivity into the corresponding partition model of the finite element geometric model of the wiring layer through the interface between the script tool and the finite element software, with high automation, convenience, speed and high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0033] Figure 1 The present invention relates to a flow chart for calculating anisotropic equivalent thermal conductivity of each partition of a wiring layer.

[0034] Figure 2 This is the process of solving the equivalent thermal resistance of the wiring layer in the x direction involved in the embodiment of the present invention.

[0035] Figure 3 It is a data file generated in the process of partition pixel identification / equivalent thermal conductivity calculation involved in the embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0037] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0038] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0039] An automated calculation method for anisotropic equivalent thermal conductivity of different partitions of the wiring area of ​​an integrated circuit product, such as Figure 1 As shown, the specific implementation steps are as follows:

[0040] Step 1: According to the geometric outline of the integrated circuit product, a wiring layer geometry model for finite element simulation is established, that is, a finite element geometry model of the wiring layer is obtained, and geometric partitioning is performed; the line image of each wiring layer is exported to obtain a wiring diagram, and the appropriate resolution of the wiring diagram can be set as needed;

[0041] The finite element geometric model here refers to the equivalent geometric model of the wiring layer established for finite element analysis. The external dimensions of the geometric model (including length × width × thickness) are established according to the external contour of the actual wiring layer; the model does not contain the actual circuit structure. By geometrically partitioning the model (i.e., dividing the model into small areas), calculating the equivalent material properties of each partition and assigning them to the corresponding partition in the model, the influence of the circuit structure in different areas of the wiring layer on the equivalent material properties of the wiring layer is reflected.

[0042] The wiring diagram is obtained by exporting the line image of each wiring layer, which is used to calculate the equivalent material performance of each partition of the wiring layer, that is, the equivalent material performance parameters of each partition are calculated according to the material distribution characteristics of each partition in the exported wiring diagram; the calculated equivalent material performance parameters of each partition are finally imported into the corresponding partition of the finite element geometric model of the above wiring layer.

[0043] This step can derive the circuit image of each wiring layer according to the design file provided by the simulated integrated circuit product or through some electronic computer-aided design software.

[0044] Preprocessing and binarizing the wiring diagram to identify differences in material distribution in different areas of the wiring diagram (in some embodiments, this step can be implemented using an existing image processing algorithm or by calling an image processing module); binarizing the wiring diagram can effectively reduce pixel information and make the outline of the circuit pattern clear;

[0045] Step 2: Generate a two-dimensional array containing position and pixel information for the binarized wiring diagram (in some embodiments, this step can be implemented by using an existing data processing algorithm or calling a data processing module), and store the generated two-dimensional array in a text document A, so as to facilitate the reading of material data in the subsequent equivalent thermal conductivity calculation process;

[0046] Step 3: geometrically partition the wiring diagram, the method of geometrically partitioning the wiring diagram is the same as the in-plane partitioning method of the finite element geometric model of the wiring layer described in step 1; according to the mapping relationship between each pixel point in the geometric partition of the wiring diagram and each element in the two-dimensional array containing position and pixel information obtained in step 2, calculate the anisotropic equivalent thermal conductivity of each partition of the wiring area (in some embodiments, this step can be implemented using a batch calculation script);

[0047] Specifically, when calculating the equivalent thermal conductivity in two directions within the plane of each partition of the wiring area, it is necessary to first calculate the equivalent thermal resistance of each partition, and then obtain the anisotropic equivalent thermal conductivity in two directions within the plane of each partition through the relationship between thermal resistance and thermal conductivity;

[0048] When calculating the equivalent thermal conductivity in the thickness direction, the mixed rule can be directly used, that is, the thermal conductivity of each material component is weighted averaged according to its respective volume fraction to obtain the equivalent thermal conductivity of each partition in the thickness direction;

[0049] When calculating the equivalent thermal resistance in two directions within the plane of any partition of the wiring area, it is necessary to calculate the equivalent thermal resistance of the unit represented by each pixel point in each partition and regard it as a thermal resistance unit, and then perform a series of series / parallel processing on the above thermal resistance units according to the heat transfer direction to construct an equivalent thermal resistance network model in two directions within the plane of the corresponding partition. Since different equivalent thermal resistance network models will be obtained based on different assumptions, the equivalent thermal resistances obtained from different equivalent thermal resistance network models need to be averaged to reflect the actual heat transfer situation;

[0050] The calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is automatically stored in the text document B in the form of a two-dimensional array according to the partition number, so as to facilitate the parameter input and use in the subsequent finite element modeling process of the wiring layer;

[0051] Step 4: Automatically import the anisotropic equivalent thermal conductivity data of each partition of the wiring area obtained in step 3 into the corresponding partition model of the finite element geometric model of the wiring layer, thereby realizing batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer (in some embodiments, this step is implemented by an automated processing script).

[0052] As a typical embodiment, it should be noted that the parameters and the like provided in this embodiment are exemplary contents and may be changed in other embodiments, and it does not mean that the protection scope of the present invention is limited to these parameter ranges.

[0053] The specific steps for batch calculation of anisotropic equivalent thermal conductivity of a printed circuit board (PCB) are as follows:

[0054] Step 1: The selected PCB has an outer contour size of length (94 mm) × width (61 mm). The PCB has a total of 4 wiring layers. According to the outer contour of the entire wiring layer, a geometric model of the wiring layer for finite element simulation is established, and geometric partitioning is performed. This embodiment stipulates that the in-plane shape of each partition model in the wiring layer geometric model is a square, and the side length is 1 mm, and the thickness direction dimension is the actual thickness of the wiring layer 35 μm; through electronic design automation (Electronic Design Automation) The circuit image, i.e., the wiring diagram, is exported layer by layer using the PCB Design Automation (EDA) software; a suitable resolution is set for the exported wiring diagram by the image processing software; the pixel density set in this embodiment is 40 pixels per 1 mm, and according to the length and width of the wiring diagram, the resolution of each layer of the wiring diagram is 3760×2440; this embodiment uses a script developed based on the Python language to call the image processing module to perform image preprocessing and binarization on the exported wiring diagram: in the preprocessing stage, the color format of the wiring diagram is converted from the RBG mode to the grayscale mode; since the wiring diagram in the grayscale mode can still be divided into 256 grayscale levels according to the grayscale value, and the PCB wiring layer is composed of only copper foil and resin material, the wiring diagram displayed in the grayscale mode is binarized, that is, a corresponding grayscale limit is set for the wiring diagram displayed in the grayscale mode, and whether the color of the pixel is set to black or white is determined according to whether the grayscale value of each pixel is greater than the grayscale limit. In this embodiment, the binarized wiring diagram shows that the copper foil is a black area and the resin is a white area.

[0055] Step 2: Call the data processing module to generate a two-dimensional array containing position information for the above-mentioned binarized wiring diagram, that is, the row and column numbers of each element in the two-dimensional array represent the positions of each pixel in the wiring diagram, and the values ​​of each element in the two-dimensional array represent the material composition of the corresponding positions of each pixel in the wiring diagram. In this embodiment, a two-dimensional array of 3760 rows × 2440 columns composed of two elements of 1 and 0 is generated according to the selected resolution of the wiring diagram, wherein when the array element is 0, it represents that the material composition of the pixel at this position is copper, and when the array element is 1, it represents that the material composition of the pixel at this position is resin; the generated two-dimensional array is stored in a text document A.

[0056] Step 3: geometrically partition the wiring diagram. The geometric partitioning method of the wiring diagram needs to be the same as the in-plane partitioning method of the finite element geometric model of the wiring layer described in step 1. This embodiment stipulates that the partition shape of the wiring diagram is a square with a side length of 1 mm; then a batch calculation script developed based on Python language is used to calculate the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the mapping relationship between each pixel point in the geometric partition of the wiring diagram and each element in the two-dimensional array containing position and pixel information obtained in step 2. For the two-dimensional array generated in this embodiment, each 40×40 two-dimensional array from the upper left to the lower right represents the material composition information in a 1mm*1mm partition; when calculating the equivalent thermal conductivity in two directions in the plane of the wiring area, it is necessary to first calculate the equivalent thermal resistance of each partition in the plane direction, and then obtain the equivalent thermal conductivity from the relationship between thermal resistance and thermal conductivity.

[0057] The establishment of the equivalent thermal resistance network model in the plane direction is as follows Figure 2 To avoid confusion, special instructions are required. Figure 2 The partition model in the wiring layer geometry model is not the geometry model used in the finite element analysis. It is only used to explain the principle of constructing the equivalent thermal resistance network model in the in-plane direction of the wiring area. This diagram takes the calculation of the equivalent thermal resistance in the in-plane x direction of a partition in the wiring area as an example; Figure 2 (a) is a partition model in a wiring layer geometry model. In the process of performing the related operations described in step 2 above on the partition model of the wiring layer, it is equivalent to "segmenting" the partition model of the wiring layer into pixel units. Figure 2 The wiring layer partition model shown is divided into 16 pixel units, each pixel unit represents a pure copper or pure resin unit; each pixel unit is regarded as a thermal resistance unit here, and when the equivalent thermal resistance of each partition model of the wiring layer model is calculated, the equivalent thermal resistance of the thermal resistance network composed of these thermal resistance units in series / parallel is actually solved. The size (length×width×height) of each thermal resistance unit in this embodiment is: 25μm×25μm×35μm, where the length and width depend on the size of the pixel point in the surface, and the height depends on the thickness of the wiring layer (here the thickness of the wiring layer is 35μm); after the size of each pixel unit is obtained, the thermal resistance calculation formula Calculate the thermal resistance of pure copper and pure resin thermal resistance units; after the thermal resistance calculation of pure copper and pure resin units is completed, it is necessary to perform a series of series / parallel processing on the pure copper and pure resin thermal resistance units according to the material distribution of each partition of the wiring layer to realize the establishment of an equivalent thermal resistance network of each partition model of the wiring layer and obtain the corresponding equivalent thermal resistance value.

[0058] Figure 2(c) shows two equivalent thermal resistance network models based on different assumptions, which respectively adopt the equivalent modes of first series connection and then parallel connection, and first parallel connection and then series connection for the thermal resistance units distributed along the x direction; the two thermal resistance network models are established based on different assumptions. Figure 2 The thermal resistance network in the upper figure (c) is established based on the assumption that each plane parallel to the heat conduction direction is adiabatic. In this case, the predicted total thermal resistance is too high. Figure 2 The thermal resistance network in the lower figure (c) is established under the assumption that each plane perpendicular to the heat conduction direction is isothermal. In this case, the predicted total thermal resistance is low; the actual thermal resistance value is between the two, so in the process of calculating the equivalent thermal resistance, the equivalent thermal resistance obtained by different equivalent thermal resistance network models should be averaged to reflect the actual heat transfer situation; when calculating the equivalent thermal conductivity in the thickness direction, it can be directly calculated by the mixed rule, that is, the thermal conductivity of the two is weighted averaged according to the content of copper and resin in each partition to obtain the equivalent thermal conductivity in the thickness direction of each partition; in the relevant Python script, the number of copper pixels contained in each partition is counted by the accumulation function, and then divided by the total number of pixels contained in each partition (each partition in this embodiment contains 40×40=1600 pixels), the copper content and corresponding resin content data of each partition can be obtained; the calculated anisotropic equivalent thermal conductivity of each partition is automatically stored in the text document B in the form of a two-dimensional array according to the partition number; Figure 3 Shows the data files generated by the script for pixel identification and equivalent thermal conductivity calculation of the partition model of the wiring layer.

[0059] Step 4: With the help of the interface between the finite element software and the script file, the anisotropic equivalent thermal conductivity data of each partition of the wiring area obtained in step 3 is automatically imported into the corresponding partition model of the finite element geometric model of the wiring layer by using the automated processing script, thereby realizing the batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer; Figure 3 (d) is an anisotropic equivalent thermal conductivity data file of each partition of the wiring area recorded by the partition number. The first column is the partition number of the wiring area, the second to fourth columns are the equivalent thermal conductivities of the corresponding partitions of the wiring area in three orthogonal directions, and the fifth column is the copper content data of each partition of the wiring area.

[0060] On the other hand, the present invention also provides a batch calculation system for equivalent thermal conductivity of wiring areas of integrated circuit products, comprising:

[0061] A modeling module is configured to establish a wiring layer geometry model for finite element simulation and perform geometry partitioning according to an external geometry profile of an integrated circuit product;

[0062] An image processing module, configured to perform image processing on all line images;

[0063] A data processing module configured to generate a two-dimensional array containing position and pixel information for the processed line image;

[0064] The batch calculation module is configured to calculate and store the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the geometric partitioning method of the line image and the mapping relationship between each pixel point in the geometric partition of the line image and each element in the two-dimensional array;

[0065] The automatic import module is configured to import the calculated anisotropic equivalent thermal conductivity into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer.

[0066] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0071] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A batch calculation method for equivalent thermal conductivity of integrated circuit product wiring area, characterized in that: The following steps are involved: According to the geometric outline of the integrated circuit product, a wiring layer geometric model for finite element simulation is established and geometric partitioning is performed; the line image of each wiring layer is obtained and image processing is performed on it; Generate a two-dimensional array containing position and pixel information for the processed line image; Geometrically partitioning the processed line image, and calculating and storing the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the mapping relationship between each pixel point in the geometric partition of the line image and each element in the two-dimensional array; The calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is imported into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer.

2. The batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1, characterized in that: The finite element geometric model of the wiring layer is a geometric model established according to the outer contour of the entire wiring layer, and the geometric model does not contain the actual wiring structure.

3. The batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1, characterized in that: The image processing includes preprocessing and binarization processing. The preprocessing includes adjusting the wiring diagram resolution and grayscale processing of the image. The binarization processing can effectively reduce pixel information and make the outline of the circuit pattern clear.

4. A batch calculation method for equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1 or 2, characterized in that: The method of geometrically partitioning the processed circuit image is the same as the in-plane partitioning method of the finite element geometric model of the wiring layer. The process of geometric partitioning is to divide the geometric model or image to be partitioned into multiple units of the same size.

5. The batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1, characterized in that: The two-dimensional array is stored in a first text document.

6. The batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1, characterized in that: In the specific process of calculating the anisotropic equivalent thermal conductivity of each partition of the wiring area, when calculating the equivalent thermal conductivity of each partition in two directions within the plane of the wiring area, the equivalent thermal resistance of each partition is first calculated, and then the anisotropic equivalent thermal conductivity of each partition in two directions within the plane is obtained through the relationship between thermal resistance and thermal conductivity.

7. A batch calculation method for equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 6, characterized in that: When calculating the equivalent thermal resistance in two directions within the plane of any partition of the wiring area, the equivalent thermal resistance is calculated for the unit represented by each pixel point in the partition and regarded as a thermal resistance unit. Then, a series of series / parallel processing is performed on the above thermal resistance units according to the heat transfer direction to construct an equivalent thermal resistance network model in two directions within the plane of the partition. Since different equivalent thermal resistance network models will be obtained based on different assumptions, the equivalent thermal resistances obtained from different equivalent thermal resistance network models are averaged to reflect the actual heat transfer situation.

8. A batch calculation method for equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1 or 6, characterized in that: In the specific process of calculating the anisotropic equivalent thermal conductivity of each partition of the wiring area, when calculating the equivalent thermal conductivity in the thickness direction, the mixing rule is adopted to perform weighted average on the thermal conductivity of each material component according to its respective volume fraction to obtain the equivalent thermal conductivity of each partition in the thickness direction.

9. The batch calculation method of equivalent thermal conductivity of wiring area of ​​integrated circuit products as claimed in claim 1, characterized in that: The calculated anisotropic equivalent thermal conductivity of each partition of the wiring area is automatically stored in the second text document in the form of a two-dimensional array according to the partition number.

10. A batch calculation system for equivalent thermal conductivity of integrated circuit product wiring areas, characterized in that: include: A modeling module is configured to establish a wiring layer geometry model for finite element simulation and perform geometry partitioning according to an external geometry profile of an integrated circuit product; An image processing module, configured to perform image processing on all line images; A data processing module configured to generate a two-dimensional array containing position and pixel information for the processed line image; The batch calculation module is configured to calculate and store the anisotropic equivalent thermal conductivity of each partition of the wiring area according to the geometric partitioning method of the line image and the mapping relationship between each pixel point in the geometric partition of the line image and each element in the two-dimensional array; The automatic import module is configured to import the calculated anisotropic equivalent thermal conductivity into the corresponding partition model of the finite element geometric model of the wiring layer, so as to realize batch assignment of the anisotropic equivalent thermal conductivity of each partition model in the finite element geometric model of the wiring layer.

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