Memory and memory operation method

Abstract

The present disclosure embodiment discloses a memory and an operation method thereof. The memory includes: a memory cell array; a first column decoder coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder coupled to the memory cell array and configured to perform a read operation on the memory cell array; a read amplifier located on two opposite sides of the memory cell array and coupled to the memory cell array, and configured to receive read data information output by the memory cell array based on the read operation; wherein the read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory and a method for operating the memory. Background Art

[0002] Dynamic random access memory (DRAM) includes memory cells arranged in an array, each memory cell includes a transistor and a capacitor. DRAM is widely used in electronic devices such as mobile devices and computers. With the development of manufacturing process technology, the capacity of DRAM is gradually increasing. However, during the operation of the memory, there is a problem of read error. Therefore, how to improve the reading accuracy of the memory has become a problem that needs to be solved urgently. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, a memory is provided, including:

[0004] A memory cell array;

[0005] A first column decoder, coupled to the memory cell array, configured to perform a write operation on the memory cell array;

[0006] A second column decoder, coupled to the memory cell array, configured to perform a read operation on the memory cell array;

[0007] a sense amplifier, located on two opposite sides of the memory cell array and the second column decoder, coupled to the memory cell array, and configured to receive read data information output by the memory cell array based on the read operation;

[0008] The sense amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

[0009] In some embodiments, the memory further comprises:

[0010] a command decoder, coupled to the first column decoder, configured to control the first column decoder to perform the write operation according to a received write operation command;

[0011] The command decoder is coupled to the second column decoder, and is further configured to control the second column decoder to perform the read operation according to the received read operation command.

[0012] In some embodiments, the memory further comprises: a first column selection line and a second column selection line;

[0013] The first column selection line is coupled to the first column decoder and the memory cell array, and is used to transmit a first column selection signal to the memory cell array in the first direction; wherein the first column selection signal is used to select a memory cell column in the memory cell array for the write operation;

[0014] The second column selection line couples the second column decoder and the memory cell array, and is used to transmit a second column selection signal to the memory cell array in a second direction opposite to the first direction; wherein the second column selection signal is used to select a memory cell column in the memory cell array for the read operation.

[0015] In some embodiments, the memory cell array includes a first target memory cell and a second target memory cell located in the same column, and the first target memory cell is closer to the second column decoder than the second target memory cell;

[0016] The second column decoder is configured to send a second column selection signal to select the first target memory cell and the second target memory cell to perform a read operation;

[0017] The first target storage unit is configured to output first read data to the sense amplifier according to the second column selection signal during a first read cycle;

[0018] The sense amplifier is further configured to receive the first read data at a first read time interval since the second column decoder issues the second column selection signal;

[0019] The second target storage unit is configured to output second read data to the sense amplifier according to the second column selection signal during a second read cycle;

[0020] The sense amplifier is further configured to receive the second read data at a second read time interval since the second column decoder issues the second column selection signal;

[0021] The first reading time is the same as the second reading time.

[0022] In some embodiments, the memory further comprises:

[0023] The write driver is located at the same side of the memory cell array as the first column decoder, and is configured to send a data signal to be written to the memory cell array according to a received write operation command.

[0024] In some embodiments, the memory further comprises:

[0025] A row decoder is coupled to the memory cell array, wherein the row decoder and the memory cell array are arranged along a third direction, and the third direction is perpendicular to the first direction; wherein,

[0026] The row decoder is configured to send a row selection signal to the memory cell array to select a memory cell row in the memory cell array for performing the write operation or the read operation.

[0027] In some embodiments, the memory includes dynamic random access memory.

[0028] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory is provided, wherein the memory comprises a memory cell array, a first column decoder, a second column decoder, and a sense amplifier, wherein the sense amplifier, the first column decoder, the memory cell array, and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on opposite sides of the memory cell array;

[0029] The operation method comprises:

[0030] When performing a write operation, performing a write operation on the memory cell array through the first column decoder;

[0031] When performing a read operation, performing a read operation on the memory cell array through the second column decoder;

[0032] The sense amplifier receives the read data information output by the memory cell array based on the read operation; wherein the sense amplifier and the second column decoder are located on two opposite sides of the memory cell array.

[0033] In some embodiments, the memory further includes a command decoder, and the operating method further includes:

[0034] When performing a write operation, the command decoder controls the first column decoder to perform the write operation according to the received write operation command;

[0035] When a read operation is performed, the command decoder controls the second column decoder to perform the read operation according to the received read operation command.

[0036] In some embodiments, the memory further comprises a first column selection line, the first column selection line coupling the first column decoder and the memory cell array;

[0037] The performing a write operation on the memory cell array through the first column decoder comprises:

[0038] The first column decoder sends a first column selection signal through the first column selection line in the first direction to select a memory cell column in the memory cell array for a write operation.

[0039] In some embodiments, the memory further comprises a second column selection line, the second column selection line coupling the second column decoder and the memory cell array;

[0040] The performing a read operation on the memory cell array by the second column decoder comprises:

[0041] The second column decoder sends a second column selection signal through the second column selection line in a second direction opposite to the first direction to select a memory cell column in the memory cell array for a read operation.

[0042] In some embodiments, the memory cell array includes a first target memory cell and a second target memory cell located in the same column, and the first target memory cell is closer to the second column decoder than the second target memory cell;

[0043] The second column decoder performs a read operation on the memory cell array, including:

[0044] The second column decoder sends a second column selection signal to select the first target memory cell and the second target memory cell to perform a read operation;

[0045] In a first read cycle, the first target memory cell outputs first read data to the sense amplifier according to the second column selection signal;

[0046] The sense amplifier receives the first read data at a first read time interval since the second column decoder sends the second column selection signal;

[0047] In a second read cycle, the second target memory cell outputs second read data to the sense amplifier according to the second column selection signal;

[0048] The sense amplifier receives the second read data at a second read time interval since the second column decoder sends the second column selection signal;

[0049] The first reading time is the same as the second reading time.

[0050] In some embodiments, the memory further comprises a write driver located on the same side of the memory cell array as the first column decoder;

[0051] The operation method further includes:

[0052] The write driver sends the data signal to be written to the memory cell array according to the received write operation command.

[0053] In some embodiments, the memory further includes a row decoder, wherein the row decoder and the memory cell array are arranged along a third direction, and the third direction is perpendicular to the first direction;

[0054] The operation method further includes:

[0055] The row decoder sends a row selection signal to the memory cell array to select a memory cell row in the memory cell array to perform the write operation or the read operation.

[0056] In the memory provided by the embodiment of the present disclosure, the first column decoder is coupled to the memory cell array and performs a write operation on the memory cell array; the second column decoder is coupled to the memory cell array and performs a read operation on the memory cell array; the read amplifier and the second column decoder that performs the read operation are located on two opposite sides of the memory cell array. Since the read amplifier and the second column decoder are located on two opposite sides of the memory cell array, when the data information of the memory cells at different positions are read by the second column decoder and transmitted to the read amplifier, the time consumption is close to or even the same, which can increase the time margin for the subsequent circuit to receive the data information, thereby reducing the read error and improving the memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a schematic diagram of a memory structure according to an exemplary embodiment;

[0058] Figure 2 Based on Figure 1 A schematic diagram of a memory write operation is shown;

[0059] Figure 3 Based on Figure 1 A schematic diagram of a memory read operation is shown;

[0060] Figure 4 Based on Figure 1 Another schematic diagram of a read operation of a memory is shown;

[0061] Figure 5 A schematic diagram of a read operation of a memory according to an embodiment of the present disclosure;

[0062] Figure 6 is another schematic diagram of a read operation of a memory according to an embodiment of the present disclosure;

[0063] Figure 7 A timing diagram of a read operation of a memory according to an embodiment of the present disclosure;

[0064] Figure 8 The present invention is a flowchart of a method for operating a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The technical solution of the present disclosure is further elaborated in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.

[0066] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.

[0067] In the embodiments of the present disclosure, the term “A is in contact with B” includes the situation where A is in direct contact with B, or the situation where A is in indirect contact with B with other components interposed between A and B.

[0068] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. Furthermore, a layer may include multiple sublayers.

[0069] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning of “on” something with intervening features or layers.

[0070] Figure 1 FIG. 1 is a schematic diagram of a memory structure according to an exemplary embodiment. Figure 1 As shown, the memory 10 includes a memory cell array 11, a column decoder 12, a row decoder 13, a read amplifier 14 and a write driver 15 coupled to the memory cell array 11; wherein the read amplifier 14, the write driver 15, the column decoder 12 and the memory cell array 11 are arranged sequentially along the positive X-axis direction, and the row decoder 13 and the memory cell array 11 are arranged sequentially along the Y-direction.

[0071] refer to Figure 2 , Figure 2 Based on Figure 1The write driver 15 sends the data signal to be written to the memory cell array 11 according to the received write operation command, and the column decoder 12 transmits the column selection signal to the memory cell array 11 along the positive X-axis direction to select the memory cell column in the memory cell array 11 to perform the write operation. Figure 2 As shown, when a write operation is performed on the memory cell array 11, since the column decoder 12 and the write driver 15 are both in the same direction (such as Figure 2 In the positive X-axis direction, the column selection signal and the data signal to be written are transmitted to the memory cell array 11. In this way, the memory cells (such as Figure 2 A) performs a write operation, such as Figure 2 The timing of the column selection signal of the storage cell A shown in FIG. 1 and the data signal to be written can be basically kept consistent. Similarly, for the storage cell array 11 that is relatively far away from the column decoder 12 and the write driver 15 (such as Figure 2 B) performs a write operation, such as Figure 2 The timing of the column selection signal of the memory cell B and the data signal to be written can be kept substantially consistent.

[0072] refer to Figure 3 , Figure 3 Based on Figure 1 FIG. 1 is a schematic diagram of a memory read operation. Figure 3 As shown, when a read operation is performed on the memory cell array 11, for example, a memory cell (such as a memory cell) that is relatively far from the column decoder 12 and the write driver 15 in the memory cell array 11 is Figure 3 Specifically, Figure 3 The signal line with an arrow in the figure shows the process that the column decoder 12 transmits the column selection signal to the memory cell A along the positive X-axis direction, and the memory cell A outputs the read data to the sense amplifier 14 along the direction opposite to the positive X-axis direction according to the column selection signal.

[0073] refer to Figure 4 , Figure 4 Based on Figure 1 Another schematic diagram of a read operation of a memory is shown in FIG. Figure 4 As shown, when a read operation is performed on the memory cell array 11, for example, a memory cell (such as a memory cell in the memory cell array 11 that is relatively close to the column decoder 12 and the write driver 15) is read. Figure 4 Specifically, Figure 4 The signal line with an arrow in the figure shows the process that the column decoder 12 transmits the column selection signal to the memory cell B along the positive X-axis direction, and the memory cell B outputs the read data to the sense amplifier 14 along the direction opposite to the positive X-axis direction according to the column selection signal.

[0074] refer to Figure 3 and Figure 4 When performing a read operation on the memory cell array 11, for the memory cells A and B in the memory cell array 11 that are at different distances from the column decoder 12 and the write driver 15, there is a difference in the time consumption in the process of outputting the read data to the sense amplifier 14. For example, the time consumption of the memory cell A is longer than that of the memory cell B. The memory cells at different positions have different time consumptions when outputting data information to the sense amplifier respectively, which will reduce the time margin for the subsequent circuit to receive the data information, thereby causing a read error.

[0075] In view of this, an embodiment of the present disclosure provides another memory.

[0076] refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a memory according to an embodiment of the present disclosure. Figure 5 As shown, the memory 100 includes:

[0077] Memory cell array 101;

[0078] A first column decoder 102 is coupled to the memory cell array 101 and is configured to perform a write operation on the memory cell array 101;

[0079] A second column decoder 103 , coupled to the memory cell array 101 , is configured to perform a read operation on the memory cell array 101 ;

[0080] The sense amplifier 104 is located on two opposite sides of the memory cell array 101 and the second column decoder 103 , is coupled to the memory cell array 101 , and is configured to receive read data information output by the memory cell array 101 based on a read operation;

[0081] The sense amplifier 104 , the first column decoder 102 , the memory cell array 101 and the second column decoder 103 are arranged in a first direction, and the first column decoder 102 and the second column decoder 103 are located on two opposite sides of the memory cell array 101 .

[0082] It should be noted that the memory 100 includes a memory cell array 101, a first column decoder 102, a second column decoder 103 and a sense amplifier 104. Figure 5 and Figure 6The sense amplifier 104, the first column decoder 102, the memory cell array 101, and the second column decoder 103 shown are arranged sequentially in the first direction for explanation. In addition, the arrangement order of the sense amplifier 104, the first column decoder 102, the memory cell array 101, and the second column decoder 103 can be changed, and this embodiment does not limit this. The first column decoder 102, the sense amplifier 104, the memory cell array 101, and the second column decoder 103 are arranged sequentially in the first direction, or arranged in other directions, and the present invention can also be implemented.

[0083] Exemplarily, the memory 100 may include a first column decoder 102 and a second column decoder 103, which drive a memory cell array 101 in two directions (eg, in opposite directions). Figure 5 As shown, the first column decoder 102 and the second column decoder 103 can be located at both sides of the memory cell array 101 respectively, the first column decoder 102 drives the memory cell array 101 along the positive X-axis direction, and the second column decoder 103 drives the memory cell array 101 along the direction opposite to the positive X-axis direction.

[0084] When a write operation instruction is received, a write operation is performed on the memory cell array 101 through the first column decoder 102. Figure 5 As shown, when a write operation is performed on the memory cell array 101, since the first column decoder 102 and the write driver 107 are both in the same direction (such as Figure 5 The column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. Figure 5 In the writing process shown, the timing of the column selection signal and the data signal to be written can be kept basically consistent, thereby improving the consistency of the writing operation.

[0085] Exemplarily, the input column address obtained by decoding the write operation instruction is transmitted to the first column decoder 102. The first column decoder 102 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 102 can send the first column selection signal along the positive X-axis direction, thereby selecting the storage cell column corresponding to the input column address to perform the write operation.

[0086] In one example, when a read operation instruction is received, the second column decoder 103 performs a read operation on the memory cell array 101. Figure 5 As shown, a read operation is performed on a memory cell 101a of the memory cell array 101 which is relatively close to the second column decoder 103. Specifically, Figure 5The signal line indicated by the arrow shows that the second column decoder 103 transmits the second column selection signal to the storage unit 101a along the direction opposite to the positive X-axis direction (negative X-axis direction), and the storage unit 101a outputs the read data to the read-out amplifier 104 along the direction opposite to the positive X-axis direction (negative X-axis direction) according to the second column selection signal.

[0087] In another example, reference Figure 6 , Figure 6 Based on Figure 5 Another schematic diagram of a read operation of a memory is shown in FIG. Figure 6 As shown, a read operation is performed on a memory cell 101b of the memory cell array 101 which is relatively far from the second column decoder 103. Specifically, Figure 6 The signal line indicated by the arrow in the figure shows that the second column decoder 103 transmits the second column selection signal to the storage unit 101b in the direction opposite to the positive X-axis direction (negative X-axis direction), and the storage unit 101b outputs the read data to the read-out amplifier 104 in the direction opposite to the positive X-axis direction (negative X-axis direction) according to the second column selection signal.

[0088] Exemplarily, the input column address obtained by decoding the read operation instruction is transmitted to the second column decoder 103. The second column decoder 103 can decode the input column address and generate a second column selection signal based on the decoding result. Figure 5 , the second column decoder 103 can send a second column selection signal in the direction opposite to the positive X-axis direction (negative X-axis direction), thereby selecting the memory cell column corresponding to the input column address, and performing a read operation on the memory cell 101a determined by the memory cell row corresponding to the input row address. Figure 6 The second column decoder 103 can send a second column selection signal in a direction opposite to the positive X-axis direction (negative X-axis direction), thereby selecting the storage cell column corresponding to the input column address, and performing a read operation on the storage cell 101b determined by the storage cell row corresponding to the input row address.

[0089] refer to Figure 5 and Figure 6 When performing a read operation on the memory cell array 101, for the memory cells 101a and 101b in the memory cell array 101 that are at different distances from the second column decoder 103, the process of outputting the read data to the sense amplifier 104 basically takes the same time. In this way, when the data information of the memory cells at different positions are read by the second column decoder 103 and transmitted to the sense amplifier, the time consumption is close to or even the same, which can increase the time margin for the subsequent circuit to receive the data information, thereby improving the accuracy of the data information reading.

[0090] In the memory provided by the embodiment of the present disclosure, the first column decoder 102 is coupled to the memory cell array 101 and performs a write operation on the memory cell array 101; the second column decoder 103 is coupled to the memory cell array 101 and performs a read operation on the memory cell array 101; the read amplifier 104 and the second column decoder 103 that performs the read operation are located on two opposite sides of the memory cell array 101. Since the read amplifier 104 and the second column decoder 103 are located on two opposite sides of the memory cell array, when the data information of the memory cells at different positions are read by the second column decoder 103 and transmitted to the read amplifier 104, the time consumption is close to or even the same, thereby avoiding the problem of a reduction in the time margin for the subsequent circuit to receive the data information, thereby causing a read error, thereby improving the memory performance.

[0091] In some embodiments, the memory further comprises:

[0092] a command decoder, coupled to the first column decoder 102, and configured to control the first column decoder 102 to perform a write operation according to a received write operation command;

[0093] The command decoder is coupled to the second column decoder 103 , and is further configured to control the second column decoder 103 to perform a read operation according to a received read operation command.

[0094] Exemplarily, a command (CMD) decoder (not shown) may control the first column decoder 102 , the second column decoder 103 , and the row decoder 108 in response to a command (CMD) and an address (ADD) received from outside the memory 100 .

[0095] In one example, the command decoder may control the first column decoder 102 in response to a write operation command, and may send an input column address to the first column decoder 102. Thus, the first column decoder 102 may be referred to as a "write operation column decoder". In another example, the command decoder may control the second column decoder 103 in response to a read operation command, and may send an input column address to the second column decoder 103. Thus, the second column decoder 103 may be referred to as a "read operation column decoder".

[0096] In an exemplary embodiment, the command decoder may also control the row decoder 108 in response to an active command, a precharge command, a refresh command, etc., and may send an input row address to the row decoder 108 .

[0097] In the memory provided by the embodiment of the present disclosure, an additional read operation column decoding circuit, namely, a second column decoder 103, is added at one end of the memory cell array 101, and the command decoder controls the first column decoder 102 to perform a write operation and controls the second column decoder 103 to perform a read operation. Figure 5 and Figure 6 As shown, when a read operation is performed on the memory cell array 101, the memory cell 101a and the memory cell 101b respectively output data information to the sense amplifier 104 with similar or even the same time consumption, thereby improving the consistency of the read operation.

[0098] In some embodiments, the memory further includes: a first column selection line 105 and a second column selection line 106;

[0099] A first column selection line 105, coupled to the first column decoder 102 and the memory cell array 101, for transmitting a first column selection signal to the memory cell array 101 in a first direction; wherein the first column selection signal is used to select a memory cell column in the memory cell array 101 for performing a write operation;

[0100] The second column selection line 106 is coupled to the second column decoder 103 and the memory cell array 101, and is used to transmit a second column selection signal to the memory cell array 101 in a second direction opposite to the first direction; wherein the second column selection signal is used to select a memory cell column in the memory cell array 101 for performing a read operation.

[0101] Exemplarily, the column selection signal may be generated by the first column decoder 102 and the second column decoder 103. In one example, referring to Figure 5 The first column decoder 102 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 102 can decode the input column address through the first column selection line 105 in the first direction (such as Figure 5 The first column select line 105 is driven, selected or activated along the positive X-axis direction. Each of the first column select lines 105 can be connected to at least one bit line.

[0102] In another example, reference Figure 6 The second column decoder 103 can decode the input column address and generate a second column selection signal based on the decoding result. The second column decoder 103 can decode the input column address through the second column selection line 106 in the second direction (such as Figure 6 The second column select line 106 is sent along the negative X-axis direction (as shown in the negative X-axis direction) to select the memory cell column corresponding to the input column address. The second column decoder 103 can drive, select or activate the second column select line 106 along the negative X-axis direction. Each of the second column select lines 106 can be connected to at least one bit line.

[0103] In an exemplary embodiment, the column selection signal may be generated by a command decoder. For example, the command decoder may generate a first column selection line signal in response to a write operation command, and send the first column selection signal to the first column decoder 102. The command decoder may also generate a second column selection signal in response to a read operation command, and send the second column selection signal to the second column decoder 103.

[0104] It should be noted that the reference Figure 5 and Figure 6 The first column selection line 105 and the second column selection line 106 may be the same column selection line, and column selection signals are transmitted respectively during a read operation or a write operation through the same column selection line.

[0105] In some embodiments, the memory cell array 101 includes a first target memory cell 101 a and a second target memory cell 101 b located in the same column, and the first target memory cell 101 a is closer to the second column decoder 103 than the second target memory cell 101 b ;

[0106] The second column decoder 103 is configured to send a second column selection signal to select the first target memory cell 101 a and the second target memory cell 101 b to perform a read operation;

[0107] The first target memory cell 101 a is configured to output first read data to the sense amplifier 104 according to the second column selection signal during a first read cycle;

[0108] The sense amplifier 104 is further configured to receive the first read data at a first read time interval after the second column decoder 103 issues the second column selection signal;

[0109] The second target memory cell 101 b is configured to output second read data to the sense amplifier 104 according to the second column selection signal during the second read cycle;

[0110] The sense amplifier 104 is further configured to receive second read data at a second read time interval after the second column decoder 103 issues a second column selection signal;

[0111] The first reading time is the same as the second reading time.

[0112] refer to Figure 5 and Figure 6 The memory cell array 101 includes a first target memory cell 101a and a second target memory cell 101b located in the same column. The first target memory cell 101a is closer to the second column decoder 103 than the second target memory cell 101b.

[0113] refer to Figure 5 and Figure 7, the second column decoder 103 sends a second column selection signal Ysel, which is transmitted to the first target storage unit 101a after time t1. The first target storage unit 101a receives the second column selection signal (such as Figure 7 Ysel_A), and after time t2, the stored first read data Gio_A is output, and the first read data Gio_A is transmitted to the sense amplifier 104 after time t3. The sense amplifier 104 receives the first read data (such as Figure 7 in Gio_SA_A).

[0114] For example, reference Figure 7 , the sense amplifier 104 receives the first read data after the second column decoder 103 sends the second column selection signal, and the first read time T1 is equal to t1+t2+t3.

[0115] refer to Figure 6 and Figure 7 , the second column decoder 103 sends a second column selection signal Ysel, which is transmitted to the second target storage unit 101b after time t4. The second target storage unit 101b receives the second column selection signal (such as Figure 7 Ysel_B), and after time t5, the stored second read data Gio_B is output, and the second read data Gio_B is transmitted to the sense amplifier 104 after time t6. The sense amplifier 104 receives the second read data (such as Figure 7 in Gio_SA_B).

[0116] For example, reference Figure 7 , the sense amplifier 104 receives the second read data after the second column decoder 103 sends the second column selection signal, and the second read time T2 is equal to t4+t5+t6.

[0117] refer to Figures 5 to 7 When a read operation is performed on the memory cell array 101, the first target memory cell 101a and the second target memory cell 101b respectively output read data to the read amplifier 104, and the first read time T1 is the same as the second read time T2. In the memory provided by the embodiment of the present disclosure, even if a read operation is performed on different memory cells, the read time is the same, thereby avoiding the problem of a reduction in the time margin for subsequent circuits to receive data information, thereby causing a read error, thereby improving the consistency of the read operation and enhancing the memory performance.

[0118] In some embodiments, the memory further comprises:

[0119] The write driver 107 is located at the same side of the memory cell array 101 as the first column decoder 102 , and is configured to send a data signal to be written to the memory cell array 101 according to a received write operation command.

[0120] refer to Figure 5 and Figure 6 , the write driver 107, the first column decoder 102 and the memory cell array 101 are arranged in sequence along the positive X-axis direction. It should be noted that, Figure 5 and Figure 6 A memory internal arrangement is provided. However, this is only an example, and the present disclosure is not limited to such Figure 5 and Figure 6 The first column decoder 102, write driver 107, sense amplifier 104, memory cell array 101 and second column decoder 103 are sequentially arranged in a first direction, or arranged in other directions, etc., which can also implement the present invention.

[0121] When receiving a write operation instruction, a write operation is performed on the memory cell array 101. The write driver 107 can perform an operation of writing data to the memory cell through the data input line (GIO). Figure 5 As shown, when a write operation is performed on the memory cell array 101, since the first column decoder 102 and the write driver 107 are both in the same direction (such as Figure 5 The first column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. Figure 5 In the writing process shown, the timing of the first column selection signal and the data signal to be written can be kept basically consistent, thereby improving the consistency of the writing operation.

[0122] Exemplarily, the input column address obtained by decoding the write operation instruction is transmitted to the first column decoder 102. The first column decoder 102 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 102 can send the first column selection signal along the positive X-axis direction, thereby selecting the storage cell column corresponding to the input column address to perform the write operation.

[0123] In the embodiment of the present disclosure, since the first column decoder 102 and the write driver 107 are both in the same direction (eg, Figure 5 The column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. During the writing process, the timing of the column selection signal and the data signal to be written can be basically kept consistent, thereby reducing writing errors and improving memory performance.

[0124] In some embodiments, the memory further comprises:

[0125] The row decoder 108 is coupled to the memory cell array 101. The row decoder 108 and the memory cell array 101 are arranged along a third direction, which is perpendicular to the first direction.

[0126] The row decoder 108 is configured to send a row selection signal to the memory cell array 101 to select a memory cell row in the memory cell array 101 for performing a write operation or a read operation.

[0127] For example, the row decoder 108 can decode the input row address and generate a row selection signal based on the decoded result. The row decoder 108 can select the row address in the third direction (such as Figure 5 A row selection signal is sent in the negative Y-axis direction) and a storage cell corresponding to the input row address can be selected.

[0128] refer to Figure 5 and Figure 6 , the row decoder 108 and the memory cell array 101 are arranged along the third direction (eg Figure 5 It should be noted that: Figure 5 and Figure 6 A memory internal arrangement is provided. However, this is only an example, and the row decoder 108 of the present disclosure is not limited to such Figure 5 and Figure 6 The arrangement shown.

[0129] In some embodiments, the memory includes dynamic random access memory.

[0130] It should be noted that the memory may include a dynamic random access memory. The memory may also include other types of memory. For example, static random access memory (SRAM), NAND flash memory, NOR flash memory, resistive random access memory (RRAM), ferroelectric random access memory (FRAM), phase change random access memory (PRAM), thyristor random access memory (TRAM) and magnetic random access memory (MRAM). The present disclosure is not limited to this.

[0131] like Figure 8 As shown, Figure 8The present invention is a flow chart of an operation method of a memory according to an embodiment of the present disclosure. The memory includes a memory cell array, a first column decoder, a second column decoder and a sense amplifier, wherein the sense amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on opposite sides of the memory cell array;

[0132] The operation methods include:

[0133] S10: When a write operation is performed, a write operation is performed on the memory cell array through the first column decoder;

[0134] S20: when a read operation is performed, a read operation is performed on the memory cell array through the second column decoder;

[0135] S30: The sense amplifier receives the read data information outputted by the memory cell array based on the read operation; wherein the sense amplifier and the second column decoder are located on two opposite sides of the memory cell array.

[0136] It should be noted that the memory includes a storage cell array, a first column decoder, a second column decoder and a sense amplifier. Figure 5 and Figure 6 The arrangement of the sense amplifier, the first column decoder, the memory cell array, and the second column decoder in the first direction is described as an example. In addition, the arrangement order of the sense amplifier, the first column decoder, the memory cell array, and the second column decoder in the first direction may be variable, and this embodiment does not limit this. The first column decoder 102, the sense amplifier 104, the memory cell array 101, and the second column decoder 103 may be arranged in sequence in the first direction, or may be arranged in other directions to implement the present invention.

[0137] Step S10 is executed, and when a write operation instruction is received, a write operation is performed on the memory cell array through the first column decoder. Specifically, the input column address obtained by decoding the write operation instruction is transmitted to the first column decoder. The first column decoder can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder can send the first column selection signal along the positive X-axis direction, thereby selecting the memory cell column corresponding to the input column address to perform the write operation.

[0138] For example, Figure 5 As shown, when a write operation is performed on the memory cell array 101, since the first column decoder 102 and the write driver 107 are both in the same direction (such as Figure 5 The column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. Figure 5In the writing process shown, the timing of the column selection signal and the data signal to be written can be kept basically consistent, thereby improving the consistency of the writing operation.

[0139] Step S20 is performed, when a read operation instruction is received, a read operation is performed on the memory cell array 101 through the second column decoder. Specifically, the input column address obtained by decoding the read operation instruction is transmitted to the second column decoder. The second column decoder can decode the input column address and generate a second column selection signal based on the decoding result. The memory cell column corresponding to the input column address is selected according to the second column selection signal to perform the read operation.

[0140] In one example, reference Figure 5 , the second column decoder 103 can send a second column selection signal in the direction opposite to the positive X-axis direction (negative X-axis direction), thereby selecting the storage cell column corresponding to the input column address, and performing a read operation on the storage cell 101a determined by the storage cell row corresponding to the input row address. Figure 5 As shown, Figure 5 The signal line indicated by the arrow shows that the second column decoder 103 transmits the second column selection signal to the storage unit 101a along the direction opposite to the positive X-axis direction (negative X-axis direction), and the storage unit 101a outputs the read data to the read-out amplifier 104 along the direction opposite to the positive X-axis direction (negative X-axis direction) according to the second column selection signal.

[0141] In another example, reference Figure 6 , the second column decoder 103 can send a second column selection signal in the direction opposite to the positive X-axis direction (negative X-axis direction), thereby selecting the storage cell column corresponding to the input column address, and performing a read operation on the storage cell 101b determined by the storage cell row corresponding to the input row address. Figure 6 As shown, Figure 6 The signal line indicated by the arrow in the figure shows that the second column decoder 103 transmits the second column selection signal to the storage unit 101b in the direction opposite to the positive X-axis direction (negative X-axis direction), and the storage unit 101b outputs the read data to the read-out amplifier 104 in the direction opposite to the positive X-axis direction (negative X-axis direction) according to the second column selection signal.

[0142] refer to Figure 5 and Figure 6 When a read operation is performed on the memory cell array 101, for the memory cell 101a and the memory cell 101b in the memory cell array 101 that are at different distances from the second column decoder 103, the process of outputting the read data to the sense amplifier 104 takes substantially the same time.

[0143] In the memory provided by the embodiment of the present disclosure, when a write operation is performed, a write operation is performed on the memory cell array through the first column decoder; when a read operation is performed, a read operation is performed on the memory cell array through the second column decoder; a read amplifier receives read data information output by the memory cell array based on the read operation; wherein the read amplifier and the second column decoder are located on opposite sides of the memory cell array. Since the read amplifier and the second column decoder are located on opposite sides of the memory cell array, when the data information of the memory cells at different positions is read respectively by the second column decoder and transmitted to the read amplifier, the time consumption is close to or even the same, thereby avoiding the problem of a reduction in the time margin for the subsequent circuit to receive the data information, thereby causing a read error, thereby improving the memory performance.

[0144] In some embodiments, the memory further includes a command decoder, and the operating method further includes:

[0145] When performing a write operation, the command decoder controls the first column decoder to perform the write operation according to the received write operation command;

[0146] When a read operation is performed, the command decoder controls the second column decoder to perform the read operation according to the received read operation command.

[0147] Exemplarily, a command (CMD) decoder may control the first column decoder, the second column decoder, and the row decoder in response to a command (CMD) and an address (ADD) received from the outside of the memory 100 .

[0148] In an example, the command decoder may control the first column decoder in response to a write operation command and may send an input column address to the first column decoder. Thus, the first column decoder 102 may be referred to as a "write operation column decoder."

[0149] In another example, the command decoder may control the second column decoder in response to the read operation command and may send the input column address to the second column decoder. Thus, the second column decoder may be referred to as a “read operation column decoder”.

[0150] In an exemplary embodiment, the command decoder may also control the row decoder in response to an active command, a precharge command, a refresh command, etc., and may transmit an input row address to the row decoder.

[0151] In some embodiments, the memory further comprises a first column selection line, the first column selection line being coupled to the first column decoder and the memory cell array;

[0152] A write operation is performed on the memory cell array through the first column decoder, including:

[0153] The first column decoder sends a first column selection signal in a first direction through a first column selection line to select a column of memory cells in the memory cell array for a write operation.

[0154] In an example, the column selection signal may be generated by the first column decoder 102 and the second column decoder 103. Figure 5 The first column decoder 102 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 102 can decode the input column address through the first column selection line 105 in the first direction (such as Figure 5 The first column select line 105 is driven, selected or activated along the positive X-axis direction. Each of the first column select lines 105 can be connected to at least one bit line.

[0155] In another example, the column selection signal may be generated by a command decoder. For example, the command decoder may generate a first column selection line signal in response to a write operation command, and send the first column selection signal to a first column decoder.

[0156] In some embodiments, the memory further comprises a second column selection line, the second column selection line being coupled to the second column decoder and the memory cell array;

[0157] A read operation is performed on the memory cell array through the second column decoder, including:

[0158] The second column decoder sends a second column selection signal through a second column selection line in a second direction opposite to the first direction to select a memory cell column in the memory cell array for a read operation.

[0159] In an example, the column selection signal may be generated by the first column decoder 102 and the second column decoder 103. Figure 6 The second column decoder 103 can decode the input column address and generate a second column selection signal based on the decoding result. The second column decoder 103 can decode the input column address through the second column selection line 106 in the second direction (such as Figure 6 The second column select line 106 is sent along the negative X-axis direction (as shown in the negative X-axis direction) to select the memory cell column corresponding to the input column address. The second column decoder 103 can drive, select or activate the second column select line 106 along the negative X-axis direction. Each of the second column select lines 106 can be connected to at least one bit line.

[0160] In another example, the column selection signal may be generated by the command decoder. For example, the command decoder may also generate a second column selection signal in response to the read operation command, and send the second column selection signal to the second column decoder.

[0161] It should be noted that the reference Figure 5 and Figure 6 The first column selection line 105 and the second column selection line 106 may be the same column selection line, and column selection signals are transmitted respectively during a read operation or a write operation through the same column selection line.

[0162] In some embodiments, the memory cell array includes a first target memory cell and a second target memory cell located in the same column, the first target memory cell being closer to the second column decoder than the second target memory cell;

[0163] The second column decoder performs a read operation on the memory cell array, including:

[0164] The second column decoder sends a second column selection signal to select the first target memory cell and the second target memory cell to perform a read operation;

[0165] In a first read cycle, the first target memory cell outputs first read data to the sense amplifier according to a second column selection signal;

[0166] The sense amplifier receives the first read data at a first read time interval after the second column decoder issues the second column selection signal;

[0167] In a second read cycle, the second target memory cell outputs second read data to the sense amplifier according to a second column selection signal;

[0168] The sense amplifier receives the second read data at a second read time interval after the second column decoder issues the second column selection signal;

[0169] The first reading time is the same as the second reading time.

[0170] refer to Figure 5 and Figure 6 The memory cell array 101 includes a first target memory cell 101a and a second target memory cell 101b located in the same column. The first target memory cell 101a is closer to the second column decoder 103 than the second target memory cell 101b.

[0171] refer to Figure 5 and Figure 7 , the second column decoder 103 sends a second column selection signal Ysel, which is transmitted to the first target storage unit 101a after time t1. The first target storage unit 101a receives the second column selection signal (such as Figure 7 The first read data stored is output after time t2 (such as Figure 7 After time t3, the first read data is transmitted to the sense amplifier 104, and the sense amplifier 104 receives the first read data (such as Figure 7 in Gio_SA_A).

[0172] For example, reference Figure 7 , the sense amplifier 104 receives the first read data after the second column decoder 103 sends the second column selection signal, and the first read time T1 is equal to t1+t2+t3.

[0173] refer to Figure 6 and Figure 7 , the second column decoder 103 sends a second column selection signal Ysel, which is transmitted to the second target storage unit 101b after time t4. The second target storage unit 101b receives the second column selection signal (such as Figure 7 The second read data stored is output after time t5 (eg Figure 7 After time t6, the second read data is transmitted to the sense amplifier 104, and the sense amplifier 104 receives the second read data (such as Figure 7 in Gio_SA_B).

[0174] For example, reference Figure 7 , the sense amplifier 104 receives the second read data after the second column decoder 103 sends the second column selection signal, and the second read time T2 is equal to t4+t5+t6.

[0175] refer to Figures 5 to 7 When a read operation is performed on the memory cell array 101, the first target memory cell 101a and the second target memory cell 101b respectively output read data to the read amplifier 104, and the first read time T1 is the same as the second read time T2. In the memory provided by the embodiment of the present disclosure, even if a read operation is performed on different memory cells, the read time is the same, thereby avoiding the problem of a reduction in the time margin for subsequent circuits to receive data information, thereby causing a read error, thereby improving the consistency of the read operation and enhancing the memory performance.

[0176] In some embodiments, the memory further comprises a write driver located on the same side of the memory cell array as the first column decoder;

[0177] The operation method also includes:

[0178] The write driver sends the data signal to be written to the memory cell array according to the received write operation command.

[0179] refer to Figure 5 and Figure 6 , the write driver 107, the first column decoder 102 and the memory cell array 101 are arranged in sequence along the positive X-axis direction. It should be noted that, Figure 5 and Figure 6 A memory internal arrangement is provided. However, this is only an example, and the present disclosure is not limited to such Figure 5 and Figure 6 The arrangement shown.

[0180] When receiving a write operation instruction, a write operation is performed on the memory cell array 101. The write driver 107 can perform an operation of writing data to the memory cell through the data input line (GIO). Figure 5 As shown, when a write operation is performed on the memory cell array 101, since the first column decoder 102 and the write driver 107 are both in the same direction (such as Figure 5 The first column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. Figure 5 In the writing process shown, the timing of the first column selection signal and the data signal to be written can be kept basically consistent, thereby improving the consistency of the writing operation.

[0181] Exemplarily, the input column address obtained by decoding the write operation instruction is transmitted to the first column decoder 102. The first column decoder 102 can decode the input column address and generate a first column selection signal based on the decoding result. The first column decoder 102 can send the first column selection signal in the positive X-axis direction, thereby selecting the storage cell column corresponding to the input column address to perform the write operation.

[0182] In the embodiment of the present disclosure, since the first column decoder 102 and the write driver 107 are both in the same direction (eg, Figure 5 The column selection signal and the data signal to be written are transmitted to the memory cell array 101 in the positive X-axis direction. During the writing process, the timing of the column selection signal and the data signal to be written can be basically kept consistent, thereby reducing writing errors and improving memory performance.

[0183] In some embodiments, the memory further includes a row decoder, the row decoder and the memory cell array are arranged along a third direction, and the third direction is perpendicular to the first direction;

[0184] The operation method also includes:

[0185] The row decoder sends a row selection signal to the memory cell array to select a memory cell row in the memory cell array for a write operation or a read operation.

[0186] refer to Figure 5 and Figure 6 The row decoder 108 may decode the input row address and may generate a row selection signal based on the decoded result. The row decoder 108 may send the row selection signal in the positive Y-axis direction through the word line and may select a memory cell corresponding to the input row address.

[0187] For example, Figure 5 and Figure 6 As shown, the row decoder 108 and the memory cell array 101 are arranged along the third direction (eg Figure 5 It should be noted that: Figure 5 and Figure 6 A memory internal arrangement is provided. However, this is only an example, and the row decoder 108 of the present disclosure is not limited to such Figure 5 and Figure 6 The arrangement shown.

[0188] It should be understood that "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0189] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A memory cell array; A first column decoder, coupled to the memory cell array, configured to perform a write operation on the memory cell array; A second column decoder, coupled to the memory cell array, configured to perform a read operation on the memory cell array; a sense amplifier, located on opposite sides of the memory cell array and the second column decoder, coupled to the memory cell array, and configured to receive read data information output by the memory cell array based on the read operation; The sense amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array; The memory cell array includes a third target memory cell, a distance between the third target memory cell and the second column decoder is greater than a distance between the third target memory cell and the first column decoder, and the second column decoder is configured to perform a read operation on the third target memory cell.

2. The memory according to claim 1, characterized in that: The memory also includes: a command decoder, coupled to the first column decoder, configured to control the first column decoder to perform the write operation according to a received write operation command; The command decoder is coupled to the second column decoder, and is further configured to control the second column decoder to perform the read operation according to the received read operation command.

3. The memory according to claim 1, characterized in that: The memory further comprises: a first column selection line and a second column selection line; The first column selection line is coupled to the first column decoder and the memory cell array, and is used to transmit a first column selection signal to the memory cell array in the first direction; wherein the first column selection signal is used to select a memory cell column in the memory cell array for the write operation; The second column selection line couples the second column decoder and the memory cell array, and is used to transmit a second column selection signal to the memory cell array in a second direction opposite to the first direction; wherein the second column selection signal is used to select a memory cell column in the memory cell array for the read operation.

4. The memory according to claim 1, characterized in that: The memory cell array includes a first target memory cell and a second target memory cell located in the same column, the first target memory cell being closer to the second column decoder than the second target memory cell; The second column decoder is configured to send a second column selection signal to select the first target memory cell and the second target memory cell to perform a read operation; The first target storage unit is configured to output first read data to the sense amplifier according to the second column selection signal during a first read cycle; The sense amplifier is further configured to receive the first read data at a first read time interval since the second column decoder issues the second column selection signal; The second target storage unit is configured to output second read data to the sense amplifier according to the second column selection signal during a second read cycle; The sense amplifier is further configured to receive the second read data at a second read time interval since the second column decoder issues the second column selection signal; The first reading time is the same as the second reading time.

5. The memory according to claim 1, characterized in that: The memory also includes: The write driver is located at the same side of the memory cell array as the first column decoder, and is configured to send a data signal to be written to the memory cell array according to a received write operation command.

6. The memory according to claim 1, characterized in that: The memory also includes: A row decoder is coupled to the memory cell array, wherein the row decoder and the memory cell array are arranged along a third direction, and the third direction is perpendicular to the first direction; wherein, The row decoder is configured to send a row selection signal to the memory cell array to select a memory cell row in the memory cell array for performing the write operation or the read operation.

7. The memory according to claim 1, characterized in that: The memory includes dynamic random access memory.

8. A method for operating a memory, characterized in that: The memory comprises a memory cell array, a first column decoder, a second column decoder and a sense amplifier, wherein the sense amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array; The operation method comprises: When performing a write operation, performing a write operation on the memory cell array through the first column decoder; When performing a read operation, performing a read operation on the memory cell array through the second column decoder; The sense amplifier receives the read data information output by the memory cell array based on the read operation; wherein the sense amplifier and the second column decoder are located on two opposite sides of the memory cell array; The memory cell array includes a third target memory cell, the distance between the third target memory cell and the second column decoder is greater than the distance between the third target memory cell and the first column decoder, and the operation method further includes: the second column decoder performs a read operation on the third target memory cell.

9. The memory operation method according to claim 8, characterized in that: The memory further includes a command decoder, and the operating method further includes: When performing a write operation, the command decoder controls the first column decoder to perform the write operation according to the received write operation command; When a read operation is performed, the command decoder controls the second column decoder to perform the read operation according to the received read operation command.

10. The memory operation method according to claim 8, characterized in that: The memory further comprises a first column selection line, the first column selection line coupling the first column decoder and the memory cell array; The performing a write operation on the memory cell array through the first column decoder comprises: The first column decoder sends a first column selection signal through the first column selection line in the first direction to select a memory cell column in the memory cell array for a write operation.

11. The memory operation method according to claim 8, characterized in that: The memory further comprises a second column selection line, wherein the second column selection line is coupled to the second column decoder and the memory cell array; The performing a read operation on the memory cell array by the second column decoder comprises: The second column decoder sends a second column selection signal through the second column selection line in a second direction opposite to the first direction to select a memory cell column in the memory cell array for a read operation.

12. The memory operation method according to claim 8, characterized in that: The memory cell array includes a first target memory cell and a second target memory cell located in the same column, the first target memory cell being closer to the second column decoder than the second target memory cell; The second column decoder performs a read operation on the memory cell array, including: The second column decoder sends a second column selection signal to select the first target memory cell and the second target memory cell to perform a read operation; In a first read cycle, the first target memory cell outputs first read data to the sense amplifier according to the second column selection signal; The sense amplifier receives the first read data at a first read time interval since the second column decoder sends the second column selection signal; In a second read cycle, the second target memory cell outputs second read data to the sense amplifier according to the second column selection signal; The sense amplifier receives the second read data at a second read time interval since the second column decoder sends the second column selection signal; The first reading time is the same as the second reading time.

13. The memory operation method according to claim 8, characterized in that: The memory further comprises a write driver located on the same side of the memory cell array as the first column decoder; The operation method also includes: The write driver sends the data signal to be written to the memory cell array according to the received write operation command.

14. The memory operation method according to claim 8, characterized in that: The memory further comprises a row decoder, wherein the row decoder and the memory cell array are arranged along a third direction, and the third direction is perpendicular to the first direction; The operation method also includes: The row decoder sends a row selection signal to the memory cell array to select a memory cell row in the memory cell array to perform the write operation or the read operation.

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