Field emission device and method for manufacturing the same

Abstract

A manufacturing method of a field emission device is disclosed, including: forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures on the primary epitaxial layer; forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer; sequentially forming a stacked protective layer, insulating layer, gate electrode layer, and planarization layer on the dielectric layer and the plurality of secondary epitaxial structures; performing an etching process on the planarization layer to expose a part of the gate electrode layer on the dielectric layer and a part of the secondary epitaxial structures; etching and removing a part of the protective layer, insulating layer, and the exposed part of the gate electrode layer on the part of the secondary epitaxial structures to expose the part of the secondary epitaxial structures; forming a gate connection electrode layer on the exposed gate electrode layer on the dielectric layer; forming an anode opposite to the exposed part of the secondary epitaxial structures, and there is a predetermined distance between the anode and the exposed part of the secondary epitaxial structures. A field emission device is also disclosed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a field emission device and a manufacturing method thereof. Background Art

[0002] A field emission device (FE) is a vacuum transistor based on the field emission phenomenon. Due to its radiation hardness and scatter-free electron transport, it is suitable for use in harsh environments and high-frequency electronic devices. Currently, silicon (Si)-based field emission devices are the most maturely developed. To reduce the operating voltage of the FE, a sharp tip morphology or a reduced gate-emitter spacing is usually required. Group III nitride semiconductor materials are considered to be able to further improve the performance of field emission devices and reduce the turn-on voltage because their electron affinity can be adjusted (for example, GaN can be doped with Al to control the Al component for adjustment) and n-type doping is easily achievable. First, as the electron affinity decreases, electrons can more easily tunnel from the semiconductor surface into the vacuum, which will result in a lower operating voltage for the device.

[0003] Currently, there is still relatively little research on field emission devices based on group III nitrides. The reported turn-on voltages of the device results are generally greater than 100V. Since the characteristic dimensions of field emission devices are usually less than 100nm, their manufacturing processes mostly rely on advanced lithography and etching technologies, such as electron beam lithography, wet digital etching technology, etc. The main problems are low current density, poor device stability, high manufacturing difficulty, and poor on-chip uniformity, etc. Summary of the Invention

[0004] To solve the above technical problems existing in the prior art, the present invention provides a field emission device and a manufacturing method thereof.

[0005] According to one aspect of the embodiments of the present invention, a manufacturing method of a field emission device is provided, including: forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures on the primary epitaxial layer, with a gap between adjacent secondary epitaxial structures; forming an emitter electrode layer on the primary epitaxial layer and a dielectric layer between the emitter electrode layer and the plurality of secondary epitaxial structures; sequentially forming a stacked protective layer, insulating layer, gate electrode layer, and planarization layer on the dielectric layer and the plurality of secondary epitaxial structures; etching the planarization layer to expose a part of the dielectric layer and a part of the gate electrode layer on a part of the secondary epitaxial structures; etching and removing a part of the protective layer, insulating layer, and the exposed part of the gate electrode layer on a part of the secondary epitaxial structures to expose a part of the secondary epitaxial structures; forming a gate connection electrode layer on the exposed gate electrode layer on the dielectric layer; forming an anode opposite to the exposed part of the secondary epitaxial structures, with a predetermined distance between the anode and the exposed part of the secondary epitaxial structures.

[0006] In an example of the manufacturing method provided in the above-mentioned aspect, the multiple secondary epitaxial structure arrays are arranged, the secondary epitaxial structure is a secondary epitaxial bump, and the secondary epitaxial bump is in the shape of a circular frustum or a square frustum.

[0007] In an example of the manufacturing method provided in the above-mentioned aspect, the multiple secondary epitaxial structures are arranged at intervals in sequence, the secondary epitaxial structure is a secondary epitaxial strip, and the length extension direction of the secondary epitaxial strip is perpendicular to the arrangement direction of the multiple secondary epitaxial strips.

[0008] In an example of the manufacturing method provided in the above-mentioned aspect, the predetermined distance is 1 - 10 mm.

[0009] In an example of the manufacturing method provided in the above-mentioned aspect, before forming the emitter electrode layer and the dielectric layer located between the emitter electrode layer and the multiple secondary epitaxial structures on the primary epitaxial layer, the manufacturing method further includes: forming a depletion layer on the top surface and the side surface of the secondary epitaxial structure to form a depletion region between the side surface and the depletion layer.

[0010] In an example of the manufacturing method provided in the above-mentioned aspect, before forming the primary epitaxial layer on the substrate, the manufacturing method further includes: forming a buffer layer on the substrate, wherein the epitaxial layer is formed on the buffer layer.

[0011] In an example of the manufacturing method provided in the above-mentioned aspect, the method for forming multiple secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing patterning on the mask layer to form a plurality of through holes arranged in an array in the mask layer; performing secondary epitaxy on the primary epitaxial layer exposed by each through hole to form multiple secondary epitaxial structures; removing the remaining mask layer.

[0012] In an example of the manufacturing method provided in the above-mentioned aspect, the method for forming multiple secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing patterning on the mask layer to form a plurality of through holes arranged at intervals in sequence, the length extension direction of the through holes being perpendicular to the arrangement direction of the plurality of through holes; performing secondary epitaxy on the primary epitaxial layer exposed by each through hole to form multiple secondary epitaxial structures; removing the remaining mask layer.

[0013] According to another aspect of an embodiment of the present invention, a method for manufacturing a field emission device is provided, which includes: sequentially forming a stacked primary epitaxial layer and an aluminum oxide layer on a substrate; patterning the aluminum oxide layer to form a plurality of vias; forming a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by the vias; forming an emitter electrode layer on the primary epitaxial layer and a dielectric layer between the emitter electrode layer and the plurality of secondary epitaxial structures; sequentially forming a stacked insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer, the plurality of secondary epitaxial structures, and the remaining aluminum oxide layer; etching the planarization layer to expose a part of the gate electrode layer on the dielectric layer and a part of the secondary epitaxial structures; etching and removing a part of the insulating layer on a part of the secondary epitaxial structures and the exposed part of the gate electrode layer to expose a part of the secondary epitaxial structures; forming a gate connection electrode layer on the exposed gate electrode layer on the dielectric layer; forming an anode opposite to the exposed part of the secondary epitaxial structures, and having a predetermined distance between the anode and the exposed part of the secondary epitaxial structures.

[0014] According to still another aspect of an embodiment of the present invention, a field emission device manufactured by the above manufacturing method is provided.

[0015] Beneficial effects: The field emission device and its manufacturing method of the present invention can provide device performance with a low turn-on voltage and high gain. Since no etching process is required when forming the primary epitaxial layer and the secondary epitaxial structures, but they are directly formed by epitaxial deposition, the on-chip uniformity of the device is improved, the production efficiency of the device is improved, and the reliability of the device is improved. Description of the Drawings

[0016] Through the following description in conjunction with the drawings, the above and other aspects, features, and advantages of the embodiments of the present invention will become clearer. In the drawings:

[0017] Figures 1A to 1H is a process chart of a method for manufacturing a field emission device according to an embodiment of the present invention;

[0018] Figures 2A to 2D is a process chart of manufacturing a secondary epitaxial structure according to an embodiment of the present invention;

[0019] Figures 2E to 2H is a process chart of manufacturing a secondary epitaxial structure according to another embodiment of the present invention;

[0020] Figure 3 is a three-dimensional schematic structural diagram of a secondary epitaxial structure according to an embodiment of the present invention;

[0021] Figure 4Schematic three-dimensional structure diagram of a secondary epitaxial structure according to another embodiment of the present invention;

[0022] Figure 5 Schematic diagram of a depletion region according to an embodiment of the present invention. Detailed implementation manners

[0023] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as limited to the specific embodiments set forth herein. On the contrary, these embodiments are provided to explain the principles of the present invention and its practical applications, so that those skilled in the art can understand various embodiments of the present invention and various modifications suitable for specific intended applications.

[0024] As used herein, the term "comprising" and its variants represent open terms, meaning "including but not limited to". Terms such as "based on", "according to" mean "at least partially based on", "at least partially according to". The term "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". Terms such as "first", "second", etc. may refer to different or the same objects. Other definitions may be included below, whether explicit or implicit. Unless explicitly specified in the context, the definition of a term is consistent throughout the specification.

[0025] Figures 1A to 1H Process chart of a method for manufacturing a field emission device according to an embodiment of the present invention.

[0026] Referring to Figure 1A , in the first manufacturing step, a stacked buffer layer 2 and a primary epitaxial layer 3 are sequentially formed on the substrate 1. In other embodiments, the buffer layer 2 can be omitted, and thus the primary epitaxial layer 3 can be directly formed on the substrate.

[0027] Here, the buffer layer 2 can be formed of GaN or AlGaN, etc., and the primary epitaxial layer 3 can be formed of unintentionally doped GaN (U-GaN), etc.

[0028] Referring to Figure 1B , in the second manufacturing step, a plurality of secondary epitaxial structures 5 are formed on the primary epitaxial layer 3, and there is a gap between adjacent secondary epitaxial structures 5.

[0029] Here, the secondary epitaxial structure 5 can be formed of GaN or AlGaN, etc. Further, the secondary epitaxial structure 5 can be N-type doped. In this embodiment, for the specific formation process of the secondary epitaxial structure 5, please refer to Figures 2A to 2D , and the following detailed description.

[0030] Figures 2A to 2D 1 is a process diagram for forming a secondary epitaxial structure according to an embodiment of the present invention.

[0031] First, refer to Figure 2A A mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silicon dioxide (SiO2) or the like.

[0032] Secondly, refer to Figure 2B , the mask layer 4 is patterned to form a plurality of via holes 41 arranged in an array in the mask layer 4. It should be noted that the via holes 41 expose the corresponding portion of the primary epitaxial layer 3 thereunder. Figure 2B The upper figure in the figure is a side view of the patterned mask layer 4, and the lower left figure and the lower right figure are top views of the patterned mask layer 4 with two different patterns.

[0033] Next, refer to Figure 2C , performing secondary epitaxy on the primary epitaxial layer 3 exposed by each of the via holes 41 to form a plurality of secondary epitaxial structures 5 .

[0034] Finally, reference Figure 2D , and remove the remaining mask layer 4.

[0035] Depend on Figures 2A to 2D The multiple secondary epitaxial structures 5 formed by the process are arranged in an array, and the secondary epitaxial structures 5 are secondary epitaxial bumps, and the secondary epitaxial bumps are in the shape of a round pyramid or a quadrangular pyramid (refer to Figure 3 In this case, the angle between the side surface of the secondary epitaxial structure 5 and the plane where the primary epitaxial layer 3 is located may be, for example, between 58° and 60°.

[0036] Figures 2E to 2H is a process diagram for forming a secondary epitaxial structure according to another embodiment of the present invention.

[0037] First, refer to Figure 2E A mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silicon dioxide (SiO2) or the like.

[0038] Secondly, refer to Figure 2F , the mask layer 4 is patterned to form a plurality of via holes 42 arranged in sequence in the mask layer 4, wherein the length extension direction of the via holes 42 is perpendicular to the arrangement direction of the plurality of via holes 42. It should be noted that the via holes 42 expose the corresponding portion of the primary epitaxial layer 3 thereunder. Figure 2F The left figure in the figure is a side view of the patterned mask layer 4, and the right figure is a top view of the patterned mask layer 4.

[0039] Next, refer toFigure 2G , secondary epitaxy is performed on the primary epitaxial layer 3 exposed in each of the vias 41 to form a plurality of secondary epitaxial structures 5'.

[0040] Finally, referring to Figure 2H , the remaining mask layer 4 is removed.

[0041] By Figures 2E to 2H The plurality of secondary epitaxial structures 5' formed by the manufacturing process are arranged at intervals in sequence. The secondary epitaxial structure 5' is a secondary epitaxial ridge, and the length extension direction of the secondary epitaxial ridge is perpendicular to the arrangement direction of the plurality of secondary epitaxial ridges (refer to Figure 4 shown). Further, the cross-sectional shape of the secondary epitaxial ridge is an isosceles trapezoid.

[0042] Note that it should be noted that when the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), Figure 2D and Figure 2H The steps can be deleted. That is to say, the remaining mask layer 4 can exist, and its specific function will be described below.

[0043] After the completion of manufacturing step two and before the start of manufacturing step three, the manufacturing method according to an embodiment of the present invention may further include: forming a depletion layer 14 on the top surface and side surfaces of the secondary epitaxial structure 5 to form a depletion region between the side surfaces and the depletion layer 14, see Figure 5 shown. Since the depletion layer 14 can be epitaxial p-GaN, which is relatively thin, and the epitaxial rate of the inclined side surface is much greater than the epitaxial rate of the top surface, the thickness of the p-GaN on the top surface can be ignored, and its impact on the performance of the device is very small. In this way, a depletion region can be obtained on the side surface, further reducing the actual size of the top surface, and the depletion region formed on the side surface can greatly reduce the leakage current of the device.

[0044] In this embodiment, the size of the top surface (the width from left to right in the plane of the paper) can be less than 50 nm.

[0045] Referring to Figure 1C , in manufacturing step three, an emitter electrode layer 6 and a dielectric layer 7 located between the emitter electrode layer 6 and the plurality of secondary epitaxial structures 5 are formed on the primary epitaxial layer 3.

[0046] Here, the emitter electrode layer 6 can be composed of a Ti / Al / Ni / Au multi-layer metal layer, and the dielectric layer 7 can be composed of an aluminum layer and a silicon dioxide layer stacked on the aluminum layer.

[0047] Referring to Figure 1D, in the fourth manufacturing step, a stacked protective layer 8, insulating layer 9, gate electrode layer 10, and planarization layer 11 are sequentially formed on the dielectric layer 7 and the plurality of secondary epitaxial structures 5.

[0048] Here, the protective layer 8 can be formed of aluminum oxide. The insulating layer 9 and the planarization layer 11 can be formed of tetraethyl orthosilicate (TEOS). The gate electrode layer 10 can be formed of metal chromium (Cr).

[0049] In another embodiment according to the present invention, as described above, when the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), the protective layer 8 can be omitted. In this case, in the fourth manufacturing step, a stacked insulating layer 9, gate electrode layer 10, and planarization layer 11 are sequentially formed on the dielectric layer 7, the plurality of secondary epitaxial structures 5, and the remaining aluminum oxide layer 4.

[0050] Refer to Figure 1E , in the fifth manufacturing step, the planarization layer 11 is etched to expose a part of the gate electrode layer 10 on the dielectric layer 7 and a part of the secondary epitaxial structures 5.

[0051] Refer to Figure 1F , in the sixth manufacturing step, a part of the protective layer 8, insulating layer 9, and the exposed part of the gate electrode layer 10 on the part of the secondary epitaxial structures 5 are etched and removed to expose a part of the secondary epitaxial structures 5.

[0052] Here, in another embodiment according to the present invention, as described above, when the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), the protective layer 8 can be omitted. In this case, in the sixth manufacturing step, a part of the insulating layer 9 and the exposed part of the gate electrode layer 10 on the part of the secondary epitaxial structures 5 are etched and removed to expose a part of the secondary epitaxial structures 5.

[0053] Refer to Figure 1G , in the seventh manufacturing step, a gate connection electrode layer 12 is formed on the exposed gate electrode layer 10 on the dielectric layer 7.

[0054] Here, the gate connection electrode layer 12 can be composed of a Ni / Au multi-layer metal layer.

[0055] Refer to Figure 1H , in the eighth manufacturing step, an anode 13 is formed opposite to the exposed part of the secondary epitaxial structures 5, and there is a predetermined distance between the anode 13 and the exposed part of the secondary epitaxial structures 5. In one example, the predetermined distance d AE is 1 - 10 mm.

[0056] It should be noted that althoughFigure 1H The middle anode 13 is suspended, but in the actual process, the anode 13 is supported by a support member. For example, when encapsulating, the anode 13 can be formed on the inner wall of the encapsulation that is placed opposite to the component connecting the substrate 1 to the gate electrode layer 12, so as to realize the opposition between the anode 13 and the secondary epitaxial structure 5.

[0057] According to another embodiment of the present invention, a field emission device formed by the above manufacturing method is also provided.

[0058] In summary, for the field emission device and its manufacturing method according to the embodiments of the present invention, it can provide device performances of low turn-on voltage and high gain. Since no etching process is required when forming the primary epitaxial layer and the secondary epitaxial structure, but they are directly formed by the way of epitaxial deposition, the on-chip uniformity of the device is improved, the production efficiency of the device is improved, and the reliability of the device is improved.

[0059] The above describes specific embodiments of the present invention. Other embodiments are within the scope of the appended claims.

[0060] The terms "exemplary", "example", etc. used throughout this specification mean "serving as an example, instance, or illustration", and do not mean "preferred" or "advantageous" compared to other embodiments. For the purpose of providing an understanding of the described technology, the specific embodiments include specific details. However, these technologies can be implemented without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid making the concepts of the described embodiments difficult to understand.

[0061] The above has described in detail the optional embodiments of the embodiments of the present invention in conjunction with the drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept scope of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention.

[0062] The above description of the content of this specification is provided to enable any ordinary person skilled in the art to implement or use the content of this specification. For ordinary persons skilled in the art, various modifications to the content of this specification are obvious, and the general principles defined herein can also be applied to other variations without departing from the protection scope of the content of this specification. Therefore, the content of this specification is not limited to the examples and designs described herein, but is consistent with the broadest scope that conforms to the principles and novel features disclosed herein.

Claims

1. A manufacturing method of a field emission device, characterized in that The manufacturing method includes: Form a primary epitaxial layer on the substrate; Form a plurality of secondary epitaxial structures on the primary epitaxial layer, with a gap between adjacent secondary epitaxial structures; Form an emitter electrode layer on the primary epitaxial layer and a dielectric layer between the emitter electrode layer and the plurality of secondary epitaxial structures; Sequentially form a stacked protective layer, insulating layer, gate electrode layer, and planarization layer on the dielectric layer and the plurality of secondary epitaxial structures; Etch the planarization layer to expose the dielectric layer and part of the gate electrode layer on part of the secondary epitaxial structures; Etch and remove the protective layer, insulating layer, and part of the exposed gate electrode layer on part of the secondary epitaxial structures to expose part of the secondary epitaxial structures; Form a gate connection electrode layer on the exposed gate electrode layer on the dielectric layer; Form an anode opposite to the exposed part of the secondary epitaxial structures, with a predetermined distance between the anode and the exposed part of the secondary epitaxial structures.

2. The manufacturing method according to claim 1, wherein The plurality of secondary epitaxial structures are arranged in an array, and the secondary epitaxial structure is a secondary epitaxial bump, and the secondary epitaxial bump is frustum-shaped or quadrangular frustum-shaped.

3. The manufacturing method according to claim 1, wherein The plurality of secondary epitaxial structures are arranged at intervals in sequence, the secondary epitaxial structure is a secondary epitaxial strip, and the length extension direction of the secondary epitaxial strip is perpendicular to the arrangement direction of the plurality of secondary epitaxial strips.

4. The manufacturing method according to claim 1, characterized in that, The predetermined distance is 1 - 10 mm.

5. The manufacturing method according to claim 1, characterized in that Before forming the emitter electrode layer on the primary epitaxial layer and the dielectric layer between the emitter electrode layer and the plurality of secondary epitaxial structures, the manufacturing method further includes: Form a depletion layer on the top surface and side surface of the secondary epitaxial structure to form a depletion region between the side surface and the depletion layer.

6. The manufacturing method according to claim 1, wherein Before forming the primary epitaxial layer on the substrate, the manufacturing method further includes: Form a buffer layer on the substrate, wherein the epitaxial layer is formed on the buffer layer.

7. The manufacturing method according to claim 1 or 2, characterized in that, The method of forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: Form a mask layer on the primary epitaxial layer; Perform patterning on the mask layer to form a plurality of vias arranged in an array in the mask layer; Perform secondary epitaxy on the primary epitaxial layer exposed by each via to form a plurality of secondary epitaxial structures; Remove the remaining mask layer.

8. The manufacturing method according to claim 1 or 3, characterized in that The method of forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: Form a mask layer on the primary epitaxial layer; Perform patterning on the mask layer to form a plurality of vias arranged at intervals in sequence in the mask layer, and the length extension direction of the via is perpendicular to the arrangement direction of the plurality of vias; Perform secondary epitaxy on the primary epitaxial layer exposed by each via to form a plurality of secondary epitaxial structures; Remove the remaining mask layer.

9. A method for manufacturing a field emission device, characterized in that The manufacturing method includes: Sequentially form a stacked primary epitaxial layer and an aluminum oxide layer on the substrate; Perform patterning on the aluminum oxide layer to form a plurality of vias; Form a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by the vias; An emitter electrode layer is formed on the primary epitaxial layer, and a dielectric layer is formed between the emitter electrode layer and the plurality of secondary epitaxial structures; A stacked insulating layer, gate electrode layer, and planarization layer are sequentially formed on the dielectric layer, the plurality of secondary epitaxial structures, and the remaining aluminum oxide layer; The planarization layer is etched to expose a part of the gate electrode layer on the dielectric layer and a part of the secondary epitaxial structures; A part of the insulating layer and a part of the exposed gate electrode layer on a part of the secondary epitaxial structures are etched away to expose a part of the secondary epitaxial structures; A gate connection electrode layer is formed on the exposed gate electrode layer on the dielectric layer; An anode is formed opposite to the exposed part of the secondary epitaxial structures, and a predetermined distance is provided between the anode and the exposed part of the secondary epitaxial structures.

10. A field emission device formed by the manufacturing method according to any one of claims 1 to 9.

Images