A method of manufacturing a transistor and a semiconductor device

Abstract

The application discloses a transistor and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a thicker gate dielectric layer and / or gate, and to reduce the integration difficulty of the two transistors. The manufacturing method of the transistor comprises the following steps: providing a semiconductor substrate; forming an active structure and an isolation layer on the semiconductor substrate; the active structure comprises a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; the adjacent two channel layers have a first gap; the isolation layer comprises at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer form a first fin structure; and a gate stack structure is formed across the first fin structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for manufacturing transistors and semiconductor devices. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when individual transistors in a semiconductor device are GMT-A, the operating performance of the semiconductor device can be improved.

[0003] However, existing semiconductor devices include gate-ring transistors with poor compatibility with other transistors having a thicker gate dielectric layer and / or gate, making it difficult to integrate the two types of transistors using existing manufacturing methods. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing transistors and semiconductor devices, which solves the problem of poor compatibility between gate-around transistors and other transistors with thicker gate dielectric layers and / or gates in semiconductor devices, and reduces the integration difficulty of the two types of transistors.

[0005] In a first aspect, the present invention provides a method for manufacturing a transistor, the method comprising:

[0006] Provide a semiconductor substrate.

[0007] An active structure and an isolation layer are formed on a semiconductor substrate. The active structure includes a source region, a drain region, and at least two channel layers located between the source and drain regions. The at least two channel layers are in contact with the source and drain regions, respectively. A first gap exists between adjacent channel layers. The isolation layer includes at least a first isolation layer. The first isolation layer at least fills the first gap. The at least two channel layers and the isolation layer constitute a first fin structure.

[0008] A grid stack structure is formed that spans across the first fin structure.

[0009] Compared with the prior art, the transistor manufacturing method provided by the present invention includes an active structure formed on a semiconductor substrate comprising at least two channel layers located between a source region and a drain region. Furthermore, a first gap is provided between adjacent channel layers. Based on this, in the case where the channel in a gate-around transistor comprises at least two nanowires or sheets, a gap is also provided between adjacent nanowires or sheets to facilitate the formation of a gate stack structure surrounding the periphery of each nanowire or sheet. Therefore, the arrangement of at least one channel layer among all the channel layers in the above-mentioned active structure between the source and drain regions is similar to the arrangement of the nanowires or sheets included in the channel between the source and drain regions in a gate-around transistor, making the transistor manufacturing method provided by the present invention compatible with the manufacturing process of gate-around transistors.

[0010] Furthermore, the transistor manufacturing method provided by this invention forms an isolation layer on a semiconductor substrate before forming the gate stack structure, and this isolation layer includes at least a first isolation layer. The first isolation layer can at least fill the first gap located between adjacent channel layers. Based on this, in practical applications, the manufacturing process of a gate-to-ring transistor can be used to form an active structure on the semiconductor substrate, and the area released by removing the sacrificial layer is filled by the aforementioned isolation layer, so that the gate stack structure manufactured after the formation of the active structure and the isolation layer only spans the first fin structure composed of at least two channel layers and an isolation layer. That is, the gate stack structure formed by the transistor manufacturing method provided by this invention is similar to the gate stack structure included in a fin field-effect transistor. In the above-described case, when a transistor with a thicker gate dielectric layer and / or gate is manufactured in a semiconductor device using the transistor manufacturing method provided by the present invention, the transistor manufacturing method provided by the present invention is compatible with the conventional gate-around transistor manufacturing process, and the gate stack structure formed by the transistor manufacturing method provided by the present invention does not need to be formed in the region released by removing the sacrificial layer. This solves the problem of poor compatibility between gate-around transistors and other transistors with different gate dielectric layers and / or gates in the prior art, and reduces the integration difficulty of gate-around transistors with other transistors with different absolute values ​​of threshold voltage.

[0011] In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device including the method for manufacturing a transistor provided in the first aspect and various implementations thereof.

[0012] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0014] Figure 1 This is a schematic cross-sectional view of the structure of the first and second transistors integrated in the prior art, which are gate ring transistors with gate dielectric layers and / or gates of different thicknesses.

[0015] Figure 2 A flowchart illustrating a transistor manufacturing method provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the first structure after the fin-like structure is formed in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the second structure after the fin-like structure is formed in an embodiment of the present invention;

[0018] Figure 5 This is a schematic cross-sectional view of the structure after the sacrificial gate and sidewall are formed along the length of the fin-like structure in an embodiment of the present invention;

[0019] Figure 6 Parts (1) and (2) in the present invention are schematic cross-sectional views of the two structures along the length of the channel layer after removing the portion of the fin-shaped structure exposed outside the sacrificial gate and sidewall in the embodiment of the present invention;

[0020] Figure 7 Part (1) is a schematic diagram of the cross-section of the structure after selectively etching the two edge regions of the sacrificial layer along the length direction of the fin in an embodiment of the present invention; Figure 7 Part (2) is a schematic cross-sectional view of the structure after the sacrificial layer is completely removed along the length direction of the fin in an embodiment of the present invention;

[0021] Figure 8 Part (1) is a schematic diagram of the cross-section of the structure after the first isolation section is formed along the length direction of the fin; Figure 8 Part (2) is Figure 7 The cross-sectional view of the structure shown in part (2) after the formation of the first isolation layer is shown.

[0022] Figure 9 for Figure 8 The cross-sectional view of the structure shown in part (1) after the formation of the source region, drain region and dielectric layer is shown.

[0023] Figure 10 for Figure 9 The diagram shows a cross-sectional view of the structure after removing the sacrificial layer and the remaining portion after removing the sacrificial layer.

[0024] Figure 11 This is a schematic cross-sectional view of the first structure after the formation of the isolation layer in an embodiment of the present invention along the length of the channel layer;

[0025] Figure 12 This is a schematic cross-sectional view of the second structure after the formation of the isolation layer in an embodiment of the present invention along the length of the channel layer;

[0026] Figure 13 for Figure 8 The structure shown in part (2) is a cross-sectional schematic diagram of the structure along the length of the channel layer after the formation of the source region, drain region and dielectric layer and the removal of the sacrificial gate.

[0027] Figure 14Parts (1) and (2) in the present invention are cross-sectional schematic diagrams of the two structures along the length of the channel layer after obtaining the fin and forming the source region, drain region and dielectric layer in the embodiment of the present invention.

[0028] Figure 15 Parts (1) and (2) in the text are respectively Figure 14 The cross-sectional schematic diagrams of the two structures shown in parts (1) and (2) of the diagram, after removing the sacrificial gate and the sacrificial layer, are shown along the length of the channel layer.

[0029] Figure 16 Part (1) is a cross-sectional schematic diagram of the third structure after the formation of the isolation layer in the embodiment of the present invention along the length direction of the channel layer; Figure 16 Part (2) is a cross-sectional schematic diagram of the third structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0030] Figure 17 Part (1) is a cross-sectional schematic diagram of the fourth structure after the formation of the isolation layer in the embodiment of the present invention along the length direction of the channel layer; Figure 17 Part (2) is a cross-sectional schematic diagram of the fourth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0031] Figure 18 Part (1) is a cross-sectional schematic diagram of the fifth structure after the formation of the isolation layer in the embodiment of the present invention along the length direction of the channel layer; Figure 18 Part (2) is a cross-sectional schematic diagram of the fifth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0032] Figure 19 Part (1) is a cross-sectional schematic diagram of the sixth structure after the formation of the isolation layer in the embodiment of the present invention along the length direction of the channel layer; Figure 19 Part (2) is a cross-sectional schematic diagram of the sixth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0033] Figure 20 Part (1) is a cross-sectional view of the seventh structure after the isolation layer is formed in the embodiment of the present invention along the length of the channel layer and at the second isolation part; Figure 20 Part (2) is a cross-sectional view of the seventh structure after the isolation layer is formed in the embodiment of the present invention along the length of the channel layer and at the first isolation part; Figure 20 Part (3) is a cross-sectional schematic diagram of the seventh structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0034] Figure 21Part (1) is a cross-sectional view of the eighth structure after the isolation layer is formed in the embodiment of the present invention along the length of the channel layer and at the second isolation part; Figure 21 Part (2) is a cross-sectional view of the eighth structure after the isolation layer is formed in the embodiment of the present invention along the length of the channel layer and at the first isolation part; Figure 21 Part (3) is a cross-sectional schematic diagram of the eighth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0035] Figure 22 Part (1) is a cross-sectional schematic diagram of the ninth structure after the formation of the isolation layer in the embodiment of the present invention along the length direction of the channel layer; Figure 22 Part (2) is a cross-sectional schematic diagram of the ninth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0036] Figure 23 Part (1) is a cross-sectional schematic diagram of the tenth structure after the formation of the isolation layer in the embodiment of the present invention along the length of the channel layer; Figure 23 Part (2) is a cross-sectional schematic diagram of the tenth structure after the formation of the isolation layer in the embodiment of the present invention along the width direction of the channel layer;

[0037] Figure 24 Part (1) is a cross-sectional schematic diagram of the first structure after the formation of the gate stack structure in the embodiment of the present invention along the length direction of the channel layer; Figure 24 Part (2) is a cross-sectional schematic diagram of the first structure after the formation of the gate stack structure in the embodiment of the present invention along the width direction of the channel layer;

[0038] Figure 25 Part (1) is a cross-sectional schematic diagram of the second structure after the formation of the gate stack structure in the embodiment of the present invention along the length direction of the channel layer; Figure 25 Part (2) is a cross-sectional schematic diagram of the second structure after the formation of the gate stack structure in the embodiment of the present invention along the width direction of the channel layer;

[0039] Figure 26 This is a schematic cross-sectional view along the width direction of the channel layer for the third structure after the formation of the gate stack structure in an embodiment of the present invention.

[0040] Reference numerals: 11 is a semiconductor substrate, 12 is a fin-like structure, 13 is a shallow trench isolation, 14 is a sacrificial gate, 15 is a sidewall, 16 is a fin, 17 is a sacrificial layer, 18 is an active structure, 181 is a source region, 182 is a drain region, 183 is a channel layer, 19 is a first gap, 20 is a second gap, 21 is an isolation layer, 211 is a first isolation layer, 2111 is a first isolation section, 2112 is a second isolation section, 2113 is a third isolation section, 212 is a second isolation layer, 2121 is a fourth isolation section, 2122 is a fifth isolation section, 22 is a dielectric layer, 23 is a gate stack structure, 231 is a gate dielectric layer, and 232 is a gate electrode. Detailed Implementation

[0041] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0042] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0043] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] Gate-around transistors (GMT-A) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when individual transistors in a semiconductor device are GMT-A, the device's performance can be improved. Furthermore, in existing semiconductor devices, the absolute values ​​of the threshold voltages of two GMT-A transistors are often achieved by using gate dielectric layers and / or gates of different thicknesses (here, for ease of description, the GMT-A transistor with a thinner gate dielectric layer and / or gate is referred to as the first GMT-A transistor, and the GMT-A transistor with a thicker gate dielectric layer and / or gate is referred to as the second GMT-A transistor). However, in the above-described case, it is difficult to manufacture the first and second GMT-A transistors using existing manufacturing methods.

[0047] Specifically, in practical applications, to improve the manufacturing efficiency and reduce the manufacturing cost of semiconductor devices, manufacturing processes with the same structural type are typically used to fabricate different transistors within the semiconductor device on the same semiconductor substrate. Based on this, in the actual manufacturing process, such as... Figure 1 As shown, when fabricating the two gate ring transistors on the same semiconductor substrate, the distance between adjacent nanowires or sheets only meets the structural requirements of the first gate ring transistor with a thinner gate dielectric layer 231 and / or gate 232. Therefore, the thicker gate dielectric layer 231 and / or gate 232 of the second gate ring transistor cannot be filled between adjacent nanowires or sheets with a small spacing. This makes it difficult for the threshold voltage of the second gate ring transistor to meet the requirements of the preset scheme, reducing the yield and operating performance of the semiconductor device.

[0048] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing transistors and semiconductor devices. The transistor manufacturing method provided by the present invention is compatible with conventional gate-around transistor manufacturing processes, and the gate stack structure manufactured by the transistor manufacturing method provided by the present invention does not need to be formed in the region freed up by removing the sacrificial layer. Therefore, when manufacturing transistors with thicker gate dielectric layers and / or gates in semiconductor devices using the transistor manufacturing method provided by the present invention, the integration difficulty of gate-around transistors with another transistor having different absolute values ​​of threshold voltages in the semiconductor device can be reduced.

[0049] like Figure 2 As shown, this embodiment of the invention provides a method for manufacturing a transistor. The following will describe a method based on... Figures 3 to 26 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this transistor includes:

[0050] First, a semiconductor substrate is provided.

[0051] Specifically, the specific structure of the aforementioned semiconductor substrate can be set according to the actual application scenario. For example, the semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. As another example, if a transistor comprising a second or higher layer is manufactured using the transistor manufacturing method provided in this embodiment of the invention, the semiconductor substrate can include a semiconductor substrate, a first-layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first-layer device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the transistor manufacturing method provided in this embodiment of the invention.

[0052] like Figures 9 to 23 As shown in sections (1) and (2), an active structure 18 and an isolation layer 21 are formed on a semiconductor substrate 11. The active structure 18 includes a source region 181, a drain region 182, and at least two channel layers 183 located between the source region 181 and the drain region 182. The at least two channel layers 183 are in contact with the source region 181 and the drain region 182, respectively. A first gap 19 is provided between adjacent channel layers 183. The isolation layer 21 includes at least a first isolation layer 211. The first isolation layer 211 at least fills the first gap 19. The at least two channel layers 183 and the isolation layer 21 constitute a first fin structure.

[0053] Specifically, the active structure described above includes a source region, a drain region, and at least two channel layers made of semiconductor materials such as silicon, germanium-silicon, germanium, or group III-V compound semiconductors. Specifically, the source and drain regions can be made of the same or different materials. When the source and drain regions are made of the same material, they can be formed simultaneously in a unified operation, simplifying the transistor manufacturing method provided in this embodiment. Furthermore, the material of the at least two channel layers can be at least the same as, or different from, the material of one of the source and drain regions. For example, the source and drain regions can be made of germanium-silicon, and the at least two channel layers can be made of germanium-silicon or silicon. Moreover, the materials of channel layers located in different layers can be the same or different. When the material of the channel layers located in different layers is the same, the difficulty of selectively etching the sacrificial layer can be reduced, which is beneficial for improving the compatibility between the transistor manufacturing method provided in this embodiment and the conventional gate-around transistor manufacturing process.

[0054] The number of channel layers included in the active structure can be set according to the actual application scenario, and no specific limit is made here. Additionally, as... Figure 15 As shown in section (1), the bottom channel layer 183 of the active structure 18 may have a second gap 20 between itself and the semiconductor substrate 11. In this case, the first isolation layer also fills the second gap 20. Alternatively, as shown in section (1), the second gap 20 may be filled between the bottom channel layer 183 and the semiconductor substrate 11. Figure 15 As shown in section (2), the bottom channel layer 183 of all the channel layers 183 included in the active structure 18 can contact the semiconductor substrate 11. At this time, the first isolation layer only fills the first gap 19. Whether the bottom channel layer of at least two channel layers contacts the semiconductor substrate can be determined according to the actual application scenario. For example, when forming a gate ring transistor on the semiconductor substrate using a conventional gate ring transistor manufacturing process, and forming a transistor on the same semiconductor substrate using the transistor manufacturing method provided in this embodiment of the invention, the bottom channel in the above-mentioned active structure has a second gap between it and the semiconductor substrate.

[0055] Specifically, the heights of the first and second gaps can be set according to the actual application scenario, and are not specifically limited here. For example, the height of the first or second gap can be from 4nm to 12nm. Furthermore, when the active structure includes at least three channel layers, the heights of the first gaps located on different layers can be equal or unequal. When the heights of the first gaps on different layers are equal, the heights of the sacrificial layers located between adjacent channel layers are also equal during the fabrication of the active structure. This prevents the time required for different sacrificial layers to be completely etched (or completely oxidized) due to height differences between them, ensuring that the channel layers on either side of the sacrificial layer requiring less time to be completely etched (or completely oxidized) are not over-processed. This improves the yield of transistors manufactured using the manufacturing method provided in this embodiment of the invention, thereby enhancing the electrical performance of transistors manufactured using the manufacturing method provided in this embodiment of the invention.

[0056] The specifications of each channel layer in the active structure can be set according to the conductivity type of the manufactured transistor and the actual application scenario, and no specific limitations are made here.

[0057] For example: Figure 24 and Figure 25 As shown in sections (1) and (2), the aspect ratio A of each channel layer 183 is in the range of 1:10 ≤ A ≤ 1:1. In this case, the height of each channel layer 183 is less than or equal to its width, making the structure of the channel layer 183 similar to the structure of nanowires or sheets included in a gate-around-the-loop transistor. Based on this, since the crystal orientation of the channel including the nanosheets is usually

[100] , and

[100] oriented channels are favorable for electron transport but unfavorable for hole transport, when the manufactured transistor is an NMOS transistor, the aspect ratio A of each channel layer 183 can be set to 1:10 ≤ A ≤ 1:1 to improve the carrier mobility of the manufactured NMOS transistor.

[0058] For example: Figure 26 As shown, the aspect ratio A of each channel layer 183 ranges from 1:1 to 10:1. In this case, the height of each channel layer 183 is greater than its width, making the structure of the channel layer 183 similar to the fin-shaped channel structure of a fin field-effect transistor. Based on this, since the crystal orientation of the fin-shaped channel in a fin field-effect transistor is usually

[110] , and

[110] oriented channels are conducive to hole transport but not to electron transport, when the manufactured transistor is a PMOS transistor, the aspect ratio A of each channel layer 183 can be set to 1:1 < A ≤ 10:1 to improve the carrier mobility of the manufactured PMOS transistor.

[0059] Furthermore, the height of trench layers located on different levels can be the same. Alternatively, at least one trench layer can have a different height from another trench layer. Specifically, the height of each trench layer can be set according to actual needs.

[0060] For the aforementioned isolation layer, the material of the isolation layer is a dielectric material. This dielectric material can be a low dielectric constant such as silicon dioxide or silicon nitride, or a high dielectric constant such as hafnium dioxide, zirconium dioxide, titanium dioxide, or aluminum oxide. Furthermore, the isolation layer can be formed from only one dielectric material, or it can be formed from at least two dielectric materials. For example, the material of the isolation layer can include one or more of silicon dioxide, silicon nitride, hafnium dioxide, zirconium dioxide, titanium dioxide, and aluminum oxide.

[0061] The specifications of the first isolation layer, which is included in the isolation layer, can be set according to actual needs. For example... Figure 17 As shown in parts (1) and (2), since the first isolation layer 211 at least fills the first gap, the height of the first isolation layer 211 located between adjacent channel layers 183 is equal to the height of the first gap of the corresponding layer. Furthermore, as... Figure 17 As shown in sections (1) and (2), when there is a second gap between the bottom channel layer 183 and the semiconductor substrate 11, the height of the bottom first isolation layer 211 is equal to the height of the second gap. For example, the height of each first isolation layer 211 can be from 4 nm to 12 nm. In this case, the thickness of each first isolation layer 211 is moderate, preventing waste of material in manufacturing the first isolation layer 211 due to its large thickness, and reducing manufacturing costs. It can also prevent the gate of the gate-ring transistor in the semiconductor device including the transistor manufactured in the embodiment of the present invention from not being completely filled due to the small thickness of the first isolation layer 211, thereby improving the yield of the semiconductor device.

[0062] Furthermore, when the isolation layer includes at least two first isolation layers, the heights of the first isolation layers located in different layers can be the same or different. The beneficial effects of having the same height for the first isolation layers in different layers can be found in the analysis of the beneficial effects of having equal heights for the first gaps in different layers described above, and will not be repeated here.

[0063] In practical applications, the formation order of the above-mentioned active structure and isolation layer can be determined based on the structure of the first isolation layer included in the isolation layer, the material of each structure of the first isolation layer, and the actual application scenario.

[0064] In one example, forming an isolation layer on a semiconductor substrate as described above includes the following steps: Figure 6As shown in portions (1) and (2) of the diagram, at least one fin 16 is formed on the semiconductor substrate 11. The fin 16 includes at least one sacrificial layer 17 and at least two channel layers 183. The sacrificial layer 17 and the channel layers 183 are alternately stacked along the thickness direction of the semiconductor substrate 11. The top layer in the fin 16 is the channel layer 183. Figure 7 Parts (1) and (2) in the text Figure 23 As shown in sections (1) and (2), each sacrificial layer 17 is subjected to a first insulation treatment to form at least a first insulating layer 211.

[0065] Specifically, the film layer located at the bottom of the aforementioned fins can be determined based on the positional relationship between the channel layer located at the bottom of the active structure and the semiconductor substrate. For example: Figure 15 As shown in section (1), in the case where a second gap 20 exists between the bottom channel layer 183 and the semiconductor substrate 11 in the active structure 18, as Figure 6 As shown in part (1), since the sacrificial layer 17 is a pre-formed film layer used to form the first gap and the second gap, the film layer located at the bottom layer in the fin 16 is the sacrificial layer 17. The thickness of each sacrificial layer 17 can be determined according to the height of the corresponding first gap or second gap. For example: Figure 15 As shown in section (2), when the channel layer 183 located at the bottom layer of the active structure 18 is in contact with the semiconductor substrate 11, as Figure 6 As shown in section (2), the bottom layer of the fin 16 is the channel layer 183. The thickness of each sacrificial layer 17 can be determined according to the height of the corresponding first gap 19. For example, the thickness of the sacrificial layer 17 can be from 4 nm to 12 nm.

[0066] Furthermore, the sacrificial layer can be made of any semiconductor material different from the channel layer. Specifically, the difference between the sacrificial layer material and the channel layer material can be determined based on the process of performing the first insulation treatment, so that the channel layer is not affected during the first insulation treatment of the sacrificial layer, or the impact on the channel layer is minimal, which helps to ensure that the manufactured transistor has stable electrical performance.

[0067] In practical applications, epitaxial growth and other processes can be used to form sacrificial material layers and channel material layers on a semiconductor substrate for fabricating sacrificial and channel layers. Then, photolithography and etching processes can be used to etch downwards from the top channel material layer down to the semiconductor substrate, forming a fin structure. The depth of etching on the semiconductor substrate is equal to the height of the subsequently formed shallow trench isolation. Then, as... Figure 3 and Figure 4As shown, a shallow trench isolation 13 is formed on the portion of the semiconductor substrate 11 exposed outside the fin structure to define the active region of the semiconductor substrate 11 and prevent leakage. Furthermore, the portion of the fin structure exposed outside the shallow trench isolation 13 is a fin-like structure 12. Along the length direction of the fin-like structure 12, the fin-like structure 12 includes a source formation region, a drain formation region, and a transition region located between the source formation region and the drain formation region. Figure 5 As shown, processes such as deposition and etching can be used to form the sacrificial gate 14 and sidewalls 15 spanning the transition region included in the fin-like structure 12. The sidewalls 15 are located at least on both sides of the sacrificial gate 14 along its length (the length direction of the sacrificial gate 14 is parallel to the length direction of the fin-like structure 12). Finally, as... Figure 6 As shown in sections (1) and (2), the portion of the fin-like structure located in the source formation region and the drain formation region can be removed by wet or dry etching processes under the masking effect of the sacrificial layer 17 and the sidewall 15, so that the portion of the fin-like structure located in the transition region forms the fin portion 16. At this time, both sides of the fin portion 16 along the length direction are exposed.

[0068] It should be noted that, in order to facilitate those skilled in the art to implement the transistor manufacturing method provided in the embodiments of the present invention, the above-described fin formation process is illustrated by taking the gate stack structure included in the transistor manufacturing process using the back gate process as an example. It does not mean that the transistor manufacturing method provided in the embodiments of the present invention can only use the back gate process to form the gate stack structure, nor does it mean that the fin can only be formed in the above manner.

[0069] Furthermore, after forming the aforementioned fins, the process used for the first insulation treatment of each sacrificial layer can be determined based on the material of the sacrificial layer and the actual application scenario, as long as a first insulating layer can be formed at least in the area where the sacrificial layer is located. Specifically, depending on the different processes used for the first insulation treatment, the formation of the insulating layer can be categorized into at least the following types:

[0070] The first method, the aforementioned first insulation treatment of each sacrificial layer, may include the following steps: such as... Figure 16 As shown in parts (1) and (2), each sacrificial layer is subjected to a first insulation treatment by an oxidation process so that each sacrificial layer forms a first isolation layer 211.

[0071] In practical applications, an oxidation process can be used to perform the first insulation treatment on each sacrificial layer after the fins are formed and before the source and drain regions are formed. Alternatively, as... Figure 16As shown in parts (1) and (2) above, each sacrificial layer can also undergo a first insulation treatment using an oxidation process after the sacrificial gate is removed and before the gate stack structure is formed. The method and conditions of the oxidation process can be determined based on the material and specifications of the sacrificial layer, and are not specifically limited here.

[0072] Additionally, during the first insulation treatment of each sacrificial layer using an oxidation process, the surface of the channel layer exposed outside the sacrificial layer may be oxidized, forming an isolation material layer on the exposed surface of the channel layer. If this isolation material layer is not formed on both sides of the channel layer along its length, and the actual application requires a large absolute threshold voltage for the transistor, the isolation material layer can be retained, forming a second isolation layer. In this case, the isolation layer consists of a first isolation layer and a second isolation layer. If the isolation material layer includes portions formed on both sides of the channel layer along its length and / or the actual application requires a small absolute threshold voltage for the transistor, the isolation material layer needs to be removed after the first insulation treatment. In this case, the first isolation layer is formed only in the region where each sacrificial layer is located. The isolation layer consists only of the first isolation layer.

[0073] Furthermore, in the first case, the material of the isolation layer includes an oxide of the sacrificial layer material. For example, if the sacrificial layer is made of silicon, the isolation layer is made of silicon oxide. When the isolation layer also includes a second isolation layer, the material of the isolation layer also includes an oxide of the channel layer material. For example, if the channel layer is made of germanium-silicon and the sacrificial layer is made of silicon, the isolation layer is made of both germanium oxide and silicon oxide.

[0074] The second method, the aforementioned first insulation treatment of each sacrificial layer may include the following steps: such as... Figure 7 Part (2) and Figure 15 As shown in sections (1) and (2), each sacrificial layer is removed. Figure 7 Parts (1) and (2) in the middle and Figure 19 As shown in sections (1) and (2), the area released by removing each sacrificial layer is filled with the first isolation layer 211.

[0075] In practical applications, such as Figure 6 As shown in parts (1) and (2), when a fin 16 is formed on a semiconductor substrate 11, and a sacrificial gate 14 and sidewall 15 span the fin 16, as Figure 7 As shown in section (2), each sacrificial layer can be removed after the fin 16 is formed and before the source and drain regions are formed. Next, a layer of insulating material is formed, filling the areas released by the removal of each sacrificial layer and covering the periphery of the formed structure, using processes such as chemical vapor deposition. Finally, as... Figure 8 As shown in part (2), the portion of the isolation material layer outside the area released by removing the sacrificial layer is removed, such that the remaining portion of the isolation material layer forms the first isolation layer 211. At this time, the isolation layer consists only of the first isolation layer 211. Furthermore, in this case, after performing a first insulation treatment on each sacrificial layer and before forming a gate stack structure spanning the first fin structure, the transistor manufacturing method further includes the following step: A source region 181 and a drain region 182 can be formed on both sides of the fin along its length using processes such as epitaxial growth, to obtain an active structure 18. For example... Figure 13 As shown, dry or wet etching processes are used to remove the sacrificial gate.

[0076] Or, such as Figure 6 As shown in parts (1) and (2), when a fin 16 is formed on a semiconductor substrate 11, and a sacrificial gate 14 and sidewall 15 span the fin 16, as Figure 14 As shown in parts (1) and (2) of the diagram, before the first insulation treatment, source region 181 and drain region 182 can be formed on both sides of the fin along its length using processes such as epitaxial growth, to obtain the active structure 18. Then, the sacrificial gate is removed using processes such as dry or wet etching. At this point, the portion of the fin covered by the sacrificial gate is exposed. Next, as... Figure 15 As shown in sections (1) and (2), the sacrificial layer can be removed using either dry or wet etching processes. Figure 16 As shown in sections (1) and (2), a layer of insulating material is formed using processes such as chemical vapor deposition, filling the area released upon removal of each sacrificial layer and covering the trench layer 183. Among these, as... Figure 16 As shown in parts (1) and (2) of the diagram, if a large absolute threshold voltage is required for the transistor in a practical application, the portion of the isolation material layer covering the channel layer 183 can be retained, forming the second isolation layer 212. In this case, the isolation layer 21 is composed of the first isolation layer 211 and the second isolation layer 212. Figure 17 As shown in parts (1) and (2) of the diagram, if the transistor requires a small absolute threshold voltage in the actual application scenario, then after the first insulation treatment, it is also necessary to remove the portion of the isolation material layer covering the outer periphery of the channel layer 183. In this case, the first isolation layer 211 will only be formed in the region where each sacrificial layer is located. The isolation layer consists only of the first isolation layer 211.

[0077] Specifically, in the second case, there needs to be a certain etching selectivity between the materials of the sacrificial layer and the channel layer to prevent the channel layer from being affected by etching and cleaning operations during the removal of the sacrificial layer. For example, the channel layer material can be Si. 1-x Ge x The sacrificial layer can be made of Si1-y Ge y Where 0≤x≤1, 0≤y≤1, |xy|≥0.2.

[0078] Furthermore, the isolation layer is formed using at least a deposition process, so a suitable isolation material can be selected to manufacture the isolation layer according to actual needs; no specific limitation is made here. For example, after removing the sacrificial gate and sacrificial layer, during the deposition of the aforementioned isolation material layer, a first material layer is first deposited around the periphery of the channel layer. The first material layer located between two adjacent channel layers fills the first gap. Then, a second material layer of a different material is deposited on the first material layer. The first material layer and the second material layer constitute the isolation material layer. At this time, as... Figure 18 and Figure 19 As shown in parts (1) and (2) of the diagram, the first isolation layer 211 includes a first isolation portion 2111 and a second isolation portion 2112. Along the height direction of the fin 16, the first isolation portion 2111 is located on both sides of the second isolation portion 2112. The material of the first isolation portion 2111 is different from the material of the second isolation portion 2112. The first isolation portion 2111 is the portion of the aforementioned first material layer located within the first gap or the second gap. The second isolation portion 2112 is the portion of the aforementioned second material layer located within the first gap or the second gap.

[0079] The third method involves using a combination of etching and oxidation processes to perform the first insulation treatment on the sacrificial layer. Specifically, the etching sequence of the sacrificial layer can be set according to the actual application scenario.

[0080] In one example, such as Figure 6 As shown in parts (1) and (2) above, when a fin 16 and a sacrificial gate 14 and a sidewall 15 are formed on the semiconductor substrate 11, the above-mentioned first insulation treatment of each sacrificial layer may include the following steps: Figure 7 As shown in part (1), along the length of the fin 16, selective etching is performed on the two side edge regions of each sacrificial layer 17 so that the sidewalls of the remaining portion of each sacrificial layer 17 are recessed inward relative to the sidewalls of the channel layer 183, forming a notch. Figure 8 As shown in (1), the notch is filled with the first isolation portion 2111. Next, the sacrificial gate is removed. As... Figure 12 As shown, the remaining portion of the sacrificial layer undergoes a second insulation treatment to fill the space between at least two first insulating portions 2111 located on the same layer with a second insulating portion 2112. The first insulating portion 2111 and the second insulating portion 2112 constitute the first insulating layer 211.

[0081] In practical applications, the aforementioned notch can be formed using an inner wall process similar to that of a conventional gate-around transistor, and the notch can be filled with a first isolation portion. The length of the first isolation portion along the length of the fin can be set according to the actual application scenario and is not specifically limited here. After removing the sacrificial gate, the remaining portion of the sacrificial layer is exposed. This remaining portion can be directly oxidized to perform a second insulation treatment, oxidizing it into a second isolation portion. Alternatively, an etching process can be used to remove the remaining portion of the sacrificial layer, and then a deposition process can be used to fill the space between the two first isolation portions located on the same layer with a second isolation portion. The materials of the first and second isolation portions can be the same or different.

[0082] Furthermore, during the aforementioned second insulation process, not only is a second isolation layer formed, but an isolation material layer is also formed on the portion of the channel layer exposed outside the first isolation layer. As mentioned earlier, if a large absolute threshold voltage is required for the transistor in a practical application, the portion of the isolation material layer covering the channel layer can be retained, forming the second isolation layer 212. In this case, the isolation layer consists of the first isolation layer 211 and the second isolation layer 212, see [reference needed]. Figure 11 If a small absolute threshold voltage is required for the transistor in a practical application, then after the first insulation treatment, the portion of the isolation material layer covering the outer periphery of the channel layer 183 needs to be removed. In this case, the first isolation layer 211 will only be formed in the region where each sacrificial layer is located. The isolation layer consists only of the first isolation layer 211, see [link to documentation]. Figure 12 .

[0083] In another example, the first insulating treatment of each sacrificial layer described above may include the following steps: selectively etching the two side edge regions of each sacrificial layer along the width direction of the fin, such that the sidewalls of the remaining portion of each sacrificial layer are recessed inward relative to the sidewalls of the channel layer, forming a notch. Next, a second insulating treatment is performed on the remaining portion of each sacrificial layer using an oxidation process, such that the remaining portion of each sacrificial layer forms a first isolation portion. A second isolation portion is formed at least within the notch. The material of the second isolation portion is different from the material of the first isolation portion. The first isolation layer includes both the first and second isolation portions.

[0084] Specifically, such as Figure 21 As shown in parts (1), (2), and (3), the second isolation portion 2112 can completely fill the notch. Alternatively, the second isolation portion may not completely fill the notch. In this case, the formation of the second isolation portion at least within the notch is as follows: Figure 23As shown in parts (1) and (2), a second isolation portion 2112 and a third isolation portion 2113 are formed at least within the notch. Along the height direction of the fin portion 16, the second isolation portion 2112 is located on both sides of the third isolation portion 2113. The material of the second isolation portion 2112 is different from the material of the first isolation portion 2111. The material of the third isolation portion 2113 is different from the material of the second isolation portion 2112.

[0085] In practical applications, the following example illustrates the formation of fins on a semiconductor substrate, along with a sacrificial gate and sidewalls spanning the fins. After forming the source and drain regions and removing the sacrificial gate, the sacrificial layer is exposed. Based on this, a dry or wet etching process can be used to selectively etch the edge regions on both sides of each sacrificial layer along the width direction of the fin, forming notches. At this point, at least a portion of the sacrificial layer remains between two adjacent channel layers. Next, an oxidation process can be used to perform a second insulating treatment on the remaining portion of the sacrificial layer, forming a first isolation portion. During the second insulating treatment, a channel oxide layer may be formed on the surface of the channel layer outside the remaining portion of the sacrificial layer. Figure 20 As shown in parts (1) to (3), if the thickness of the channel oxide layer is large, the portion of it located within the notch can fill the notch, and the portion of the channel oxide layer located within the notch is the second isolation portion 2112. If the thickness of the channel oxide layer is small, an isolation material layer is formed on the channel oxide layer using a deposition process. This isolation material layer and the portion of the channel oxide layer located within the notch together fill the notch. Wherein, as Figure 20 As shown in parts (1) to (3), if the material of the isolation material layer is the same as the material of the channel oxide layer, then the portion of the isolation material layer and the channel oxide layer located within the notch together constitute the second isolation portion 2112. Figure 22 As shown in parts (1) and (2), if the material of the isolation material layer is different from that of the channel oxide layer, the part of the channel oxide layer located in the notch is the second isolation part 2112, and the part of the isolation material layer located in the notch is the third isolation part 2113.

[0086] In this example, the first isolation layer is made of an oxide of the sacrificial layer material, and the second isolation layer is made of an oxide of the channel layer material. The third isolation layer can be made of any isolation material different from the material of the second isolation layer.

[0087] Furthermore, in this example, such as Figure 20 As shown in parts (1) to (3), during the formation of the second isolation portion 2112 within the notch, a channel material layer is also formed on the portion of the channel layer 183 exposed outside the first isolation layer 211. Or, as Figure 22As shown in sections (1) to (3), during the formation of the second isolation portion 2112 and the third isolation portion 2113 within the notch, the channel material layer and the isolation material layer are also formed on the portion of the channel layer 183 exposed outside the first isolation layer 211. As mentioned above, if a large absolute threshold voltage is required for the transistor in a practical application, the portion of the channel oxide layer (which, when including the isolation material layer, requires both the channel oxide layer and the isolation material layer) covering the channel layer 183 can be retained, and this portion forms the second isolation layer 212. In this case, the isolation layer consists of the first isolation layer 211 and the second isolation layer 212. Figure 21 Parts (1) to (3) of the text, and Figure 23 As shown in parts (1) and (2) of the diagram, if the transistor requires a small absolute threshold voltage in the actual application scenario, then after the first insulation treatment, it is also necessary to remove the portion of the channel oxide layer (and the channel oxide layer and the isolation material layer, if included) covering the outer periphery of the channel layer 183. In this case, the first isolation layer 211 is formed only in the region where each sacrificial layer is located. The isolation layer consists only of the first isolation layer 211.

[0088] As described above, when the first isolation layer and at least two channel layers constitute the second fin structure, the transistor manufacturing method further includes the step of forming an isolation material layer covering the outer periphery of the second fin structure during the first insulation treatment of the sacrificial layer. If the actual application requires the transistor to have a small absolute threshold voltage, the transistor manufacturing method further includes the step of removing the isolation material layer after the first insulation treatment of the sacrificial layer and before forming the gate stack structure spanning the first fin structure. Specifically, atomic layer etching or reactive ion etching processes can be used to remove the isolation material layer.

[0089] Alternatively, if the practical application requires the transistor to have a large absolute threshold voltage, then the sacrificial layer undergoes the first insulation treatment described above; or, as... Figure 11 , Figure 16 and Figure 18 Parts (1) and (2) Figure 20 Parts (1), (2) and (3) in the text, and Figure 22 As shown in sections (1) and (2) above, when performing the first insulating treatment on the sacrificial layer, the transistor manufacturing method further includes the step of forming a second isolation layer 212 covering the outer periphery of the second fin structure. The first isolation layer 211 and the second isolation layer 212 constitute the isolation layer 21. Specifically, the material of the second isolation layer 212 can be referred to above. For example: Figure 11 , Figure 16 Parts (1) and (2) in the text, and Figure 20As shown in sections (1) to (3), the second insulating layer 212 can be formed from only one type of insulating material. For example: Figure 18 and Figure 22 As shown in sections (1) and (2) above, the second isolation layer 212 can be formed from two materials. In this case, the second isolation layer 212 may include a fourth isolation portion 2121 covering the outer periphery of the second fin structure, and a fifth isolation portion 2122 formed on the fourth isolation portion 2121. The materials of the fourth isolation portion 2121 and the fifth isolation portion 2122 can refer to the materials of the first isolation portion 2111, the second isolation portion 2112, or the third isolation portion 2113 described above, and will not be repeated here.

[0090] In one example, such as Figure 14 and Figure 15 As shown, after forming the source region 181 and drain region 182, and before removing the sacrificial gate 14, the transistor manufacturing method may further include the step of forming a dielectric layer 22 covering the formed structure. The top of the dielectric layer 22 is flush with the top of the sacrificial gate 14. In actual manufacturing, the presence of the dielectric layer 22 can protect the source region 181 and drain region 182 from subsequent operations such as manufacturing the isolation layer 21. The dielectric layer 22 can be made of insulating materials such as silicon oxide or silicon nitride.

[0091] Finally, as Figures 24 to 26 As shown, a gate stack structure 23 is formed that spans the first fin structure.

[0092] For example, a gate stack structure spanning the first fin structure can be formed using processes such as atomic layer deposition. Figures 24 to 26 As shown, the gate stack structure 23 may include a gate dielectric layer 231 and a gate 232 located on the gate dielectric layer 231. The gate dielectric layer 231 covers the top of the first fin structure and the sidewalls of the first fin structure along its width direction. Alternatively, the gate dielectric layer 231 may also be formed on the portion of the semiconductor substrate 11 exposed to the gate formation region. The gate formation region is the region corresponding to the gate stack structure. The gate dielectric layer 231 may be made of an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The gate 232 may be made of a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0093] As can be seen from the above manufacturing process, in the transistor manufacturing method provided by the embodiments of the present invention, the active structure formed on the semiconductor substrate includes at least two channel layers located between the source region and the drain region. Furthermore, a first gap exists between adjacent channel layers. Based on this, when the channel in a gate-around transistor includes at least two nanowires or sheets, a gap is also provided between adjacent nanowires or sheets to facilitate the formation of a gate stack structure surrounding the periphery of each nanowire or sheet. Therefore, the arrangement of at least one channel layer among all the channel layers included in the above active structure between the source region and the drain region is similar to the arrangement of the nanowires or sheets included in the channel between the source region and the drain region in a gate-around transistor, making the transistor manufacturing method provided by the embodiments of the present invention compatible with the manufacturing process of gate-around transistors.

[0094] Furthermore, in the transistor manufacturing method provided in this embodiment of the invention, an isolation layer is formed on the semiconductor substrate before forming the gate stack structure, and the isolation layer includes at least a first isolation layer. The first isolation layer can at least fill the first gap located between adjacent channel layers. Based on this, in practical applications, the manufacturing process of a gate-to-ring transistor can be used to form an active structure on the semiconductor substrate, and the area released by removing the sacrificial layer is filled by the aforementioned isolation layer, so that the gate stack structure manufactured after the formation of the active structure and the isolation layer only spans the first fin structure composed of at least two channel layers and an isolation layer. That is, the gate stack structure formed by the transistor manufacturing method provided in this embodiment of the invention is similar to the gate stack structure included in a fin field-effect transistor. In the above-described case, when a transistor with a thicker gate dielectric layer and / or gate is manufactured in a semiconductor device using the transistor manufacturing method provided in the embodiments of the present invention, the transistor manufacturing method provided in the embodiments of the present invention is compatible with the conventional gate-around transistor manufacturing process, and the gate stack structure formed by the transistor manufacturing method provided in the embodiments of the present invention does not need to be formed in the region released by removing the sacrificial layer. This solves the problem of poor compatibility between gate-around transistors and other transistors with different gate dielectric layers and / or gates in the prior art, and reduces the integration difficulty of gate-around transistors with other transistors with different absolute values ​​of threshold voltage.

[0095] This invention also provides a method for manufacturing a semiconductor device, which includes the transistor manufacturing method provided in the above embodiments. Specifically, the manufactured semiconductor device can be any semiconductor device including transistors. The semiconductor device may include only one transistor or multiple transistors. When the semiconductor device includes multiple transistors, the multiple transistors may have the same conductivity type, or at least one transistor may have a conductivity type opposite to the other transistors. Furthermore, the absolute values ​​of the threshold voltages of the multiple transistors may be the same or different.

[0096] In one example, the semiconductor device described above may include a first transistor and a second transistor. The first transistor is a gate-around transistor. The second transistor is manufactured using the transistor manufacturing method provided in the above embodiments.

[0097] Specifically, the number of first and second transistors in the semiconductor device can be set according to the actual application scenario. Furthermore, the absolute values ​​of the threshold voltages of the first and second transistors can be the same or different. When the absolute values ​​of the threshold voltages of the first and second transistors are different, the transistor with the larger absolute value of its threshold voltage has a thicker gate dielectric layer and / or gate. Based on this, in the case of a transistor with a thicker gate dielectric layer and / or gate, the manufacturing method provided by this embodiment is compatible with conventional gate-around transistor manufacturing processes. Therefore, while manufacturing the first transistor using a conventional gate-around transistor manufacturing process, the manufacturing method provided by this embodiment can be used to manufacture the second transistor. Moreover, the gate stack structure formed by the manufacturing method provided by this embodiment does not need to be formed in the space freed up by removing the sacrificial layer, thereby solving the problem of poor compatibility between gate-around transistors and other transistors with different thicknesses of gate dielectric layers and / or gates in the prior art, and reducing the integration difficulty of gate-around transistors with other transistors with different absolute values ​​of threshold voltages. In the process of forming the isolation layer included in the second transistor, a corresponding mask layer can be applied to the area where the first transistor is manufactured to prevent the first transistor formed using the conventional gate-around transistor manufacturing process from being affected, thereby improving the yield of the semiconductor device.

[0098] Furthermore, the first transistor and the second transistor can have the same or opposite conductivity types. The channel layers of the first transistor and the second transistor can be made of the same or different materials. In cases where the first transistor and the second transistor have opposite conductivity types and different channel layer materials, in practical applications, the channel materials used to manufacture the channel layer of the first transistor and the channel material used to manufacture the channel layer of the second transistor can serve as sacrificial layers for each other. Based on this, if the second transistor is manufactured using the transistor manufacturing method provided in this embodiment of the invention, and the thickness of the channel layer in the second transistor is determined by the dimensions of the gate stack structure included in the first transistor, it can be ensured that both the gate stack structures of the first transistor and the second transistor meet the operating requirements, thereby improving the electrical performance of the semiconductor device.

[0099] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0100] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a transistor, characterized in that, include: Provide a semiconductor substrate; An active structure and an isolation layer are formed on the semiconductor substrate; the active structure includes a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; a first gap is formed between adjacent channel layers; the isolation layer includes at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer constitute a first fin structure; A gate stack structure is formed across the first fin structure; an interface exists between the first isolation layer and the gate stack structure; The method of forming the isolation layer on the semiconductor substrate includes: forming at least a fin on the semiconductor substrate; the fin includes at least one sacrificial layer and the at least two channel layers; the sacrificial layer and the channel layers are alternately stacked along the thickness direction of the semiconductor substrate; the top layer of the fin is the channel layer; and each sacrificial layer is subjected to a first insulating treatment to form at least the first isolation layer. The first insulation treatment of each sacrificial layer includes: selectively etching the two side edge regions of each sacrificial layer along the width direction of the fin, so that the sidewalls of the remaining portion of each sacrificial layer are recessed inward relative to the sidewalls of the channel layer to form a notch; performing a second insulation treatment on the remaining portion of each sacrificial layer using an oxidation process, so that the remaining portion of each sacrificial layer forms a first isolation portion; forming a second isolation portion at least within the notch; the material of the second isolation portion is different from the material of the first isolation portion; the first isolation layer includes the first isolation portion and the second isolation portion.

2. The method for manufacturing a transistor according to claim 1, characterized in that, The first insulation treatment of each of the sacrificial layers includes: Each of the sacrificial layers is subjected to the first insulation treatment using an oxidation process, so that each of the sacrificial layers forms the first isolation layer.

3. The method for manufacturing a transistor according to claim 1, characterized in that, The second isolation portion fills the notch; Alternatively, the formation of the second isolation portion within the notch can be described as follows: forming both the second and third isolation portions within the notch; the second isolation portion is located on both sides of the third isolation portion along the height direction of the fin; the material of the second isolation portion is different from the material of the first isolation portion, and the material of the third isolation portion is different from the material of the second isolation portion.

4. The method for manufacturing a transistor according to claim 1, characterized in that, The first insulation treatment of each of the sacrificial layers includes: Remove the sacrificial layer from each layer; The area freed up by removing each of the sacrificial layers is filled with the first isolation layer.

5. The method for manufacturing a transistor according to claim 4, characterized in that, The formation of at least one fin on the semiconductor substrate comprises: forming the fin on the semiconductor substrate, and a sacrificial gate and sidewalls spanning the fin; the sidewalls are formed at least on both sides of the sacrificial gate along its length. The method for manufacturing the transistor, after forming the fins, and the sacrificial gate and sidewalls across the fins on the semiconductor substrate, and before performing a first insulating treatment on each of the sacrificial layers, further includes: The source region and the drain region are formed on both sides of the fin along its length to obtain the active structure; Remove the sacrificial gate.

6. The method for manufacturing a transistor according to claim 5, characterized in that, The first isolation layer includes a first isolation portion and a second isolation portion; along the height direction of the fin, the first isolation portion is located on both sides of the second isolation portion; the material of the first isolation portion is different from the material of the second isolation portion.

7. The method for manufacturing a transistor according to claim 4, characterized in that, The formation of at least one fin on the semiconductor substrate comprises: forming the fin on the semiconductor substrate, and a sacrificial gate and sidewalls spanning the fin; the sidewalls are formed at least on both sides of the sacrificial gate along its length. After performing a first insulation treatment on each of the sacrificial layers, and before forming a gate stack structure spanning the first fin structure, the method for manufacturing the transistor further includes: The source region and the drain region are formed on both sides of the fin along its length to obtain the active structure; Remove the sacrificial gate.

8. The method for manufacturing a transistor according to claim 1, characterized in that, The formation of at least one fin on the semiconductor substrate comprises: forming the fin on the semiconductor substrate, and a sacrificial gate and sidewalls spanning the fin; The sidewalls are formed at least on both sides of the sacrificial gate along its length; The first insulation treatment of each of the sacrificial layers includes: Along the length of the fin, selective etching is performed on the two side edge regions of each sacrificial layer so that the sidewalls of the remaining portion of each sacrificial layer are recessed inward relative to the sidewalls of the channel layer, forming a notch; The notch is filled with the first isolation portion; Remove the sacrificial gate; The remaining portion of the sacrificial layer is subjected to a second insulation treatment to fill at least the space between two first isolation portions located in the same layer with a second isolation portion; the first isolation portion and the second isolation portion constitute the first isolation layer.

9. The method for manufacturing a transistor according to claim 8, characterized in that, The first isolation section and the second isolation section are made of different materials.

10. A method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The first isolation layer and the at least two channel layers constitute a second fin structure; When the sacrificial layer is subjected to a first insulation treatment, the method for manufacturing the transistor further includes: forming an isolation material layer covering the outer periphery of the second fin structure; After the first insulation treatment of the sacrificial layer and before forming the gate stack structure spanning the first fin structure, the method for manufacturing the transistor further includes: removing the isolation material layer.

11. A method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The first isolation layer and the at least two channel layers constitute a second fin structure; After the first insulation treatment is performed on the sacrificial layer; or, when the first insulation treatment is performed on the sacrificial layer, the method for manufacturing the transistor further includes: A second isolation layer is formed covering the outer periphery of the second fin structure; the first isolation layer and the second isolation layer constitute the isolation layer.

12. The method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The membrane layer at the bottom of the fin is the channel layer; or, The film layer at the bottom of the fin is the sacrificial layer; there is a second gap between the channel layer at the bottom and the semiconductor substrate; after the first insulation treatment, the first isolation layer fills the first gap and the second gap.

13. The method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The thickness of the sacrificial layer is 4 nm to 12 nm; and / or, The channel layer is made of Si. 1-x Ge x The sacrificial layer is made of Si. 1-y Ge y Where 0≤x≤1, 0≤y≤1, |xy|≥0.

2.

14. The method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The aspect ratio A of each channel layer is in the range of: 1:10 ≤ A ≤ 1:1; or, The aspect ratio A of each channel layer is in the range of 1:1 < A ≤ 10:

1.

15. A method for manufacturing a transistor according to any one of claims 1 to 9, characterized in that, The material of the isolation layer includes one or more of silicon dioxide, silicon nitride, hafnium dioxide, zirconium dioxide, titanium dioxide, and aluminum oxide.

16. A method for manufacturing a semiconductor device, characterized in that, Including the method of manufacturing a transistor as described in any one of claims 1 to 15.

17. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a first transistor and a second transistor; wherein... The first transistor is a gate-around transistor; The second transistor is manufactured using the transistor manufacturing method as described in any one of claims 1 to 16.

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