Display device

Abstract

The present application provides a display device, comprising: a substrate comprising a display area and a non-display area adjacent to the display area; a plurality of light emitting diodes disposed on the display area of the substrate, wherein the light emitting diodes comprise a contact electrode; and an anisotropic conductive layer disposed between the substrate and the plurality of light emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a portion of the cross-sectional sidewall profile of the anisotropic conductive layer has a curved shape.

Description

[0001] This case is a divisional application of Chinese patent application number "201710551955.X", filed on July 7, 2017. Technical Field

[0002] This invention relates to a display device, and more particularly to a micro-light-emitting diode display and a bonding method thereof. Background Technology

[0003] In the manufacturing process of micro-LED displays, there are some issues that must be considered, such as bonding capability and electrostatic discharge.

[0004] Therefore, the development of a display device that can effectively fix light-emitting diodes and reduce electrostatic discharge is highly anticipated. Summary of the Invention

[0005] An embodiment of the present invention provides a display device, comprising: a substrate including a display area and a non-display area, the non-display area being adjacent to the display area; a plurality of light-emitting diodes disposed on the display area of ​​the substrate, wherein the light-emitting diodes include contact electrodes; and an anisotropic conductive layer disposed between the substrate and the light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a portion of the cross-sectional sidewall profile of the anisotropic conductive layer is curved.

[0006] An embodiment of the present invention provides a display device, comprising: a substrate including a display area and a non-display area, the non-display area being adjacent to the display area; a plurality of bonding pads disposed on the substrate; a plurality of light-emitting diodes disposed on the display area of ​​the substrate and corresponding to the bonding pads, wherein the light-emitting diodes include contact electrodes; and a plurality of bumps disposed between the bonding pads and the contact electrodes of the light-emitting diodes, wherein the projected area of ​​the bumps is larger than the projected area of ​​the bonding pads.

[0007] An embodiment of the present invention provides a display device, comprising: a substrate including a display area and a non-display area, the non-display area being adjacent to the display area; a plurality of light-emitting diodes disposed on the display area of ​​the substrate; and a connection structure disposed on the non-display area and / or the display area of ​​the substrate, wherein the connection structure includes a first electrode, at least a portion of the cross-sectional profile of the electrode being curved.

[0008] An embodiment of the present invention provides a display device, comprising: a substrate including a display area; a plurality of bonding pads disposed on the substrate; a plurality of light-emitting diodes disposed on the display area of ​​the substrate, wherein the light-emitting diodes include electrodes; a plurality of conductive elements disposed between the plurality of bonding pads and the plurality of electrodes of the plurality of light-emitting diodes; and a black matrix disposed on the substrate, wherein, in a cross-sectional direction, the black matrix is ​​located between two adjacent of the plurality of bonding pads. Attached Figure Description

[0009] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0010] Figure 1 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0011] Figure 2 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0012] Figure 3A-3J This is a cross-sectional schematic diagram of a method for manufacturing a display device according to an embodiment of the present invention;

[0013] Figure 4 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0014] Figures 5A-5D This is a cross-sectional schematic diagram of a method for manufacturing a display device according to an embodiment of the present invention;

[0015] Figure 6 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0016] Figures 7A-7D This is a cross-sectional schematic diagram of a method for manufacturing a display device according to an embodiment of the present invention;

[0017] Figure 8A This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0018] Figure 8B This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0019] Figure 9 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0020] Figure 10 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0021] Figure 11 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0022] Figure 12 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0023] Figure 13 This is a schematic diagram of the outline of a conductive particle according to an embodiment of the present invention;

[0024] Figure 14 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0025] Figures 15A-15H This is a cross-sectional schematic diagram of a method for manufacturing a display device according to an embodiment of the present invention;

[0026] Figure 16 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0027] Figures 17A-17E This is a cross-sectional schematic diagram of a method for manufacturing a display device according to an embodiment of the present invention;

[0028] Figure 18A This is a cross-sectional schematic diagram of a light-emitting diode according to an embodiment of the present invention;

[0029] Figure 18B This is a cross-sectional schematic diagram of a connection structure according to an embodiment of the present invention;

[0030] Figure 19A This is a cross-sectional schematic diagram of a light-emitting diode according to an embodiment of the present invention;

[0031] Figure 19B This is a cross-sectional schematic diagram of a connection structure according to an embodiment of the present invention;

[0032] Figure 20 This is a cross-sectional schematic diagram of a light-emitting diode according to an embodiment of the present invention;

[0033] Figure 21 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0034] Figure 22 This is a top view of a mating pad and a protrusion according to an embodiment of the present invention;

[0035] Figure 23 This is a cross-sectional schematic diagram of a partial display device according to an embodiment of the present invention;

[0036] Figure 24This is a top view of a mating pad and a protrusion according to an embodiment of the present invention; and

[0037] Figure 25 This is a top view of a wafer substrate according to an embodiment of the present invention.

[0038] Explanation of component labels in the diagram:

[0039] 10. Display devices;

[0040] 11. Wafer substrate;

[0041] 12 substrate;

[0042] 12' Thin Film Transistor (TFT) Substrate;

[0043] 13 Undoped gallium nitride layer;

[0044] 14. B. Light-emitting diode;

[0045] 15, 15' (patterned) N-type semiconductor layer;

[0046] 16. Anisotropic conductive layer;

[0047] 16' Separated portion of the anisotropic conductive layer;

[0048] 17 (patterned) P-type semiconductor layer;

[0049] 18 substrate surface;

[0050] 19, 19' lower electrode;

[0051] 20 display areas;

[0052] 21, 21' Insulation layer;

[0053] 22 Non-display area;

[0054] 23. Array layer;

[0055] 24. Bottom of the LED;

[0056] 26, 26' Upper electrode (contact electrode);

[0057] 28. Sectional sidewall profile;

[0058] 30 Joint pads;

[0059] 32. Conductive particles;

[0060] 34. Phosphor layer;

[0061] 36, 38 Black Matrix;

[0062] 40. Protrusions on the surface of conductive particles;

[0063] 42' and 42' bumps;

[0064] 44. A. Connection structure;

[0065] 46. ​​The central region of the wafer substrate;

[0066] 48. Peripheral area of ​​the wafer substrate;

[0067] Edges of components 50, 52, 54, 56, and 58;

[0068] A1 is the projected area of ​​the bump;

[0069] A2 Projected area of ​​the bonding pad;

[0070] d1 is the inner diameter of the pressure-bearing conductive particles;

[0071] d2 is the inner diameter of the uncompressed conductive particle;

[0072] D1 is the distance between the substrate surface and the bottom of the light-emitting diode;

[0073] D2 Distance between the substrate surface and the upper electrode (contact electrode);

[0074] G is the gap between the anisotropic conductive layer and the bottom of the light-emitting diode;

[0075] h1 is the thickness of the patterned N-type semiconductor layer located in the central region;

[0076] h2 is the thickness of the patterned N-type semiconductor layer located in the peripheral region;

[0077] H and H1 are the maximum heights of the anisotropic conductive layers.

[0078] H2 is the height of the black matrix;

[0079] He refers to the thickness of the lower electrode;

[0080] Hn1 and Hn2 are the thicknesses of the patterned N-type semiconductor layers;

[0081] Hp is the thickness of the patterned P-type semiconductor layer;

[0082] 1 / 2H is half the height of the anisotropic conductive layer;

[0083] L1 is the width of the bump;

[0084] L2 is the width of the bonding pad;

[0085] W1 is the maximum width of the separated portion of the anisotropic conductive layer.

[0086] The maximum width of the upper electrode (contact electrode) of W2;

[0087] θ is the angle between the substrate surface and the profile of the anisotropic conductive layer. Detailed Implementation

[0088] The following describes the manufacture and use of embodiments of the present invention. However, it will be readily apparent that the embodiments of the present invention provide many suitable inventive concepts and can be implemented in a wide range of specific contexts. The specific embodiments disclosed are merely illustrative of making and using the present invention in particular ways and are not intended to limit the scope of the present invention. Furthermore, the same reference numerals are used in the accompanying drawings and descriptions of the embodiments of the present invention to denote the same or similar components.

[0089] Please see Figure 1 According to an embodiment of the present invention, a display device 10 is provided. Figure 1 This is a cross-sectional view of the display device 10 in this embodiment. The cross-sectional view can be obtained by a section line, and the position where the section line is cut off corresponds to a plurality of light-emitting diodes formed on the substrate.

[0090] like Figure 1 As shown, the display device 10 includes a substrate 12, a plurality of light-emitting diodes (LEDs) 14, and an anisotropic conductive layer 16. The substrate 12 includes a display area 20 and a non-display area (not shown), with the non-display area adjacent to the display area 20. The LEDs 14 are disposed on the display area 20 of the substrate 12. The LEDs 14 include an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and a contact electrode 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19, and the contact electrode 26 is formed on the insulating layer 21 and contacts the P-type semiconductor layer 17. An array layer 23 is further disposed between the anisotropic conductive layer 16 and the substrate 12. The array layer 23 includes a driving circuit to drive the LEDs 14 thereon. The driving circuit can be a passive driving circuit or an active driving circuit. An anisotropic conductive layer 16 is disposed on the substrate 12 and surrounds the light-emitting diode (LED) 14. Notably, the anisotropic conductive layer 16 has a cross-sectional sidewall profile 28, and at least a portion of the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 is curved. In this invention, "formed on" includes both directly and indirectly on.

[0091] In some embodiments, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 may be less than 90 degrees, such as... Figure 1 As shown. In some embodiments, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 may be greater than or equal to 30 degrees. The range of the cross-sectional sidewall profile 28 is defined from the position in contact with the insulating layer 21 to the position in contact with the array layer 23. Furthermore, the angle θ is defined as the angle between any tangent formed by the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 from bottom to top, for example, as... Figure 1 As shown, the angle θ between the surface 18 of the substrate 12 and the tangent at half height (1 / 2H) of the profile sidewall 28 can be between 30 degrees and 90 degrees.

[0092] In this embodiment, the anisotropic conductive layer 16 is a continuous state.

[0093] In some embodiments, the display device 10 may further include a plurality of bonding pads 30 disposed on the substrate 12 and corresponding to light-emitting diodes (LEDs) 14.

[0094] In some embodiments, the anisotropic conductive layer 16 may include a plurality of conductive particles 32 located between the contact electrode 26 of the light-emitting diode (LED) 14 and the bonding pad 30.

[0095] In some embodiments, the display device 10 may further include a patterned phosphor layer 34 and a plurality of black matrices 36 disposed in the patterned phosphor layer 34. This structure is disposed on a light-emitting diode (LED) 14. In another embodiment, the patterned phosphor layer 34 may also be replaced by a patterned quantum dot layer.

[0096] In some embodiments, depending on the optical requirements of different light-emitting diodes (LEDs) 14, a patterned phosphor layer 34 with varying thickness can be selected to correspond to different light-emitting diodes (LEDs) 14.

[0097] In this embodiment, a gap G exists between the bottom 24 of the light-emitting diode (LED) 14 and the anisotropic conductive layer 16. When the gap G exists, the amount of anisotropic conductive layer 16 can be reduced, thereby lowering the cost.

[0098] In some embodiments, by appropriately increasing the amount of the anisotropic conductive layer 16, a display device 10 without gaps between the bottom 24 of the light-emitting diode (LED) 14 and the anisotropic conductive layer 16 can be obtained (that is, the anisotropic conductive layer 16 fills the space between the bottom 24 of the light-emitting diode (LED) 14 and the substrate 12), such as Figure 2 As shown.

[0099] Please see Figure 3A-3J According to an embodiment of the present invention, a method for manufacturing a display device 10 is provided. Figure 3A-3J This is a cross-sectional schematic diagram of the manufacturing method of the display device 10 in this embodiment.

[0100] like Figure 3A As shown, a wafer substrate 11 is provided, on which an undoped gallium nitride layer 13, an N-type semiconductor layer 15, and a P-type semiconductor layer 17 are sequentially formed. The undoped gallium nitride layer 13 is formed on the wafer substrate 11, the N-type semiconductor layer 15 is formed on the undoped gallium nitride layer 13, and the P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15. In some embodiments, multiple quantum wells (not shown) are further formed between the N-type semiconductor layer 15 and the P-type semiconductor layer 17.

[0101] like Figure 3B As shown, the P-type semiconductor layer 17 and the N-type semiconductor layer 15 are then etched to form a stack of patterned N-type semiconductor layer 15 and patterned P-type semiconductor layer 17.

[0102] like Figure 3C As shown, a lower electrode 19 is then formed on a portion of the patterned N-type semiconductor layer 15.

[0103] like Figure 3D As shown, an insulating layer 21 is then formed on the patterned N-type semiconductor layer 15, a portion of the patterned P-type semiconductor layer 17, and the lower electrode 19.

[0104] like Figure 3E As shown, an upper electrode (contact electrode) 26 is then formed on the insulating layer 21 and contacts the patterned P-type semiconductor layer 17. This completes the fabrication of the wafer substrate 11 on which multiple light-emitting diodes (LEDs) 14 are formed.

[0105] like Figure 3F As shown, a wafer substrate 11 is inverted. A thin-film transistor (TFT) substrate 12' is provided, on which a plurality of bonding pads 30 and an anisotropic conductive layer 16 are formed. The TFT substrate 12' includes a substrate and an array layer formed thereon. The bonding pads 30 are formed on the TFT substrate 12', and the anisotropic conductive layer 16 covers the bonding pads 30 and a portion of the TFT substrate 12'.

[0106] like Figure 3G As shown, the wafer substrate 11 is bonded to the thin film transistor (TFT) substrate 12'.

[0107] After that, as Figure 3HAs shown, remove wafer substrate 11.

[0108] After that, as Figure 3I As shown, the undoped gallium nitride layer 13 is removed.

[0109] like Figure 3J As shown, the fabrication of the display device 10 is completed after a patterned phosphor layer 34 is formed on the light-emitting diode (LED) 14. The patterned phosphor layer 34 has a plurality of black matrices 36 located therein.

[0110] Please see Figure 4 According to an embodiment of the present invention, a display device 10 is provided. Figure 4 This is a cross-sectional view of the display device 10 in this embodiment.

[0111] like Figure 4 As shown, the display device 10 includes a substrate 12, a plurality of light-emitting diodes (LEDs) 14, and an anisotropic conductive layer 16. The substrate 12 includes a display area 20 and a non-display area (not shown), with the non-display area adjacent to the display area 20. The LEDs 14 are disposed on the display area 20 of the substrate 12. The LEDs 14 include an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and a contact electrode 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19, and the contact electrode 26 is formed on the insulating layer 21 and contacts the P-type semiconductor layer 17. An array layer 23 is further disposed between the anisotropic conductive layer 16 and the substrate 12. An anisotropic conductive layer 16 is disposed on the substrate 12 and surrounds the light-emitting diode (LED) 14.

[0112] In this embodiment, the anisotropic conductive layer 16 includes a plurality of separation portions 16'. Each separation portion 16' surrounds a light-emitting diode (LED) 14. A plurality of black matrices 38 are disposed on the substrate 12 and located between the separation portions 16' of the anisotropic conductive layer 16 to avoid light mixing between adjacent light-emitting diodes (LEDs) 14.

[0113] In some embodiments, the display device 10 may further include a plurality of bonding pads 30 disposed on the substrate 12 and corresponding to light-emitting diodes (LEDs) 14.

[0114] In some embodiments, the anisotropic conductive layer 16 may include a plurality of conductive particles 32 located between the contact electrode 26 of the light-emitting diode (LED) 14 and the bonding pad 30.

[0115] In some embodiments, the display device 10 may further include a patterned phosphor layer 34 and a plurality of black matrices 36 disposed in the patterned phosphor layer 34. The above structure is disposed on a light-emitting diode (LED) 14.

[0116] Please see Figures 5A-5D According to an embodiment of the present invention, a method for manufacturing a display device 10 is provided. Figures 5A-5D This is a cross-sectional schematic diagram of the manufacturing method of the display device 10 in this embodiment.

[0117] For details on the fabrication of the wafer substrate 11 on which multiple light-emitting diodes (LEDs) 14 are formed, please refer to [link to relevant documentation]. Figures 3A-3E .

[0118] like Figure 5A As shown, a wafer substrate 11 is inverted. A thin-film transistor (TFT) substrate 12' is provided on which a plurality of bonding pads 30, an anisotropic conductive layer 16 (divided into a plurality of separated portions 16'), and a plurality of black matrices 38 are formed. The bonding pads 30 are formed on the TFT substrate 12', the anisotropic conductive layer 16 covers the bonding pads 30 and a portion of the TFT substrate 12', and the black matrices 38 are formed on the TFT substrate 12' and located between the separated portions 16' of the anisotropic conductive layer 16.

[0119] like Figure 5B As shown, the wafer substrate 11 is bonded to the thin-film transistor (TFT) substrate 12'. Then, the wafer substrate 11 is removed.

[0120] like Figure 5C As shown, the undoped gallium nitride layer 13 is removed.

[0121] like Figure 5D As shown, the fabrication of the display device 10 is completed after a patterned phosphor layer 34 is formed on the light-emitting diode (LED) 14. The patterned phosphor layer 34 has a plurality of black matrices 36 located therein.

[0122] Please see Figure 6 According to an embodiment of the present invention, a display device 10 is provided. Figure 6 This is a cross-sectional view of the display device 10 in this embodiment.

[0123] like Figure 6As shown, the display device 10 includes a substrate 12, a plurality of light-emitting diodes (LEDs) 14, and an anisotropic conductive layer 16. The substrate 12 includes a display area 20 and a non-display area (not shown), with the non-display area adjacent to the display area 20. The LEDs 14 are disposed on the display area 20 of the substrate 12. The LEDs 14 include an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and a contact electrode 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19, and the contact electrode 26 is formed on the insulating layer 21 and contacts the P-type semiconductor layer 17. An array layer 23 is further disposed between the anisotropic conductive layer 16 and the substrate 12. Furthermore, an anisotropic conductive layer 16 is disposed on the substrate 12 and surrounds the light-emitting diode (LED) 14. Notably, the anisotropic conductive layer 16 has a cross-sectional sidewall profile 28, and at least a portion of the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 is curved.

[0124] In some embodiments, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 may be less than 90 degrees, such as... Figure 6 As shown. In some embodiments, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 may be greater than or equal to 30 degrees.

[0125] In this embodiment, the anisotropic conductive layer 16 includes a plurality of separated portions 16'. Each separated portion 16' surrounds a light-emitting diode (LED) 14. Notably, the anisotropic conductive layer 16 (with separated portions 16') is black. The black anisotropic conductive layer 16 prevents light mixing between adjacent light-emitting diodes (LEDs) 14.

[0126] In some embodiments, the display device 10 may further include a plurality of bonding pads 30 disposed on the substrate 12 and corresponding to light-emitting diodes (LEDs) 14.

[0127] In some embodiments, the anisotropic conductive layer 16 may include a plurality of conductive particles 32 located between the contact electrode 26 of the light-emitting diode (LED) 14 and the bonding pad 30.

[0128] In some embodiments, the display device 10 may further include a patterned phosphor layer 34 and a plurality of black matrices 36 disposed in the patterned phosphor layer 34. The above structure is disposed on a light-emitting diode (LED) 14.

[0129] Please see Figures 7A-7D According to an embodiment of the present invention, a method for manufacturing a display device 10 is provided. Figures 7A-7D This is a cross-sectional schematic diagram of the manufacturing method of the display device 10 in this embodiment.

[0130] For details on the fabrication of the wafer substrate 11 on which multiple light-emitting diodes (LEDs) 14 are formed, please refer to [link to relevant documentation]. Figures 3A-3E .

[0131] like Figure 7A As shown, a wafer substrate 11 is inverted. A thin-film transistor (TFT) substrate 12' is provided on which a plurality of bonding pads 30 and an anisotropic conductive layer 16 (divided into a plurality of separate portions 16') are formed. The bonding pads 30 are formed on the thin-film transistor (TFT) substrate 12', and the anisotropic conductive layer 16 covers the bonding pads 30 and a portion of the thin-film transistor (TFT) substrate 12'.

[0132] like Figure 7B As shown, the wafer substrate 11 is bonded to the thin-film transistor (TFT) substrate 12'. Then, the wafer substrate 11 is removed.

[0133] like Figure 7C As shown, the undoped gallium nitride layer 13 is removed.

[0134] like Figure 7D As shown, the fabrication of the display device 10 is completed after a patterned phosphor layer 34 is formed on the light-emitting diode (LED) 14. The patterned phosphor layer 34 has a plurality of black matrices 36 located therein.

[0135] In some embodiments, a suitable cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 is provided, such as... Figure 8A and 8B As shown. Figure 8A and 8B This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment. Figure 8A In the middle, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 is approximately 30 degrees. Figure 8B In this case, the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 is approximately 90 degrees. Therefore, it can be concluded that the bonding between the wafer substrate 11 and the thin-film transistor (TFT) substrate 12' is successful when the angle θ between the surface 18 of the substrate 12 and the cross-sectional sidewall profile 28 of the anisotropic conductive layer 16 falls within the range of greater than or equal to 30 degrees and less than 90 degrees.

[0136] In some embodiments, appropriate dimensional relationships are provided between the distance D1 between the surface 18 of the substrate 12 and the bottom 24 of the light-emitting diode (LED) 14, the maximum height H1 of the continuous portion of the anisotropic conductive layer 16, and the distance D2 between the surface 18 of the substrate 12 and the contact electrode 26 of the light-emitting diode (LED) 14, such as... Figure 9 As shown. Figure 9 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment. Figure 9 In this process, the distance D1 between the surface 18 of the substrate 12 and the bottom 24 of the light-emitting diode (LED) 14 is greater than the maximum height H1 of the continuous portion of the anisotropic conductive layer 16, and the maximum height H1 of the continuous portion of the anisotropic conductive layer 16 is greater than the distance D2 between the surface 18 of the substrate 12 and the contact electrode 26 of the light-emitting diode (LED) 14, so as to ensure that the light-emitting diode (LED) 14 can still be firmly fixed with a small amount of anisotropic conductive layer 16.

[0137] In some embodiments, a suitable dimensional relationship is provided between the maximum width W1 of the separation portion 16' of the anisotropic conductive layer 16 and the maximum width W2 of the contact electrode 26 of the light-emitting diode (LED) 14, such as... Figure 10 As shown. Figure 10 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment. Figure 10 In this process, the maximum width W1 of the separation portion 16' of the anisotropic conductive layer 16 is greater than the maximum width W2 of the contact electrode 26 of the light-emitting diode (LED) 14, so as to ensure good bonding yield while providing sufficient maximum width W1 of the separation portion 16' of the anisotropic conductive layer 16.

[0138] In some embodiments, a height H2 of the black matrix 38 and a maximum height H1 of the separated portion 16' of the anisotropic conductive layer 16 are provided, with an appropriate dimensional relationship between the two, such as... Figure 11 As shown. Figure 11 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment. Figure 11 In the middle, the height H2 of the black matrix 38 is greater than the maximum height H1 of the separated portion 16' of the anisotropic conductive layer 16.

[0139] In some embodiments, different states of the conductive particles 32 in the anisotropic conductive layer 16 during bonding are provided, such as... Figure 12 As shown. Figure 12 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment. Figure 12 In the process, the conductive particles 32 located between the contact electrode 26 of the light-emitting diode (LED) 14 and the bonding pad 30 are deformed by compression, so that the inner diameter d1 of the compressed conductive particles 32 is smaller than the inner diameter d2 of the uncompressed conductive particles 32, thereby ensuring successful bonding.

[0140] In some embodiments, the conductive particles 32 have a plurality of protrusions 40 extending from their surface, such as Figure 13 As shown. Figure 13 This is a schematic diagram showing the outline of the conductive particle 32 in this embodiment. Please refer to [link / reference]. Figure 12 and 13 The protrusions 40 of the conductive particles 32 pierce the oxide layer formed on the surfaces of the contact electrode 26 and the bonding pad 30, which can effectively improve the contact effect between them.

[0141] Please see Figure 14 According to an embodiment of the present invention, a display device 10 is provided. Figure 14 This is a cross-sectional view of the display device 10 in this embodiment.

[0142] like Figure 14 As shown, the display device 10 includes a thin-film transistor (TFT) substrate 12', a plurality of bonding pads 30, a plurality of light-emitting diodes (LEDs) 14, and a plurality of bumps (42, 42'). The TFT substrate 12' includes a display area 20 and a non-display area 22, with the non-display area 22 adjacent to the display area 20. The bonding pads 30 are disposed on the TFT substrate 12'. The LEDs 14 are disposed on the display area 20 of the TFT substrate 12' and correspond to the bonding pads 30. The LEDs 14 include contact electrodes 26. The bumps 42 are disposed between the bonding pads 30 and the contact electrodes 26 of the LEDs 14.

[0143] In some embodiments, the display device 10 further includes at least one connection structure 44. The connection structure 44 is disposed on the non-display area 22 and / or display area 20 of the thin-film transistor (TFT) substrate 12' and corresponds to the bonding pad 30. The connection structure 44 has a contact electrode 26'.

[0144] In this embodiment, the connection structure 44 includes an insulating layer 21' that is separate from the light-emitting diode (LED) 14 (that is, separate from the insulating layer 21 of the light-emitting diode (LED) 14).

[0145] In some embodiments, the bump 42' is disposed between the bonding pad 30 and the contact electrode 26' of the connection structure 44.

[0146] In some embodiments, the bump 42' includes the metallic material of the bonding pad 30 and the contact electrode 26'. The metallic material of the bonding pad 30 includes copper, tin, indium, lead, or alloys thereof. The metallic material of the contact electrode 26' includes copper, aluminum, molybdenum, titanium, nickel, or alloys thereof. Furthermore, the bump 42 is disposed between the bonding pad 30 and the contact electrode 26 of the light-emitting diode (LED) 14. The bump 42 also includes the metallic material of the bonding pad 30 and the contact electrode 26. The metallic material of the bonding pad 30 includes copper, tin, indium, lead, or alloys thereof. The metallic material of the contact electrode 26 includes copper, aluminum, molybdenum, titanium, nickel, or alloys thereof.

[0147] Please see Figures 15A-15H According to an embodiment of the present invention, a method for manufacturing a display device 10 is provided. Figures 15A-15H This is a cross-sectional schematic diagram of the manufacturing method of the display device 10 in this embodiment.

[0148] like Figure 15A As shown, a wafer substrate 11 is provided, on which an undoped gallium nitride layer 13, an N-type semiconductor layer 15, and a P-type semiconductor layer 17 are sequentially formed. The undoped gallium nitride layer 13 is formed on the wafer substrate 11, the N-type semiconductor layer 15 is formed on the undoped gallium nitride layer 13, and the P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15. The wafer substrate 11 includes a central region 46 and a peripheral region 48, with the peripheral region 48 adjacent to the central region 46. In some embodiments, multiple quantum wells (not shown) are further formed between the N-type semiconductor layer 15 and the P-type semiconductor layer 17.

[0149] like Figure 15B As shown, the P-type semiconductor layer 17 and the N-type semiconductor layer 15 are then etched to form a stack of patterned N-type semiconductor layer 15 and patterned P-type semiconductor layer 17 in the central region 46, respectively, and another patterned N-type semiconductor layer 15' in the peripheral region 48. It is worth noting that the thickness h1 of the patterned N-type semiconductor layer 15 in the central region 46 is greater than the thickness h2 of the patterned N-type semiconductor layer 15' in the peripheral region 48.

[0150] like Figure 15C As shown, a lower electrode 19 is then formed on a portion of the patterned N-type semiconductor layer 15 in the central region 46. Simultaneously, another lower electrode 19' is formed on the patterned N-type semiconductor layer 15' in the peripheral region 48. In this embodiment, the lower electrode 19 in the central region 46 and the lower electrode 19' in the peripheral region 48 are made of the same material.

[0151] like Figure 15DAs shown, an insulating layer 21 is then formed in the central region 46 on the patterned N-type semiconductor layer 15, a portion of the patterned P-type semiconductor layer 17, and the lower electrode 19. Simultaneously, another insulating layer 21' is formed in the peripheral region 48 on the lower electrode 19'. In this embodiment, the insulating layer 21 in the central region 46 and the insulating layer 21' in the peripheral region 48 have the same material.

[0152] like Figure 15E As shown, an upper electrode (contact electrode) 26 is then formed on the insulating layer 21 in the central region 46, and contacts the patterned P-type semiconductor layer 17. Simultaneously, another upper electrode (another contact electrode) 26' is formed on the insulating layer 21' in the peripheral region 48, and contacts the lower electrode 19'. This completes the fabrication of a wafer substrate 11 with multiple light-emitting diodes (LEDs) 14 formed in the central region 46 and at least one connection structure 44 formed in the peripheral region 48.

[0153] like Figure 15F As shown, a thin-film transistor (TFT) substrate 12' having a plurality of bonding pads 30 formed thereon is provided. The TFT substrate 12' includes a display area 20 and a non-display area 22, the non-display area 22 being adjacent to the display area 20. The display area 20 and the non-display area 22 of the TFT substrate 12' correspond to the central region 46 and the peripheral region 48 of the wafer substrate 11, respectively.

[0154] like Figure 15G As shown, a thin-film transistor (TFT) substrate 12' is bonded to a wafer substrate 11 by performing a fusion process. During the fusion process, in the display area 20, the bonding pads 30 of the TFT substrate 12' are fused to the upper electrode 26 of the light-emitting diode (LED) 14. In the non-display area 22, the bonding pads 30 of the TFT substrate 12' are fused to the upper electrode 26' of the connection structure 44.

[0155] After that, as Figure 15H As shown, remove wafer substrate 11.

[0156] Please see Figure 16 According to an embodiment of the present invention, a display device 10 is provided. Figure 16 This is a cross-sectional view of the display device 10 in this embodiment.

[0157] like Figure 16As shown, the display device 10 includes a thin-film transistor (TFT) substrate 12', a plurality of bonding pads 30, a plurality of light-emitting diodes (LEDs) 14, and a plurality of bumps (42, 42'). The TFT substrate 12' includes a display area 20 and a non-display area 22, with the non-display area 22 adjacent to the display area 20. The bonding pads 30 are disposed on the TFT substrate 12'. The LEDs 14 are disposed on the display area 20 of the TFT substrate 12' and correspond to the bonding pads 30. The LEDs 14 include contact electrodes 26. The bumps 42 are disposed between the bonding pads 30 and the contact electrodes 26 of the LEDs 14.

[0158] In some embodiments, the display device 10 further includes at least one connection structure 44. The connection structure 44 is disposed on the non-display area 22 and / or display area 20 of the thin-film transistor (TFT) substrate 12' and corresponds to the bonding pad 30. The connection structure 44 has a contact electrode 26'.

[0159] In this embodiment, the connection structure 44 includes an insulating layer 21 that extends to cover a portion of the light-emitting diode (LED) 14 (that is, serves as the insulating layer for the light-emitting diode (LED) 14).

[0160] In some embodiments, the bump 42' is disposed between the bonding pad 30 and the contact electrode 26' of the connection structure 44.

[0161] In some embodiments, the bump 42' includes the metallic material of the bonding pad 30 and the contact electrode 26'. The metallic material of the bonding pad 30 includes copper, tin, indium, lead, or alloys thereof. The metallic material of the contact electrode 26' includes copper, aluminum, molybdenum, titanium, nickel, or alloys thereof. Furthermore, the bump 42 is disposed between the bonding pad 30 and the contact electrode 26 of the light-emitting diode (LED) 14. The bump 42 also includes the metallic material of the bonding pad 30 and the contact electrode 26. The metallic material of the bonding pad 30 includes copper, tin, indium, lead, or alloys thereof. The metallic material of the contact electrode 26 includes copper, aluminum, molybdenum, titanium, nickel, or alloys thereof.

[0162] Please see Figures 17A-17E According to an embodiment of the present invention, a method for manufacturing a display device 10 is provided. Figures 17A-17E This is a cross-sectional schematic diagram of the manufacturing method of the display device 10 in this embodiment.

[0163] For information on the fabrication of the display device 10 prior to the formation of the insulating layer 21, please refer to [link to documentation]. Figures 15A-15C .

[0164] like Figure 17AAs shown, an insulating layer 21 is formed in the central region 46 on the patterned N-type semiconductor layer 15, a portion of the patterned P-type semiconductor layer 17, and the lower electrode 19. Simultaneously, the insulating layer 21 extends to the peripheral region 48 and is formed on the lower electrode 19'. It is noteworthy that in this embodiment, the insulating layer 21 extends from the central region 46 to the peripheral region 48.

[0165] like Figure 17B As shown, an upper electrode (contact electrode) 26 is then formed on the insulating layer 21 in the central region 46, and contacts the patterned P-type semiconductor layer 17. Simultaneously, another upper electrode (another contact electrode) 26' is formed on the insulating layer 21 in the peripheral region 48, and contacts the lower electrode 19'. This completes the fabrication of a wafer substrate 11 with multiple light-emitting diodes (LEDs) 14 formed in the central region 46 and at least one connection structure 44 formed in the peripheral region 48.

[0166] like Figure 17C As shown, a thin-film transistor (TFT) substrate 12' having a plurality of bonding pads 30 formed thereon is provided. The TFT substrate 12' includes a display area 20 and a non-display area 22, the non-display area 22 being adjacent to the display area 20. The display area 20 and the non-display area 22 of the TFT substrate 12' correspond to the central region 46 and the peripheral region 48 of the wafer substrate 11, respectively.

[0167] like Figure 17D As shown, a thin-film transistor (TFT) substrate 12' is bonded to a wafer substrate 11 by performing a fusion process. During the fusion process, in the display area 20, the bonding pads 30 of the TFT substrate 12' are fused to the upper electrode 26 of the light-emitting diode (LED) 14. In the non-display area 22, the bonding pads 30 of the TFT substrate 12' are fused to the upper electrode 26' of the connection structure 44.

[0168] After that, as Figure 17E As shown, remove wafer substrate 11.

[0169] In some embodiments, the components between the light-emitting diode (LED) 14 and the connection structure 44 are provided with appropriate profiles and dimensional relationships, such as... Figure 18A and Figure 18B As shown. Figure 18A This is a cross-sectional view of the light-emitting diode (LED) 14 in this embodiment. Figure 18B This is a cross-sectional view of the connection structure 44 in this embodiment.

[0170] like Figure 18AAs shown, the light-emitting diode (LED) 14 includes an N-type semiconductor layer 15 with a thickness Hn1, a P-type semiconductor layer 17 with a thickness Hp, a lower electrode 19, an insulating layer 21, and an upper electrode (contact electrode) 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17 and the lower electrode 19, and the upper electrode (contact electrode) 26 is formed on the insulating layer 21 and is in contact with the P-type semiconductor layer 17.

[0171] like Figure 18B As shown, the connection structure 44 includes an N-type semiconductor layer 15' with a thickness of Hn2, a lower electrode 19' with a thickness of He, an insulating layer 21', and an upper electrode (contact electrode) 26'. The lower electrode 19' is formed on the N-type semiconductor layer 15', the insulating layer 21' is formed on the lower electrode 19', and the upper electrode (contact electrode) 26' is formed on the insulating layer 21' and is in contact with the lower electrode 19'.

[0172] It is worth noting that by adjusting the etching parameters, the edges of the cross-sectional profiles of the light-emitting diode (LED) 14 and the multiple components in the connection structure 44 are made into curved shapes to effectively reduce electrostatic discharge caused by charge accumulation. The edges of the aforementioned cross-sectional profiles extend from the top of the components to the sidewalls. For example, the cross-sectional profile of the lower electrode 19 of the LED 14 forms a curved shape at least at edge 50 and the cross-sectional profile of the insulating layer 21 at least at edge 52. Figure 18A As shown. The cross-sectional profile of the lower electrode 19' of the connecting structure 44, at least at edge 54, also forms a curved shape with the cross-sectional profile of the upper electrode (contact electrode) 26', at least at edge 56, as shown. Figure 18B As shown.

[0173] Furthermore, the thickness Hn1 of the N-type semiconductor layer 15 of the light-emitting diode (LED) 14 is greater than the thickness Hn2 of the N-type semiconductor layer 15' of the connection structure 44, to ensure that no P-type semiconductor layer remains on the N-type semiconductor layer 15' in the connection structure 44. Moreover, the ratio of the total thickness Hn2 of the N-type semiconductor layer 15' of the connection structure 44 and the thickness He of the lower electrode 19' to the total thickness Hn1 of the N-type semiconductor layer 15' of the light-emitting diode (LED) 14 and the thickness Hp of the P-type semiconductor layer 17 is approximately between 0.9 and 1.1, to avoid thickness differences between the light-emitting diode (LED) 14 and the connection structure 44, ensuring good contact between components and improving productivity.

[0174] In some embodiments, the components between the light-emitting diode (LED) 14 and the connection structure 44 are provided with appropriate profiles and dimensional relationships, such as... Figure 19A and Figure 19B As shown. Figure 19A This is a cross-sectional view of the light-emitting diode (LED) 14 in this embodiment. Figure 19B This is a cross-sectional view of the connection structure 44 in this embodiment.

[0175] like Figure 19A As shown, the light-emitting diode (LED) 14 includes an N-type semiconductor layer 15 with a thickness Hn1, a P-type semiconductor layer 17 with a thickness Hp, a lower electrode 19, an insulating layer 21, and an upper electrode (contact electrode) 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17 and the lower electrode 19, and the upper electrode (contact electrode) 26 is formed on the insulating layer 21 and is in contact with the P-type semiconductor layer 17.

[0176] like Figure 19B As shown, the connection structure 44 includes an N-type semiconductor layer 15' with a thickness of Hn2, a lower electrode 19' with a thickness of He, an insulating layer 21, and an upper electrode (contact electrode) 26'. The lower electrode 19' is formed on the N-type semiconductor layer 15', the insulating layer 21 is formed on the lower electrode 19' and the N-type semiconductor layer 15', and the upper electrode (contact electrode) 26' is formed on the insulating layer 21 and is in contact with the lower electrode 19'.

[0177] It is worth noting that by adjusting the etching parameters, the edges of the cross-sectional profiles of the light-emitting diode (LED) 14 and the multiple components in the connection structure 44 are made into curved shapes to effectively reduce electrostatic discharge caused by charge accumulation. The edges of the aforementioned cross-sectional profiles extend from the top of the components to the sidewalls. For example, the cross-sectional profile of the lower electrode 19 of the LED 14 forms a curved shape at least at edge 50 and the cross-sectional profile of the insulating layer 21 at least at edge 52. Figure 19A As shown. The cross-sectional profile of the lower electrode 19' of the connecting structure 44 also forms a curved shape at least at edge 54 and at least at edge 58 with the cross-sectional profile of the insulating layer 21, as shown. Figure 19B As shown.

[0178] Furthermore, the thickness Hn1 of the N-type semiconductor layer 15 of the light-emitting diode (LED) 14 is greater than the thickness Hn2 of the N-type semiconductor layer 15' of the connection structure 44. Moreover, the ratio of the total thickness Hn2 of the N-type semiconductor layer 15' of the connection structure 44 and the thickness He of the lower electrode 19' to the total thickness Hn1 of the N-type semiconductor layer 15 of the light-emitting diode (LED) 14 and the thickness Hp of the P-type semiconductor layer 17 is approximately between 0.9 and 1.1.

[0179] In some embodiments, other outline patterns of the light-emitting diode (LED) 14 assembly are provided, such as... Figure 20 As shown. Figure 20 This is a cross-sectional view of the light-emitting diode (LED) 14. Figure 20 In this design, the light-emitting diode (LED) 14 includes an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and an upper electrode (contact electrode) 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, and the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19. Notably, the upper electrode (contact electrode) 26 covers the insulating layer 21 and extends to the wafer substrate. The upper electrode (contact electrode) 26 can serve as a reflective plate to concentrate light emission.

[0180] In some embodiments, an appropriate dimensional relationship is provided between the bonding pad 30 and the bumps (42, 42') in the display device 10, such as... Figure 21 As shown. Figure 21 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment.

[0181] Figure 21 In this structure, the light-emitting diode (LED) 14 includes an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and an upper electrode (contact electrode) 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19, and the upper electrode (contact electrode) 26 is formed on the insulating layer 21 and contacts the P-type semiconductor layer 17. The LED 14 is further bonded to the bonding pad 30 of the thin-film transistor (TFT) substrate 12' via bumps 42. The connection structure 44 includes the N-type semiconductor layer 15', the lower electrode 19', the insulating layer 21', and the upper electrode (contact electrode) 26'. The lower electrode 19' is formed on the N-type semiconductor layer 15', the insulating layer 21' is formed on the lower electrode 19', and the upper electrode (contact electrode) 26' is formed on the insulating layer 21' and contacts the lower electrode 19'. The connection structure 44 is further bonded to the bonding pad 30 of the thin-film transistor (TFT) substrate 12' via bumps 42'.

[0182] It is worth noting that the width L1 of the bumps (42, 42') is greater than the width L2 of the mating pad 30. Furthermore, the projected area A1 of the bumps (42, 42') is greater than the projected area A2 of the mating pad 30, such as... Figure 22 As shown. Figure 22This is a top view of the bonding pad 30 and the bumps (42, 42') in this embodiment. In the display device 10, the width L1 and projected area A1 of the bumps (42, 42') are both greater than the width L2 and projected area A2 of the bonding pad 30. This indicates that the bonding pad 30 and the upper electrode (contact electrode) (26, 26') have been effectively fused together, and good conductivity can be achieved between them through the bumps (42, 42').

[0183] In some embodiments, an appropriate dimensional relationship is provided between the bonding pad 30 and the bumps (42, 42') in other display devices 10, such as... Figure 23 As shown. Figure 23 This is a cross-sectional schematic diagram of part of the display device 10 in this embodiment.

[0184] Figure 23 In this structure, the light-emitting diode (LED) 14 includes an N-type semiconductor layer 15, a P-type semiconductor layer 17, a lower electrode 19, an insulating layer 21, and an upper electrode (contact electrode) 26. The P-type semiconductor layer 17 is formed on the N-type semiconductor layer 15, the lower electrode 19 is formed on a portion of the N-type semiconductor layer 15, the insulating layer 21 is formed on the N-type semiconductor layer 15, a portion of the P-type semiconductor layer 17, and the lower electrode 19, and the upper electrode (contact electrode) 26 is formed on the insulating layer 21 and contacts the P-type semiconductor layer 17. The LED 14 is further bonded to the bonding pad 30 of the thin-film transistor (TFT) substrate 12' via bumps 42. The connection structure 44 includes the N-type semiconductor layer 15', the lower electrode 19', the insulating layer 21, and the upper electrode (contact electrode) 26'. The lower electrode 19' is formed on the N-type semiconductor layer 15', the insulating layer 21 is formed on the lower electrode 19' and the N-type semiconductor layer 15', and the upper electrode (contact electrode) 26' is formed on the insulating layer 21 and contacts the lower electrode 19'. The connection structure 44 is further bonded to the bonding pad 30 of the thin-film transistor (TFT) substrate 12' via bumps 42'.

[0185] It is worth noting that the width L1 of the bumps (42, 42') is greater than the width L2 of the mating pad 30. Furthermore, the projected area A1 of the bumps (42, 42') is greater than the projected area A2 of the mating pad 30, such as... Figure 24 As shown. Figure 24 This is a top view of the mating pad 30 and the protrusions (42, 42') in this embodiment.

[0186] In some embodiments, the distribution of the connection structure A and the light-emitting diode (LED) B on the wafer substrate 11 is as follows: Figure 25 As shown. Figure 25 This is a top view of the wafer substrate 11. Figure 25In this design, most of the light-emitting diodes (LEDs) B are located on the central region 46 of the wafer substrate 11, while most of the connection structures A are located on the peripheral region 48 of the wafer substrate 11. It is worth noting that the number of light-emitting diodes (LEDs) B is greater than the number of connection structures A.

[0187] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A display device, characterized in that, include: A substrate includes a display area and a non-display area, wherein the non-display area is adjacent to the display area; Multiple light-emitting diodes are disposed on the display area of ​​the substrate, wherein one of the multiple light-emitting diodes includes a second electrode, a second insulating layer and a second semiconductor layer, the second electrode is recessed inward through the second insulating layer toward the second semiconductor layer, and the second electrode extends to cover the second insulating layer; as well as A connection structure is disposed on the non-display area and / or the display area of ​​the substrate, wherein the connection structure includes a first electrode, a first insulating layer and a third electrode, the first insulating layer is located between the third electrode and the first electrode, the first electrode covers the first insulating layer and contacts the third electrode, and at least a portion of the cross-sectional contours of the first electrode and the third electrode are respectively curved.

2. The display device of claim 1, wherein the connection structure further includes a first insulating layer that contacts the first electrode.

3. The display device of claim 2, wherein the width of the first insulating layer is smaller than the width of the second insulating layer.

4. The display device of claim 1, wherein the connection structure further includes a first semiconductor layer electrically connected to the first electrode.

5. The display device of claim 1 further includes a conductive element disposed between the substrate and the light-emitting diode, wherein the conductive element includes bumps or anisotropic conductive layers.

6. A display device, characterized in that, include: The substrate includes the display area; Multiple bonding pads are disposed on the substrate; Multiple light-emitting diodes are disposed on the display area of ​​the substrate, wherein each light-emitting diode includes an electrode; A conductive layer is disposed on the substrate, wherein the conductive layer includes multiple discrete portions; Multiple conductive elements are disposed between the multiple bonding pads and the multiple electrodes of the multiple light-emitting diodes; as well as A black matrix is ​​disposed on the substrate and located between two adjacent portions of the plurality of separated portions, wherein, in a cross-sectional direction, the black matrix is ​​located between two adjacent bonding pads and the plurality of light-emitting diodes; One of the plurality of light-emitting diodes includes a first semiconductor layer and a second semiconductor layer, and the height of the black matrix is ​​greater than the height of the second semiconductor layer.

7. The display device of claim 6, wherein the conductive element comprises bumps or anisotropic conductive layers.

8. The display device as claimed in claim 6, wherein, In one cross-sectional direction, the width of the bottom surface of the black matrix is ​​greater than the width of the top surface of the black matrix.

9. The display device of claim 6, further comprising an array layer disposed on the substrate, wherein the array layer includes transistors electrically connected to one of the plurality of bonding pads.

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