Display panel and display device

Abstract

The present invention discloses a display panel and a display device, belonging to the field of display technology. The display panel includes a plurality of sub-pixels, and the sub-pixels include electrically connected pixel circuits and light-emitting elements; the pixel circuit includes at least a driving transistor, a first reset module, and a second reset module; the first end of the first reset module is connected to the gate of the driving transistor, and the second end of the first reset module is connected to the first reset signal line; the first end of the second reset module is connected to the light-emitting element, and the second end of the second reset module is connected to the second reset signal line; the first reset signal line and the second reset signal line corresponding to the same sub-pixel are arranged in different layers. The display device includes the above-mentioned display panel. The present invention can improve the display resolution of the product without affecting the pixel circuit driving effect and display quality.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] Compared to liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays require no backlight and offer advantages such as low energy consumption, low production costs, self-luminescence, wide viewing angles, and fast response times. Their manufacturing costs are lower than those of LCDs with equivalent resolution. Therefore, OLED displays have broad application prospects and have become a hot topic in current display research.

[0003] In OLED displays, light-emitting devices like OLEDs are driven by pixel circuits, whose driving signals are provided by signal traces within the display panel. Currently, displays are trending towards thinner and lighter sizes, with higher pixel density (PPI). This high PPI allows for finer display patterns.

[0004] In the existing technology, in order to achieve high PPI of OLED displays, it is generally achieved by improving the alignment accuracy of OLED evaporation. However, with the gradual improvement and advancement of evaporation technology, it is no longer possible to further meet the demand for higher resolution of products without affecting the pixel circuit driving effect.

[0005] Therefore, providing a display panel and a display device that can improve the display resolution of a product without affecting the pixel circuit driving effect and display quality is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device to solve the problem in the prior art that displays cannot achieve higher resolution requirements of products without affecting the pixel circuit driving effect and display quality.

[0007] The present invention discloses a display panel, comprising: a plurality of sub-pixels, each sub-pixel comprising an electrically connected pixel circuit and a light-emitting element; the pixel circuit comprising at least a driving transistor, a first reset module, and a second reset module; a first end of the first reset module being connected to the gate of the driving transistor, and a second end of the first reset module being connected to a first reset signal line; a first end of the second reset module being connected to the light-emitting element, and a second end of the second reset module being connected to a second reset signal line; and the first reset signal line and the second reset signal line corresponding to the same sub-pixel being arranged in different layers.

[0008] Based on the same inventive concept, the present invention also discloses a display device, which includes the above-mentioned display panel.

[0009] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0010] The sub-pixels of the display panel provided by the present invention include a pixel circuit electrically connected to the light-emitting element, the pixel circuit is used to drive the light-emitting element to emit light, and the pixel circuit includes at least a driving transistor, a first reset module and a second reset module, wherein the first reset module is used to transmit the first reset signal provided by the first reset signal line to the gate of the driving transistor, to reset the gate of the driving transistor, so as to facilitate the driving transistor to be turned on during subsequent threshold compensation. The second reset module is used to transmit the second reset signal provided by the second reset signal line to the anode of the light-emitting element, so that the anode of the light-emitting element is initialized, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel. The present invention sets the first reset signal line and the second reset signal line corresponding to the same sub-pixel to be independent of each other to provide different reset signal values, which can improve the afterimage problem and improve the visual effect of the display panel under low grayscale, thereby helping to ensure the display quality. The present invention also provides a first reset signal line and a second reset signal line corresponding to the same sub-pixel in different layers, thereby ensuring that the first reset signal line and the second reset signal line corresponding to the same sub-pixel have sufficient line width to reduce the routing impedance and improve signal transmission performance, while also not having to consider the spacing between the first reset signal line and the second reset signal line. Since the two are arranged in different layers, even if the two overlap, it will not cause a short circuit problem between the signal lines. Thus, the first reset signal line and the second reset signal line corresponding to the same sub-pixel can be as close as possible to or even overlap in their arrangement direction, thereby ensuring the normal driving effect of the pixel circuit while minimizing the length occupied by a sub-pixel in the second direction, which is conducive to achieving a high PPI effect of the display panel. The present invention arranges the first reset signal line and the second reset signal line corresponding to the same sub-pixel in different layers, saving panel wiring space, reducing the size of a single sub-pixel, and providing a higher possibility for increasing the overall number of sub-pixels in the display panel, thereby improving the PPI of the display panel without adversely affecting the layout of the pixel circuit or the conduction of electrical signals.

[0011] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0012] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1 is a schematic diagram of the planar structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 yes Figure 1 Schematic diagram of the electrical connection structure between the pixel circuit and the light-emitting element of the neutron pixel;

[0016] Figure 3 yes Figure 2 A schematic diagram of the layout structure of the first reset signal line and the second reset signal line corresponding to the same sub-pixel;

[0017] Figure 4 yes Figure 1 A schematic diagram of another electrical connection structure between the pixel circuit and the light-emitting element of the neutron pixel;

[0018] Figure 5 yes Figure 4 Schematic diagram of the layout structure of a part of the neutron pixel;

[0019] Figure 6 yes Figure 4 Schematic diagram of another layout structure of a part of the neutron pixel;

[0020] Figure 7 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0021] Figure 8 yes Figure 7 Schematic diagram of the layout structure of a part of the neutron pixel;

[0022] Figure 9 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0023] Figure 10 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel;

[0024] Figure 11 yes Figure 8 Schematic diagram of the split structure of the middle part of the signal line;

[0025] Figure 12 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel;

[0026] Figure 13 yes Figure 12 Schematic diagram of the split structure of the middle part of the signal line;

[0027] Figure 14 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel;

[0028] Figure 15 yes Figure 14 Schematic diagram of the split structure of the middle part of the signal line;

[0029] Figure 16 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel;

[0030] Figure 17 yes Figure 16 Schematic diagram of the split structure of the middle part of the signal line;

[0031] Figure 18 It is a schematic diagram of the planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0033] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0034] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0035] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0036] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0037] Please refer to Figure 1-Figure 3 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 Schematic diagram of the electrical connection structure between the pixel circuit and the light-emitting element of the neutron pixel, Figure 3 yes Figure 2Schematic diagram of the layout structure of the first reset signal line and the second reset signal line corresponding to the same sub-pixel (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 1 and Figure 3 The display panel 000 provided in this embodiment includes: a plurality of sub-pixels P, each sub-pixel P including a pixel circuit 10 and a light-emitting element 20 that are electrically connected;

[0038] The pixel circuit 10 at least includes a driving transistor DT, a first reset module 101 and a second reset module 102;

[0039] A first terminal of the first reset module 101 is connected to the gate of the driving transistor DT, and a second terminal of the first reset module 101 is connected to the first reset signal line REF1;

[0040] A first end of the second reset module 102 is connected to the light emitting element 20 , and a second end of the second reset module 102 is connected to the second reset signal line REF2 ;

[0041] The first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged in different layers.

[0042] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting diode display panel, and the light-emitting element 20 included in the sub-pixel P can be an organic light-emitting diode. In some other optional embodiments, the light-emitting element 20 included in the sub-pixel P can also be a micro light-emitting diode (Micro LED) or a sub-millimeter light-emitting diode (Mini LED), which is not limited in this embodiment. The sub-pixel P of this embodiment includes a pixel circuit 10 electrically connected to the light-emitting element 20. The pixel circuit 10 is used to drive the light-emitting element 20 to emit light. The pixel circuit 10 generally includes a plurality of TFTs (Thin Film Transistors) and capacitors, which are respectively used to implement functions such as compensation or data storage of the pixel circuit. The pixel circuit 10 in this embodiment includes at least a driving transistor DT, a first reset module 101 and a second reset module 102, wherein a first end of the first reset module 101 is connected to the gate of the driving transistor DT, and a second end of the first reset module 101 is connected to the first reset signal line REF1. The first reset module 101 is configured to transmit a first reset signal provided by the first reset signal line REF1 to the gate of the driving transistor DT when the first reset module 101 is turned on, so as to reset the gate of the driving transistor DT. That is, when the first reset module 101 is turned on, the gate potential of the driving transistor DT is the first reset signal provided by the first reset signal line REF1, so that the driving transistor DT can be turned on under the control of its gate potential, thereby facilitating the turning on of the driving transistor DT during subsequent threshold compensation. The second reset module 102 is used to transmit the second reset signal provided by the second reset signal line REF2 to the anode of the light-emitting element 20 when the second reset module 102 is turned on. That is, when the second reset module 102 is turned on, the anode potential of the light-emitting element 20 is the second reset signal provided by the second reset signal line REF2, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual of the previous frame data signal, improving the afterimage phenomenon, and enhancing the display effect of the display panel 000.

[0043] It is understood that in this embodiment, the values of the first reset signal provided by the first reset signal line REF1 and the second reset signal provided by the second reset signal line REF2 can be the same or different, and can be set according to actual needs during implementation. This embodiment uses the example where the values of the first reset signal provided by the first reset signal line REF1 and the second reset signal provided by the second reset signal line REF2 are different.

[0044] Optionally, in this embodiment, the value of the first reset signal provided by the first reset signal line REF1 and the value of the second reset signal provided by the second reset signal line REF2 connected to the same sub-pixel P are different. That is, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are independent of each other, so that the first reset module 101 and the second reset module 102 use different reset signals to reset the gate of the driving transistor DT and the anode of the light-emitting element 20. Further, optionally, the value of the first reset signal provided by the first reset signal line REF1 can be greater than the value of the second reset signal provided by the second reset signal line REF2. When the first reset signal provided by the first reset signal line REF1 is a square wave signal, the first reset signal includes a low potential and a high potential, and the low potential of the first reset signal is greater than the potential of the second reset signal. Since the first reset signal cannot be too low, if the potential of the first reset signal is too low, when the pixel circuit 10 writes a fixed data voltage signal to the gate of the driving transistor DT during the data writing phase, the first reset signal will pull the original potential of the gate of the driving transistor DT very low, which may cause the gate of the driving transistor DT to be undercharged. The potential value of the second reset signal is preferably lower, so as to reset the anode of the light-emitting element more thoroughly and avoid the phenomenon of the sub-pixel P being secretly lit due to the lateral leakage current between the light-emitting elements 20 of adjacent sub-pixels P.

[0045] In this embodiment, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are independent of each other. The value of the first reset signal is different from the value of the second reset signal. When the second reset signal needs to be lowered to improve the problem of light-emitting element 20 being stuttered, the low potential of the first reset signal does not need to be lowered as the second reset signal is lowered. As a result, the low potential of the first reset signal can be higher than the potential of the second reset signal after being lowered. After resetting the gate of the driving transistor DT, when writing the data voltage signal to the gate of the driving transistor DT, the data voltage signal can be written based on a slightly higher low potential. This helps reduce the voltage difference between the initial potential of the gate of the driving transistor DT and the data voltage signal to be written, thereby allowing the data voltage signal to be written more fully during the data writing phase of the pixel circuit 10. Therefore, in this embodiment, the reset signals of the first reset module 101 and the second reset module 102 of the pixel circuit 10 in the same sub-pixel P are independently provided by different reset signal lines. This can improve the problem of image sticking and enhance the visual effect of the display panel 000 at low grayscales, thereby helping to ensure display quality.

[0046] It can be understood that this embodiment does not specifically limit the types of the first reset signal provided by the first reset signal line REF1 and the second reset signal provided by the second reset signal line REF2 connected to the same sub-pixel P. The first reset signal and the second reset signal can both be DC signals, or the first reset signal can be a square wave AC signal and the second reset signal can be a DC signal, or the first reset signal and the second reset signal can also be other types of signals, as long as the value of the first reset signal is greater than the value of the second reset signal. This embodiment does not specifically limit this.

[0047] Because the light-emitting elements of each sub-pixel in a display panel need to be driven by a pixel circuit, the driving signals for the pixel circuits need to be provided by multiple signal lines in the display panel (such as the reset signal line shown in this embodiment, and the scan lines, data lines, and power signal lines not shown in the figure). The higher the resolution of a display panel, the greater the number of sub-pixels and the greater the total number of signal lines in the panel. Therefore, improving the array layout of sub-pixels and reducing the layout space of each sub-pixel in the entire display panel have become important means of improving the resolution of display panels.

[0048] In the prior art, although the reset signals of the first reset module and the second reset module of the pixel circuit in the same sub-pixel are independent of each other, they are generally provided by different reset signal lines on the same film layer. When the first reset signal line and the second reset signal line are on the same layer, it is necessary to ensure that both signal lines have sufficient line width to reduce the routing impedance, and also to ensure that there is sufficient spacing between the two reset signal lines set on the same layer to avoid signal interference and short circuit. Therefore, when the reset signals of the first reset module and the second reset module of the pixel circuit in the same sub-pixel in the display panel are independently provided by the same film layer but different reset signal lines, the sub-pixel will often occupy a larger space on the panel. For example, if the two independent reset signal lines both extend in the horizontal direction, for the same sub-pixel, the space occupied by the two independent reset signal lines on the same layer in the vertical direction is larger, and the space occupied by the sub-pixel in the vertical direction is also larger, and the PPI of the display panel of the same size will be significantly reduced.

[0049] In order to solve the above problems, in this embodiment, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged in different layers, that is, the reset signals of the first reset module 101 and the second reset module 102 of the pixel circuit 10 in the same sub-pixel P are not only independent of each other, but the first reset signal line REF1 providing the first reset signal and the second reset signal line REF2 providing the second reset signal for the same sub-pixel P are made of different film layers. Therefore, when setting the PPI of the display panel 000, it is possible to ensure that the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P have sufficient line width to reduce the routing impedance and improve the signal transmission performance, while also not needing to consider the spacing between the first reset signal line REF1 and the second reset signal line REF2. Since the two are arranged in different layers, even if the two overlap, it will not cause a short circuit problem between the signal lines. The first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P can also be arranged as close as possible in their arrangement direction, such as Figure 3 As shown, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged along the first direction X. Then, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P can be as close as possible to or even overlap in the second direction Y (the second direction Y and the first direction X can be understood as being perpendicular to or intersecting each other in a direction parallel to the plane of the display panel 000). This ensures the normal driving effect of the pixel circuit 10 while minimizing the length occupied by a sub-pixel P in the second direction Y, which is conducive to achieving a high PPI effect of the display panel 000. In this embodiment, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged in different layers, which saves panel wiring space, reduces the size of a single sub-pixel P, and provides a higher possibility for increasing the overall number of sub-pixels P in the display panel 000. In turn, the PPI of the display panel 000 can be improved without adversely affecting the layout of the pixel circuit 10 or the conduction of electrical signals.

[0050] It can be understood that the first reset signal line REF1 and the second reset signal line REF2 in this embodiment are extended along the first direction X. It can be understood that the overall extension direction of the first reset signal line REF1 and the second reset signal line REF2 is substantially the same and extends in the same direction as the first direction X shown in the figure. Figure 2The structure of the first reset module 101 and the second reset module 102 is merely a block diagram. In specific implementation, the first reset module 101 and the second reset module 102 may respectively include thin film transistors to achieve their own reset effects during the reset phase of the pixel circuit 10. This embodiment does not limit the specific circuit connection structure of the first reset module 101 and the second reset module 102. For details, reference may be made to the circuit structure of the reset module in related arts for understanding.

[0051] It should be noted that the display panel 000 provided in this embodiment can be an organic light-emitting diode display panel. The diagram of this embodiment only illustrates the structure of the display panel. In specific implementation, the structure of the display panel 000 includes, but is not limited to, this structure, and may also include other structures capable of achieving a display function. For details, reference may be made to the structure of an organic light-emitting diode display panel in the related art for understanding, and this embodiment will not be described in detail here. The diagram of this embodiment only illustrates the structure of the pixel circuit 10. In specific implementation, the structure of the pixel circuit 10 includes, but is not limited to this structure, and may also include other functional modules such as a data writing module and a light control module. For details, reference may be made to the structure of a pixel circuit in the related art for understanding, and this embodiment will not be described in detail here.

[0052] Optional, such as Figure 1 、 Figure 4 and Figure 5 As shown, Figure 4 yes Figure 1 Schematic diagram of another electrical connection structure between the pixel circuit of the neutron pixel and the light-emitting element, Figure 5 yes Figure 4 Schematic diagram of the layout structure of a part of the neutron pixel area (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 5 (Transparency is filled in). This embodiment uses a 7T1C (7 thin-film transistors and 1 capacitor) structure of the pixel circuit 10 of a sub-pixel P as an example to explain the layout structure of the first reset signal line REF1 connected to the first reset module 101 and the second reset signal line REF2 connected to the second reset module 102. The first reset module 101 of the pixel circuit 10 may include a first transistor T1, the gate of the first transistor T1 being connected to the first scan signal line Scan1, the source of the first transistor T1 being connected to the first reset signal line REF1, and the drain of the first transistor T1 being connected to the gate of the drive transistor DT.

[0053] The second reset module 102 may include a second transistor T2 , a gate of the second transistor T2 connected to the second scan signal line Scan2 , a source of the second transistor T2 connected to the second reset signal line REF2 , and a drain of the second transistor T2 connected to the anode of the light emitting element 20 .

[0054] The pixel circuit 10 may further include a third transistor T3 and a fourth transistor T4 of the light emitting control module, wherein the gate of the third transistor T3 and the gate of the fourth transistor T4 are commonly connected to the light emitting control signal line EM, the source of the third transistor T3 is connected to the first power supply signal line PVDD, and the drain of the third transistor T3 is connected to the first electrode of the driving transistor DT; the source of the fourth transistor T4 is connected to the second electrode of the driving transistor DT, and the drain of the fourth transistor T4 is connected to the anode of the light emitting element 20.

[0055] The pixel circuit 10 may further include a fifth transistor T5 of the data writing module, wherein the gate of the fifth transistor T5 is connected to the second scan signal line Scan2, the source of the fifth transistor T5 is connected to the data line S in the display panel 000, and the drain of the fifth transistor T5 is connected to the first electrode of the driving transistor DT.

[0056] The pixel circuit 10 may further include a sixth transistor T6 of the threshold compensation module, wherein the gate of the sixth transistor T6 is connected to the second scan signal line Scan2 , the source of the sixth transistor T6 is connected to the gate of the driving transistor DT, and the drain of the sixth transistor T6 is connected to the second electrode of the driving transistor DT.

[0057] It is understandable that the working principle and working process of the pixel circuit 10 with a 7T1C structure are not described in detail in this embodiment. For details, reference may be made to the working principle of the pixel circuit with a 7T1C structure in the related art.

[0058] In this embodiment, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged in different layers (filled with different filling patterns in the figure), so the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P can be as close as possible to or even overlap in the second direction Y, thereby ensuring the normal driving effect of the pixel circuit 10 and reducing the length occupied by a sub-pixel P in the second direction Y as much as possible (such as Figure 5 The length L occupied by one sub-pixel P in the second direction is shown, which is conducive to achieving a high PPI effect of the display panel 000.

[0059] It should be noted that, in this embodiment Figure 5The example of each transistor in the pixel circuit 10 being a P-type low-temperature polycrystalline silicon thin film transistor is only used for illustration. In specific implementation, the structure of the pixel circuit 10 includes but is not limited to this. The pixel circuit 10 can also be an electrically connected structure composed of other numbers of transistors and capacitors, or the pixel circuit 10 can also be an electrically connected structure composed of other types of transistors (such as N-type metal oxide transistors). This embodiment only uses the 7T1C pixel circuit structure as an example to illustrate the structure in which two reset signal lines corresponding to the same sub-pixel P are set in different layers, and does not mean that the structure of the pixel circuit 10 in the display panel 000 of this embodiment is limited to this.

[0060] In some optional embodiments, please refer to Figure 1 、 Figure 4 and Figure 6 , Figure 6 yes Figure 4 Another schematic diagram of the layout structure of a part of the neutron pixel area (it can be understood that Figure 6 The pixel circuit in the embodiment is described by taking the electrical connection structure of 7T1C as an example to clearly illustrate the overlapping relationship between the first reset signal line and the second reset signal line. In a specific implementation, it does not mean that the structure of the pixel circuit 10 in the display panel 000 is limited to this. In order to clearly illustrate the structure of this embodiment, Figure 6 In this embodiment, the extending direction of the first reset signal line REF1 is the same as the extending direction of the second reset signal line REF2;

[0061] Along a direction perpendicular to the plane of the display panel 000 , the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P at least partially overlap.

[0062] This embodiment explains that since the first reset signal line REF1 and the second reset signal line REF2 are arranged in different layers, the extending direction of the first reset signal line REF1 can be set to be the same as the extending direction of the second reset signal line REF2. Figure 4 The extension direction of the first reset signal line REF1 and the extension direction of the second reset signal line REF2 shown are both the first direction Y, and in the direction perpendicular to the plane of the display panel 000, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P at least partially overlap. Optionally, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P can completely overlap or completely coincide, thereby further reducing the width space occupied by the first reset signal line REF1 and the second reset signal line REF in the second direction Y, which is beneficial to further reduce the length occupied by a sub-pixel P in the second direction Y, and is beneficial to further improve the PPI of the display panel 000.

[0063] In some optional embodiments, please refer to Figure 7 and Figure 8 , Figure 7 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 8 yes Figure 7 Schematic diagram of the layout structure of a part of the neutron pixel area (it can be understood that Figure 8 The pixel circuit in the embodiment is described by taking the electrical connection structure of 7T1C as an example. In a specific implementation, it does not mean that the structure of the pixel circuit 10 in the display panel 000 is limited to this. In order to clearly illustrate the structure of this embodiment, Figure 7 and Figure 8 In this embodiment, the display panel 000 includes a display area AA and a non-display area NA;

[0064] The non-display area NA includes a binding area BA, which is located on one side of the display area AA. Optionally, Figure 7 As shown, the binding area BA is located on one side of the display area AA in the second direction Y;

[0065] The binding area BA includes a plurality of conductive pads 30 , which are electrically connected to fan-out traces 40 , which are located in the non-display area NA.

[0066] The display area AA includes a plurality of first data lines S1 . The first data lines S1 are electrically connected to the fan-out wiring 40 through at least one first connection line 50 . The first connection line 50 is located in the display area AA.

[0067] This embodiment illustrates how some data lines S in the display panel 000 can be connected to fan-out traces in the non-display area NA via connecting lines located within the display area AA. Specifically, the display panel 000 includes the display area AA and the non-display area NA. Optionally, the non-display area NA may be partially disposed around the display area AA. The non-display area NA includes a binding area BA, which is located to one side of the display area AA in the second direction Y. The binding area BA includes a plurality of conductive pads 30. The conductive pads 30 are used for subsequent binding with a driver chip or a flexible circuit board, transmitting drive signals provided by the driver chip or flexible circuit board to various signal lines within the display panel 000 to implement the panel's display driving function. The conductive pads 30 are electrically connected to fan-out traces 40, which are located in the non-display area NA. It will be understood that this embodiment does not specifically limit the film layer of the fan-out traces 40 in the non-display area NA; it is only required that the fan-out traces 40 enable electrical signal transmission between the data lines S in the display area AA and the conductive pads 30 in the binding area BA. The display area AA of this embodiment includes a plurality of first data lines S1. Optionally, the first data lines S1 may be understood as data lines S within a portion of the display area near both sides of the edge of the display panel 000 in the second direction X. The first data lines S1 are electrically connected to the fan-out traces 40 via at least one first connecting line 50. The first connecting line 50 is located in the display area AA and implements signal transmission between the first data lines S1 and the conductive pads 30.

[0068] In this embodiment, the first connection line 50 electrically connecting the conductive pad 30 and the first data line S1 is located in the display area AA, and the fan-out line 40 is located in the non-display area NA. That is, in this embodiment, when the first data line S1 located near the two side edges of the display panel 000 in the first direction X is electrically connected to the conductive pad 30 in the binding area BA, the first connection line 50 can be prevented from occupying the space of the non-display area NA. Figure 7 As shown, the first connecting line 50 can gradually extend within the display area AA toward the center of the display area AA, and then be connected to the fan-out line 40 of the non-display area NA. This allows the fan-out line 40 corresponding to the first connecting line 50 to be as far away from the edge of the display panel 000 as possible in the first direction X, which is beneficial to reducing the width of the binding area BA, that is, the non-display area NA in the first direction X, and further reducing the lower frame of the display panel 000.

[0069] It can be understood that when the first connection line 50 and the first data line S1 are set in different layers, the electrical connection effect between the two can be achieved through vias. The same first connection line 50 can be set in the same layer, or the same first connection line 50 can be set in different layers and electrically connected to each other. This embodiment will not be elaborated here.

[0070] Optional, such as Figure 9 As shown, Figure 9 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 9 Transparency is filled in), the display panel 000 of this embodiment may further include a functional device area QA, which may be used to subsequently set a camera or other photosensitive element within the range, and at least part of the display area AA is set around the functional device area QA; in the arrangement direction of the display area AA and the binding area BA (i.e., the second direction Y in the figure), the display area AA includes a first display area AA1 and a second display area AA2 located on opposite sides of the functional device area QA, and the first display area AA1 is located on a side of the second display area AA2 away from the binding area BA; the display area AA includes a plurality of second data lines S2, and a second data line S2 includes a first portion S21 and a second portion S22 connected to each other, the first portion S21 is located in the first display area AA1, and the second portion S22 is located in the second display area AA2; the second portion S21 of the same second data line S2 is located in the first display area AA1, and the second portion S22 is located in the second display area AA2; The first part S21 and the second part S22 are connected by a second connecting line 60, and the second connecting line 60 is arranged around the functional device area QA, that is, the first part S21 and the second part S22 of the same second data line S2 disconnected by the functional device area QA can be connected together through the second connecting line 60. The second connecting line 60 is located within the display area AA and is arranged on a different layer from the second data line S2. The second connecting line 60 and the first connecting line 50 can be arranged on the same layer, so that the second connecting line 60 can be made using the film layer where the first connecting line 50 is located. There is no need to set up a separate film layer for the second connecting line 60, which can reduce the thickness of the panel. In addition, setting the second connecting line 60 within the display area AA can avoid the second connecting line 60 occupying the border space of the functional device area QA when it is arranged around the functional device area QA, which is beneficial to reducing the border of the functional device area QA.

[0071] In some optional embodiments, please refer to Figure 7 、 Figure 8 and Figure 10 , Figure 10 yes Figure 7 Another schematic diagram of the layout structure of a partial area of a neutron pixel (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 10 In this embodiment, the first reset signal line REF1 is provided at the same layer as at least part of the first connection line 50 (eg Figure 10 Alternatively, the second reset signal line REF2 is provided at the same layer as at least part of the first connection line 50 (as shown in FIG. Figure 8 shown).

[0072] This embodiment explains that in order to ensure the display quality while improving the PPI of the display panel, the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P are arranged in different layers, so that the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P can be as close as possible to or even overlap in the second direction Y, thereby minimizing the length occupied by one sub-pixel P in the second direction Y. When achieving a high PPI effect of the display panel 000, the film layer where part of the first connecting line 50 is located can be used to make one of the first reset signal line REF1 and the second reset signal line REF2, such as the first reset signal line REF1 and at least part of the first connecting line 50 are arranged in the same layer (such as Figure 10 As shown), the second reset signal line REF2 can be set in the film layer where it is originally located; or, the second reset signal line REF2 is set in the same layer as at least part of the first connection line 50 (as shown). Figure 8 As shown), the first reset signal line REF1 can be set in the film layer where it is originally located, so that the film layer where the first connecting line 50 originally existed in the display panel 000 is located can be used to make the first reset signal line REF1 and the second reset signal line REF2 corresponding to the same sub-pixel P arranged in different layers, without having to set up another film layer for making reset signal lines of different layers, thereby reducing the thickness of the panel and realizing a thin design of the panel.

[0073] Optionally, the same first connecting line 50 may be provided in different layers, that is, the same first connecting line 50 may include a structure in which some segments are in the same film layer and the remaining segments are in another film layer, that is, the same first connecting line 50 is made of two film layers ( Figure 8 and Figure 10 When the first connection line 50 extends along the second direction Y to the non-display area NA and connects to the fan-out line 40, it needs to avoid one of the second reset signal line REF2 and the first reset signal line REF1 on the same layer. Figure 8 As shown, the second reset signal line REF2 is arranged in the same layer as at least part of the first connection line 50. When the first connection line 50 extends along the second direction Y to the position of the second reset signal line REF2, the first connection line 50 needs to be changed to another layer to avoid the second reset signal line REF2 in the same layer. After leaving the position of the second reset signal line REF2, it can also be changed back to the film layer where the first connection line 50 was originally located to ensure the normal signal transmission effect of the first connection line 50 and the second reset signal line REF2.

[0074] In some optional embodiments, please continue to refer to Figure 7 and Figure 8In this embodiment, the display panel 000 includes a plurality of first power signal lines PVDD, and the first power signal line PVDD is electrically connected to the first electrode of the driving transistor DT;

[0075] The display panel 000 includes a substrate 00 (not filled in the figure) and a first metal layer M1, a capacitor metal layer Mc, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 located on one side of the substrate 00; optionally, the substrate 00 may further include an active layer. When the transistor in the pixel circuit 10 is a low-temperature polysilicon thin film transistor, the active layer may be a polysilicon semiconductor layer ( Figure 8 and Figure 10 (marked with POLY in the

[0076] The gate of the driving transistor DT is located on the first metal layer M1. Optionally, the gates of other transistors in the pixel circuit 10 may also be disposed on the first metal layer M1.

[0077] The first reset signal line REF1 is located on the capacitor metal layer Mc;

[0078] The source (first electrode) and drain (second electrode) of the driving transistor DT are located in the second metal layer M2, and the same first power signal line PVDD is located in the second metal layer M2. Optionally, the source and drain of other transistors in the pixel circuit 10 can also be set in the first metal layer M1. It can be understood that this embodiment is summarized by taking the first power signal line PVDD located in the same hungry second metal layer M2 as an example for illustration. In specific implementation, the film layer setting structure of the same first power signal line PVDD includes but is not limited to this. The first power signal line PVDD can also be set in a double film layer, which is not described in detail in this embodiment.

[0079] The first connection line 50 includes a first conductive line 501 and a second conductive line 502 connected in sequence, wherein the first conductive line 501 is located in the third metal layer M3; and the second conductive line 502 is located in the fourth metal layer M4;

[0080] The second reset signal line REF2 is located in the fourth metal layer M4.

[0081] This embodiment explains that the same first connection line 50 can be arranged in different layers. Specifically, the same first connection line 50 can include a first conductive line 501 and a second conductive line 502 connected in sequence. The first conductive line 501 is located in the third metal layer M3; the second conductive line 502 is located in the fourth metal layer M4. When the first connection line 50 extends along the second direction Y to the non-display area NA and connects to the fan-out line 40, it is necessary to avoid the second reset signal line REF2 located in the fourth metal layer M4. Figure 8As shown, the second reset signal line REF2 and at least part of the first connecting line 50 (the second conductive wire 502) are arranged in the same layer, and both are located in the fourth metal layer M4. Then, when the second conductive wire 502 of the first connecting line 50 located in the fourth metal layer M4 extends along the second direction Y to the position of the second reset signal line REF2 located in the fourth metal layer M4, the first connecting line 50 needs to be changed in layer, that is, the first conductive wire 501 of the first connecting line 50 is changed to the third metal layer M3, avoiding the second reset signal line REF2 located in the fourth metal layer M4. After leaving the position of the second reset signal line REF2 in the fourth metal layer M4, it can be changed back to the second conductive wire 502 of the fourth metal layer M4 to ensure the normal signal transmission effect of the first connecting line 50 and the second reset signal line REF2, avoid the short circuit problem between the first connecting line 50 and the second reset signal line REF2 at the intersection, and help to ensure the display quality of the display panel 000.

[0082] Optional, such as Figure 7 、 Figure 8 and Figure 11 As shown, Figure 11 yes Figure 8 Schematic diagram of the split structure of some signal lines in the middle (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 11 In this embodiment, the first reset signal line REF1 and the second reset signal line REF2 extend along the first direction X;

[0083] The first conductive line 501 extends along a second direction Y, wherein the first direction X and the second direction Y intersect each other. Optionally, in the figures of this embodiment, the first direction X and the second direction Y are perpendicular to each other in a direction parallel to the plane where the display panel 000 is located.

[0084] Along a direction perpendicular to the plane of the display panel 000 , the first conductive line 501 at least partially overlaps with the second reset signal line REF2 .

[0085] This embodiment explains that when the second reset signal line REF2 and the second conductor 502 of the first connecting line 50 are arranged in the same layer and are both located in the fourth metal layer M4, when the second conductor 502 located in the fourth metal layer M4 extends along the second direction Y to the position of the second reset signal line REF2 located in the fourth metal layer M4, the first connecting line 50 needs to be changed in layer, that is, the first conductor 501 of the first connecting line 50 is changed to the third metal layer M3, so that along the direction perpendicular to the plane where the display panel 000 is located, the first conductor 501 and the second reset signal line REF2 at least partially overlap. After the first conductor 501 leaves the position of the second reset signal line REF2 in the fourth metal layer M4, it continues to be routed along the second conductor 502 located in the fourth metal layer M4 to avoid the short circuit problem between the first connecting line 50 and the second reset signal line REF2 at the intersection, which is beneficial to ensuring the display quality of the display panel 000.

[0086] In some optional embodiments, please refer to Figure 7 、 Figure 12 and Figure 13 , Figure 12 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel area, Figure 13 yes Figure 12 Schematic diagram of the split structure of some signal lines in the middle (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 12 and Figure 13 In this embodiment, the same first power signal line PVDD extends along the second direction Y, and the first power signal line PVDD is located in the second metal layer M2;

[0087] The first conductive wire 501 and the second conductive wire 502 both extend along the second direction Y;

[0088] Along a direction perpendicular to the plane where the display panel 000 is located, the first connection line 50 at least partially overlaps with the first power signal line PVDD.

[0089] This embodiment explains that the same first power signal line PVDD extends along the second direction Y, and the first power signal line PVDD is located in the same second metal layer M2, that is, the first power signal line PVDD can be made of the same conductive film layer, and the first conductor 501 and the second conductor 502 of the first connecting line 50 can be set to extend along the same second direction Y. Since the film layer where the first connecting line 50 is located is different from the film layer of the first power signal line PVDD, the first conductor 501 and the second conductor 502 of the first connecting line 50 do not need to avoid the position of the first power signal line PVDD. When the first connection line 50 of the display area AA is used to electrically connect the first data line S1 of the display area AA with the conductive pad 30 of the binding area BA, the first connection line 50 can be set in a direction perpendicular to the plane where the display panel 000 is located, and the first connection line 50 and the first power signal line PVDD at least partially overlap. Since the first power signal line PVDD is generally connected to a high-potential signal with a fixed potential, the first connection line 50 located in the display area AA is set to at least partially overlap with the first power signal line PVDD, so that the first connection line 50 can avoid the position where the data line S (or the first data line S1) is located in the display area AA. The polarity of the data voltage signal generally connected to the data line S in different frames is generally interchanged. Therefore, the first connection line 50 is set to avoid the position where the data line S is located in the display area AA, which can avoid the first connection line 50 and the data line S from overlapping and thus affecting the transmission performance of the data voltage signal of the data line S.

[0090] In some optional embodiments, please refer to Figure 7 、 Figure 14 and Figure 15 , Figure 14 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel area, Figure 15 yes Figure 14 Schematic diagram of the split structure of some signal lines in the middle (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 14 and Figure 15 (The first power signal line PVDD is filled with transparency.) In this embodiment, the same first power signal line PVDD extends along the second direction Y. The same first power signal line PVDD includes a first sub-line PVDD1 and a second sub-line PVDD2. The first sub-line PVDD1 is located in the second metal layer M2, and the second sub-line PVDD2 is located in the third metal layer M3. The first sub-line PVDD1 and the second sub-line PVDD2 are connected through a via K1.

[0091] Along a direction perpendicular to the plane where the display panel 000 is located, the second sub-line PVDD2 does not overlap with the first conductive line 501 .

[0092] This embodiment illustrates that the same first power signal line PVDD extends along the second direction Y. The same first power signal line PVDD corresponding to a sub-pixel P may include a first sub-line PVDD1 and a second sub-line PVDD2 located in different film layers. The first sub-line PVDD1 is located in the second metal layer M2, i.e., the first sub-line PVDD1 of the first power signal line PVDD is provided in the same layer as the data line S. The second sub-line PVDD2 is located in the third metal layer M3, i.e., the second sub-line PVDD2 of the first power signal line PVDD is provided in the same layer as the first conductive line 501 of the first connecting line 50. In this embodiment, the first sub-line PVDD1 and the second sub-line PVDD2 of different film layers are connected through a via K1. This allows the first sub-line PVDD1 and the second sub-line PVDD2 of different film layers of the same first power signal line PVDD to form a parallel structure, thereby reducing the routing impedance of the first power signal line PVDD and facilitating improved display uniformity of the display panel 000. In this embodiment, when the first connecting line 50 of the display area AA is used to electrically connect the first data line S1 of the display area AA with the conductive pad 30 of the binding area BA, the first connecting line 50 and the first power signal line PVDD at least partially overlap. Since the first power signal line PVDD is generally connected to a high-potential signal with a fixed potential, the first connecting line 50 and the data line S can be prevented from overlapping, thereby affecting the transmission performance of the data voltage signal of the data line S. At this time, it is necessary to set the direction perpendicular to the plane where the display panel 000 is located, so that the second sub-line PVDD2 located in the third metal layer M3 and the first wire 501 located in the third metal layer M3 do not overlap, that is, the first wire 501 located in the third metal layer M3 can avoid the second sub-line PVDD2 of the first power signal line PVDD located in the third metal layer M3 through the design of the winding structure, so as to avoid the short circuit problem of the first connecting line 50 and the first power signal line PVDD at the intersection, which is beneficial to ensure the display quality of the display panel 000.

[0093] Optional, such as Figure 7 、 Figure 14 and Figure 15 As shown, the same first power signal line PVDD corresponding to a sub-pixel P in this embodiment may include a first sub-line PVDD1 and a second sub-line PVDD2 located in different film layers, which can be arranged in a direction perpendicular to the plane where the display panel 000 is located. The first sub-line PVDD1 and the second sub-line PVDD2 at least partially overlap, which can avoid the first power signal lines PVDD of different film layers occupying too much panel space, and since the two are located in different film layers, even if they overlap with each other, it will not affect the signal transmission performance in the panel.

[0094] Optional, such as Figure 7 、 Figure 14 and Figure 15As shown, in this embodiment, the first conductive wire 501 extends along the second direction Y, and the second conductive wire 502 includes a first sub-portion 502A extending along the second direction Y and two second sub-portions 502B extending along the first direction X; wherein the first direction X and the second direction Y intersect; a first conductive wire 501, a second sub-portion 502B, a first sub-portion 502A, another second sub-portion 502B, and another first conductive wire 501 are connected in sequence.

[0095] This embodiment explains that the second sub-wire PVDD2 located in the third metal layer M3 does not overlap with the first wire 501 located in the third metal layer M3 in a direction perpendicular to the plane where the display panel 000 is located. The first wire 501 located in the third metal layer M3 can avoid the second sub-wire PVDD2 of the first power signal wire PVDD located in the third metal layer M3 through the design of a U-shaped winding structure. Specifically, the first wire 501 located in the third metal layer M3 of the first connecting wire 50 extends along the second direction Y, and the second wire 502 located in the fourth metal layer M4 of the first connecting wire 50 includes a first sub-portion 502A extending along the second direction Y and two second sub-portions 502B extending along the first direction X; wherein, a first wire located in the third metal layer M3 is provided. The first conductive line 501, a second sub-portion 502B located in the fourth metal layer M4, a first sub-portion 502A located in the fourth metal layer M4, another second sub-portion 502B located in the fourth metal layer M4, and another first conductive line 501 located in the third metal layer M3 are sequentially connected. By designing the second conductive line 502 located in the fourth metal layer M4 in a sub-pixel P as a U-shaped structure, a short circuit between the first connecting line 50 and the first power signal line PVDD at the intersection can be avoided. Furthermore, a portion of the second conductive line 502 located in the fourth metal layer M4 can overlap with the second sub-line PVDD2 of the first power signal line PVDD located in the third metal layer M3, thereby preventing interference with the transmitted data voltage signal when the second conductive line 502 is located at the data line S. Furthermore, in this embodiment, the first conductive line 501 located in the third metal layer M3 can avoid a short circuit between the second reset signal line REF2 of the fourth metal layer M4 and the first connecting line 50 at the intersection, thereby further ensuring the display quality of the display panel 000.

[0096] In some optional embodiments, please refer to Figure 7 、 Figure 16 and Figure 17 , Figure 16 yes Figure 7 Schematic diagram of another layout structure of a part of the neutron pixel area, Figure 17 yes Figure 16 Schematic diagram of the split structure of some signal lines in the middle (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 16 and Figure 17In the embodiment, the display panel 000 further includes a plurality of scan lines G (such as the first scan signal line Scan1 connected to the first reset module 101 and the second scan signal line Scan2 connected to the second reset module 102 in the pixel circuit 10), and at least one scan line G is arranged in a different layer from the second reset signal line REF2.

[0097] This embodiment explains that when the extension direction of the scan line G in the display panel 000 is the same as the extension direction of the reset signal line, for example, the first reset signal line REF1 and the second reset signal line REF2 are both extended along the first direction X, and the multiple scan lines G included in the display panel 000 are also extended along the first direction X, at least one scan line G and the second reset signal line REF2 can be arranged in different layers, such as Figure 16 As shown, if the scan line G is generally set in the first metal layer M1, the second reset signal line REF2 is set in the fourth metal layer M4, and at least one scan line G and the second reset signal line REF2 are set in different film layers, at least one scan line G and the second reset signal line REF2 corresponding to the same sub-pixel P can be set as close as possible in their arrangement direction (the first direction X shown in the figure), and even at least one scan line G and the second reset signal line REF2 corresponding to the same sub-pixel P can be set to at least partially overlap, thereby ensuring the normal driving effect of the pixel circuit 10 while further reducing the length occupied by a sub-pixel P in the second direction Y, so as to further improve the PPI of the display panel 000 and ensure the display quality.

[0098] In some alternative embodiments, please refer to Figure 18 , Figure 18 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 18 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in the embodiment of the present invention can be a computer, a television, an in-vehicle display device, or other display device 111 having a display function, and the present invention does not impose any specific limitations thereon. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0099] It can be seen from the above embodiments that the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0100] The sub-pixels of the display panel provided by the present invention include a pixel circuit electrically connected to the light-emitting element, the pixel circuit is used to drive the light-emitting element to emit light, and the pixel circuit includes at least a driving transistor, a first reset module and a second reset module, wherein the first reset module is used to transmit the first reset signal provided by the first reset signal line to the gate of the driving transistor, to reset the gate of the driving transistor, so as to facilitate the driving transistor to be turned on during subsequent threshold compensation. The second reset module is used to transmit the second reset signal provided by the second reset signal line to the anode of the light-emitting element, so that the anode of the light-emitting element is initialized, thereby improving the residual of the data signal of the previous frame, improving the afterimage phenomenon, and enhancing the display effect of the display panel. The present invention sets the first reset signal line and the second reset signal line corresponding to the same sub-pixel to be independent of each other to provide different reset signal values, which can improve the afterimage problem and improve the visual effect of the display panel under low grayscale, thereby helping to ensure the display quality. The present invention also provides a first reset signal line and a second reset signal line corresponding to the same sub-pixel in different layers, thereby ensuring that the first reset signal line and the second reset signal line corresponding to the same sub-pixel have sufficient line width to reduce the routing impedance and improve signal transmission performance, while also not having to consider the spacing between the first reset signal line and the second reset signal line. Since the two are arranged in different layers, even if the two overlap, it will not cause a short circuit problem between the signal lines. Thus, the first reset signal line and the second reset signal line corresponding to the same sub-pixel can be as close as possible to or even overlap in their arrangement direction, thereby ensuring the normal driving effect of the pixel circuit while minimizing the length occupied by a sub-pixel in the second direction, which is conducive to achieving a high PPI effect of the display panel. The present invention arranges the first reset signal line and the second reset signal line corresponding to the same sub-pixel in different layers, saving panel wiring space, reducing the size of a single sub-pixel, and providing a higher possibility for increasing the overall number of sub-pixels in the display panel, thereby improving the PPI of the display panel without adversely affecting the layout of the pixel circuit or the conduction of electrical signals.

[0101] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: a plurality of sub-pixels, each of the sub-pixels comprising a pixel circuit and a light-emitting element electrically connected; The pixel circuit at least includes a driving transistor, a first reset module and a second reset module; A first end of the first reset module is connected to the gate of the driving transistor, and a second end of the first reset module is connected to a first reset signal line; A first end of the second reset module is connected to the light emitting element, and a second end of the second reset module is connected to a second reset signal line; The first reset signal line and the second reset signal line corresponding to the same sub-pixel are arranged in different layers; The display panel includes a display area and a non-display area; The non-display area includes a binding area, and the binding area is located on one side of the display area; The binding area includes a plurality of conductive pads, the conductive pads are electrically connected to the fan-out wiring, and the fan-out wiring is located in the non-display area; The display area includes a plurality of first data lines, the first data lines are electrically connected to the fan-out lines through at least one first connecting line, and the first connecting line is located in the display area; The first connecting line includes a first conductive line and a second conductive line connected in sequence, and the first conductive line and the second conductive line are arranged in different layers; The first reset signal line and the second reset signal line extend along a first direction; The first conductive line extends along a second direction, wherein the first direction and the second direction intersect; The second conductive line and the second reset signal line are arranged on the same layer; Along a direction perpendicular to the plane where the display panel is located, the first conductive line at least partially overlaps with the second reset signal line.

2. The display panel according to claim 1, wherein: Along a direction perpendicular to the plane where the display panel is located, the first reset signal line and the second reset signal line corresponding to the same sub-pixel at least partially overlap.

3. The display panel according to claim 1, wherein: The display panel includes a plurality of first power signal lines, wherein the first power signal lines are electrically connected to the first electrode of the driving transistor; The display panel includes a substrate and a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer, and a fourth metal layer located on one side of the substrate; The gate of the driving transistor is located in the first metal layer; The first reset signal line is located in the capacitor metal layer; The source and drain of the driving transistor are located in the second metal layer, and the first power signal line is located in the second metal layer; The first conductive line is located in the third metal layer; the second conductive line is located in the fourth metal layer; The second reset signal line is located in the fourth metal layer.

4. The display panel according to claim 3, wherein: The same first power signal line extends along the second direction, and the first power signal line is located in the second metal layer; The second conductive line extends along the second direction; Along a direction perpendicular to the plane where the display panel is located, the first connecting line and the first power signal line at least partially overlap.

5. The display panel according to claim 3, wherein: The same first power signal line extends along the second direction, and the same first power signal line includes a first sub-line and a second sub-line, the first sub-line is located in the second metal layer, and the second sub-line is located in the third metal layer; the first sub-line and the second sub-line are connected through a via; Along a direction perpendicular to the plane where the display panel is located, the second sub-line does not overlap with the first conductive line.

6. The display panel according to claim 5, wherein: The second conductive line includes a first sub-portion extending along the second direction and two second sub-portions extending along the first direction; one first conductive line, one second sub-portion, one first sub-portion, another second sub-portion, and another first conductive line are connected in sequence.

7. The display panel according to claim 5, wherein: Along a direction perpendicular to the plane where the display panel is located, the first sub-line and the second sub-line at least partially overlap.

8. The display panel according to claim 3, wherein: The display panel further includes a plurality of scan lines, and at least one of the scan lines is disposed in a different layer from the second reset signal line.

9. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 8.

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